200 MHz Spread Spectrum Clock Synthesizer/Driver
with Differential CPU Outputs
W320-04
................ .......Document #: 38-07010 Rev. *C Page 1 of 16
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com
Features
• Compliant with Intel® CK-Titan clock synthesizer/driver
specifications
• Multiple output clocks at different frequencies
— Three pairs of differential CPU outputs, up to
200 MHz
— Ten synchronous PCI clocks, three free-running
— Six 3V66 clocks
— Two 48 MHz clocks
— One reference clock at 14.318 MHz
— One VCH clock
• Spread Spectrum clocking (down spread)
• Power-down fe atu r es (PCI_STOP# , CPU_ STOP#
PWR_DWN#)
• Three Select inputs (Mode select and IC Frequency
Select)
• OE and Test Mode support
• 56-pin SSOP package and 56-pin TSSOP package
Benefits
• Support s nex t-generatio n Pentium® processors using
differential clock drivers
• Motherboard clock generator
— Supports multiple CPUs and a chipset
— Support for PCI slots and chipset
— Supports AGP, DRCG reference, and Hub Link
— Supports USB host controller and graphic controller
— Supports ISA slots and I/O chip
• Enables reduction of electromagne tic inter f erence
(EMI) and overall system cost
• Enables ACPI-compl ia nt de s ign s
• Supports up to four CPU clock frequencies
• Enables ATE and “bed of nails” testing
• Widely available standard package enables lower cost
Logic Block Diagram SSOP and TSSOP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
36
35
VDD_REF
34
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
XTAL_IN
XTAL_OUT
GND_REF
25
26
27
28
49
52
51
50
53
56
55
54
PCI0
PCI5
66BUFF2/3V66_4
GND_3V66
PCI_STOP#
S2
GND_CPU
CPU_STOP#
PCI_F2
GND_PCI
GND_3V66
VDD_CORE
VDD_ 48 MHz
MULT0#
VDD_CPU
REF
PCI_F0
PCI_F1
VDD_PCI
GND_PCI
PCI1
PCI2
PCI3
VDD_PCI
PCI4
PCI6
VDD_3V66
66BUFF0/3V66_2
66BUFF1/3V66_3
66IN/3V66_5
PWR_DWN#
3V66_0
VDD_3V66
3V66_1/VCH
GND_ 48 MHz
DOT
USB
GND_IREF
IREF
CPU#2
CPU2
VDD_CPU
CPU#1
CPU1
CPU#0
CPU0
S0
S1
GND_CORE
PWR_GD# SCLK
SDATA
W320-04
VDD_REF
CPU0:2
CPU#0:2
PCI_F0:2
XTAL
PLL Ref Freq
X2
X1 REF
VDD_PCI
USB (48MHz)
VCH_CLK/ 3V66_1
OSC
VDD_CPU
CPU_STOP#
SCLK
PCI0:6
PCI_STOP#
Stop
Clock
Control
Stop
Clock
Control
PLL 1
SMBus
Logic
DOT (48MHz)
PWR_DWN#
S0:2
VDD_48MHz
SDATA
VDD_3V66
3V66_0
3V66_2:4/
Divider
Network
3V66_5/ 66IN
PWR
PWR
PWR
PWR
PWR
PLL 2
PWR
66BUFF0:2
Gate
PWR_GD#
Pin Configurations
/2
W320-04
................. ......Document #: 38-07010 Rev. *C Page 2 of 16
Pin Summary
Name Pins Description
REF 56 3.3V 14.318-MHz clock output.
XTAL_IN 214.318 -MHz crystal input.
XTAL_OUT 314.318 -MHz crystal input.
CPU, CPU# [0:2] 44, 45, 48, 49, 51, 52 Differential CPU clock outputs.
3V66_0 33 3.3V 66-MHz clock output.
3V66_1/VCH 35 3.3V selectable through SMBus to be 66 MHz or 48 MHz.
66IN/3V66_5 24 66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from
internal VCO.
66BUFF [2:0] /3V66 [4:2] 21, 22, 23 66-MHz buffered outputs from 66Input or 66-MHz clocks from internal
VCO.
PCI_F [0:2] 5, 6, 7, 33-MHz clocks divided down from 66Input or divided down from 3V66.
PCI [0:6] 10, 11, 12 , 13, 16, 17, 18 PCI clock outputs divided down from 66Input or divided down from
3V66.
USB 39 Fixed 48-MHz clock output.
DOT 38 Fixed 48-MHz clock output.
S2 40 Special 3.3V 3-level input for Mode selection.
S1, S0 54, 55 3.3V LVTTL inputs for CPU frequency selection.
IREF 42 A precision resistor is attached to this pin, which is connected to the
internal current reference.
MULT0 43 3.3V LVTTL input for selecting the current multiplier for the CPU
outputs.
PWR_DWN# 25 3.3V LVTTL input for Power_Down# (active LOW).
PCI_STOP# 34 3. 3V LVTTL input for PCI_STOP# (active LOW).
CPU_STOP# 53 3.3V LVTTL input for CPU_STOP# (active LOW).
PWRGD# 28 3.3V LVTTL input is a level sensitive strobe used to determine when
S[2:0] and MULTI0 inputs are valid and OK to be sampled (Active
LOW). Once PWRGD# is sampled LOW , the status of this output will
be ignored.
SDATA 29 SMBus compatible SDATA.
SCLK 30 SMBus compatible SCLK.
VDD_REF, VDD_PCI,
VDD_3V66, VDD_CPU 1, 8, 14, 19, 32, 46, 50 3.3V power supply for outputs.
VDD_48 MHz 37 3.3V power supply for 48 MHz.
VDD_CORE 26 3.3V power supply for PLL.
GND_REF, GND_PCI,
GND_3V66, GND_IREF,
VDD_CPU
4, 9, 15, 20, 31, 36, 41, 47 Ground for outputs.
GND_CORE 27 Ground for PLL.
W320-04
................. ......Document #: 38-07010 Rev. *C Page 3 of 16
Function Table[1]
S2 S1 S0 CPU
(MHz) 3V66[0:1]
(MHz)
66BUFF[0:2]/
3V66[2:4]
(MHz) 66IN/3V66_5
(MHz) PCI_F/PCI
(MHz) REF0(MHz) USB/DOT
(MHz) Notes
1 0 0 66 MHz 66 MHz 66IN 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4
1 0 1 100 MHz 66 MHz 66IN 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4
1 1 0 200 MHz 66 MHz 66IN 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4
1 1 1 133 MHz 66 MHz 66IN 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4
0 0 0 66 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4
0 0 1 100 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4
0 1 0 200 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4
0 1 1 133 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4
Mid 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1, 5
Mid 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2 5, 6, 7
Mid 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved –
Mid 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved –
Swing Select Functions
Mult0 Board Ta rget Trace/Term Z Reference R, IREF = VDD/(3*Rr) Output Current VOH @ Z
050Rr = 221 1%, IREF = 5.00 mA IOH = 4*IREF 1.0V @ 50
150Rr = 475 1%, IREF = 2.32 mA IOH = 6*IREF 0.7V @ 50
Clock Driver Impedances
Impedance
Buffer Name VDD Range Buffer Type Min. Typ. Max.
CPU, CPU# Type X1 50
REF 3.135–3.465 Type 5 12 30 55
PCI, 3V66, 66BUFF 3.135–3.4 65 Type 5 12 30 55
USB 3.135–3.465 Type 3A 12 30 60
DOT 3.135–3.465 Type 3B 12 30 60
Clock Enable Configuration
PWR_DWN# CPU_STOP# PCI_STOP# CPU CPU# 3V66 66BUFF PCI_F PCI USB/DOT VCOS/ OSC
0 X X IREF*2 FLOAT LOW LOW LOW LOW LOW OFF
1 0 0 ON FLOAT ON ON ON OFF ON ON
1 0 1 ON LOW ON ON ON ON ON ON
1 1 0 ON ON ON ON ON OFF ON ON
111ONONONONONONONON
Note:
1. TCLK is a test clock driven in on the XTALIN input in test mode.
2. “Normal” mode of operation
3. Range of reference frequency allowed is min. = 14.316, nom. = 14.31818 MHz, max. = 14.32 MHz.
4. Frequency accuracy of 48 MHz must be +167PPM to match USB default.
5. Mid. is defined a Voltage level between 1.0V and 1.8V for three-level input functionality. Low is below 0.8V. High is above 2.0V.
6. Required for DC output impedance verification.
7. These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.
W320-04
................. ......Document #: 38-07010 Rev. *C Page 4 of 16
Serial Data Interface (SMBus)
To enhance the flexibility and function of the clock synthesizer ,
a two-signal SMBus interface is provided according to SMBus
specification. Through the Serial Data Interface, various
device functions such as individual clock output buffers, can
be individually enabled or disabled. W320-04 supports both
block read and block write operations.
The registers associated with the Serial Data Interface
initialize to their d efault setting upon power-up, a nd therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power manag ement functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller . The bytes must be accessed in sequential order
from lowest to highest b yte, (most signif ican t bit f irst) with th e
ability to stop after any complete byte has been transferred.
Indexed bytes are not allowed.
A block write begins with a slave address and a WRITE
condition. The R/W bit is used by the SMBus controller as a
data direction bit. A zero indicates a WRITE condition to the
clock device. The slave receiver address is 11010010 (D2h).
A command code of 0000 0000 (00h) and the byte count bytes
are required for any transfer. After the command code, the
core logic issues a byte count which describes number of
additional bytes required for the transfer, not including the
command code and byte count bytes. For example, if the host
has 20 data bytes to send, the first byte would be the number
20 (14h), followed by the 20 bytes of data. The byte count byte
is required to be a minimum of 1 byte and a maximum of 32
bytes It may not be 0. Figure 1 shows an example of a block
write.
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller.
Data Byte Configuration Map
Figure 1.
Start
bit Slave Address
1 1 0 1 0 0 1 0 R/W 0/1 A Command
Code
0 0 0 0 0 0 0 0
A Byte Count = N A Data Byte 0 A . . . Data Byte N-1 AStop
bit
1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit
From Master to Slave
From Slave to Master Figure 1. An Example of a Block Write
Data Byte 0: Control Register (0 = Enable, 1 = Disable)
Bit Affected
Pin# Name Description Type Power On
Default
Bit 7 5, 6, 7, 10,
11, 12, 13,
16, 17, 18,
33, 35
PCI [0:6]
CPU[2:0]
3V66[1:0]
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On R/W 0
Bit 6 – TBD TBD R 0
Bit 5 35 3V66_1/VCH VCH Select 66 MHz/48 MHz
0 = 66 MHz, 1 = 48 MHz R/W 0
Bit 4 44, 45, 48,
49, 51, 52 CPU [2:0]
CPU# [2:0] CPU_STOP#
Reflects the current value of the external CPU_STOP# pin RN/A
Bit 3 10, 11, 12,
13, 16, 17,
18
PCI [6:0] PCI_STOP#
(Does not affect PCI_F [2:0] pins) R/W N/A
Bit 2 – – S2
Reflects the value of the S2 pin sampled on power-up RN/A
Bit 1 – – S1
Reflects the value of the S1 pin sampled on power-up RN/A
Bit 0 – – S0
Reflects the value of the S1 pin sampled on power-up RN/A
W320-04
................. ......Document #: 38-07010 Rev. *C Page 5 of 16
Data Byte 1
Bit Pin# Name Description Type Power On
Default
Bit 7 – N/A CPU Mult0 Value R N/A
Bit 6 52, 49, 45 CPU0:2 Three-State CPU0:2 during power down
0 = Normal; 1 = Three-stated R/W 0
Bit 5 44, 45 CPU2
CPU2# Allow Control of CPU2 with assertion of CPU_STOP#
0 = Not free running; 1 = Free running R/W 0
Bit 4 48, 49 CPU1
CPU1# Allow Control of CPU1 with assertion of CPU_STOP#
0 = Not free running;1 = Free running R/W 0
Bit 3 51, 52 CPU0
CPU0# Allow Control of CPU0 with assertion of CPU_STOP#
0= Not free running; 1 = Free running R/W 0
Bit 2 44, 45 CPU2
CPU2# CPU2 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Bit 1 48, 49 CPU1
CPU1# CPU1Output Enable
1 = Enabled; 0= Disabled R/W 1
Bit 0 51, 52 CPU0
CPU0# CPU0 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Data Byte 2
Bit Pin# Name Pin Description Type Power On
Default
Bit 7 – N/A N/A R 0
Bit 6 18 PCI6 PCI6 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Bit 5 17 PCI5 PCI5 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Bit 4 16 PCI4 PCI4 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Bit 3 13 PCI3 PCI3 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Bit 2 12 PCI2 PCI2 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Bit 1 11 PCI1 PCI1 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Bit 0 10 PCI0 PCI0 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Data Byte 3
Bit Pin# Name Pin Description Type Power On
Default
Bit 7 38 DOT DOT 48-MHz Output Enable R/W 1
Bit 6 39 USB USB 48-MHz Output Enable R/W 1
Bit 5 7 PCI_F2 Allow control of PCI_F2 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP# R/W 0
Bit 4 6 PCI_F1 Allow control of PCI_F1 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP# R/W 0
Bit 3 5 PCI_F0 Allow control of PCI_F0 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP# R/W 0
Bit 2 7 PCI_F2 PCI_F2 Output Enable R/W 1
Bit 1 6 PCI_F1 PCI_F1Output Enable R/W 1
Bit 0 5 PCI_F0 PCI_F0 Output Enable R/W 1
W320-04
................. ......Document #: 38-07010 Rev. *C Page 6 of 16
Data Byte 4
Bit Pin# Name Pin Description Type Power On
Default
Bit 7 – TBD N/A R 0
Bit 6 – TBD N/A R 0
Bit 5 33 3V66_0 3V66_ 0 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Bit 4 35 3V66_1/VCH 3V66_1/VCH Output Enable
1 = Enabled; 0 = Disabled R/W 1
Bit 3 24 66IN/3V66_5 3V66_5 Output Enable
1 = Enable; 0 = Disable
NOTE: This bit should be used when pin 24 is configured
as 3v66_5 output. Do not clear this bit when pin 24 is
configured as 66in input.
R/W 1
Bit 2 23 66BUFF2 66-MHz Buffered 2 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Bit 1 22 66BUFF1 66-MHz Buffered 1 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Bit 0 21 66BUFF0 66-MHz Buffered 0 Output Enable
1 = Enabled; 0 = Disabled R/W 1
Data Byte 5
Bit Pin# Name Pin Description Type Power On
Default
Bit 7 N/A N/A R 0
Bit 6 N/A N/A R 0
Bit 5 66BUFF [2:0] Tpd 66IN to 66BUFF propagation delay control R/W 0
Bit 4 66BUFF [2:0] R/W 0
Bit 3 DOT DOT edge rate control R/W 0
Bit 2 DOT R/W 0
Bit 1 USB USB edge rate control R/W 0
Bit 0 USB R/W 0
Byte 6: Vendor ID
Bit Description Type Power On Default
Bit 7 Revision Code Bit 3 R 0
Bit 6 Revision Code Bit 2 R 0
Bit 5 Revision Code Bit 1 R 0
Bit 4 Revision Code Bit 0 R 0
Bit 3 Vendor ID Bit 3 R 1
Bit 2 Vendor ID Bit 2 R 0
Bit 1 Vendor ID Bit 1 R 0
Bit 0 Vendor ID Bit 0 R 0
W320-04
................. ......Document #: 38-07010 Rev. *C Page 7 of 16
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested .)
Supply Voltage..................................................–0.5 to +7.0V
Input Voltage......................... .. ................. ..–0.5V to VDD+0.5
Storage Temperature (Non-Condensing) ....–65C to +150C
Max. Soldering Te mperature (10 sec)....................... +260C
Junction Temperature......................................... ... .... +150C
Package Power Dissipation...............................................1
Static Discharge Voltage
(per MIL-STD-883, Method 3015)............................> 2000V
Operating Conditions[8] Over which Electrical Parame ters are Guaranteed
Parameter Description Min. Max. Unit
VDD_REF, VDD_PCI,VDD_CORE,
VDD_3V66, VDD_CPU, 3.3V Supply Voltages 3.135 3.465 V
VDD_48 MHz 48-MHz Supply Voltage 2.85 3.465 V
TAOperating Temperature, Ambient 0 70 C
Cin Input Pin Capacitance 5 pF
CXTAL XTAL Pin Capacitance 22.5 pF
CLMax. Capacitive Load on
USBCLK, REF
PCICLK, 3V66 20
30
pF
f(REF) Reference Frequency, Oscillator Nominal Value 14.318 14.318 MHz
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
VIH High-level Input Voltage Except Crystal Pads. Threshold Voltage for Crystal Pads = VDD/2 2.0 V
VIL Low-level Input Voltage Except Crystal Pads 0.8 V
VOH High-level Output Voltage USB, REF, 3V66 IOH = –1 mA 2.4 V
PCI IOH = –1 mA 2.4 V
VOL Low-level Output Vo ltage USB, REF, 3V66 IOL = 1 mA 0.4 V
PCI IOL = 1 mA 0.55 V
IIH Input HIGH Current 0 < VIN < VDD –5 5 mA
IIL Input LOW Current 0 < VIN < VDD –5 5 mA
IOH High-level Output Current CPU
For IOH =6*IRef Configuration Type X1, VOH = 0.65V 12.9 mA
Type X1, VOH = 0.74V 14.9
REF, DOT, USB Type 3, VOH = 1.00V –29
Type 3, VOH = 3.135V –23
3V66, DOT, PCI, REF Type 5, VOH = 1.00V –33
Type 5, VOH = 3.135V –33
IOL Low-level Output Current REF, DOT, USB Type 3, VOL = 1.95V 29 mA
Type 3, VOL = 0.4V 27
3V66, PCI, REF Type 5, VOL = 1.95 V 30
Type 5, VOL = 0.4V 38
IOZ Output Leakage Current Three-state 10 mA
IDD3 3.3V Power Supply Current VDD_CORE/VDD3.3 = 3.465V, FCPU = 133 MHz 360 mA
IDDPD3 3.3V Shut-down Current VDD_CORE/VDD3.3 = 3.465V and @ IREF = 2.32 mA 25 mA
IDDPD3 3.3V Shut-down Current VDD_CORE/VDD3.3 = 3.465V and @ IREF = 5.0 mA 45 mA
Note:
8. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
W320-04
................. ......Document #: 38-07010 Rev. *C Page 8 of 16
-
Switching Characteristics[9] Over the Operating Range
Parameter Output Description Test Conditions Min. Max. Unit
t1All Output Duty Cycle[10] Measured at 1.5V 45 55 %
t3USB, REF, DOT Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 ns
t3PCI,3V66 Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns
t53V66[0:1] 3V66-3V66 Skew Measured at 1.5V 500 ps
t566BUFF[0:2] 66BUFF-66BUFF Skew Measured at 1.5V 175 ps
t6PCI PCI-PCI Skew Measured at 1.5V 500 ps
t73V66, PCI 3V66-PCI Clock Jitter 3V66 leads. Measured at 1.5V 1.5 3.5 ns
t93V66 Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 250 ps
t9USB, DOT Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 350 ps
t9PCI Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 500 ps
t9REF Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 1000 ps
CPU 1.0V Switching Characteristics
t2CPU Rise Time Measured differential waveform from
–0.35V to +0.35V 175 467 ps
t3CPU Fall Time Measured differential waveform from
–0.35V to +0.35V 175 467 ps
t4CPU CPU-CPU Skew Measured at Crossover 150 ps
t8CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B 150 ps
CPU Rise/Fall Matching Measured with test loads[11] 325 mV
Voh CPU High-level Output Voltage
including overshoot Measured with test loads[11] 0.92 1.45 V
Vol CPU Low-level Output Voltage
including undershoo t Measured with test loads[11] –0.2 0.35 V
Vcrossover CPU Crossover Vo ltage Measured with test loads[11] 0.51 0.76 V
CPU 0.7V Switching Characteristics
t2CPU Rise Time Measured single ended waveform from
0.175V to 0.525V 175 700 ps
t3CPU Fall Time Measured single ended waveform from
0.175V to 0.525V 175 700 ps
t4CPU CPU-CPU Skew Measured at Crossover 150 ps
t8CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B
With all outputs running 150 ps
CPU Rise/Fall Matching Measured with test loads[12, 13] 20 %
Voh CPU High-level Output Voltage
Including Oversh oot Measured with test loads[13] 0.85 V
Vol CPU Low-level Output Voltage
Including Unde rshoot Measured with test loads[13] –0.15 V
Vcrossover CPU Crossover Vo ltage Measured with test loads[13] 0.28 0.43 V
Notes:
9. All parameters specified with loaded outputs.
10.Duty cycle is measured at 1.5V when V DD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
11.The 1.0V test load is shown on the test circui t page.
12.Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge.
13.The 0.7V test load is Rs = 33.2 ohm, Rp = 49.9 ohm in test circuit.
W320-04
................. ......Document #: 38-07010 Rev. *C Page 9 of 16
Definition and Application of PWRGD# Signal
CPU
VRM8.5
3.3V
PWRGD#
NPN
CLOCK
GENERATOR 10K
10K
10K
10K GMCH
S1
S0
3.3V 3.3V
PWRGD#
BSEL0 BSEL1
Vtt
W320-04
.....................Document #: 38-07010 Rev. *C Page 10 of 16
Switching Waveforms
Duty Cycle Timing (Single-ended Out put)
t1B
t1A
Duty Cycle Timing (CPU Differential Output)
t1B
t1A
All Outputs Rise/Fall Time
OUTPUT
t2
VDD
0V
t3
CPU-CPU Clock Skew
Host_b
Host
t4
Host_b
Host
3V66-3V66 Clock Skew
3V66
3V66
t
PCI-PCI Clock Skew
PCI
PCI
t
W320-04
.....................Document #: 38-07010 Rev . *C Page 11 of 16
Switching Waveforms (continued)
3V66
PCI t7
3V66-PCI Clock Skew
t8A t8B
CPU Clock Cycle-Cycle Jitter
Host_b
Host
t9A t9B
Cycle-Cycle Clock Jitter
CLK
PWRDWN# Assertion
Power Down Rest of Generator
UNDEF
66BUFF
PCI_F (APIC)
CPU
CPU#
3V66
66IN
USB
REF
PCI
PWR_DWN#
Note: PCI_STOP# asserted LOW
W320-04
.....................Document #: 38-07010 Rev. *C Page 12 of 16
PWRGD# Timing Diagrams
PWRDWN# Deassertion
10-30 s min.
100-200 s max.
< 3 ms
66BUFF1/GMCH
66BUFF0,2
PCI
PWR_DWN#
CPU
CPU#
3V66
66IN
USB
REF
PCI_F (APIC)
Note: PCI_STO P# asserted LOW
GND VRM 5/12V
PWRGD#
VID [3:0]
BSEL [1:0]
PWRGD# FROM
VRM
PWRGD# FROM
NPN
Possible glitch while Clock VCC is coming
up. Will be gone in 0.2–0.3 mS delay.
VCC CPU CORE
PWRGD#
VCC W320 CLOCK 0.2 -- 0.3 ms
delay Wait for
PWRGD# Sample
BSELS
CLOCK STATE State 0 State 1 State 2 State 3
ON
OFF
OFF
CLOCK VCO
CLOCK OUTPUTS
Figure 2. CPU Power Before Clock Power
ON
GEN
W320-04
.....................Document #: 38-07010 Rev. *C Page 13 of 16
Figure 3. CPU Power After Clock Power
GND VRM 5/12V
PWRGD#
VID [3:0]
BSEL [1:0]
PWRGD# FROM
VRM
PWRGD# FROM
NPN
VCC CPU CORE
PWRGD#
VCC W320 CLOCK 0.2 – 0.3 ms
delay Wait for
PWRGD#
Sample
BSELS
CLOCK STATE State 0 Stat e 1 State 2 State 3
OFF
OFF
CLOCK VCO
CLOCK OUTPUTS ON
ON
GEN
W320-04
.....................Document #: 38-07010 Rev. *C Page 14 of 16
Layout Example
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
6
7
13
19
20
24
G
= VIA to GND plane layer.
V
= VIA to respective supply plane layer.
Note: Each supply plane or strip should have a ferrite bead and capacitors.
1
2
3
4
5
8
9
11
12
14
15
16
17
22
23
21
25
26
27
28
40
3918
41
10
31
30
29
36
35
34
33
32
37
38
FB
+3.3V Supply
C2
Ceramic Caps C1 = 10–22 µF
10
F
FB = Dale ILB1206 - 300 or 2TDKACB2012L-120 or 2 Murata BLM21B601S.
0.005

F
G G
VDDQ3
C1
C5 = 0.1 F C6 = 10 F
G
V
GV
GV
GV
GV
GV
G
V
GG
VDDQ3
C5 C6

W320-04
G
V
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
C2 = 0.005 F
W320-04
.....................Document #: 38-07010 Rev. *C Page 15 of 16
Test Circuit
Note: All capacitors mu st be placed as close to the pins as is physica lly p ossible.
4, 9, 15, 20, 27, 31, 36, 41
VDD_REF, VDD_PCI,
OUTPUTS
W320-04
Note: Each supply pin must have an individual decoupling capacitor.
VDD_3V66, VDD_CORE
VDD_48 MHz, VDD_CPU
Test
Nodes
Rs
Rs
Rp
Rp
CPURef,USB Outputs
PCI,3V66 Outputs
30 pF
20 pF
Test Node
Test Node
8, 14, 19, 26, 32, 37, 46, 50
0.7V amplitude: RS = 33 ohm, R P = 50 ohm
0.7V Test Load
2 pF
2 pF
Ordering Information
Ordering Code Package Type Operating Range
W320-04H 56-pin SSOP Commercial 0C TO 70C
W320-04HT 56-pin SSOP - Tape and Reel Commercial 0C TO 70C
W320-04X 56-pin TSSOP Commercial 0C TO 70C
W320-04XT 56-pin TSSOP - Tape and Reel Commercial 0C TO 70C
Lead-Free
CYW320OXC-4 56-pin SSOP Commercial 0C TO 70C
CYW320OXC-4T 56-pin SSOP - Tape and Reel Commercial 0C TO 70C
CYW320ZXC-4 56-pin TSSOP Commercial 0C TO 70C
CYW320ZXC-4T 56-pin TSSOP - Tape and Reel Commercial 0C TO 70C
4, 9, 15, 20, 27, 31, 36, 41
VDD_REF, VDD_PCI,
OUTPUTS
W320-04
VDD_3V66, VDD_CORE
VDD_48 MHz, VDD_CPU
Test
Nodes
CPU
Ref,USB Outputs
PCI,3V66 Outputs
30 pF
20 pF
Test Node
Test Node
8, 14, 19, 26, 32, 37, 46 ,50
1.0V Test Load
2 pF
2 pF
33
33
63.4 63.4
475
1.0V Amplitude
W320-04
.....................Document #: 38-07010 Rev. *C Page 16 of 16
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-
icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-
sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Labora tories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-
cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Package Diagrams
0.095
0.025
0.008
SEATING PLANE
0.420
0.088
.020
0.292
0.299
0.395
0.092
BSC
0.110
0.016
0.720
0.008
0.0135
0.730
DIMENSIONS IN INCHES MIN.
MAX.
0.040
0.024
0°-8°
GAUGE PLANE
.010
1
28
56
29
0.110
0.005
0.010