STP5NK65Z N-CHANNEL 650V - 1.5 - 5A TO-220 Zener-Protected SuperMESHTMPower MOSFET TYPE STP5NK65Z VDSS RDS(on) ID Pw 650 V < 1.8 5A 85 W TYPICAL RDS(on) = 1.5 EXTREMELY HIGH dv/dt CAPABILITY IMPROVED ESD CAPABILITY 100% AVALANCHE RATED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY TO-220 DESCRIPTION The SuperMESHTM series is obtained through an extreme optimization of ST's well established stripbased PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products. ) s ( ct c u d e t le ) s t( o r P INTERNAL SCHEMATIC DIAGRAM o s b O - APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC u d o r P e t e l o s b O ORDERING INFORMATION SALES TYPE MARKING PACKAGE PACKAGING STP5NK65Z P5NK65Z TO-220 TUBE April 2002 1/9 STP5NK65Z ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Value Unit Drain-source Voltage (VGS = 0) 650 V Drain-gate Voltage (RGS = 20 k) 650 V Gate- source Voltage 30 V ID Drain Current (continuous) at TC = 25C 5 A ID Drain Current (continuous) at TC = 100C 3.1 A Drain Current (pulsed) 20 A IDM (l) PTOT VESD(G-S) dv/dt (1) Tj Tstg Total Dissipation at TC = 25C 85 W Derating Factor 0.6 W/C 2000 V 4.5 V/ns -55 to 150 -55 to 150 C C Gate source ESD(HBM-C=100pF, R=1.5K) Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature (l) Pulse width limited by safe operating area (1) I SD 5A, di/dt 100 A, VDD V(BR)DSS, T j TJMAX. (*) Limited only by maximum temperature allowed c u d THERMAL DATA Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-ambient Max Tl 1.64 e t le AVALANCHE CHARACTERISTICS Symbol Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) ) s ( ct GATE-SOURCE ZENER DIODE Symbol BVGSO so Parameter IAR Parameter u d o Gate-Source Breakdown Voltage r P e o r P 50 Maximum Lead Temperature For Soldering Purpose b O - Test Conditions Igs= 1mA (Open Drain) ) s t( Min. 30 300 C/W C/W C Max Value Unit 4.2 A 190 mJ Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to souce. In this respect the Zener voltage is appropriate to achieve an efficient and costeffective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. t e l o s b O 2/9 STP5NK65Z ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol Parameter Test Conditions Min. Typ. Max. Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 C 1 50 A A IGSS Gate-body Leakage Current (VDS = 0) VGS = 20V 10 A VGS(th) Gate Threshold Voltage VDS = VGS, ID = 50A 3.75 4.5 V RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 2.1 A 1.5 1.8 Typ. Max. Unit V(BR)DSS 650 Unit 3 V DYNAMIC Symbol gfs (1) Ciss Coss Crss Coss eq. (3) Parameter Test Conditions Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. VDS = 10 V, ID = 2.1 A 5 VDS = 25V, f = 1 MHz, VGS = 0 Equivalent Output Capacitance 680 80 17 c u d VGS = 0V, VDS = 0V to 480 V Parameter e t le Test Conditions td(on) tr Turn-on Delay Time Rise Time VDD = 325 V, ID = 2.1 A RG = 4.7 VGS = 10 V (Resistive Load see, Figure 3) Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 520V, ID = 4.2 A, VGS = 10V ) s ( ct SWITCHING OFF Symbol Parameter du td(off) tf Turn-off Delay Time Fall Time tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time o r P e t e l o s b O o r P Min. o s b O Test Conditions ) s t( 98 SWITCHING ON Symbol S Min. Typ. Max. 20 15 pF pF pF pF Unit ns ns 25 4.4 13.7 35 nC nC nC Typ. Max. Unit VDD = 325 V, ID = 2.1 A RG = 4.7 VGS = 10 V (Resistive Load see, Figure 3) 140 40 ns ns VDD = 520 V, ID = 4.2 A, RG = 4.7, VGS = 10V (Inductive Load see, Figure 5) 12 7 15 ns ns ns SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 5 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 4.2 A, di/dt = 100A/s VDD = 100V, Tj = 150C (see test circuit, Figure 5) trr Qrr IRRM Test Conditions Min. Typ. 375 1.76 10 Max. Unit 5 20 A A 1.6 V ns C A Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/9 STP5NK65Z Safe Operating Area Thermal Impedance Transfer Characteristics Output Characteristics e t le ) s ( ct r P e u d o Transconductance t e l o s b O 4/9 c u d o r P o s b O - Static Drain-source On Resistance ) s t( STP5NK65Z Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temp. c u d e t le ) s ( ct u d o Source-drain Diode Forward Characteristics r P e ) s t( Normalized On Resistance vs Temperature o r P o s b O - Normalized BVDSS vs Temperature t e l o s b O 5/9 STP5NK65Z Maximum Avalanche Energy vs Temperature c u d e t le ) s ( ct u d o r P e t e l o s b O 6/9 o s b O - o r P ) s t( STP5NK65Z Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit c u d e t le ) s ( ct ) s t( o r P o s b O - u d o Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times r P e t e l o s b O 7/9 STP5NK65Z TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 ) s t( G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 16.4 c u d 0.645 13.0 14.0 0.511 L5 2.65 2.95 0.104 L6 15.25 15.75 0.600 L7 6.2 6.6 0.244 L9 3.5 3.93 0.137 DIA. 3.75 3.85 0.147 0.551 e t le o s b O - o r P 0.116 0.620 0.260 0.154 0.151 u d o L2 G1 r P e G t e l o H2 D1 ) s ( ct F1 C D A L4 E L2 F2 F Dia. L5 L9 L7 L6 8/9 MAX. A D1 s b O TYP. L4 P011C STP5NK65Z c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics s b O (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 9/9