AS1710/AS1712
High-Output-Drive, 10MHz, 10V/µs, Rail-to-Rail I/O
Op Amps with Shutdown
Data Sheet
www.austriamicrosystems.com Revision 1.04 1 - 17
1 General Description
The AS1710/AS1712 are low-offset, high-output CMOS
op amps that deliver 200mA of peak output current from
a single supply (2.7 to 5.5V).
These devices were specifically designed to drive typical
headset levels (32Ω), as well as bias RF power amplifi-
ers for wireless handset applications.
The devices are available as the standard prod ucts
shown in Table 1. See also Ordering Information on
page 16.
These rail-to-rail I/O, wide-bandwidth amplifiers exhibit a
high slew rate of 10V/µs and a gain-bandwidth product
of 10MHz.
The integrated shutdown feature (not included in B ver-
sions) drives the output low.
These devices operate over the entire au tomotive tem-
perature range (-40°C to +125°C).
Figure 1. Typical Application
2 Key Features
! Constant Output Drive Capability: 50mA
! Rail-to-Rail Input and Output
! Supply Current: 1.6mA
! Single-Supply Operation: 2.7 to 5.5V
! Gain-Bandwidth Product: 10MHz
! High Slew Rate: 10V/µs
! Voltage Gain: 100dB (RLOAD = 100kΩ)
! Power-Supply Rejection Ratio: -85dB
! No Phase Reversal for Overdriven Inputs
! Unity-Gain S t able for Capacitive Loads: Up to 100pF
! Shutdow n Mode (AS1 71 0 A ) Curre nt : 1n A ty p
! Package Types:
-SC70-6
-SC70-5
- TQFN-16 3x3mm
3 Applications
The devices are ideal for portable/battery-powered
audio applications, portable headphone speaker drivers
(32Ω), hands-free mobile phone kits, TFT panels, sound
ports/cards, set-top boxes, biasing controls, DAC con-
verter buffers, transformer/line drivers, motor drivers,
and any other battery-operated audio device.
Table 1. Standard Products
Model Description Package
AS1710A Single Op Amp
with Shutdown SC70-6
AS1710B Single Op Amp SC70-5
AS1712A Quad Op Amp
w/Shutdown TQFN-16
3x3mm
VBIAS
RIN Headphone Jack
to 32Ω Stereo
Headset
CIN
+
–
AS1710
RF
RIN
CIN
RF
+
–
AS1710
COUT
+
COUT
+
Audio In
Left
Audio In
Right
www.austriamicrosystems.com Revision 1.04 2 - 17
AS1710/AS1712
Data Sheet - P i n o u t
4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top View)
Pin Descriptions
Table 2. Pin Descriptions
Pin Number Pin Name Description
See Figure 2
IN+ Non-inverting Input
IN- Inverting Input
VDD Positive Supply Input
VSS Negative Supply Input. This pin must be connected to groun d in single-supply
applications.
SHDNN Active Low Shutdown Control
OUT Amplifier Output
4OUT3IN-
2VSS
1
IN+ 5VDD
AS1710-B
SC70-5
4OUT3IN-
2VSS
1
IN+ 6VDD
AS1710-A
SC70-6 5 SHDNN
14 OUT4
15 OUT1
16 IN1-
13 IN4-
10 IN3+
11 VSS
12 IN4+
9IN3-
6SHDNN1/2
7
SHDNN3/4
8OUT3
5OUT2
3IN2+
2VDD
1IN1+
4
IN2-
AS1712-A
TQFN-16 3x3mm
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AS1710/AS1712
Data Sheet - A b s o l u te M a x im u m R a t in g s
5 Absolute Maximum Ratings
Stresses beyo n d th o s e li st ed in Table 3 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Electri cal Chara cter-
istics on page 4 is not implied. Exposure to absolute maximum rating conditions for extend ed periods may affect
device reliability.
Table 3. Absolute Maximum Ratings
Parameter Min Max Units Comments
Supply Voltage (VDD to VSS)+7V
Supply Voltage (All Other Pins) VSS
- 0.3 VDD
+ 0.3 V
Output Short-Circuit Duration to
VDD or VSS 1s
Continuous Power
Dissipation SC70-5 247 mW Derate at 31mW/ºC above 70ºC
SC70-6 245 Derate at 31mW/ºC above 70ºC
Thermal Resistance ΘJA TQFN-16
3x3mm 33 ºC/W on PCB
Operating Temperature Range -40 +125 ºC
Storage Temperature Range -65 +150 ºC
Junction Temperature +150 ºC
Package Body Temperature +260 ºC
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020C “Moisture/Reflow
Sensitivity Classification for Non-Hermetic
Solid State Surface Mount Devices”.
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
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AS1710/AS1712
Data Sheet - E l e c t ri c a l C ha r a c t e r is t i c s
6 Electrical Characteristics
DC Electrical Characteristics
VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = VDD/2, RLOAD = Infinite, VSHDNN = VDD, TAMB = -40 to +125ºC. Typical val-
ues at TAMB = 25°C.
Table 4. DC Electrical Characteristics
Symbol Parameter Condition Min Typ Max Unit
VDD Supply Voltage Range Inferred from Power Supply
Rejection Ratio Test 2.7 5.5 V
VOFFSET Input Offset Voltage -3 0.6 +3 mV
IBIAS Input Bias Current VCM = VSS to VDD 501
1. Guaranteed by design.
pA
IOFFSET Input Offset Current VCM = VSS to VDD 501pA
RIN Input Resistance 10001MΩ
VCM Common Mode In pu t
Voltage Range Inferred from Common Mode
Rejection Ratio1VSS VDD V
CMRR Common Mode
Rejection Ratio VSS < VCM < VDD -45 -70 dB
PSRR Power Supply Rejection Ratio VDD = 2.7 to 5.5V -70 -85 dB
ROUT Shutdown Output Impedance VSHDNN = 0V (A-Versions) 1301Ω
VOUT-SHDNN Shutdown Output Voltage VSHDNN = 0V, RLOAD = 2kΩ to VDD
(A-Versions) 170 300 mV
AVOL Large Signal Voltage Gain VSS + 0.20V < VOUT <
VDD - 0.20V
RLOAD = 100kΩ85 100 dBRLOAD = 2kΩ79 92
RLOAD = 200Ω69 80
VOUT Output Voltage Swing VDD - VOH or
VOL - VSS
RLOAD = 32Ω350 650 mVRLOAD = 200Ω70 120
RLOAD = 2kΩ920
Output V oltage VDD - VOH or
VOL - VSS
ILOAD = 10mA,
VDD = 2.7V 55 100 mV
ILOAD = 30mA,
VDD = 5V 100 180
IOUT Output Source/Sink Current
VDD = 2.7V,
V- = VCM, V+ = VCM±100mV 100 mA
VDD = 5.0V,
V- = VCM, V+ = VCM±100mV 200
IDD Quiescent Supply Current per
OpAmp Output VDD = 2.7V, VCM = VDD/2 1.6 3.2 mA
VDD = 5.0V, VCM = VDD/2 2.3 4.6
IDD-SHDNN Shutdown Supply Current
per OpAmp (A-Versions) VSHDNN = 0V VDD = 2.7V 1 20001nA
SHDNN Logic Threshold
(A-Versions)
Shutdown Mode VSS +
0.3 V
Normal Operation VDD -
0.3
SHDNN Input Bias Current VSS < VSHDNN < VDD (A-Versions) 501pA
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AS1710/AS1712
Data Sheet - E l e c t ri c a l C ha r a c t e r is t i c s
AC Electrical Characteristics
VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = VDD/2, RLOAD = Infinite, VSHDNN = VDD, TAMB = -40 to +125ºC. Typical val-
ues at TAMB = 25°C.
Table 5. AC Electrical Characteri stics
Symbol Parameter Conditions Min Typ Max Units
GBWP Gain-Bandwidth Product VCM = VDD/2 10 MHz
FPBW Full-Power Bandwidth VOUT = 2VP-P, VDD = 5V 2.5 MHz
SR Slew Rate 10 V/µs
PM Phase Margin 70 deg
GM Gain Margin 115 dB
THD+N Total Harmonic Distortion
Plus Noise f = 10kHz, VOUT = 2VP-P, AVCL = 1V/V 0.05 %
CIN Input Capacitance 6 pF
en Voltage-Noise Density1
1. Guaranteed by design.
f = 1kHz 15 nV/
√Hz
f = 10kHz 10
Capacitive-Load Stability AVCL = 1V/V, no sustained oscillations 100 pF
tSHDN Shutdown Time
(AS1710A) 1 µs
tENABLE Enable Time from Shutdown
(AS1710A) 7µs
tON Power-Up T ime 20 ns
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AS1710/AS1712
Data Sheet - Ty p i c a l O p e r a ti n g C h a ra c t e r i s ti c s
7 Typical Operating Characteristics
VDD = 2.7V; VSS = 0V, VCM = VDD/2, VOUT = VDD/2, RLOAD = ∞, VSHDNN = VDD TAMB = +25ºC (unless otherwise spec-
ified).
Figure 3. Gain and Phase vs. Frequency Figure 4. Gain and Phase vs. Frequency, CLOAD = 100pF
Figure 5. PSRR vs. Frequency Figure 6. CMRR vs. Frequency
Figure 7. Supply Current vs. Temperat ure Figure 8. Shutdo w n Cur r en t vs. Temperature
-40
-20
0
20
40
60
80
100
120
0.001 0.1 10 1000 100000
F r equenc y (k Hz)
Gain (dB) .
0
40
80
120
160
200
240
280
320
P hase (deg)
-40
-20
0
20
40
60
80
100
120
0.001 0.1 10 1000 100000
F r equenc y (k Hz)
Gain (dB) .
0
40
80
120
160
200
240
280
320
P hase (deg)
Gain
Phase
Gain
Phase
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.001 0.1 10 1000
F r equenc y (k Hz)
CM RR ( dB ) .
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.001 0.1 10 1000
F r equenc y (k Hz)
PSRR ( dB ) .
PSRR pos
PSRR neg
CMRR
0
0.5
1
1.5
2
2.5
3
3.5
4
-45 -20 5 30 55 80 105 130
Temperatur e ( ° C)
Supply Cur r ent (m A ) .
5V
2.7V
0.1
1
10
100
1000
-45 -20 5 30 55 80 105 130
T emperature (° C)
S hut down Cur r ent ( nA ) .
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AS1710/AS1712
Data Sheet - Ty p i c a l O p e r a ti n g C h a ra c t e r i s ti c s
Figure 9. Supply Current vs. Common-Mo de Voltage Figure 10. Input Voltage Noise vs. Freque ncy
Figure 11. Ou tput Voltage vs. Output Current, sourcing Figure 12. Output Voltage vs. Output Current, sinking
Figure 13. Output Swing High vs. Temperature Figure 14. Output Swing Low vs. Temperature
0
0.5
1
1.5
2
2.5
3
012345
Common-Mode Volt age ( V)
Supply Cur r ent (m A ) .
2.7V
5V
1
10
100
1000
0.001 0.1 10 1000
Fr equenc y (k Hz)
Input Voltage Nois e ( nV /Hz) .
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 50 100 150 200 250
O utput Cur rent (mA)
O utput V olt age ( V ) .
2.7V
5V
t<1s
t>10s
t>10s
t<1s
0
0.25
0.5
0.75
1
1.25
1.5
1.75
0 50 100 150 200
Output Current (mA)
O utput V olt age ( V ) .
2.7V
5V
t>10s
t<1s
t>10s
t<1s
40
50
60
70
80
90
100
-45 -20 5 30 55 80 105 130
Temperatur e ( ° C)
VOUT - VSS (mV) .
40
50
60
70
80
90
100
-45 -20 5 30 55 80 105 130
Temperatur e ( ° C)
VOUT - VSS (mV) .
10mA
200Ω
10mA
200Ω
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AS1710/AS1712
Data Sheet - Ty p i c a l O p e r a ti n g C h a ra c t e r i s ti c s
Figure 15. Tran sient Response, 100mV, 10pF load Figure 16. Transient Response, 100mV, 100pF load
Figure 17. Transient Response, 1V, 10pF load Figure 18. Transient Response, 1V, 100pF load
Figure 19. Transient Response, 2V, 10pF load Figure 20. Transient Response, 2V, 100pF load
500ns/Div
OUT
50mV/DIV
IN
500ns/Div
OUT
50mV/DIV
IN
500ns/Div
OUT
500mV/DIV
IN
500ns/Div
OUT
500mV/DIV
IN
500ns/Div
OUT
1V/DIV
IN
500ns/Div
OUT
1V/DIV
IN
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AS1710/AS1712
Data Sheet - A p p l ic a t i o n In f o r m a t io n
8 Application Information
Package Power Dissipation
Caution: Due to the high output current drive, this op amp can exceed the absolute maximum power-dissipation rat-
ing. Normally, when peak current is less than or equal to 40mA the maximum package power dissipation is
not exceeded for any of the package types offered.
The absolute maximum power-dissipation rating of each package should always be verified. (EQ 1) gives an approxi-
mation of the package power dissipation:
PPACKAGEDISS
≅
VRMS IRMS COS
θ
(EQ 1)
Where:
VRMS is the RMS voltage from VDD to VOUT when sourcing current, and from VOUT to VSS when sinking current.
IRMS is the RMS current flowing in or out of the op amp and the load.
θ is the phase difference between the voltage and the current. For resistive loads, COSθ = 1.
Figure 21. Typical AS1710/AS1712 Single-Supply Appli c ation
VRMS can be calculated as:
VRMS
≅
(VDD - VDC) + VPEAK /
√
2(EQ 2)
Where:
VDC is the DC component of the output voltage.
VPEAK is the highest positive excursion of the AC component of the output voltage.
For the circuit shown in Figure 21:
VRMS = (3.6V - 1.8V) + 1.0V/√2 = 2.507VRMS
IRMS can be calculated as:
IRMS
≅
IDC + (IPEAK/
√
2) (EQ 3)
Where:
IDC is the DC compone nt of th e ou tp u t current.
IPEAK is the highest positive excursion of the AC component of the output current.
For the circuit shown in Figure 21:
IRMS = (1.8V/32Ω) + (1.0V/32Ω)/
√
2 = 78.4mARMS
Therefore, for the circuit in Figure 21 the package power dissipation can be calculated as:
PPACKAGEDISS = VRMS IRMS COSθ = 196mW
Adding a coupling capacitor improves the package power dissipation because there is no DC current to the load, as
shown in Figure 22 on page 10.
VIN = 2VP-P
R
+
–
RAS1710
32Ω
C
3.6V
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AS1710/AS1712
Data Sheet - A p p l ic a t i o n In f o r m a t io n
60mW Single-Supply Stereo Headphone Driver
Two AS1710 amplifiers can be used as a single-supply, stereo headphone driver . The circuit shown in Figure 22 can
deliver 60mW per channel with 1% distortion from a single 5V supply.
Figure 22. Stereo Headphone Driver Application (with Coupling Capacitor)
In Figure 22, CIN and RIN form a high-pass filter that removes the DC bias from the incoming signal. The -3dB point of
the high-pass filter is given by:
f-3dB = 1/(2
π
RINCIN)(EQ 4)
Choose gain-setting resistors RIN and RF according to the amount of desired gain, keeping in mind the maximum out-
put amplitude.
COUT blocks the DC component of the amplifier output, preventing DC current flowing to the load. The output capacitor
and the load impedance form a high-pass filter with the -3dB point determined by:
f-3dB = 1/(2
π
RLOADCOUT)(EQ 5)
For a 32Ω load, a 100µF aluminum electrolytic capacitor gives a low-frequency pole at 50Hz.
Rail-to-Rail Input Stage
The AS1710/AS1712 CMOS op amps have parallel connected N- and P-channel differential input stages that combine
to accept a common-mode range extending to both supply rails. The N-channel stage is active for common-mode input
voltages typically greater than (VSS + 1.2V), and the p-channel stage is active for common-mode input voltages typi-
cally less than (VDD - 1.2V).
Rail-to-Rail Output Stage
The minimum output is within millivolts of ground for single- supply operation, where the load is referenced to ground
(VSS). Figure 23 shows the input voltage range and the output voltage swing of an AS1710 connected as a voltage fol-
lower. The maximum output voltage swing is load dependent although it is guaranteed to be within 50 0mV of th e posi-
tive rail (VDD = 2.7V) even with maximum load (32Ω to ground).
VBIAS
RIN Headphone Jack
to 32Ω Stereo
Headset
CIN
+
–
AS1710
RF
RIN
CIN
RF
+
–
AS1710
COUT
+
COUT
+
Audio In
Left
Audio In
Right
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AS1710/AS1712
Data Sheet - A p p l ic a t i o n In f o r m a t io n
Figure 23. Rail-to-Rail Inpu t/Output Range, 100kΩFigure 24. Rail-to-Rail Input/Output Range, 32Ω
Note: The absolute maximum ratings (see page 3) for power dissipation and output short-circuit duration (10s, max)
must be adhered to since the output current can exceed 200mA (se e Typical Operating Chara c teristics on
page 6).
Input Capacitance
The parallel-connected differential input stages for rail-to-rail operation results in relatively large input capacitance CIN
(6pF typ). This introduces a pole at frequency (2πR′CIN)-1, where R′ is the parallel combination of the gain-setting
resistors for the inverting or non-inverting amplifier configuration (Figure 25). If the pole frequency is less than or com-
parable to the unity-gain bandwidth (10MHz), the phase margin is reduced, and the amplifier exhibits degraded AC
performance through either ringing in the step response or sustained oscillations.
Figure 25. Inverting and Non-inverting Amplifiers with Feedback Compensation
The pole frequency is 10MHz when R′ = 2kΩ. To maximize stability, R′ << 2kΩ is recommended.
To improve step response when R′ > 2kΩ, connect a small capacitor (CF) between the inverting input and output. CF
can be calculated by: CF = 6(R/RF) [pf] (EQ 6)
Where:
RF is the feedback resistor.
R is the gain-setting resistor.
2.5µs/Div
OUT
1V/DIV
IN
2.5µs/Div
OUT
1V/DIV
IN
VCC = 3.0V,
RLOAD = 32Ω
VCC = 3.0V,
RLOAD = 100kΩ
VIN
RF
–
+
AS1710
CF
VOUT
R
R′ = R II RF
RFCF = RCIN
Inverting
VIN
RF
–
+
AS1710
CF
VOUT
R
Non-Inverting
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AS1710/AS1712
Data Sheet - A p p l ic a t i o n In f o r m a t io n
Driving Capacitive Loads
The AS1710/AS1712 amplifiers have a hig h tolerance for capacitive loads, and are stable with capacitive loads up to
100pF.
Figure 26 shows a typical non-inverting capacitive-load driving circuit in the unity-gain configuration.
Figure 26. Capacitive-Load Driving Circuit
Note: Resistor RISO improves the circuit’s phase margin by isolating the load capacitor from the AS1710/AS1712 out-
put.
Power-Up
The AS1710/AS1712 typically settle within 5µs after power-up.
Shutdown
When SHDNN (not included in B versions) is pulled low, supply current drops to 0.5µA (per amplifier , VDD = 2.7V), the
amplifiers are disabled, and their outputs are driven to VSS. Because the outputs ar e actively driven to VSS in shut-
down, any pullup resistor on the output causes a current drain from the supply.
Note: Pulling SHDNN high enables the amplifier. In the AS1712 the amplifiers shutdown in pairs.
When exiting shutdown, there is a 6µs delay before the amplifier output becomes active.
Power Supplies and Layout
The AS1710/AS1712 can operate from a single 2.7 to 5.5V supply or from dual ±1.35 to ±2.5V supplies. Good design
improves device performance by decreasing the amount of stray capacitance at the op amp inputs/outputs.
! For single-supply operation, bypass the power supply with a 0.1µF ceramic capacitor.
! For dual-supply operation, bypass each supply to ground.
! Decrease stray capacitance by placing external components close to the op amp pins, minimizing trace and lead
lengths.
RISO
–
+
AS1710
CF
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AS1710/AS1712
Data Sheet - P a c k age Drawings and Markings
9 Package Drawings and Markings
Figure 27. SC70-5 Package
Symbol Min Max
e 0.65BSC
D1.802.20
b0.150.30
E1.151.35
HE 1.80 2.40
Q1 0.10 0.40
A2 0.80 1.00
A1 0.00 0.10
A0.801.10
c0.100.18
L0.100.30
Lj 0.26 0.46
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating.
3. Dimensions are exclusive of mold flash and metal burr.
4. All specifications comply with JEITA SC88A and JEDEC
MO203.
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AS1710/AS1712
Data Sheet - P a c k age Drawings and Markings
Figure 28. SC70-6 Package
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating.
3. Dimensions are exclusive of mold flash and metal burr.
4. All specifications comply with JEITA SC88 and JEDEC
MO203.
Symbol Min Max
e 0.65BSC
D1.802.20
b0.150.30
E1.151.35
HE 1.80 2.40
Q1 0.10 0.40
A2 0.80 1.00
A1 0.00 0.10
A0.801.10
c0.100.18
L0.100.30
Lj 0.26 0.46
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AS1710/AS1712
Data Sheet - P a c k age Drawings and Markings
Figure 29. TQFN-16 3x3mm Package
Notes:
1. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
2. All dimensions are in millimeters while angle is in degrees (°).
3. N is the total number of terminals.
4. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC 95, SPP-002. Details of
terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1 identifier may
be either a mold or marked feature.
5. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal
tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be mea-
sured in that radius area.
6. Depopulation is possible in a symmetrical fashion.
7. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal
tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be mea-
sured in that radius area.
8. ND and NE refer to the number of terminals on side s D and E respectively.
-C-
A3
A1
SIDE VIEW
PLANE
A
ccc C
0.08 C
NX SEATING
D
D/2
INDEX AREA
E
aaa C
aaa C
TOP VIEW
2x
2x
4
(D/2 xE/2)
E/2
-B-
-A-
NXL
e
NXb
D2/2
D2
E2/2
2
1
E2
bbb C A B
ddd C
-B-
-A-
NN-1
BTM VIEW
65
(D/2 xE/2)
INDEX AREA
4
SEE
DETAIL B
SEE
DETAIL B
Datum A or B
ODD TERMINAL SIDE Terminal T ip
e
L1
5
Symbol Min Typ Max Notes
L1 0.03 0.15 1, 2
D BSC 3.00 1, 2, 8
E BSC 3.00 1, 2, 8
D2 1.30 1.45 1.55 1, 2, 8
E2 1.30 1.45 1.55 1, 2, 8
L 0.30 0.40 0.50 1, 2, 8
N161, 2, 8
ND 4 1, 2, 8
NE 4
Symbol Min Typ Max Notes
aaa 0.15 1, 2
bbb 0.10 1, 2
ccc 0.10 1, 2
ddd 0.05 1, 2
b 0.18 0.25 0.30 1, 2
A 0.70 0.75 0.80 1, 2
A1 0.00 0.02 0.05 1, 2
A3 0.20REF 1, 2
e0.50
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AS1710/AS1712
Data Sheet
10 Ordering Information
The device is available as the standard products shown in Table 6.
Table 6. Ordering Information
Model Description Delivery Form Package
AS1710A-ASCT Single Op Amp with Shutdown Tape and Reel SC70-6
AS1710B-ASCT Single Op Amp Tape and Reel SC70-5
AS1712A-AQFT Quad Op Amp with Shutdown Tape and Reel TQFN-16 3x3 mm
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AS1710/AS1712
Data Sheet - O r d e r in g I n f or m a t i o n
Copyrights
Copyright © 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reprodu ced, adapted, merged, trans-
lated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, st atutory, implied, or by description regarding
the information set forth herein or regardi ng th e fre e do m of the described devices from patent infringement. austriami-
crosystems AG reserves the right to change specifications and prices at any time and withou t notice. Therefore, prior
to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information.
This product is intended for use in normal commercial applications. Applicati ons requiring extended temperature
range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-
sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for
each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, speci al, incide ntal or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech-
nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Cont act Information
Headquarters
austriamicrosystems AG
A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
