Qualcomm Atheros, Inc. QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification 80-Y7545-6 Rev. D January 7, 2015 (c) 2014-2015 Qualcomm Atheros, Inc. All rights reserved. Qualcomm Atheros, Inc. ("QCA") and its affiliates reserve the right to make any updates, corrections and any other modifications to its documentation. The information provided in this document represents QCA's knowledge and belief as of the date this document is provided. QCA makes no representation or warranty as to the accuracy of such information, and QCA assumes no liability for any use of the information in this documentation. You should obtain the latest information before placing orders for any hardware, and you should verify that such information is current and complete. Information published by QCA regarding any third-party products does not constitute a license to use such products or a warranty or endorsement thereof. Use of such information may require a license from a third party under the intellectual property rights of such third party, or a license from QCA or its affiliates under the intellectual property rights of QCA or its affiliates. All hardware, equipment, components or products are sold subject to QCA's (or QCA's affiliated company Qualcomm Atheros Technology Ltd., a Bermuda corporation, or such other QCA affiliated company that is designated by QCA) standard terms and conditions of sale, as applicable. Notwithstanding anything to the contrary in this documentation or otherwise: (i) you do not receive any rights, licenses, or immunities from suit under any patents of QUALCOMM Incorporated, QCA or their respective affiliates as a result of receiving this documentation (whether expressly, impliedly, by virtue of estoppel or exhaustion, or otherwise), (ii) without limitation, you shall not use or sell any wireless wide area network ("WWAN") baseband integrated circuit that you purchase or acquire from QCA or any product that incorporates any such WWAN baseband integrated circuit (whether alone or in combination with any other software or components) without a separate license or nonassertion covenant from QUALCOMM Incorporated in respect of or under all applicable patents, (iii) nothing in this document modifies or abrogates your obligations under any license or other agreement between you and QUALCOMM Incorporated, including without limitation any obligation to pay any royalties, and (iv) you will not contend that you have obtained any right, license, or immunity from suit with respect to any patents of QUALCOMM Incorporated, QCA or their respective affiliates under or as a result of receiving this documentation (whether expressly, impliedly, by virtue of estoppel or exhaustion, or otherwise). Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other countries. All Qualcomm Incorporated trademarks are used with permission. Other product and brand names may be trademarks or registered trademarks of their respective owners. This technical data may be subject to U.S. and international export, re-export, or transfer ("export") laws. Diversion contrary to U.S. and international law is strictly prohibited. Qualcomm Atheros, Inc. 1700 Technology Drive San Jose, CA 95110 U.S.A. Revision history Revision Date A April 2014 B September 2014 Description Initial release. For regular distribution as part of PDK. 80-Y7545-6 Rev. D Global change: Converted the data sheet to device specification. The content movings below are not marked with change bar. Moved functional description to Section 1.5 through Section 1.15. Moved voltage regulator and bootstrap mode to Section 1.16 and Section 1.17. Moved package dimensions, ordering information, and thermal characteristics to Chapter 4. Moved power sequence to Section 3.3 and clock/timing to Section 3.5. Section 1.1, Section 1.4: Added document overview and special marks. Section 1.15: Added DNS, SNTP, bridging/routing, and raw socket support. Chapter 4: Added the Mechanical information chapter. Section 4.1: Updated the package drawing and dimensions according to NT90-Y5242-1. Section 4.3: Updated ordering number for chip revision B. Chapter 5: Added Carrier, Storage, and Handling Information. Chapter 6: Added PCB Mounting Guidelines. Chapter 7: Added chip reliability data. C October 2014 Table 3-2: Corrected the chip case temperature for industrial part. D January 2015 Cover page: Replaced the cover with new branding and legal statements. Table 3-1: Deleted legacy ESD-HBM, ESD-CDM, ESD-CDM-RF rows. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 3 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 80-Y7545-6 Rev. D Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 QCA4004 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Product features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Special marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Integrated network processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reset and startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.7.1 Wakeup manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.7.2 Detailed SPI slave startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.7.3 Power management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.8.1 Sleep state management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.8.2 Hardware power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 System clocking (RTC block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.9.1 High speed clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.9.2 Low-speed clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.9.3 Interface clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.9.4 Wakeup manager clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MAC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Baseband block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Active power save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.12.1 Low Power Listen (LPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.12.2 Green Tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IPv4/IPv6 networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Internal voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.14.1 Switching 1.2 V regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.14.2 Linear 1.2 V regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bootstrap modes and pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.15.1 Internal bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.15.2 Host mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.15.3 Crystal value configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.15.4 1.2 V regulator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.15.5 1.8 V regulator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 4 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification 2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1 3 5.2 5.3 5.4 6.3 29 30 31 31 31 Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Matrix tray information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Bag storage conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Out of bag duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Baking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Barcode label and packing for shipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 32 33 34 34 34 34 34 34 35 RoHS compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMT parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Land pad and stencil design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 SMT peak package-body temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.4 SMT process verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board-level reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 36 37 38 38 38 Part Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 7.2 80-Y7545-6 Rev. D Device physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Part marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device moisture-sensitivity level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB Mounting Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 6.2 7 24 25 25 26 26 26 27 28 Carrier, Storage, and Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital logic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 External reference clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 SPI slave interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 SPI master interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 4.2 4.3 4.4 4.5 5 I/O parameter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 3.2 3.3 3.4 3.5 4 Contents Reliability qualifications summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Qualification sample description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 5 1 Introduction 1.1 Document overview Technical information for the QCA4004 is primarily covered by the documents listed in Table 1-1. Each is a self-contained document, but a thorough understanding of the device and its applications requires familiarization with all of them. The device description in is a good place to start. Table 1-1 Primary QCA4004 documentation Document No. 80-Y7545-6 (this document) Title/Description QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Conveys all QCA4004 IC electrical and mechanical specifications. Additional material includes pin assignments; shipping, storage, and handling instructions; PCB mounting guidelines; and part reliability. This document can be used by company purchasing departments to facilitate procurement. The QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification is organized as follows: 80-Y7545-6 Rev. D Chapter 1 Gives a high-level functional description of the device, lists the device features, and defines marking conventions, terms, and acronyms used throughout this document. Chapter 2 Defines the device pin assignments. Chapter 3 Defines the device electrical characteristics, including absolute maximum ratings and recommended operating conditions. Chapter 4 Provides IC mechanical information, including dimensions, markings, ordering information, moisture sensitivity, and thermal characteristics. Chapter 5 Describes carrier, storage and handing information of the QCA4004 device. Chapter 6 Presents procedures and specifications for mounting the QCA4004 device onto printed circuit boards (PCBs). Chapter 7 Presents the QCA4004 device reliability data, including a definition of the qualification samples and a summary of qualification test results. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 6 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Introduction 1.2 QCA4004 device description The QCA4004 is an intelligent platform for the Internet of Everything that contains a low-power Wi-Fi connectivity solution on a single chip. It includes a number of TCP/IP-based connectivity protocols along with SSL, enabling a low-cost, low-complexity system to obtain full-featured internet connectivity and reliable information exchange. The QCA4004 provides two interfaces for connecting to local system controllers. A UART-based host interface can be used for rapid development and deployment of simple data streams between the local device and the internet cloud. An SPI slave interface is available for applications that require more advanced connectivity to the network. The QCA4004 Wi-Fi link is a full-featured, dual-band, single stream 802.11n solution. The Wi-Fi link is highly integrated, and includes an energy efficient on-board power amplifier and LNA. For the 2.4 GHz band, RF switches are also integrated. The QCA4004 Wi-Fi link is optimized for low system cost, and minimizes the number and cost of any components required to achieve a reliable Wi-Fi link. 1.3 Product features Wi-Fi link Support for IEEE 802.11a/b/g/n Single stream 1 x 1 Dual-band 2.4 GHz/5 GHz Integrated PA, LNA, with support for external PA and external LNA Single or dual Rx front end for antenna diversity Green Tx power saving mode Low power listen mode Data rates up to 150 Mbps Full security support: WPS, WPA, WPA2, WAPI, WEP, TKIP System cost optimization 80-Y7545-6 Rev. D Highly-Integrated Wi-Fi solution that requires only a single crystal, antenna, and antenna matching components to complete the RF link. Integrated IPv4/IPv6 TCP/IP stack Integrated Network services such as HTTP, DNS, FTP 8 mm x 8 mm, 68-pin QFN package QCA4004 patch firmware is stored and automatically loaded from a low cost serial flash memory MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 7 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Introduction Manufacturing interface USB 2.0 device interface, providing a simplified, high-speed, and scalable manufacturing test and configuration interface for QCA4004-based systems Host interfaces SPI slave interface Allows for simplified connection to local host microcontrollers. Host driver source code and programming APIs are available. UART/SPI host interface allows simple interfacing to microcontrollers. UART with an AT style command set Wakeup manager Non-volatile 8 KB RAM Suspend/resume timer 2.4/5 GHz RF Front End OR RF Front End 802.11n WLAN MAC/BB/ Radio OTP CPU OnChip ROM OnChip RAM Host/ Manufacturing Interface Block GPIO/ Peripherals UART USB 2.0 SPI HighSpeed UART UART JTAG GPIOs 2 x I2S, I2C Wakeup Manager SPI Flash Memory Figure 1-1 QCA4004 functional block diagram 1.4 Special marks Table 1-2 defines special marks used in this document. Table 1-2 Mark 80-Y7545-6 Rev. D Special marks Definition [] Brackets ([ ]) sometimes follow a pin, register, or bit name. These brackets enclose a range of numbers. For example, SDC1_DATA[7:4] may indicate a range that is 4 bits in length, or DATA[7:0] may refer to all eight DATA pins. _N A suffix of _N indicates an active low signal. For example, RESIN_N. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 8 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Table 1-2 Introduction Special marks Mark Definition 0x000 Hexadecimal numbers are identified with an x in the number (for example, 0x0000). All numbers are decimal (base 10) unless otherwise specified. Non-obvious binary numbers have the term binary enclosed in parentheses at the end of the number; for example, 0011 (binary). | A blue vertical bar in the outside margin of a page indicates that a change was made since the previous revision of this document. 1.5 Integrated network processor The QCA4004 includes a network processor that provides IP services and manages Wi-Fi link operations. The network processor code is loaded automatically from ROM off-chip serial flash memory. The flash memory is also used to store system configuration and persistent data sets. The network processor is optimized for energy efficient communications and includes multiple power states (see Section 1.8). Customers can use the integrated network processor to implement application-specific solutions. This customized code is stored on an off-chip serial flash. 1.6 Serial interface The QCA4004 includes two high-speed Universal Asynchronous Receiver/Transmitter (UART) interfaces, which may be configured to serve as either a host interface link or a debug message console. 1.7 Reset and startup sequence The QCA4004 CHIP_PWD_L pin can be used to completely reset the entire chip. After this signal has been de-asserted, if configured for SPI slave operation, the QCA4004 waits in a low-power state until communication from the host, indicating that the Wi-Fi and the network services should be started. When configured for UART host mode, the QCA4004 begins its boot up process and starts network services as soon as CHIP_PWD_L is de-asserted. 1.7.1 Wakeup manager The wakeup manager enables use of the QCA4004 in low power environments with no external host CPU. To achieve the lowest average power profile, the QCA4004 must be placed in suspend mode for the majority of the time. While in suspend state, the QCA4004 shuts down all circuits except a few critical blocks needed to resume operation after suspend; these include I/O pads to detect a wakeup request, a sleep timer to detect a synchronous wakeup event, and a small RAM that stores state information spanning a suspend-resume cycle. To enter SUSPEND state, QCA4004 firmware saves state in the on-chip non-volatile RAM (NVRAM) and configures wakeup timers. Firmware then triggers the suspend operation, which turns on isolation circuits and turns off voltage regulators to the QCA4004 main core block. 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 9 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Introduction Only the wakeup manager block and PMU circuits remain powered in suspend mode. When a wakeup event is detected, the device exits suspend back to active state. Wakeup events include synchronous wakeup, which occurs when the sleep timer in the wakeup manager expires, and asynchronous wakeup, which occurs when a pin event is detected on the wakeup pin. Power on Reset = 0 Reset Power on Reset = 1 Bootstrap Latch Delay Suspend Suspend Request = 1 Suspend Request = 1 Cold Boot = 1 Timer Wakeup Event = 1 WAKEUP_L = 1 (pin 27) Delay Core Ready CHIP_PWD_L = 1 (pin 14) LPO Clock Ready = 1 Wait for Power Down Core Power Ready = 1 Host FN Disable Wait for Power Down Request * Host Off Sleep PWRDWN_OUT_L = 1 (pin 26) Host FN Enable Sleep Criteria XTAL Off LPO CLK Enable is Controlled by CHIP_PWD_L Wakeup Clocks Gated Wait for Power Up XTAL_SETTLE Active * On * Isolation Buffers Open Figure 1-2 1.7.2 Wakeup manager Detailed SPI slave startup sequence After a COLD_RESET event (e.g., the host toggles CHIP_PWD_L), the QCA4004 enters the HOST_OFF state and awaits communication from the host indicating that Wi-Fi and network services should be started. When configured for UART host mode, the QCA4004 begins its boot up process and starts network services as soon as CHIP_PWD_L pin is de-asserted. 80-Y7545-6 Rev. D When the host is ready to use the QCA4004, it initiates communication via SPI slave and enables network services by writing to a specific register via the SPI slave interface. When the QCA4004 enters the WAKEUP state for some duration and transits to the ON state, the on-chip network processor configures the QCA4004 functions and interfaces, as per the configuration and customization data set provided by the serial flash memory. When the QCA4004 is ready to receive commands from the host, it sets a specific flag that is accessible from the Host CPU via the SPI slave interface. The host reads the ready bit and can now send function commands to the QCA4004. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 10 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification 1.7.3 Introduction Power management unit The QCA4004 has an integrated power management unit (PMU) that generates all the power supplies required by its internal circuitry either from an external battery or a 3.3 V supply. The main components of the PMU include: A switching regulator (SWREG) that produces a 1.2 V supply from the 3.3 V supply. A linear regulator (SREG) which converts the host I/O supply to a 1.2 V supply for some small control blocks which are turned on when CHIP_PWD_L is de-asserted. A linear regulator which produces a 1.2 V supply from a 3.3 V supply (can be used instead of the SWREG to reduce the BOM cost). 1.8 Power transition The QCA4004 provides integrated power management and control functions and extremely low power operation for maximum battery life across all operational states by: 1.8.1 Gating clocks for logic when not needed Shutting down unneeded high speed clock sources Reducing voltage levels to specific blocks in some states Sleep state management SLEEP state minimizes power consumption while network services are not required, yet the system must remain ready for use within a short time. In SLEEP state, all high speed clocks are gated off and the external reference clock source is powered off. The network processor and Wi-Fi link are also suspended and not operational. All state information in the network processor (and its memory) and the Wi-Fi link are preserved to allow a fast resume to full network services. The system remains in sleep state until a wakeup event causes the system to enter the WAKEUP state. Once WAKEUP state is entered, the QCA4004 restores all voltage levels and clocks, then automatically moves to the ON state. This wakeup event can be either a pin event or internal timer based event. The pin event may be triggered by the host CPU, or some system level event. 1.8.2 Hardware power states Table 1-3 describes the top level hardware power states in the QCA4004. Table 1-3 Power management states State Description POWER_ DOWN CHIP_PWD_L pin assertion immediately brings the chip to this state. Sleep clock is disabled. No state is preserved. SUSPEND 80-Y7545-6 Rev. D While in suspend state, the chip shuts down all circuits except a few critical blocks needed to resume operation after suspend. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 11 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Table 1-3 Introduction Power management states State Description HOST_OFF Network services and WLAN are off. Only the SPI host interface is powered on, the rest of the chip is power gated (off). The host can transition QCA4004 to WAKEUP (followed by ON) at any time by writing a register in the host interface domain. WLAN and CPU states are not retained. For UART hosted, or USB manufacturing configurations, this state is bypassed by pulling GPIO0 low at the de-assertion of CHIP_PWD_L. This state applies only to SPI designs. SLEEP Only the sleep clock is operating. The crystal or oscillator is disabled. Any wakeup events (MAC, host, LF timer, GPIO interrupt force a transition to WAKEUP. All internal states are maintained. Host interface is idle (USB is in SUSPEND). WAKEUP The system transition from sleep OFF states to ON. The high frequency clock is gated off as the oscillator is brought up and the PLL is enabled. WAKEUP duration is less than 2 ms. ON The high speed clock is operational. Lower-level clock gating is implemented at the block level, including the CPU, which can be gated off using WAITI instructions while the system is on. Figure 1-3 depicts the USB and UART power state transition diagrams. CHIP_PWD_L POWER_DOWN ~CHIP_PWD_L Sleep XTAL Off WAKEUP Events Sleep Criteria Wakeup Clocks Gated XTAL_SETTLE On Figure 1-3 QCA4004 Power State: USB and UART Host Modes or Hostless Systems 1.9 System clocking (RTC block) The QCA4004 has an RTC block which controls the clocks and power going to other internal modules. Its inputs consist of sleep requests from these modules and its outputs consist of clock enable and power signals which are used to gate the clocks going to these modules. The RTC block also manages resets going to other modules with the device. The QCA4004's clocking is grouped into two types: 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 12 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification 1.9.1 High-speed Low-speed Introduction High speed clocking The reference clock source drives the PLL and RF synthesizer within the QCA4004. It can be either an external crystal or oscillator. To minimize power consumption, the reference clock source is powered off in SLEEP, HOST_OFF, POWER_DOWN and after HOST_OFF states. For an external crystal, the QCA4004 disables the on-chip oscillator driver. For an external oscillator, the QCA4004 de-asserts its CLK_REQ signal to indicate that a reference clock is not needed. When exiting SLEEP state, the QCA4004 waits in WAKEUP state for a programmable duration. During this time, the CLK_REQ signal is asserted to allow for the reference clock source to settle. The CLK_REQ signal remains asserted in ON state. The QCA4004 supports reference clock sharing in all power states. For an external crystal, the onchip oscillator driver drives a reference clock output whenever an external clock request signal is asserted. For an external oscillator, the external clock request signal is forwarded on the CLK_ REQ signal, and the input clock is passed along to the reference clock output. 1.9.2 Low-speed clocking The QCA4004 has eliminated the need for an external sleep clock source thereby reducing system cost. Instead, an internal ring oscillator is used to generate a low frequency sleep clock. It is also used to run the state machines and counters related to low power states. The QCA4004 has an internal calibration module which produces a 32.768 KHz output with minimal variation. For this, it uses the reference clock source as the golden clock. As a result, the calibration module adjusts for process and temperature variations in the ring oscillator when the system is in ON state. 1.9.3 Interface clock The host interface clock represents another clock domain for the QCA4004. This clock comes from the host and is completely independent from the other internal clocks. It drives the host interface logic as well as certain registers which can be accessed by the host in HOST_OFF and SLEEP states. 1.9.4 Wakeup manager clock The QCA4004 includes a dedicated always-on clock oscillator. In the SUSPEND state, this clock oscillator is the only clock that continues to run. This clock is used to calculate the resume from SUSPEND time interval. The QCA4004 has an option for using an external 32-KHz oscillator instead of the onboard low-power oscillator. 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 13 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Introduction 1.10 MAC block The QCA4004 Wireless MAC consists of these major blocks: Host interface unit (HIU) for bridging to the AHB for bulk data accesses and APB for register accesses 10 queue control units (QCU) for transferring Tx data 10 DCF control units (DCU) for managing channel access Protocol control unit (PCU) for interfacing to baseband DMA receive unit (DRU) for transferring Rx data Supports Rx diversity 1.11 Baseband block The QCA4004 baseband (BB) module is the physical layer controller for the 1x1 802.11a/b/g/n air interface. It is responsible for modulating data packets in the transmit direction, and detecting and demodulating data packets in the receive direction. It has a direct control interface to the radio to enable hardware to adjust analog gains and modes dynamically. 1.12 Active power save 1.12.1 Low Power Listen (LPL) To minimize active current consumption, the QCA4004 firmware will set the receiver in a low power listen mode, thus saving active power in between frames, when the transceiver is awaiting frames, as well as during active reception. It can be enabled in most conditions with minimal performance impact, between 1 and 2 dB. If harsh channel conditions require it, firmware will automatically revert to full power mode. 1.12.2 Green Tx To minimize active current consumption during transmission, the QCA4004 will utilize Green Tx. This feature allows the device to save power when communicating with a nearby station or access point when high output power is not required to sustain reliable communications. In such cases, the transmitter will reduce the transmit power to obtain current saving, while maintaining its high uplink throughput. 1.13 IPv4/IPv6 networking The QCA4004 includes a TCP/IP and UDP offload capability. This capability can reduce Flash requirements on a host MCU by up to 100 KBytes and also free up CPU cycles. The IP stack is a simultaneous IPv4/IPv6 stack with a BSD-like interface to simplify porting and integration with 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 14 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Introduction common embedded operating systems. The supported features of the QCA4004 (support for DHCP, multicast, and ARP) include: ARP Forwarding Fragmentation/reassembly (supported with limitation) IPv4/v6 header processing UDP/TCP socket support DHCP v4 Neighbor discovery Broadcast/multicast Address auto-configuration Multicast TCP zero-copy feature HTTP/SSL client/server feature DNS proxy server and client SNTP client Bridging/Routing Raw sockets The QCA4004 supports many key IPv4 and IPv6 RFCs as shown in Table 1-4 and Table 1-5. Table 1-4 QCA4004 IPv4 supported RFCs IPv4 RFC Number RFC1122: TCP Timeout/retransmission RFC1122: TCP Keep-alive RFC1122: TCP Zero-Window-Probe RFC1122: TCP Sliding window protocol Table 1-5 QCA4004 IPv6 supported RFCs IPv6 RFC Number RFC2464:Transmission of IPv6 packets over Ethernet networks RFC2460: Internet Protocol version 6 RFC2462: Duplicate Address Detection (DAD) RFC2463: ICMPv6 RFC3513: IP version 6 addressing architecture RFC3484: Default Address Selection RFC2461: Neighbor discovery for IPv6 host RFC4862: Stateless Address Auto-configuration 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 15 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Introduction 1.14 Internal voltage regulator The QCA4004 supports two regulator modes for its on-chip 1.2 V regulator; see Section 1.15.4 for more information. 1.14.1 Switching 1.2 V regulator Figure 1-4 depicts the switching 1.2 V switching power supply regulated by the QCA4004. Refer to the reference design schematics for details. VDD33 12 VD33_xxx SREG_OUT 18, 38, 46, 49, 61 SWREG_IN 17 C1 C2 = 470 pF Switching Regulator (1.2 V) 16 SWREG_OUT L1 15 DVDD12 1, 21, 34 Decoupling capacitors should be connected to each power rail C3 SWREG_FB_VDD12 47, 48, 56 VDD12_xxx Typical values for L1 = 1-4.7 nH, For C3 = 10 F Figure 1-4 1.14.2 1.2 V switching power supply regulated by the QCA4004 Linear 1.2 V regulator Figure 1-5 depicts the switching 1.2 V linear power supply regulated by the QCA4004. Refer to the reference design schematics for details. VDD33 12 VD33_xxx SREG_OUT 18, 38, 46, 49, 61 SWREG_IN C1 17 C2 = 470 pF Linear Regulator (1.2 V) 16 C3 15 Decoupling capacitors should be connected to each power rail SWREG_OUT SWREG_FB_VDD12 DVDD12 1, 21, 34 47, 48, 56 VDD12_xxx Typical values C3 = 10 F Figure 1-5 1.2 V linear power supply regulated by the QCA4004 1.15 Bootstrap modes and pins Certain pins in the QCA4004 are sampled at startup, and these sampled values are used to select among various bootstrap modes and chip configurations. 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 16 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification 1.15.1 Introduction Internal bias Table 1-6 shows the pins biased by chip hardware during power down. After startup, chip firmware may change the bias. Table 1-6 Internal bias during power down GPIO Internal bias GPIO6 Pull-Down GPIO11 GPIO20 Pull-Up GPIO30 GPIO31 1.15.2 Host mode configuration Table 1-7 lists the QCA4004 bootstrap pins that select the interface used to communicate with the external host CPU. Host mode selection affects pin behavior of host interface pins as well as bootup processes in the PCM state machine. It informs the QCA4004 about the presence of an external CPU (referred to as the host controller) and the interface used to exchange messages. Table 1-7 1.15.3 Host mode configuration Pin name Bootstrap function name On chip biasing GPIO [0,2] GPIO0, GPIO2 hostmode -- 00 QCA4004 CPU bootup is under control of the host CPU via the USB interface. The external CPU is required and the host interface is USB. 01 No host required at startup time. The QCA4004 CPU self boots and firmware may configure any of the available interfaces. No external CPU is required. 10 The QCA4004 CPU bootup is under control of host CPU via SPI Slave interface. The external CPU is required and the SPI interface is the host interface. 11 Reserved Description Crystal value configuration Table 1-8 shows the bootstrap pin to configure the crystal value. Table 1-8 80-Y7545-6 Rev. D Crystal value configuration Pin name Bootstrap function name On chip biasing GPIO20 xtal_freq[0] - Description 0 Reserved 1 40 MHz MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 17 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification 1.15.4 Introduction 1.2 V regulator configuration The QCA4004 supports two regulator modes for its on-chip 1.2 V regulator: switching and linear. Linear mode requires fewer board-level components, but at a slightly higher power consumption than switching mode. Table 1-9 shows the bootstrap pin to configure the 1.2 V regulator. Table 1-9 1.15.5 1.2 V regulator configuration Pin name Bootstrap function name On chip biasing GPIO13 en_linear - Description 0 Switching regulator 1 Linear regulator 1.8 V regulator configuration The QCA4004 supports a regulator mode for its on-chip 1.8 V regulator. Table 1-10 80-Y7545-6 Rev. D 1.8 V regulator Configuration Pin name Bootstrap function name On chip biasing GPIO31 1p8_reg_enable Pull Up Description Enable for on chip 1.8 V regulator 0 1.8 V regulator is disabled 1 1.8 V regulator is enabled MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 18 2 Pin Descriptions 57 56 55 54 53 52 IOT_MODE_EN RFOUT5P1 RFOUT5N1 VDD33_RF1 RFOUT2NT RFIN5P1 RFIN5N1 VDD12_RF1 RFIN2N1 RFIN2P1 RFIN2P1_ANT2 RFIN2N1_ANT2 GPIO13 65 64 63 62 61 60 59 RFOUT2P1 GPIO12 66 58 GPIO10 GPIO11 67 68 The QCA4004 device is available in the 68-pin QFN that includes several ground pins for electrical grounding, mechanical strength, and thermal continuity. See Chapter 4 for package details. A high-level view of the pin assignments is shown in Figure 2-1. DVDD12 1 51 XPABIAS2 GPIO9 GPIO8 2 3 49 VDD33_SYNTH GPIO7 GPIO6 4 5 48 VDD12_SYNTH GPIO5 46 VDD33_PLL_XTAL GPIO4 6 7 GPIO3 8 GPIO2 9 50 XPABIAS5 47 VDD12_BB_PLL 45 XTALI 44 XTALO (Top View) GPIO1 10 42 ANTA GPIO0 11 41 ANTB 39 ANTD CHIP_PWD_L 14 38 VDD33_ANT SWREG_FB_DVDD12 15 37 GPIO15 SWREG_OUT 16 36 GPIO16 17 35 GPIO17 VBATT_3P3 VDD_1P8_OUT 32K_OSC_IN 32K_OSC_OUT PWRDWN_OUT_L WAKEUP_L 18 VDD33_USB Figure 2-1 23 24 25 26 27 GPIO31 28 VDDIO_GPIO 29 GPIO21 30 GPIO20 31 GPIO19 32 GPIO18 33 DVDD12 34 13 22 40 ANTC VDDIO_HOST USB_DPOS 19 USB_DNEG 20 DVDD12 21 SREG_OUT 12 SWREG_IN 80-Y7545-6 Rev. D 43 EXT_CLK_OUT QCA4004 pin assignments (top view) MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 19 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Pin Descriptions 2.1 I/O parameter definitions The following nomenclature is used for signal names: NC/Reserved No connection should be made to this pin _L At the end of the signal name, indicates active low signals P At the end of the signal name, indicates the positive side of a differential signal N At the end of the signal name indicates the negative side of a differential signal The following nomenclature is used for signal types: IA Analog input signal I Digital input signal IH Input signals with weak internal pull-up, to prevent signals from floating when left open IL Input signals with weak internal pull-down, to prevent signals from floating when left open I/O A digital bidirectional signal OA An analog output signal O A digital output signal P A power or ground signal Table 2-1 Pin description Signal Name Pin Type Description EXT_CLK_OUT 43 O External clock out: 40 or 26 MHz; its corresponding half rate is available when configured. XTALI 45 I/O XTALO 44 I Supports 40 MHz or 26 MHz crystal. When an external reference clock is used, connect the clock signal to the XTALO pin and ground the XTALI pin. CHIP_PWD_L 14 I Chip power-down control RFIN2N1 55 IA RFIN2P1 54 IA RFIN5N1 57 IA RFIN5P1 58 IA General Radio 80-Y7545-6 Rev. D The first differential RF inputs MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 20 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Table 2-1 Pin Descriptions Pin description (cont.) Signal Name Pin Type Description RFOUT2N1 60 OA RFOUT2P1 59 OA RFOUT5N1 62 OA RFOUT5P1 63 OA RFIN2P1_ANT2 53 IA RFIN2N1_ANT2 52 IA XPABIAS2 51 OA Bias for optional external power amplifier in 2.4 GHz XPABIAS5 50 OA Bias for optional external power amplifier in 5 GHz The first differential RF outputs The second differential RF inputs for 2.4 GHz Rx/LNA diversity using two antennas; can be left open if not in use Analog Interface External Switch Control ANTA 42 O External RF switch control ANTB 41 O ANTC 40 O ANTD 39 O USB_DPOS 19 IA/OA USB D+ signal; carries USB data to and from the USB 2.0 PHY USB_DNEG 20 IA/OA USB D- signal; carries USB data to and from the USB 2.0 PHY USB Internal Switching Regulator SREG_OUT 12 P 1.2 V regulator output, connect to a 470 pF bypass capacitor on the board SWREG_OUT 16 P Output of the switching regulator to an LC filter or the LDO SWREG_IN 17 P 3.3 V input to the internal switching regulator or LDO IOT_MODE_EN 64 I Power island isolation setting. This pin should be tied to the VBATT_3P3 signal. When this pin is low, the internal signal connections between pins 23 through 28 are isolated from rest of the chip. When this pin is high, internal connections are enabled, and pins 23 through 28 can be used. 32K_OSC_IN 24 IA 32 KHz crystal oscillator input 32K_OSC_OUT 25 OA 32 KHz crystal oscillator output PWRDWN_OUT_L 26 O Suspend Control signal. This pin is driven low by the QCA4004 when the wakeup manager power island is requesting a power down of the top level power island (SUSPEND state). This pin is driven high by the QCA4004 when the wakeup manager power island is requesting a resume to active to the top level power island. WAKEUP_L 27 I Wakeup Control. While in SUSPEND state, the QCA4004 monitors this pin, and if a falling edge or rising edge is detected, the resume from SUSPEND sequence is started. Wakeup Manager 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 21 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Table 2-1 Pin Descriptions Pin description (cont.) Signal Name Pin Type Description GPIO0 11 I/O GPIO1 10 I/O GPIO2 9 I/O GPIO3 8 I/O GPIO4 7 I/O GPIO5 6 I/O GPIO6 5 I/O GPIO7 4 I/O GPIO8 3 I/O GPIO9 2 I/O GPIO10 68 I/O GPIO11 67 I/O GPIO12 66 I/O GPIO13 65 I/O GPIO15 37 I/O GPIO16 36 I/O GPIO17 35 I/O GPIO18 33 I/O GPIO19 32 I/O GPIO20 31 I/O GPIO21 30 I/O GPIO31 28 I/O DVDD12 1, 21, 34 P Digital 1.2 V power supply, should be connected to the SWREG_FB pin. SWREG_FB_ DVDD12 15 P Reference feedback voltage to the internal switching regulator or LDO VBATT_3P3 22 P Connect to 3.3 V host IO supply VDD_1P8_OUT 23 P 1.8 V LDO output, connect to a > 1 F bypass capacitor on the board VDD12_BB_PLL 47 P VDD12_RF1 56 P Analog 1.2 V power supply, should be connected to the SWREG_FB pin. VDD12_SYNTH 48 P GPIO 80-Y7545-6 Rev. D General purpose input/output. The QCA4004 supports a USB interface as well as an RGMII interface. The QCA4004 can be configured to support any of these interfaces by tying certain inputs externally. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 22 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Table 2-1 Pin Descriptions Pin description (cont.) Signal Name Pin Type Description VDD33_ANT 38 P VDD33_RF1 61 P VDD33_PLL_XTAL 46 P VDD33_SYNTH 49 P VDD33_USB 18 P VDDIO_HOST 13 P Connect to 3.3 V host IO supply VDDIO_GPIO 29 P Connect to 3.3 V host IO supply or 1.8 V peripheral IO supply - P Exposed ground pad (Mechanical Information) Analog 3.3 V power supply Ground GND 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 23 3 Electrical Characteristics 3.1 Absolute maximum ratings Absolute maximum ratings are those values beyond which damage to the device can occur. Functional operation under these conditions, or at any other condition beyond those indicated in this chapter, is not recommended. Table 3-1 summarizes the absolute maximum ratings for the QCA4004 device. Table 3-2 shows the recommended operating conditions. Maximum rating for signals follows the supply domain of the signals. NOTE Table 3-1 Absolute maximum ratings Symbol (Domain) Description Max rating Unit VDDIO_GPIO I/O supply for GPIO15-GPIO31 pins -0.3 to 4.0 V VDDIO_HOST I/O supply for GPIO0-GPIO13 pins -0.3 to 4.0 V DVDD12 Digital 1.2 V supply1 -0.3 to 1.32 V VDD12_BB_PLL 1.2 V supply for analog BB PLL -0.3 to 1.32 V VDD12_RF 1.2 V supply for analog RF -0.3 to 1.32 V VDD12_SYNTH 1.2 V supply for analog SYNTH -0.3 to 1.32 V VDD33_ANT Antenna control I/O supply -0.3 to 4.0 V VDD33_RF 3.3 V supply for analog RFs -0.3 to 4.0 V VDD33_SYNTH 3.3 V supply for analog SYNTH -0.3 to 4.0 V VDD33 3.3 V supply for switching regulator/PMU -0.3 to 4.0 V VDD33_PLL_XTAL 3.3 V supply for XTAL/PLL -0.3 to 4.0 V VDD33_USB 3.3 V supply for USB -0.3 to 4.0 V VIH MIN Minimum Digital I/O Input Voltage for 1.8 V or 3.3 V I/O Supply -0.3 V 3.3 V I/O VIH MAX Maximum Digital I/O Input Voltage for 3.3 V I/O Supply Vdd +0.3 V RFin Maximum RF input (reference to 50- input) +10 dBm Tstore Storage Temperature -45 to 135 C Tj Junction Temperature 125 C SWREG_FB_VDD12 SWREG_IN 1. DVDD12 and SWREG_FB are connected through an external LC filter to the SWREG_OUT pin. See Figure 1-4. 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 24 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Electrical Characteristics 3.2 Recommended operating conditions Table 3-2 Recommended operating conditions Symbol (Domain) Parameter Min Typ Max Unit VDDIO_GPIO I/O supply for GPIO15-GPIO21 pins 1.71 - 3.46 V VDDIO_HOST I/O supply for GPIO0-GPIO13 pins 3.0 - 3.6 V 3.14 - 3.46 V Digital 1.2 V supply1 1.20 1.26 1.32 V Analog 1.2 V supplies 1.20 1.26 1.32 V Internal switching regulator supply 3.14 3.3 3.46 V Antenna control I/O supply 3.14 3.3 3.46 V 3.14 3.3 3.46 V Standard case temperature 0 - 85 C Industrial case temperature -40 - 105 C VBATT_3P3 DVDD12 I/O supply for GPIO31 pin SWREG_FB_VDD12 VDD12_BB_PLL, VDD12_ SYNTH, VDD12_RF VDD33 SWREG_IN VDD33_ANT VDD33_RF, VDD33_SYNTH, Analog 3.3 V supplies VDD33_PLL_XTAL, VDD33_ USB Tcase 1. DVDD12 and SWREG_FB_VDD12 are connected through an external LC filter to the SWREG_OUT pin. See Figure 1-4. 3.3 Power sequencing If a host processor controls the QCA4004 CHIP_PWD_L reset pin, then all supplies should be stable for a minimum of 5 S before CHIP_PWD_L is de-asserted (that is, is greater than VIL for VDDIO_SDIO). In the case where CHIP_PWD_L is not driven, but is a delayed version of VDD33 (power-on reset), the timing diagram in Figure 3-1 applies. Figure 3-1 Power-On-Reset Timing Table 3-3 shows the values for timing for power on reset. 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 25 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Table 3-3 Electrical Characteristics Power-on-reset timing Parameter Description Min Max Unit tA Rise time of VDD33 to 90% of 3.3 V - 25 mS tC Time from VDD33 reaching 90% of 3.3 V to the level of CHIP_PWD_L going above 0.5 * VDD33 5 -- S tB The value is tA + tC; during this time, the level of CHIP_PWD_L should stay below 0.5 x VDD33 3.4 Digital logic characteristics These conditions apply to all DC characteristics unless otherwise specified: Tamb = 25 C, Vdd33= 3.3 V Table 3-4 Symbol DC electrical characteristics for digital I/Os Parameter Min Typ Max Unit VIH High Level Input Voltage 1.8 - 3.6 V VIL Low Level Input Voltage -0.3 - 0.3 V VOH High Level Output Voltage 2.2 - 3.3 V VOL Low Level Output Voltage 0 - 0.4 V IIH High Level Input Current - - 0.1 A IIL Low Level Input Current - - 0.1 A IOH High Level Output Current for GPIO0 to GPIO13 - - 20 mA High Level Output Current for GPIO15 to GPIO31 - - 20 Low Level Output Current for GPIO0 to GPIO13 - - 20 Low Level Output Current for GPIO15 to GPIO31 - - 20 Input Capacitance for GPIO0 to GPIO13 - 5 - Input Capacitance for GPIO15 to GPIO31 - 3 - IOL CIN mA pF 3.5 Clock requirements 3.5.1 External reference clock timing Figure 3-2 and Table 3-5 show the external 40 MHz reference input clock timing requirements. 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 26 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Electrical Characteristics CK1 CK5 CK6 CK2 Figure 3-2 Table 3-5 3.5.2 CK3 External reference input clock timing External 40 MHz reference input clock timing Symbol Description Min Typ Max Unit CK1 Frequency accuracy -20 - 20 ppm Frequency - 40 - MHz CK2 Fall time - - 0.1 x period ns CK3 Rise time - - 0.1 x period ns CK4 Duty cycle (high-to-low ratio) 40 - 60 % CK5 Input high voltage 0.75 - 1.26 V CK6 Input low voltage -0.55 - 0.3 V SPI slave interface timing Figure 3-3 shows the write timing for SPI slave style transactions. FPP Clock TWL TWH VIH VIL TTLH TTHL TISU TIH Input VIH VIL Outpu t VOH VOL Shaded areas not valid Figure 3-3 TO_DLY (max) TO_DLY (min) SPI slave timing Table 3-6 shows the values for timing constraints for SPI slave. Table 3-6 80-Y7545-6 Rev. D SPI slave timing constraints Parameter Description Min Max Unit fPP Clock frequency 0 48 MHz tWL Clock low time 8.3 - ns tWH Clock high time 8.3 - ns tTLH Clock rise time - 2 ns MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 27 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Table 3-6 3.5.3 Electrical Characteristics SPI slave timing constraints Parameter Description Min Max Unit tTHL Clock fall time - 2 ns tISU Input setup time 5 - ns tIH Input hold time 5 - ns tO_DLY Output delay 0 5 ns SPI master interface timing Figure 3-4 shows the write timing for SPI master style transactions. tCP SPI_CLK tCSD SPI_CS[3:0] tDS tDD tDH SDI0_D[3:0] Shaded areas not valid Figure 3-4 SPI master timing Table 3-6 shows the values for timing constraints for SPI master. Table 3-7 80-Y7545-6 Rev. D SPI master timing constraints Parameter Description Min Max Unit tCP Clock period 30.7 1000 ns tCSD Chip select valid delay -5.5 5 ns tDD Data valid delay -5.5 5 ns tDS Data setup 3 - ns tDH Data hold 0 - ns MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 28 4 Mechanical Information 4.1 Device physical dimensions The QCA4004 device is available in the 8 mm x 8 mm x 0.85 mm Micro Quad Flat pack No-lead (MQFN) package that includes a ground pad for improved grounding, mechanical strength, and thermal continuity. Pin 1 is located by an indicator mark on the top of the package. Figure 4-1 shows the QCA4004 device mechanical dimensions, top and bottom views. (4004) Figure 4-1 80-Y7545-6 Rev. D QCA4004 mechanical dimensions, top and bottom views MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 29 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Mechanical Information Mechanical dimensions 1 Table 4-1 Dimension label Min Nom Max Unit A - - 0.90 mm A1 0.00 0.01 0.05 mm A2 0.60 0.65 0.70 mm A3 0.20 REF mm b 0.15 0.20 0.25 mm L 0.30 0.40 0.50 mm D1/E1 7.75 BSC D2 4.35 4.50 4.65 E2 3.55 3.70 3.85 e 0.40 BSC 0 - mm 14 1. Reference document: NT90-Y5242-1 4.2 Part marking This device can be ordered using the identification code shown in Section 4.3. Figure 4-2 Table 4-2 Line 80-Y7545-6 Rev. D Package marking layout Package marking identifiers Marking Line 1 QCA4004 Line 2 Assembly lot code Line 3 Date code (YYWW) Line 4 Country of origin (COO) MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 30 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Mechanical Information 4.3 Device ordering information QCA4004X-AL3A: a lead-free halogen-free standard-temperature version of the QCA4004. QCA4004X-AL3B: a lead-free halogen-free industrial-temperature version of the QCA4004. QCA4004X-BL3A: a lead-free halogen-free standard-temperature version of the QCA4004. QCA4004X-BL3B: a lead-free halogen-free industrial-temperature version of the QCA4004. 4.4 Device moisture-sensitivity level During device qualification, Qualcomm Atheros follows the latest revision IPC/JEDEC J-STD020 standard to determine the IC's moisture-sensitivity level (MSL). See Chapter 7 for more information. To ensure proper SMT assembly, procedures must follow the MSL and maximum reflow temperature specified on the shipping bag labels or barcode labels accompanying all QCA4004 IC shipments. Additional MSL information is included in: Section 5.2 - Storage Section 5.3 - Handling Section 7.1 - Reliability qualifications summary ASIC Packing Methods and Materials Specification (80-VK055-1) 4.5 Thermal characteristics Table 4-3 Device thermal resistance Parameter PsiJT 80-Y7545-6 Rev. D Comment Thermal parameter Typ Unit 3 C/W MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 31 5 Carrier, Storage, and Handling Information 5.1 Carrier 5.1.1 Tape and reel information Carrier tape system conforms to the EIA-481 standard. Simplified sketches of the QCA4004 tape carrier is shown in Figure 5-1 and Figure 5-2, including the part orientation. Tape and reel details for the QCA4004 are as follows: Reel diameter: 330 mm Hub size: 102 mm Tape width: 16 mm Tape pocket pitch: 12 mm Feed: Single Units per reel: 4,000 Figure 5-1 80-Y7545-6 Rev. D Tape orientation on reel MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 32 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Figure 5-2 5.1.2 Carrier, Storage, and Handling Information Part orientation in tape Matrix tray information All Qualcomm Atheros matrix tray carriers conform to JEDEC standards. The device pin 1 is oriented to the chamfered corner of the matrix tray. Each tray of the QCA4004 device contains up to 260 devices. See Figure 5-3 for matrix-tray key attributes and dimensions. Key dimensions Figure 5-3 80-Y7545-6 Rev. D Array 10 x 26 = 260 M 10.35 mm M1 10.00 mm M2 11.80 mm M3 12.80 mm Matrix tray part orientation MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 33 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Carrier, Storage, and Handling Information 5.2 Storage 5.2.1 Bag storage conditions The packages described in this document must be stored in a nitrogen-purged, sealed moisture barrier antistatic bag. The Qualcomm-calculated shelf life in a sealed moisture bag is 60 months at < 40C and < 90% relative humidity (RH). 5.2.2 Out of bag duration After unpacking, the package must be soldered to the PCB within the factory floor life according to the MSL rating when factory conditions are < 30C and < 60% RH, as specified in the IPC/JEDEC-STD-033 standard. 5.3 Handling Tape handling was described in Section 5.1.1. Other handling guidelines are presented below. 5.3.1 Baking It is not necessary to bake the QCA4004 if the conditions specified in Section 5.2.1 and Section 5.2.2 have not been exceeded. It is necessary to bake the QCA4004 if any condition specified in Section 5.2.1 or Section 5.2.2 has been exceeded. The baking conditions are specified on the moisture-sensitive caution label attached to each bag. See ASIC Packing Methods and Materials Specification (80-VK055-1) for details. CAUTION 5.3.2 If baking is required, the devices must be transferred into trays that can be baked to at least 125C. Devices should not be baked in tape and reel carriers at any temperature. Electrostatic discharge Electrostatic discharge (ESD) occurs naturally in laboratory and factory environments. An established high-voltage potential is always at risk of discharging to a lower potential. If this discharge path is through a semiconductor device, destructive damage may result. ESD countermeasures and handling methods must be developed and used to control the factory environment at each manufacturing site. Qualcomm products must be handled according to the ESD Association standard: ANSI/ESD S20.20-1999, Protection of Electrical and Electronic Parts, Assemblies, and Equipment. 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 34 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Carrier, Storage, and Handling Information 5.4 Barcode label and packing for shipment Refer to the ASIC Packing and Materials Specification (80-VK055-1) document for all packingrelated information, including barcode label details. 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 35 6 PCB Mounting Guidelines Guidelines for mounting the QCA4004 device onto a PCB are presented in this chapter, including land pad and stencil design details, surface mount technology (SMT) process characterization, and SMT process verification. 6.1 RoHS compliance The device is externally lead-free and RoHS-compliant. Qualcomm Atheros defines its lead-free (or Pb-free) semiconductor products as having a maximum lead concentration of 1000 ppm (0.1% by weight) in raw (homogeneous) materials and end products. Qualcomm Atheros package environmental programs, RoHS compliance details, and tables defining pertinent characteristics of all Qualcomm Atheros IC products are described in the IC Package Environmental Roadmap (80V6921-1). 6.2 SMT parameters The information presented in this section describes Qualcomm Atheros board-level characterization process parameters. It is included to assist customers when starting their SMT process development; it is not intended to be a specification for customer SMT processes. NOTE Qualcomm Atheros recommends that customers follow their solder paste vendor recommendations for the screen-printing process parameters and reflow profile conditions. Qualcomm Atheros characterization tests attempt to optimize the SMT process for the best boardlevel reliability possible. This is done by performing physical tests on evaluation boards, which may include: 6.2.1 Drop shock Temperature cycling Bend cycle (optional) Land pad and stencil design Qualcomm Atheros recommends characterizing the land patterns according to each customer's processes, materials, equipment, stencil design, and reflow profile prior to PCB production. Optimizing the solder stencil-pattern design and print process is critical to ensure print uniformity, 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 36 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification PCB Mounting Guidelines decrease voiding, and increase board-level reliability. See PCB Land and Stencil Design Guide (LS90-NG134-1) for characterization. 6.2.2 Reflow profile Reflow profile conditions typically used by Qualcomm Atheros for SnPb and lead-free systems are given in Table 6-1. Table 6-1 Qualcomm Atheros typical SMT reflow profile conditions (for reference only) Profile stage Preheat Description Initial ramp Temp range Lead-free (high temperature condition limits) < 150C 3C/sec max Soak Dry out and flux activation 150 to 190C 60 to 120 sec Ramp Transition to liquidus (solder-paste melting point) 190 to 220C < 30 sec Reflow Time above liquidus 220 to 245C1 50 to 70 sec < 220C 6C/sec max Cool down Cool rate - ramp-to-ambient 1. During the reflow state, the peak temperature should not exceed 245C. This temperature should not be confused with the peak temperature reached during MSL testing. Figure 6-1 shows the typical SMT reflow profile. Figure 6-1 80-Y7545-6 Rev. D Typical SMT reflow profile MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 37 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification 6.2.3 PCB Mounting Guidelines SMT peak package-body temperature During a production board's reflow process, the temperature for the package must be controlled. The recommended peak temperature during production assembly is 245C. This is comfortably above the solder melting point (220C), yet well below the proven temperature reached during qualification (255C or more). Although the solder-paste manufacturer's recommendations for optimum temperature and duration for solder reflow must be followed, the Qualcomm Atheros recommended limits must not be exceeded. 6.2.4 SMT process verification Qualcomm Atheros recommends verification of the SMT process prior to high-volume PCB fabrication, including: Electrical continuity X-ray inspection of the package installation for proper alignment, solder voids, solder balls, and solder bridging Visual inspection Cross-section inspection of solder joints to confirm registration, fillet shape, and print volume 6.3 Board-level reliability Qualcomm Atheros conducts characterization tests to assess the device's board-level reliability, including the following physical tests on evaluation boards: Drop shock (JESD22-B111) Temperature cycling (JESD22-A104) (Optional) Cyclic bend testing (JESD22-B113) See Board-level Reliability (BR80-NT096-1) for details. 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 38 7 Part Reliability 7.1 Reliability qualifications summary Table 7-1 QCA4004 reliability evaluation Reliability tests, standards, and conditions Sample # Lots Result Assembly1 Assembly2 231 3 lots = 20 FIT - - ESD - (HBM) human body model rating JESD22-A114-B 3 Pass 2000 V, all pins - - ESD - (CDM) charge device model rating JESD22-C101-C 3 Pass 500 V, all pins except RFIN2P1 and RFIN2N1 pass 400 V - - Latch-up (Overcurrent test): EIA/JESD78 Trigger current: 200 mA; temperature: 25C 6 1 lot Pass - - Latch-up (Overvoltage test): EIA/JESD78 Trigger voltage: 1.6 x Vnom; temperature: 25C 6 1 lot Pass - - High Temperature Storage Life (HTSL) JESD-22 A104, -50 to +150C, 1000 hrs 462 3 + 3 lots - Pass Pass Moisture/Reflow Sensitivity Classification: MSL3; JSTD-020D, (30C/60% RH, 192 hrs, 3 x IR @ 260C) 1078 3 + 3 lots - Pass Pass Temperature cycle: JESD22-A104 Temperature: -65 to +150 C Number of cycles: 1000 Min soak time at min/max temperature: 5 minutes Cycle rate: 2 cycles per hour (cph) Prerequisite: All samples subjected to preconditioning MSL 3 and reflow (260C) 3X prior to TC 462 3 + 3 lots - Pass Pass Highly accelerated stress test, unbiased (HAST) JESD22-A118 Prerequisite: All samples subjected to preconditioning MSL 3 and reflow (260C) 3X prior to HAST 474 3 + 3 lots - Pass Pass Average failure rate (AFR) in FIT () Failure in billion device-hours Functional HTOL: JESD22-A108 80-Y7545-6 Rev. D MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 39 QCA4004 Low-Energy Wi-Fi Dual-Band 802.11a/b/g/n SoC Device Specification Table 7-1 Part Reliability QCA4004 reliability evaluation Reliability tests, standards, and conditions Highly accelerated stress test, biased (bHAST) JESD22-A118 Sample # Lots Result Assembly1 Assembly2 158 1 + 1 lots - Pass Pass 5 - Pass Pass Prerequisite: All samples subjected to preconditioning MSL 3 and reflow (260C) 3X prior to HAST Die shear (5 kg) 7.2 Qualification sample description 80-Y7545-6 Rev. D Device name: QCA4004 Package type: QFN 68L Package body size: 8 mm x 8 mm x 0.85 mm Lead count: 68 Lead pitch: 0.4 mm MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 40