12025-801 - AMI Semiconductor, Inc.

AMERICAN MICROSYSTEMS, INC.

April 2000

This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. 4.28.00

FS6219

FS6219FS6219

FS6219

Dual-VCXO/Triple-PLL Programmable Cloc k Generator IC

Dual-VCXO/Triple-PLL Programmable Cloc k Generator ICDual-VCXO/Triple-PLL Programmable Cloc k Generator IC

Dual-VCXO/Triple-PLL Programmable Cloc k Generator IC

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ISO9001

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1.0 Features

• Two voltage-controlled crystal oscillators (VCXO)

• Three fully programmable phase-locked loops (PLL)

• Three system clock frequency outputs

• I

2C-bus serial interface

• 3.3 volt operation (contact factory for 5 volt versions)

• Compact 16-pin SOIC (0.150”) package

Figure 1: Pin Configuration

116

XAO

XAI

XTUNEA

SCL

SDA

VDD

ADDR

VSS CLKA

CLKB

VDD

CLKC

VSS

XTUNEB

XBI

XBO

FS6219

2.0 Description

The FS6219 is a monolithic CMOS clock generator IC

designed to m inim ize cost a nd com ponen t count in digi tal

video / audio systems.

Two fully independent VCXOs permit accurate and

simulaneous phase locking of the generated clocks to

independe nt sources, such as satellite or cable delivered

video and terrestrial broadcasts.

Three fully independent, fully programmable PLLs with

flexible post-dividers permit the generation of desired

clock frequencies precisely, with no added “synthesis”

errors.

The FS621 9 m akes use of the latest AMI PL L tec hnol og y

for low clock period jitter and low cumulative jitter.

The ADDR pin permits two FS6219 to be uniquely con-

trolled by a single I2C bus. The full read/write slave

capabil it y of the FS6219 al lo ws a ll de vic e pr ogr am ming to

be completely verified.

Contact factory for custom requirements.

Figure 2: Device Block Diagram

Crystal

Oscillator

"B"

Crystal

Oscillator

"A"

FS6219

XTUNEA

XAI

XAO

XBI

XBO

XTUNEB

PLL "A"

PLL "B"

PLL "C"

C Interface

(Read / Write Slave)

SCL

SDA

Source

Select Source

Select

FPLLA

FPLLB

FXA

FXB

Post-Divider

"A"

Post-Divider

"B"

Post-Divider

"C"

Source

Select

CLKC

CLKB

CLKA

FPLLC

FXA

FXB

AMERICAN MICROSYSTEMS, INC.

April 2000

24.28.00

FS6219

FS6219FS6219

FS6219

Dual-VCXO/Triple-PLL Programmable Cloc k Generator IC

Dual-VCXO/Triple-PLL Programmable Cloc k Generator ICDual-VCXO/Triple-PLL Programmable Clock Generator IC

Dual-VCXO/Triple-PLL Programmable Cloc k Generator IC

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Table 1: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active Low pin

PIN TYPE NAME DESCRIPTION

1 AO XAO Crystal Oscillator “A” Drive

2 AI XAI Crystal Oscillator “A” Feedback

3 AI XTUNEA Crystal Oscillator “A” Voltage Tuning Input

4DI

USCL Serial I nterface Clock Input

5DI

UO SDA Serial I nterf ace Dat a Input/Output

6 P VDD Power Supply (+3.3V nominal)

7DI

UADDR Serial I nterface Address Select

8 P VSS Ground

9DOCLKAClock Output “A”

10 DO CLKB Clock Output “B”

11 P VDD Power Supply (+3.3V nominal )

12 DO CLKC Clock Outp ut “C”

13 P VSS Ground

14 AI XTUNEB Crystal Oscillator “B” Voltage Tuning Input

15 AI XBI Crystal Oscillator “B” Feedback

16 AO XBO Crystal Oscillator “B” Drive

Note: When applying an external reference clock to the FS6219, it should be capacitively coupled to the XAO or XBO pins. The

XAI and/or XBI pins should be floating (no connection).

FS6219 VCXO Typi cal Charact er istic

-200

-150

-100

-50

100

150

200

250

00.511.522.53

V( XTUNE) - vol ts

Deviation - ppm

AMERICAN MICROSYSTEMS, INC.

April 2000

34.28.00

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FS6219

FS6219FS6219

FS6219

Dual-VCXO/Triple-PLL Programmable Clock Generator IC

Dual-VCXO/Triple-PLL Programmable Clock Generator I CDual-V CXO/Triple-PLL Programmable Clock Generator IC

Dual-VCXO/Triple-PLL Programmable Clock Generator I C

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3.0 Programming Information

Table 2: Register Map (Note: All Register Bits are cleared to zero on power-up.)

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

BYTE 15 ********

BYTE 14 * * * * TSCLK_C STOPCLK_C SRCCLK_C[2:0]

BYTE 13 * * * * TSCLK_B STOPCLK_B SRCCLK_B[2:0]

BYTE 12 * * * * TSCLK_A STOPCLK_A SRCCLK_A[2:0]

BYTE 11 MODPOST_C[3:0] SRCPOST_C[2:0]

BYTE 10 MODPOST_B[3:0] SRCPOST_B[2:0]

BYTE 9 MODPOST_A[3:0] SRCPOST_A[2:0]

BYTE 8 SRCPLL_C[1:0] PDPLL_C LFTC_C CP_C FBKDIV_C[10:8] M-Counter

BYTE 7 FBKDIV_C[7:3] M-Counter FBKDIV_C[2:0] A-Counter

BYTE 6 REFDIV_C[7:0]

BYTE 5 SRCPLL_B[1:0] PDPLL_B LFTC_B CP_B FBKDIV_B[10:8] M-Counter

BYTE 4 FBKDIV_B[7:3] M-Counter FBKDIV_ B[2:0] A-Counter

BYTE 3 REFDIV_B[7:0]

BYTE 2 SRCPLL_A[1:0] PDPLL_A LFTC_A CP_A FBKDIV_A[10:8] M-Counter

BYTE 1 FBKDIV_A[7:3] M-Counter FBKDIV_ A[2:0] A-Counter

BYTE 0 REFDIV_A[7:0]

3.1 Control Bit Assignment

If any PLL control bit is altered during device operation,

including those bits controlling the Reference and Feed-

back Dividers, the out put frequ ency will s lew sm oothly (in

a glitch-f ree m anner) to the ne w frequency. The s lew rate

is related to the programmed charge pump current and

loop filter time constant.

However, any programming changes to any Mux or Post

Divider control bits will cause a glitch on an operating

clock output.

Table 3: PLL Power-Down Bits

NAME DESCRIPTION

Power-Down PLL “x”

Bit = 0 Power On

PDPLL_x

Bit = 1 Power Off

Table 4: Divider Control Bits

NAME DESCRIPTION

REFDIV_x[7:0] REFerence DIVider for PLL “x” (NR)

FeedBacK DIVider for PLL “x” (NF)

FBKDIV_x[2:0] A-Counter Val ue

FBKDIV_x[10:0]

FBKDIV_x[10:3] M-Counter Value

Table 5: Post-Divider Control Bits

NAME DESCRIPTION

MODPOST_x[3:0] Modulus for POST divider “x”

(see Table 7: Post Divi der Modulus )

Table 6: CLK Pin Stop Bit

NAME DESCRIPTION

CLK “x” Stop Bit

Bit=0 Normal, CLK running

STOPCLK_x

Bit=1 CLK Stopped Low

AMERICAN MICROSYSTEMS, INC.

April 2000

44.28.00

FS6219

FS6219FS6219

FS6219

Dual-VCXO/Triple-PLL Programmable Clock Generator I C

Dual-VCXO/Triple-PLL Programmable Clock Generator I CDual-V CXO/Triple-PLL Programmable Clock Generator IC

Dual-VCXO/Triple-PLL Programmable Clock Generator I C

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Table 7: Post Divider Modulus

BIT [3] BIT [2] BIT [1] BIT [0] DIVIDE BY

00001

00012

00103

00114

01005

01016

01108

01119

100010

100112

101015

101116

110018

110120

111025

111150

Table 8: PLL Reference Source Select Bits

NAME DESCRIPTION

PLL “A” Reference Source Select

Bit[1] Bit[0]

0 0 Referenc e Frequency A

0 1 Referenc e Frequency B

1 0 PLL B Frequency

SRCPLL_A

1 1 PLL C Frequency

PLL “B” Reference Source Select

Bit[1] Bit[0]

0 0 Referenc e Frequency A

0 1 Referenc e Frequency B

1 0 PLL A Frequency

SRCPLL_B

1 1 PLL C Frequency

PLL “C” Reference Source Select

Bit[1] Bit[0]

0 0 Referenc e Frequency A

0 1 Referenc e Frequency B

1 0 PLL A Frequency

SRCPLL_C

1 1 PLL B Frequency

Table 9: Post-Divider Source Select Bits

NAME DESCRIPTION

Post-Divid er “x” Reference Source Select

Bit[2] Bit[1] Bit[0]

0 0 0 Referenc e Frequency A

0 0 1 Referenc e Frequency B

0 1 0 PLL A Frequency

0 1 1 PLL B Frequency

1 0 0 PLL C Frequency

SRCPOST_x

1 1 1 Shutdown Post-Di vider

Table 10: CLK Pin Source Select Bits

NAME DESCRIPTION

CLK “x” Source Select

Bit[1] Bit[0]

0 0 Post-Divider “A”

0 1 Post-Divider “B”

1 0 Post-Divider “C”

SRCCLK_x

11TEST MODE

Table 11: CLK Pin Tri-State Bit

NAME DESCRIPTION

CLK “x” Source Select

Bit=0 Normal, CLK enabled

TSCLK_x

Bit=1 CLK Tri-Stated

Table 12: PLL Tuning Bits

NAME DESCRIPTION

Loop Filter Time Constant for PLL “x”

Bit = 0 Time Constant = t.b.d.

LFTC_x

Bit = 1 Time Constant = t.b.d.

Charge Pump Current for PLL”x”

Bit = 0 Current = t.b.d.

CP_x

Bit = 1 Current = t.b.d.

AMERICAN MICROSYSTEMS, INC.

April 2000

54.28.00

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FS6219

FS6219FS6219

FS6219

Dual-VCXO/Triple-PLL Programmable Clock Generator IC

Dual-VCXO/Triple-PLL Programmable Clock Generator I CDual-V CXO/Triple-PLL Programmable Clock Generator IC

Dual-VCXO/Triple-PLL Programmable Clock Generator I C

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4.0 Electrical Specifications

Table 13: Absolute Maximum Ratings

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at

these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,

functionality, and reliability.

PARAMETER SYMBOL MIN. MAX. UNITS

Supply Voltage (VSS = ground) VDD VSS-0.5 7 V

Input Voltage, dc VIVSS-0.5 VDD+0.5 V

Output Voltage, dc VOVSS-0.5 VDD+0.5 V

Input Clamp Current, dc (V I < 0 or VI > V DD)I

IK -50 50 mA

Output Clamp Current, dc (VI < 0 or VI > VDD)I

OK -50 50 mA

Storage Temperature Range (non-condensing) TS-65 150 °C

Ambient Temperature Range, Under Bias TA-55 125 °C

Junction Temperature TJ125 °C

Lead Temperature (soldering, 10s) 260 °C

Input Static Disc harge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV

CAUTION: ELECTROSTA TIC SENSITIVE DEVICE

Permanent damage res ulting in a loss of functi onality or performance may occur if this devi ce is subjected to a high-energy elec-

trostatic discharge.

Table 14: Operating Conditions

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Supply Voltage (3.3 volt system) VDD 3.0 3.3 3.6 V

Ambient Operating Temperature

Range TA070°C

Crystal Resonator Frequency fXTAL Fundamental Mode 5 13.5 18 MHz

AMERICAN MICROSYSTEMS, INC.

April 2000

64.28.00

FS6219

FS6219FS6219

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Dual-VCXO/Triple-PLL Programmable Clock Generator I C

Dual-VCXO/Triple-PLL Programmable Clock Generator I CDual-V CXO/Triple-PLL Programmable Clock Generator IC

Dual-VCXO/Triple-PLL Programmable Clock Generator I C

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Tabl e 15: DC Electrical Sp ecifications

Unless otherwise stated, VDD = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data

and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Overall

Supply Current, Dynamic, with

Loaded Outputs IDD mA

Voltage Controlled Crystal Oscillator

Crystal Loadi ng Capaci tance CL(xtal)

As seen by a crystal connected to XIN and

XOUT (@ VXTUNE = 1.5V)

PURCHASE CRYSTAL TO THIS VALUE of

CLOAD

20 pF

Crystal Resonator Motional Ca-

pacitance C1(xtal) 25 fF

VCXO Tuning Range Active tuning range 03V

Crystal Frequency Change fXTAL = 13.5MHz; CL(xtal) = 20pF; C1(xtal) = 25fF

VXTUNE = 0 to 3 V 300 ppm

VCXO Tuning Characterist ic Note: posit i ve delta F for positive delta V 100 ppm/V

Crystal Dri ve Level RXTAL=20Ω; CL = 20pF 200 uW

Clock Outputs (CLKA, CLKB, CL KC)

High-Level Output Sourc e Current* I OH VO = 2.0V -40 mA

Low-Level Output Sink Current * IOL VO = 0.4V 17 mA

zOH VO = 0.1VDD; output drivi ng hi gh 25

Output Impedance * zOL VO = 0.1VDD; output drivi ng l ow 25 Ω

Short Circuit S ource Current * IOSH VO = 0V; shorted for 30s, max. -55 mA

Short Circuit S i nk Current * IOSL VO = 3.3V; shorted for 30s, max. 55 mA

Table 16: AC Timing Specifications

Unless otherwise stated, VDD = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data

and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Clock Outputs (CLKA, CLKB, CL KC)

Duty Cycle * Ratio of high pulse width (as measured f rom

rising edge to next falling edge at 1.4V) to one

clock period 45 55 %

Rise Time * trVDD = 3.3V; VO = 0.3V to 3.0V ; CL = 15pF 1.7 ns

Fall Time * tfVDD = 3.3V; VO = 3. 0V t o 0. 3V; CL = 15pF 1.7 ns

AMERICAN MICROSYSTEMS, INC.

April 2000

74.28.00

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FS6219

FS6219FS6219

FS6219

Dual-VCXO/Triple-PLL Programmable Clock Generator IC

Dual-VCXO/Triple-PLL Programmable Clock Generator I CDual-V CXO/Triple-PLL Programmable Clock Generator IC

Dual-VCXO/Triple-PLL Programmable Clock Generator I C

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5.0 Package Information

Table 17: 16-pin SOIC (0.150") Package Dimensions

DIMENSIONS

INCHES MILLIMETERS

MIN. MAX. MIN. MAX.

A 0.061 0.068 1.55 1.73

A1 0.004 0.0098 0.102 0.249

A2 0.055 0.061 1.40 1.55

B 0.013 0.019 0.33 0.49

C 0.0075 0.0098 0.191 0.249

D 0.386 0.393 9.80 9.98

E 0.150 0.157 3.81 3.99

e 0.050 BSC 1.27 BSC

H 0.230 0.244 5.84 6.20

h 0.010 0.016 0.25 0.41

L 0.016 0.035 0.41 0.89

Θ0°8°0°8°

SEATING PLANE

1ALL RADII:

0.005" TO 0.01"

BASE PLANE

7° typ.h x 45°

AMERICAN MICROSYSTEMS, INC.

Table 18: 16-pin SOIC (0.150") Package Characteristics

PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS

Thermal Impedance, Junction to Free-Air

16-pin 0.150” SOIC ΘJA Air flow = 0 m/s 110 °C/W

Corner lead 4.0

Lead Inductanc e, Self L11 Center lead 3.0 nH

Lead Inductanc e, Mutual L12 Any lead to any adjacent l ead 0.4 nH

Lead Capacitance, Bulk C11 Any lead to VSS 0.5 pF

AMERICAN MICROSYSTEMS, INC.

April 2000

84.28.00

FS6219

FS6219FS6219

FS6219

Dual-VCXO/Triple-PLL Programmable Clock Generator I C

Dual-VCXO/Triple-PLL Programmable Clock Generator I CDual-V CXO/Triple-PLL Programmable Clock Generator IC

Dual-VCXO/Triple-PLL Programmable Clock Generator I C

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6.0 Ordering Information

Table 19: Device Ordering Codes

DEVICE NUMBER ORDERING CODE PACKAGE TYPE OPERATING

TEMPERATURE RANGE SHIPPING

CONFIGURATION

FS6219 12025-801 16-pin (0.150”) S OIC

(Small Outl i ne Package) 0°C to 70 °C (Commercial) Tape and Reel

7.0 Revision Information

DATE PAGE DESCRIPTION

4/27/00 5-8 Fi xed formatting errors

Purchase of I2C components of Amer ican Micr os ystem s, Inc., or one of its subl icens ed Ass ociat ed Com pa-

nies conveys a license under Philips I2C P aten t Rights to us e t hes e componen ts in a n I2C system, provided

that the system conforms to the I2C Standard Specification as defined by Philips.

Devices sold by AMI are covered b y the warranty and pat ent indem nif ication pro visions ap pearing in its T erms of Sale

only. AMI m akes no warrant y, express, s tatutory im plied or b y descript ion, r egarding the i nfor m ation set f orth here in or

regarding t he f r eed om of the desc r ibed de vices f r om patent inf r ingement. AMI makes no warranty of m erc hantabi lit y or

fitness for any pur poses. AMI reser ves the right to discont inue pro duction and c hange s pecific ations and prices a t any

time and without notice. AMI’s products are intended for use in commercial applications. Applications requiring ex-

tended tem perature range, u nusual environm enta l requirem ents, or h igh reliab ilit y applications , such as m ilitary, m edi-

cal life-s uppor t or life-sus tain i ng e qu ipment, are s p ec if ic ally not recom mended witho ut add it ion al proces s ing by AMI for

such applications.

American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,

WWW Address: http://www.amis.com E-mail: t

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