To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old company name remains in t his document, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electr onics Corporat ion (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume an y liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas
Electronics products or the technology described in this document for any purpose relating to military applications or use by
the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and
technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liabil ity whatso ever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified acco rding to the following three quality grades: “Standard”, “High Qu ality”, and
“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior
written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way
liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an
application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written
consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic app liances; machine tool s; p ersonal electron i c equipment; and indust r ial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
crime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equ ipment; submersible repeaters; nuclear reactor control systems; medical equi pment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific chara cterist ics such as the o ccurren ce of failure at a certai n rate and mal functi on s under certai n u se cond itions. Further,
Renesas Electronics pr oducts are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sal es office for details as to environmental matters such as t he environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with
applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Ren esas E lectro nics Corpor ation and also inclu des its majority-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
R8A66162SP
32-BIT LED DRIVER WITH SHIFT REGISTER AND LATCH
REJ03F0263-0100 Rev.1.00 Jan.24.2008
page 1 of 7
REJ03F0263-0100
Rev. 1.00
Jan. 24. 2008
DESCRIPTION
The R8A66162SP is a semiconductor integrated circuit for LED array driver with 32-bit serial-input, parallel -
output shift register, equipped with direct set input and output latches.
The R8A66162SP guarantees sufficient 24mA (Vcc=5.0V case) output current to drive anode common LED,
allowing 32-bit simultaneous and contin uous current output. The parallel output s are open-drain outputs.
In addition, as this product has been designed in complete CMOS, power consumption can be greatly
reduced when compared with conventional BIPOLAR or Bi-CMOS products. Furthermore, pin layout ensures
the realization of an easy printed circuit. R8A66162SP is the su ccession product of M66313FP.
FEATURES
● Anode common LED drive
● VCC 5V or 3.3V single power supply
● High output current: All parallel outputs Q1~Q32 IOL=24mA (at VCC=5.0V), IOL=12mA (at VCC=3.3V),
LEDs can be turned on sim ultaneously.
● Low power dissipation: 200uW/package (max) (VCC=5.0V, Ta=25OC, quiescent state)
● High noise margin: Employment of Schmitt-trigger circuit on all inputs allows application with long wiring.
● Direct set input (SD)
● Open-drain output (Q1~Q32)
● Serial data output for cascadi ng (SQ32)
● Wide operating temperature range (Ta=-40oC~+85oC)
● Pin configuration for easy layout on PCB. (Pin configuration allows easy cascade connection or LED
connection)
APPLICATION
● LED array drive, The various LED display modules
● PPC, Printer, VCR, Mini-compo, Button-Telephone etc. All of LED display equipments
BLOCK DIAGRAM
PA RA LLEL DA TA OUT PUTS
LO GIC DIAGR AM
OUTPUT FO RMAT
PARALLEL
DATA
OUTPUTS
Q
1
〜Q
32
DATA
SIGNAL
OE
SIGNAL
SERIAL
DATA
OUTPUT
SQ
32
A
5
0LE
DS
1CK
DS
Q
4
4
0LE
DS
1CK
DS
Q
3
OE
11
S
10
S
3
0LE
DS
1CK
DS
Q
2
2
0LE
DS
1CK
DS
Q
1
CK
SHIFT
CLOCK
INPUT
LE
LATCH
ENABLE
INPUT
S
D
DIRECT
SET
INPUT
SERI AL DAT A
OUTPUT
23
0LE
DS
1CK
DS
Q
32
22
0LE
DS
1CK
DS
Q
31
21
0LE
DS
1CK
DS
Q
30
20
0LE
DS
1CK
DS
Q
29
14 13 12
S
S
S
17
SQ
32
Vcc
915 37
GND
30 36 43
816 241
OUTPUT
ENABLE
INPUT
SERIAL
DATA
INPUT
PA RA LLEL DA TA OUT PUTS
LO GIC DIAGR AM
OUTPUT FO RMAT
PARALLEL
DATA
OUTPUTS
Q
1
〜Q
32
DATA
SIGNAL
OE
SIGNAL
PARALLEL
DATA
OUTPUTS
Q
1
〜Q
32
DATA
SIGNAL
OE
SIGNAL
SERIAL
DATA
OUTPUT
SQ
32
SERIAL
DATA
OUTPUT
SQ
32
A
5
0LE
DS
1CK
DS
Q
4
Q
4
4
0LE
DS
1CK
DS
Q
3
Q
3
OEOE
11
SSS
10
SSS
3
0LE
DS
1CK
DS
Q
2
Q
2
2
0LE
DS
1CK
DS
Q
1
Q
1
CK
SHIFT
CLOCK
INPUT
LE
LATCH
ENABLE
INPUT
S
D
DIRECT
SET
INPUT
SERI AL DAT A
OUTPUT
23
0LE
DS
1CK
DS
Q
32
Q
32
22
0LE
DS
1CK
DS
Q
31
Q
31
21
0LE
DS
1CK
DS
Q
30
Q
30
20
0LE
DS
1CK
DS
Q
29
Q
29
14 13 12
SS
SSS
SSS
17
SQ
32
Vcc
915 37
Vcc
99 15 37
GND
30 36 433030 3636 4343
816 241 88 16 2411
OUTPUT
ENABLE
INPUT
SERIAL
DATA
INPUT
R8A66162SP
REJ03F0263-0100 Rev.1.00 Jan.24.2008
page 2 of 7
PIN CONFIGURATION ( TOP VIEW )
FUNCTIONAL DESCRIPTION
The employment of silicon gate CMOS process of the R8A66162SP guarantees low power dissipation and
maintains high noise margin as well as high output current and high speed required to drive LEDs.
Each shift register bit consi sts of a flip-flop for shifting and an outp ut latch.
The shift operation takes place when the shift clock input CK changes from lo w-level to high-level.
The serial data input A corresponds to the data input of the first-stage shift register, and the shift register is
shifted in seq uence when a pulse is applied to CK.
If the latch-enable input LE is turned high-level, the content of the shift register at that inst ant is latched.
The parall el data outputs Q1~Q32 are open-drain outputs.
To expand the number of bits, use the serial data output SQ32 which shows the output of the shift register of
the 32nd bit.
If the direct set input SD is turned low-level, Q1~Q32 and SQ32 are set. Then shift register and latches are set.
If the high-level input is applied to the output enable input OE, Q1~Q32 are set to the high-impedance state,
but SQ32 is not set to the high-impedance state. The shift operation is not affected when OE is changed.
PARALLEL
DATA
OUTPUTS
SER IAL D ATA I N PUT
OU TPU T ENABLE INPUT
LATC H EN ABLE IN PU T
DIRECT SET INPUT
SH IF T CLOCK IN PUT
S ERIA L DA TA O UTPUT
PARALLEL
DATA
OUTPUTS
PARALLEL
DATA
OUTPUTS
Q
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
22
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
26
27
25
Q
2
Q
3
Q
4
Q
5
Q
6
A
OE
LE
SD
CK
SQ
32
Q
27
Q
28
Q
29
Q
30
Q
31
Q
32
Q
26
Q
25
Q
24
Q
23
Q
22
GND
Q
21
Q
20
Q
19
Q
18
Q
17
GND
V
CC
Q
16
Q
15
Q
14
Q
13
Q
12
GND
Q
11
Q
10
Q
9
Q
8
Q
7
V
CC
GND
GND
V
CC
GND
GND
PARALLEL
DATA
OUTPUTS
PARALLEL
DATA
OUTPUTS
PARALLEL
DATA
OUTPUTS
PARALLEL
DATA
OUTPUTS
SER IAL D ATA I N PUT
OU TPU T ENABLE INPUT
LATC H EN ABLE IN PU T
DIRECT SET INPUT
SH IF T CLOCK IN PUT
S ERIA L DA TA O UTPUT
PARALLEL
DATA
OUTPUTS
PARALLEL
DATA
OUTPUTS
Q
1
Q
1
Q
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
22
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
26
27
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
22
24
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2323
2222
2424
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
26
27
25
4848
4747
4646
4545
4444
4343
4242
4141
4040
3939
3838
3737
3636
3535
3434
3333
3232
3131
3030
2929
2828
2626
2727
2525
Q
2
Q
2
Q
2
Q
3
Q
3
Q
3
Q
4
Q
4
Q
4
Q
5
Q
5
Q
5
Q
6
Q
6
Q
6
AA
OEOEOE
LELELE
SDSDSD
CKCK
SQ
32
SQ
32
Q
27
Q
27
Q
27
Q
28
Q
28
Q
28
Q
29
Q
29
Q
29
Q
30
Q
30
Q
30
Q
31
Q
31
Q
31
Q
32
Q
32
Q
32
Q
26
Q
26
Q
26
Q
25
Q
25
Q
25
Q
24
Q
24
Q
24
Q
23
Q
23
Q
23
Q
22
Q
22
Q
22
GND
Q
21
Q
21
Q
21
Q
20
Q
20
Q
20
Q
19
Q
19
Q
19
Q
18
Q
18
Q
18
Q
17
Q
17
Q
17
GND
V
CC
Q
16
Q
16
Q
16
Q
15
Q
15
Q
15
Q
14
Q
14
Q
14
Q
13
Q
13
Q
13
Q
12
Q
12
Q
12
GND
Q
11
Q
11
Q
11
Q
10
Q
10
Q
10
Q
9
Q
9
Q
9
Q
8
Q
8
Q
8
Q
7
Q
7
Q
7
V
CC
GND
GND
V
CC
GND
GND
PARALLEL
DATA
OUTPUTS
PARALLEL
DATA
OUTPUTS
PARALLEL
DATA
OUTPUTS
R8A66162SP
REJ03F0263-0100 Rev.1.00 Jan.24.2008
page 3 of 7
FUNCTION TABLE (Note: 1)
ABSOLUTE MA XIMUM RATING S (Ta=-40~85oC, unless otherwise noted)
Symbol Parameter Conditions Ratings Unit
Vcc Supply voltage -0.5~+7.0 V
VI Input voltage -0.5~Vcc+0.5 V
VO Output voltage -0.5~Vcc+0.5 V
Q1~Q32 50 IO Output current per output pin SQ32 ±25 mA
Icc Supply/GND current Vcc, GND -920, +20 mA
Pd Power dissipation 650 mW
Tstg Storage temperature range -65~150 oC
RECOMMENDED OPERATING CONDITIONS (Ta=-40~85oC, unless otherwise noted)
Limits Symbol Parameter Min. Typ. Max.
Unit
5.0V support 4.5 5.0 5.5 V Vcc Supply voltage 3.3V support 3.0 3.3 3.6 V
VI Input voltage 0 Vcc V
VO Output voltage 0 Vcc V
Topr Operating temperature ran ge -40 85 oC
Note 1. ↑
Q
X
q
q
Z
0
：T ransition from low-to-high-level
：Shows the status of output Q before CK input changes
：Irrelevant
：T he content of shift register before C K changes
：T he content of shift register
：High-impedance state
0
OPERATION
MODE
SHIFT
LATCH
INPUT PAR ALLEL OU TPUTS
SERIAL
OUTPUT
SQ
32
CK ASD LE OE Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
Q
9
Q
10
Q
11
Q
12
Q
13
Q
14
Q
15
Q
16
Q
17
Q
18
Q
19
Q
20
Q
21
Q
22
Q
23
Q
24
Q
25
Q
26
Q
27
Q
28
Q
29
Q
30
Q
31
Q
32
H↑LHL
H↑LLL
HXHXL
SET LXXXL LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLH
Q
2
0
Q
3
0
Q
4
0
Q
5
0
Q
6
0
Q
7
0
Q
8
0
Q
9
0
Q
12
0
Q
13
0
Q
14
0
Q
15
0
Q
16
0
Q
17
0
Q
18
0
Q
19
0
Q
20
0
Q
21
0
Q
22
0
Q
23
0
Q
24
0
Q
25
0
Q
26
0
Q
27
0
Q
28
0
Q
29
0
Q
30
0
Q
31
0
q
31
0
Q
2
0
Q
3
0
Q
4
0
Q
5
0
Q
6
0
Q
7
0
Q
8
0
Q
9
0
Q
10
0
Q
11
0
Q
12
0
Q
13
0
Q
14
0
Q
15
0
Q
16
0
Q
17
0
Q
18
0
Q
19
0
Q
20
0
Q
21
0
Q
22
0
Q
23
0
Q
24
0
Q
25
0
Q
26
0
Q
27
0
Q
28
0
Q
29
0
Q
30
0
Q
31
0
q
31
0
L
Z
Z
L
Q
1
0
Q
3
0
Q
4
0
Q
5
0
Q
6
0
Q
7
0
Q
8
0
Q
9
0
Q
10
0
Q
11
0
Q
12
0
Q
13
0
Q
14
0
Q
15
0
Q
16
0
Q
17
0
Q
18
0
Q
19
0
Q
20
0
Q
21
0
Q
22
0
Q
23
0
Q
24
0
Q
25
0
Q
26
0
Q
27
0
Q
28
0
Q
29
0
Q
30
0
Q
31
0
q
32
Q
32
0
L
Q
1
0
Q
1
0
Q
2
0
Z
OUTPUT
DIS-
ABLE XXXXH ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
q
32
Q
10
0
Q
11
0
Note 1. ↑
Q
X
q
q
Z
0
：T ransition from low-to-high-level
：Shows the status of output Q before CK input changes
：Irrelevant
：T he content of shift register before C K changes
：T he content of shift register
：High-impedance state
0
OPERATION
MODE
SHIFT
LATCH
INPUT PAR ALLEL OU TPUTS
SERIAL
OUTPUT
SQ
32
CK ASD LE OE Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
Q
9
Q
10
Q
11
Q
12
Q
13
Q
14
Q
15
Q
16
Q
17
Q
18
Q
19
Q
20
Q
21
Q
22
Q
23
Q
24
Q
25
Q
26
Q
27
Q
28
Q
29
Q
30
Q
31
Q
32
H↑LHL
H↑LLL
HXHXL
SET LXXXL LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLH
Q
2
0
Q
2
0
Q
3
0
Q
3
0
Q
4
0
Q
4
0
Q
5
0
Q
5
0
Q
6
0
Q
6
0
Q
7
0
Q
7
0
Q
8
0
Q
8
0
Q
9
0
Q
9
0
Q
12
0
Q
12
0
Q
13
0
Q
13
0
Q
14
0
Q
14
0
Q
15
0
Q
15
0
Q
16
0
Q
16
0
Q
17
0
Q
17
0
Q
18
0
Q
18
0
Q
19
0
Q
19
0
Q
20
0
Q
20
0
Q
21
0
Q
21
0
Q
22
0
Q
22
0
Q
23
0
Q
23
0
Q
24
0
Q
24
0
Q
25
0
Q
25
0
Q
26
0
Q
26
0
Q
27
0
Q
27
0
Q
28
0
Q
28
0
Q
29
0
Q
29
0
Q
30
0
Q
30
0
Q
31
0
Q
31
0
q
31
0
Q
2
0
Q
2
0
Q
3
0
Q
3
0
Q
4
0
Q
4
0
Q
5
0
Q
5
0
Q
6
0
Q
6
0
Q
7
0
Q
7
0
Q
8
0
Q
8
0
Q
9
0
Q
9
0
Q
10
0
Q
10
0
Q
11
0
Q
11
0
Q
12
0
Q
12
0
Q
13
0
Q
13
0
Q
14
0
Q
14
0
Q
15
0
Q
15
0
Q
16
0
Q
16
0
Q
17
0
Q
17
0
Q
18
0
Q
18
0
Q
19
0
Q
19
0
Q
20
0
Q
20
0
Q
21
0
Q
21
0
Q
22
0
Q
22
0
Q
23
0
Q
23
0
Q
24
0
Q
24
0
Q
25
0
Q
25
0
Q
26
0
Q
26
0
Q
27
0
Q
27
0
Q
28
0
Q
28
0
Q
29
0
Q
29
0
Q
30
0
Q
30
0
Q
31
0
Q
31
0
q
31
0
L
Z
Z
L
Q
1
0
L
Z
Z
L
Q
1
0
Q
1
0
Q
3
0
Q
3
0
Q
4
0
Q
4
0
Q
5
0
Q
5
0
Q
6
0
Q
6
0
Q
7
0
Q
7
0
Q
8
0
Q
8
0
Q
9
0
Q
9
0
Q
10
0
Q
10
0
Q
11
0
Q
11
0
Q
12
0
Q
12
0
Q
13
0
Q
13
0
Q
14
0
Q
14
0
Q
15
0
Q
15
0
Q
16
0
Q
16
0
Q
17
0
Q
17
0
Q
18
0
Q
18
0
Q
19
0
Q
19
0
Q
20
0
Q
20
0
Q
21
0
Q
21
0
Q
22
0
Q
22
0
Q
23
0
Q
23
0
Q
24
0
Q
24
0
Q
25
0
Q
25
0
Q
26
0
Q
26
0
Q
27
0
Q
27
0
Q
28
0
Q
28
0
Q
29
0
Q
29
0
Q
30
0
Q
30
0
Q
31
0
Q
31
0
q
32
Q
32
0
Q
32
0
L
Q
1
0
Q
1
0
Q
2
0
Z
L
Q
1
0
Q
1
0
Q
1
0
Q
1
0
Q
2
0
Q
2
0
Z
OUTPUT
DIS-
ABLE XXXXH ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
q
32
OUTPUT
DIS-
ABLE XXXXH ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
q
32
Q
10
0
Q
10
0
Q
11
0
Q
11
0
R8A66162SP
REJ03F0263-0100 Rev.1.00 Jan.24.2008
page 4 of 7
ELECTRICAL CHARACTERISTICS
■5.0V version support specifications (Ta=-40~85oC, Vcc=4.5V~5.5V, unless otherwise note d)
Limits Symbol
Parameter Test conditions
Min. Typ. Max.
Unit
VT+ Positive going
threshold voltage 0.35xVcc 0.70xVcc V
VT- Negative going
threshold voltage 0.20xVcc 0.55xVcc V
IOH=-20uA Vcc-0.1 VOH High level
output voltage SQ32 V
I=VT+, VT-
Vcc=4.5V IOH=-4mA 3.66 V
IOL=20uA 0.10
IOL=24mA 0.50
Q1~Q32
IOL=28mA 0.55(Note2)
IOL=20uA 0.10
VOL Low level
output voltage
SQ32
VI=VT+, VT-
Vcc=4.5V
IOL=4mA 0.53
V
IIH High level input current VI=Vcc Vcc=5.5V 5 uA
IIL Low level input current VI=GND Vcc=5.5V -5 uA
VO=Vcc 10 IO Maximum
output
leakage current
Q1~Q32
VI=VT+, VT-
Vcc=5.5V VO=GND -10
uA
Icc Quiescent supply current VI=Vcc, GND Vcc=5.5V 400 uA
Note2 : Ta = -40~70oC
■3.3V version support specifications (Ta=-40~85 oC, Vcc=3.0V~3.6V, unless otherwise note d)
Limits Symbol
Parameter Test conditions
Min. Typ. Max.
Unit
VT+ Positive going
threshold voltage 0.35xVcc 0.70xVcc V
VT- Negative going
threshold voltage 0.20xVcc 0.55xVcc V
IOH=-20uA Vcc-0.1 VOH High level
output voltage SQ32 V
I=VT+, VT-
Vcc=3.0V IOH=-2mA 2.60 V
IOL=20uA 0.10 Q1~Q32 IOL=12mA 0.54
IOL=20uA 0.10
VOL Low level
output voltage SQ32
VI=VT+, VT-
Vcc=3.0V
IOL=2mA 0.40
V
IIH High level input current VI=Vcc Vcc=3.6V 5 uA
IIL Low level input current VI=GND Vcc=3.6V -5 uA
VO=Vcc 10 IO Maximum
output
leakage current
Q1~Q32
VI=VT+, VT-
Vcc=3.6V VO=GND -10
uA
Icc Quiescent supply current VI=Vcc, GND Vcc=3.6V 400 uA
R8A66162SP
REJ03F0263-0100 Rev.1.00 Jan.24.2008
page 5 of 7
SWITCHING CHARACTERISTICS (Ta=-40~85 oC, Vcc=5.0V or 3.3V, unless otherwise noted)
5.0V specification 3.3V specification
Symbol Parameter Test
conditions Min. Typ. Max. Min. Typ. Max. Unit
fmax Maximum clock frequency 4 3.3 MHz
tPZL CK-Q1~Q32
(Turned on) 200 220 ns
tPLZ
Output “Z-L” and “L-Z”
propagation time CK-Q1~Q32
(Turned off) 250 270 ns
tPLH 125 150 ns
tPHL Output “L-H” and “H-L”
propagation time CK-SQ32
125 150 ns
tPZL Output “Z-L”
propagation time SD-Q1~Q32
(Turned on) 200 220 ns
tPLH Output “L-H”
propagation time SD-SQ32 125 150 ns
tPZL LE-Q1~Q32
(Turned on) 125 150 ns
tPLZ
Output “Z-L” and “L-Z”
propagation time LE-Q1~Q32
(Turned off) 200 220 ns
tPZL OE-Q1~Q32
(Turned on) 125 150 ns
tPLZ
Output “Z-L” and “L-Z”
propagation time OE-Q1~Q32
(Turned off)
CL=50pF
RL=1kΩ
(Note3)
200 220 ns
CI Input capacitance 10 10 pF
CO Output capacitance OE=Vcc 15 15 pF
TIMING REQUIREMENTS (Ta=-40~85 oC, Vcc=5.0V or 3.3V, unless otherwise noted)
5.0V specification 3.3V specification Symbol Parameter Test
conditions Min. Typ. Max. Min. Typ. Max. Unit
tw CK, LE, SD pulse width 125 150 ns
tsu Setup time A to CK 125 150 ns
Hold time A to CK 15 20 ns th Hold time LE to CK 70 80 ns
trec Recovery time CK to SD
(Note3)
70 80 ns
Note3. Tes t c ircuit
PG
GND
50Ω
INPUT V
CC
C
L
SQ
32
(1) The pulse generator(P G) has the following characteri sti cs(10%~90% ) :t
r
=6ns,t
f
=6ns
(2) The capacitance C
L
includes stray wiring capacitance and the prob e input capacitance.
R
L
V
CC
C
L
Q
1
〜Q
32
DUT
Note3. Tes t c ircuit
PG
GND
50Ω
INPUT V
CC
C
L
SQ
32
C
L
SQ
32
(1) The pulse generator(P G) has the following characteri sti cs(10%~90% ) :t
r
=6ns,t
f
=6ns
(2) The capacitance C
L
includes stray wiring capacitance and the prob e input capacitance.
R
L
V
CC
C
L
Q
1
〜Q
32
R
L
V
CC
C
L
Q
1
〜Q
32
DUT
R8A66162SP
REJ03F0263-0100 Rev.1.00 Jan.24.2008
page 6 of 7
TIMING DIAGRAM
CK
SQ
32
Q
1
〜Q
32
t
w
50% 50% 50%
t
PLH
t
PHL
50% 50%
V
CC
GND
V
OH
V
OL
10%
t
w
t
PLZ
t
PZL
50%
V
OL
〜
〜V
CC
50% 50%
OE
10%
t
PZL
V
OL
V
CC
GND
Q
1
〜Q
32
〜
〜V
CC
50%
t
PLZ
50%
t
PZL
t
PLZ
50%
10%
V
CC
GND
V
OL
V
OL
LE
Q
1
〜Q
32
Q
1
〜Q
32
t
w
50%
〜
〜V
CC
〜
〜V
CC
50%
CK
t
h
V
CC
GND
V
CC
GND
50%
Q
1
〜Q
32
V
OL
〜
〜V
CC
LE
CK
SQ
32
Q
1
〜Q
32
50% 50%
50%
50%
50%
V
CC
GND
V
OH
V
OL
V
CC
GND
V
OL
S
D
t
w
t
rec
t
PLH
t
PZL
〜
〜V
CC
50% 50%
t
su
t
h
50%
CK
AV
CC
GND
V
CC
GND
CK
SQ
32
Q
1
〜Q
32
t
w
50% 50% 50%
t
PLH
t
PHL
50% 50%
V
CC
GND
V
OH
V
OL
10%
t
w
t
PLZ
t
PZL
50%
V
OL
〜
〜V
CC
CK
SQ
32
Q
1
〜Q
32
Q
1
〜Q
32
t
w
50% 50% 50%
t
PLH
t
PHL
50% 50%
V
CC
GND
V
OH
V
OL
10%
t
w
t
PLZ
t
PZL
50%
V
OL
〜
〜V
CC
〜
〜
〜
〜V
CC
50% 50%
OE
10%
t
PZL
V
OL
V
CC
GND
Q
1
〜Q
32
〜
〜V
CC
50%
t
PLZ
50% 50%
OEOE
10%
t
PZL
V
OL
V
CC
GND
Q
1
〜Q
32
Q
1
〜Q
32
〜
〜V
CC
〜
〜
〜
〜V
CC
50%
t
PLZ
50%
t
PZL
t
PLZ
50%
10%
V
CC
GND
V
OL
V
OL
LE
Q
1
〜Q
32
Q
1
〜Q
32
t
w
50%
〜
〜V
CC
〜
〜V
CC
50%
t
PZL
t
PLZ
50%
10%
V
CC
GND
V
OL
V
OL
LELE
Q
1
〜Q
32
Q
1
〜Q
32
Q
1
〜Q
32
Q
1
〜Q
32
t
w
50%
〜
〜V
CC
〜
〜
〜
〜V
CC
〜
〜V
CC
〜
〜
〜
〜V
CC
50%
CK
t
h
V
CC
GND
V
CC
GND
50%
Q
1
〜Q
32
V
OL
〜
〜V
CC
LE
50%
CK
t
h
V
CC
GND
V
CC
GND
50%
Q
1
〜Q
32
Q
1
〜Q
32
V
OL
〜
〜V
CC
〜
〜
〜
〜V
CC
LELE
CK
SQ
32
Q
1
〜Q
32
50% 50%
50%
50%
50%
V
CC
GND
V
OH
V
OL
V
CC
GND
V
OL
S
D
t
w
t
rec
t
PLH
t
PZL
〜
〜V
CC
CK
SQ
32
Q
1
〜Q
32
Q
1
〜Q
32
50% 50%
50%
50%
50%
V
CC
GND
V
OH
V
OL
V
CC
GND
V
OL
S
D
S
D
t
w
t
rec
t
PLH
t
PZL
〜
〜V
CC
〜
〜
〜
〜V
CC
50% 50%
t
su
t
h
50%
CK
AV
CC
GND
V
CC
GND
50% 50%
t
su
t
h
50%
CK
AV
CC
GND
V
CC
GND
R8A66162SP
REJ03F0263-0100 Rev.1.00 Jan.24.2008
page 7 of 7
PACKAGE OUTLINE
Package RENESAS Code Previous Code
48pin SSOP PRSP0048ZB-A 48P2X-A
All trademarks and registered trademarks are the property of their respective owners.
