1/39November 2003
M95640
M95320
64Kbit and 32Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
■Compatible with SPI Bus S erial Interface
(Positive Clock SPI Modes)
■Single Supply Voltage:
– 4.5 to 5.5V for M95xxx
– 2.5 to 5.5V for M95xxx-W
– 1.8 to 5.5V for M95xxx-R
■10MHz, 5MHz or 2MHz clock rate (depending
on ordering options)
■5ms or 10ms Write Time (depending on
ordering opt ions)
■Status Register
■Hardware Protection of the Status Register
■BYTE and PAG E WRIT E (u p to 32 Bytes)
■Self-Tim ed P ro gr a m ming Cycle
■Adjustable Size Read-Only EEPROM Area
■Enhanced E SD Protection
■More than 100,000 or 1 mi llion Erase/ Write
Cycles (depending on ordering options)
■More than 40 Year Data Retention
Figure 1. Packages
PDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
8
1
TSSOP8 (DW)
169 mil width
TSSOP14 (DL)
169 mil width
M95640, M95320
2/39
TABLE OF CONT ENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. L ogic D iagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. DIP and SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. TSSO P 14 Connec tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Se lect (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Bus Master and Memory Dev ices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. SPI Modes Supporte d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power On Reset: VCC Lock-Out Write Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Active Power and Stand-by Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Protection and Protocol Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Write-Protecte d Blo ck Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3/39
M95640, M95320
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Write Enable (WREN) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Write Disable (WRDI) Sequen ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Read Status Register (RDSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Write Status Register (WRSR) Sequen ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Address Range Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Read from Memory Array (READ) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Byte Write (WRITE) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write to Memory Ar ray (WRITE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 15. Pag e Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-up Sta te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
INITIAL DELIVERY STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Operating Conditions (M95xxx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Operating Conditions (M95xxx-W ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Operating Conditi ons (M95xxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3
Table 13. DC Characteristics (M 95xxx, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. DC Characteristics (M 95xxx, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. DC Characteristics (M 95xxx-W, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. DC Characteristics (M 95xxx-W, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. DC Ch aracteristics (M95xxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. AC Characteristics (M95xxx, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
M95640, M95320
4/39
Table 19. AC Characteristics (M95xxx, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. AC Characteristics (M95xxx-W, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. AC Characteristics (M95xxx-W, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22. AC Characteristics (M95xxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Hold Tim ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1
Figure 19. Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PAC KAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20. PDIP 8 – 8 pin Plastic DIP, 0.25mm lead frame, Pac kage Out line . . . . . . . . . . . . . . . . . 33
Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Pac kage Mecha nical Dat a. . . . . . . . . . 33
Figure 21. SO 8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Out line. . . . 34
Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Pac kage Mechanical Data
34
Figure 22. TS SOP 8 – 8 lead Thin Shrink Small Outline, Package Out line . . . . . . . . . . . . . . . . . . . 35
Table 25. TSSOP 8 – 8 lead Thin Shrink Small Outline, Package M echanical Data . . . . . . . . . . . . 35
Figure 23. TS SOP 14 - 14 lead Thin Shrink Small Outline, Package Out lin e . . . . . . . . . . . . . . . . . 36
Table 26. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . 36
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 28. How to Identify Current and Forthcomi ng Products by the Process Identification Letter 37
REVISIO N HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 29. Document Revision Hi story. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5/39
M95640, M95320
SUMMARY DESCRIPTION
These electrical ly erasable program m able mem o-
ry (EEPROM) devices are accessed by a high
speed SPI-compatible bus. The memory array is
organized as 8192 x 8 bit (M95640), and 4096 x 8
bit (M95320) .
The device is accessed by a simple serial interface
that is SPI-compatible. The bus signals are C, D
and Q, as shown in Table 1 and Figure 2.
The device is selected when Chip Select (S) is t ak-
en Low. Communications with the device can be
interrupted using Hold (HOLD).
Figure 2. Logic Diagram
Figure 3. DIP and SO Connections
Note: 1. See page 33 (onwards) for package dimensions, and how
to identify pin-1.
Figu re 4. T S S O P 14 Connec tions
Note: 1. See page 33 (onwards) for package dimensions, and how
to identify pin-1.
2. NC = Not Connected
Table 1. Sign al Names
AI01789C
S
VCC
M95xxx
HOLD
VSS
W
Q
C
D
C Serial Clock
D Serial Data Input
Q Serial Data Outp ut
SChip Select
W Write Protect
HOLD Hold
VCC Supply Voltage
VSS Ground
DVSS C
HOLDQ
SV
CC
W
AI01790D
M95xxx
1
2
3
4
8
7
6
5
1
AI02346C
2
3
4
14
9
10
8DVSS
WC
SHOLD
M95xxx
NC
Q
NC
NC NC
NC
NC
5
6
7
12
13
11
VCC
M95640, M95320
6/39
SIGNAL DESCRIPTION
During all operations, VCC must be held stable and
within the specified valid range: VCC(min) to
VCC(max).
All of the input and output signals must be held
High or Low (according to voltages of VIH, VOH, VIL
or VOL, as specified in Tables 13 to 17). These sig-
nals are described next.
Serial Data O utp ut (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data I n put (D). Thi s input signal is used to
transfer data serial ly into t he device. It receives in-
structions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C). This input signal provides the
timing of the s erial interface. Instructions , address-
es, or data present at Serial Data Input (D) are
latched on the ris ing edge of Serial Clock ( C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an int ernal Write
cycle is in progress, the device will be in the Stand-
by mode. Driving Chip Select (S) Low enables the
device, placing it in the active power m ode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communi cations with the device
without deselecti ng the device.
During the Hold condition, the Serial Data Output
(Q) is hig h impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Ca re.
To start the Hol d condit ion, t he device must be se-
lected, with C hip S ele c t ( S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of m em-
ory that is protect ed agai nst W rite instruct ions (as
specified by the values in the BP 1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and
must be stable during all write operati ons.
7/39
M95640, M95320
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Se l e c t ( S ) goes Low.
All output data bytes are shift ed out of the dev ice,
most significant bit first. The Serial Data Output
(Q) is lat ch ed on the fi rst fa llin g edge of th e Se rial
Clock (C) after the instruction (such as the Read
from Mem ory Array and Read S tatus Register in-
structions) have been cl ocked into the dev ice.
Figure 5 shows three devices, connected to an
MCU, on a SPI bus. Only one dev ice is selected at
a time, so only one device drives the Serial Data
Output (Q) li ne at a t im e, all the others being h igh
impedance.
Figure 5. Bus Master and Memo ry Devi ces on the SPI Bus
No te : 1. The Write Protect (W) and Hold (H O LD) signals should be dr iven, Hi gh or Lo w as appropriate.
SPI Mode s
These dev ices can be drive n by a microcont roller
with its SPI peripheral running in ei ther of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 6, is the clock polarity when the bus mas-
ter is in Stand-by mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
AI03746D
Bus Master
(ST6, ST7, ST9,
ST10, Others) SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
M95640, M95320
8/39
Figu re 6. S PI Modes S up ported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
9/39
M95640, M95320
OPERATING FEATURES
Power-up
When the power supply is turned on, VCC rises
fro m V SS to VCC.
During this time, the Chip Select (S) must be al-
lowed to follow the VCC vol tage . It mu st not be al-
lowed to float, but should be connected to VCC via
a suitable pull-up resistor.
As a built in safety feat ure, Chip Selec t (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has fi rst been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first op-
eration.
Po wer On Reset: VCC Lock-Out Wr i te Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until VCC has reached the POR
threshold value, and all opera tions are disab led –
the device will not respond to any command. In the
same way, when VCC drops from the operating
voltage, below the POR threshold value , all oper-
ations are disabled and the device will not respond
to any command.
A stable and valid VCC must be applied before ap-
plying any logic signal.
Power-down
At Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage appli ed on VCC.
Active Power and Stand-by Power M odes
When Chip Select (S) is Low, the device is en-
abled, and in the Activ e Power mode. The dev ice
consume s ICC, as spe cified in T ables 13 to 17.
When Chip Select (S) is High, the device is dis-
abled. If an Erase/Write cycle is not currently in
progress, the device then goes in to the St and-by
Power mode, and the device consumption drops
to I CC1.
Hold Conditio n
The Hold (HOLD) signal is used to pause any se-
rial comm unication s with the device without reset-
ting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is hig h impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Ca re.
To enter the Hold condition, the device must be
sele c te d , wit h C h ip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of t he Hold condition. Deselecting the de-
vice while it is in the Hold c ondition, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
The Hold condition starts wh en the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low (as shown in Figure
7).
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.
Figure 7 also shows what happens if the rising and
falling edges are not timed to coincide with Serial
Clock (C) bei ng Low.
Figure 7. Hold Conditio n Activation
AI02029D
HOLD
C
Hold
Condition Hold
Condition
M95640, M95320
10/39
Status Register
Figure 8 shows the pos ition of the St atus Register
in the control logic o f the device. The Status Reg-
ister contains a number of status and control bits
that can be read or set (as appropriate) by speci fic
instructions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Regist er cycle.
WEL bit. The W ri te Enable Latch (WEL) bit indi-
cates the status of the int ernal Write Enable Lat ch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bit s
are non-volatile. They define the size of the area to
be software p rotected again st Write instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-v ol atile bits
of t he Status Register (SRWD, BP1, BP0) become
read-only bits.
Table 2. Status Register Format
Data Protection and Protocol Control
Non-volatile memory devi ces can be used in envi-
ronments that are particular ly noisy, and wi thin ap-
plications that could experience problems if
memory bytes are corrupted. Consequently, the
device features the following data protection
mechanisms:
■Write and Write Status Register instructions are
checked that they consist of a number of clock
pulses that is a multiple of eight, before they are
accepted for execution.
■All instructions that modify data mus t be
preceded by a Write Enable (WREN) instruction
to set the Write Enable Latch (WEL) bit . This bit
is returned to its reset state by the following
events:
– Power-up
– W rite Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction
completion
– W rite (WRITE) instruction completion
■The Bl ock Protect (B P1, BP0) bits al l ow part of
the memory to be configured as read-only. This
is the Software Protected Mode (SPM).
■The Write Protect (W) sign al allows the Block
Protect (BP1, BP0) bits to be protected . This is
the Hardware Protected Mode (HPM).
For any instruct ion to be acc epted, and executed,
Chip Select (S) must be driven High aft er the rising
edge of Serial Clock (C) for the last bit of the in-
struction, and bef ore the next rising edge of Serial
Clock (C).
Two point s need to be noted in the p revious s en-
tence:
– Th e ‘last bit of the instruction’ can be the eighth
bit of the i nstruction cod e, or the eig hth bit of a
data b yte, depending on th e i nstruction (except
for Read Status Register (RDSR) and Read
(READ) instructions).
– The ‘next rising edge of Serial Clock (C)’ might
(or might not) be the next bus transaction for
some other device on the SPI bus.
Table 3. W rite-Protected Block Size
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
Status Regis ter Bits Protected Block Array Addresses Protected
BP1 BP0 M95640 M95320
0 0 none none none
0 1 Upper quarter 1800h - 1FFFh 0C00h - 0FFFh
1 0 Upper half 1000h - 1FFFh 0800h - 0FFFh
1 1 Whole memory 0000h - 1FFFh 0000h - 0FFFh
M95640, M95320
12/39
INSTRUCTIONS
Each instruction starts with a single-b yte code, as
summarized in Table 4.
If an inval id instruction is sent (on e not con tained
in Table 4), the device automatically deselects it-
self.
Table 4. Instructi on Set
Figure 9. Write Enable (WREN) S eq uen ce
Write Enable (WREN)
The Write Enabl e Latch (WEL) bi t must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the d evice.
As shown in Figure 9, to send this instruction to the
device, Chip Select (S) is driven Low, and the bits
of the inst ruction byte are shifted in, on Serial Data
Input (D). The device then enters a wait state. It
waits for a the device to be deselected, by Chip
Se l e c t ( S ) being driven High.
Instruc
tion Description Instruction
Format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
13/39
M95640, M95320
Figure 10. Write Disable (WRDI) S equence
Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 10, to send this instruction to
the de v ic e, C hip S elec t ( S ) i s driven Lo w, a nd the
bits of the instru ction byte are shifte d in, on Serial
Data Input (D).
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
– Power-up
– WRDI instruction execut ion
– WR S R in s t ru ctio n co m p let io n
– WRITE inst ruction completion.
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M95640, M95320
14/39
Figure 11. Read Status Register (RDSR) Sequen ce
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Write or Wri te St at us Reg ister cycle is in progress.
When one of these cycles is in progress, it is rec-
ommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register con-
tinuously, as shown in Figure 11.
The status a nd control bits of the S tatus Regi ster
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The W ri te Enable Latch (WEL) bit indi-
cates the status of the int ernal Write Enable Lat ch.
When set to 1 the internal Write Enable Latch is
set, whe n set to 0 the i nternal Write Enabl e Latc h
is reset and no Write o r W rite Status Register in-
struction i s accepted.
BP1, BP0 bits. The Block Protect (BP1, BP0) bit s
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are wri tten with t he Write St atus Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in Table 2) be-
comes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protect-
ed mode has not been set.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) be-
come read-only bit s and the Write Status Register
(WRSR) instruction is no longer accepted for exe-
cution.
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
15/39
M95640, M95320
Figure 12. Write Status Register (WRSR) Sequence
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction al-
lows new val ues to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Wri te Enable (WREN) instruction
has been d ecoded and ex ecuted, the de vice se ts
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the dat a byt e on Serial
Data Input (D).
The instruct ion sequence is shown in Figure 12.
The Write Stat us Register (WRSR) instruct ion has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are alway s read as 0.
Chip Select (S) must be driven High aft er the rising
edge of Serial Clock (C) that latches in the eighth
bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status
Register (WRSR) instruction is not executed. As
soon as Chip Select (S) is driven High, the self-
timed Write Status Register cycle (whose d ur a tion
is tW) is initiated. While the Write Status Register
cycle is in progress, the Status Register may still
be read to check the value of t he Write In Progress
(WIP) bit. T he Wri te In Progress (WIP) bit i s 1 dur-
ing the sel f-timed Write Status Register cycle, and
is 0 when it is c ompleted. When the cycle is com-
pleted, the Write Ena ble Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that i s to be treated as rea d-only, as defined
in Table 2.
The Write Status Register (WRSR) instruction also
allows the us er to s et or res et the S tatus Regi ster
Write Disable (SRWD ) bit in accordance with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected Mode (HPM). The Writ e Status Register
(WRSR) instruction is not executed once the Hard-
ware Protected Mode (HPM) is entered.
The contents of the Status Register Write Di sa ble
(SRWD) and Block Protect (BP1, BP0) bit s are fro-
zen at their current values from just before the
start of the execution of Write Status Register
(WRSR) instruction. The new, updated, values
take effect at the moment of complet ion of the ex-
ecution of Write Sta tus Register (WRSR) instruc-
tion.
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
M95640, M95320
16/39
Table 5. Pro tection M ode s
Note: 1. As defi ned by th e values in the Block Pr otect (B P1, BP0) bi ts o f the St at us Regi st er, as shown in Table 3.
The protection feat ures of t he de vic e are su mma-
rized in T able 3.
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Regi ster
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, rega rdless of th e whether W rite Protect
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered , depending on the state of
Write Protect (W):
– If Write Protect (W) is driven Hi gh, it is possible
to write to the Status Regis ter provided that the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
– If Write Protec t (W) is driven Low, it is
not
pos-
sible to write to the Status Register
even
if the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
(Attempts t o write to the Status Register are re-
jected, and are no t accepted for ex ecution). As
a consequence, all the data bytes in the memo-
ry area that are sof tware protected (SPM) by the
Block Protect (BP1, BP0) bits of the Status Reg-
ister, are also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be ent ered:
– by setting the Status Register Write Disable
(SRWD) bi t after driving Writ e Protect (W) Low
– or by driving Wri te Protect (W) Low aft er setting
the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using t he Bloc k Protect (B P1, BP0) bi ts of
the Stat us Register, can be used.
Table 6. Address Rang e Bits
Note: 1. b15 to b13 are Don’t Care on the M95640.
b15 to b12 are Don’t Care on the M95320.
W
Signal SRWD
Bit Mode Write Protection of the
Status Register
Memory Content
Protected Area1Unprotected Area1
10
Software
Protected
(SPM)
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
The values in the BP1
and BP0 bits can be
changed
Write Protected Ready to accept Write
instructions
00
11
01
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the BP1
and BP0 bits cannot be
changed
Write Protected Ready to accept Write
instructions
Device M95640 M95320
Address Bits A12-A0 A11-A0
17/39
M95640, M95320
Figure 13. Read from Memory Array (READ) Sequence
Note: Dep ending on the memory s i ze, as shown in T abl e 6 , t he m ost sign i ficant addres s bits are Do n’ t Care.
Read from Memory Array (READ)
As shown in Figure 13, to send this instruction to
th e device , Chip Se l e ct (S) is first dri ven Low. The
bits of the instruction byte and add ress bytes are
then shifted in, on Serial Data Input (D). The ad-
dress is loaded into an internal address register,
and the byte of data at that address is s hifte d out,
on Serial Dat a Output (Q).
If Chip Select (S) continues to be driven Low, the
internal address register is automatically incre-
mented, and the byte of data at the new address is
shifted out.
When the highes t address is reached, the address
counter rolls over to zero, allowing the Read cycle
to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruc-
tion.
The Read cycle is terminated b y driving Chip Se-
lect (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not execut-
ed, if a Write cycle is currentl y in progress.
C
D
AI01793D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
76543 1 7
0
High Impedance Data Out 1
Instruction 16-Bit Address
0
MSB
MSB
2
31
Data Out 2
M95640, M95320
18/39
Figure 14. Byte Write (WRI TE) Sequence
Note: Dep ending on the memory s i ze, as shown in T abl e 6 , t he m ost sign i ficant addres s bits are Do n’ t Care.
Wr ite to Memory Array (WRITE)
As shown in Figure 14, to send this instruction to
th e device , Chip Se l e ct (S) is first dri ven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S ) High at a byt e boundary of the input data.
In the case of Figure 14, this occurs after the
eighth bit of the data byte ha s been l atched in, in-
dicating that the instruction is being used to write
a single byte. The self-timed Write cycle starts,
and continues for a period tWC (as specif ied i n Ta-
bles 18 to 22), at the end of which the Write in
Progress (WIP) bit i s reset to 0.
If, though, Chip Select (S) continues to be driven
Low, as shown in Figure 15, the next byte of input
data i s s hifted in , s o that m ore than a sin gle by te,
starting from the given address towards the end of
the same page, can be written in a single intern al
Write cycl e.
Each time a new data byte is shifted in, the least
significant bits of the in ternal addres s coun ter are
incremented. If the number of data bytes sent to
the device exceeds t he page b oundary, t he inter-
nal address counter ro lls over to t he beginni ng of
the page, and the previous data there are overwrit-
ten with the incoming data. (The page size of
these de v ice s i s 32 bytes).
The instruction is not accepted, and is not execut-
ed, under the following conditions:
– if the Write Enable Latch (WEL) bit has not been
set to 1 (by executing a Write Enable instruction
just before)
– if a Write cycl e is already in progress
– if the device has not been deselected, by Chip
Select (S) being driven High, at a byte boundary
(after the ei ghth bit , b0, of the last dat a byt e t hat
has been latched in)
– if the addres sed page is in th e region p rotected
by the Block Protect (BP1 and BP0) bit s.
C
D
AI01795D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
High Impedance
Instruction 16-Bit Address
0
765432 0
1
Data Byte
31
19/39
M95640, M95320
Figure 15. P age Write (WRITE) Sequence
Note: Dep ending on the memory s i ze, as shown in T abl e 6 , t he m ost sign i ficant addres s bits are Do n’ t Care.
C
D
AI01796D
S
3433 35 36 37 38 39 40 41 42 44 45 46 4732
C
D
S
15
21 345678910 2021222324252627
1413 3210
28 29 30
Instruction 16-Bit Address
0
765432 0
1
Data Byte 1
31
43
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3
65432 0
1
Data Byte N
M95640, M95320
20/39
POWER-UP AND DELIVER Y STATE
Power-u p State
After Power-up, the device is in the following state:
– Stand-by mode
– deselected (after Power-up, a falling edge is re-
quired on Chip Select (S) before any instruc-
tions can be started).
– not in the Hold Condition
– the Writ e Enable Latch (WEL) is reset to 0
– Write In Progress (WIP) is reset to 0
the SRWD, BP1 and BP0 bits of the Status Regis-
ter are u nchanged from th e pre vious power-down
(they are non-volatile bits).
INITIAL DELIVERY STATE
The device is delivered with the memory array set
at all 1s (FFh). The Status Register Write Disable
(SRWD) and Block Protect (BP1 and BP0) bits are
initia l iz e d to 0 .
21/39
M95640, M95320
MAX I MUM R A TI N G
Stressing the device ab ove t he rati ng l isted in t he
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at t hes e or
any other con ditions ab ove those i ndicated i n the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 7. Absolute Maximum Ratings
No te : 1. Compliant wi th the ECOPAC K® 71 91395 specifii cation for lead-free so l dering pr ocesse s
2. No longer than 10 seconds
3. Not ex ceedin g 250°C for more than 30 se conds, and peaking at 260°C
4. JE DEC Std J ESD22-A114A (C1=100 pF , R1=1500 Ω, R2=500 Ω)
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering1PDIP
SO
TSSOP
2602
2603
2603°C
VOOutput Voltage –0.45 VCC+0.6 V
VIInput Voltage –0.45 6.5 V
VCC Supply Voltage –0.3 6.5 V
VESD Electrostatic Discharge Voltage (Human Body model) 4–4000 4000 V
M95640, M95320
22/39
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Des igners shoul d c heck that the operating
conditions i n their circuit match the meas urement
conditions when relying on the quoted parame-
ters.
Table 8. Oper ating Condi tions (M95xxx)
Table 9. Operating Conditions (M95 xxx -W)
Table 10. Oper ating Condi tions (M95xxx-R)
No te : 1. This product is u nder development. For more informa tion, pl ease contact you r nearest ST sales office.
Table 11. AC Measuremen t Condition s
Note: 1. Output Hi-Z i s defined as the point where data out is no l onger dri ven.
Figure 16. AC Measurement I/O Waveform
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
TAAmbient Operating Temperature (range 6) –40 85 °C
Ambient Operating Temperature (range 3) –40 125 °C
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.5 5.5 V
TAAmbient Operating Temperature (range 6) –40 85 °C
Ambient Operating Temperature (range 3) –40 125 °C
Symbol Parameter1Min. Max. Unit
VCC Supply Voltage 1.8 5.5 V
TAAmbient Operati ng Tem peratur e –40 85 ° C
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 100 pF
Input Rise and Fall Times 50 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC V
AI00825B
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
23/39
M95640, M95320
Table 12. Capacitance
Note: S am pled o nl y, not 100% tested , at TA=25°C an d a frequency of 5 M Hz.
Table 13. DC Characteristics ( M 95xxx, temperature range 6)
No te : 1. For all 5V range device s, the device meets the output requ i rem ents f or both TT L and CMOS standa rds.
2. Current product: identified by Process Identification letter S.
3. New product : id entified by Process Iden t ifi cation l et ter V.
Symbol Parameter Test Condition Min.Max.Unit
COUT Output Capacitance (Q) VOUT = 0V 8 pF
CIN Input Capacitance (D) VIN = 0V 8 pF
Input Capacitance (other pins) VIN = 0V 6 pF
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leak age Curren t S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Curre nt
C = 0.1VCC/0.9VCC at 5MHz,
VCC = 5 V, Q = open, Current Product 2 4mA
C=0.1V
CC/0.9VCC at 10MHz,
VCC = 5 V, Q = open, New Product 3 5mA
ICC1 Supply Curre nt
(Stand-by)
S = VCC , VCC = 5 V,
VIN = VSS or VCC, Current Product 2 10 µA
S = VCC , VCC = 5 V,
VIN = VSS or VCC, New Product 3 2µA
VIL Input Low Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC+1 V
VOL1Output Low Voltage IOL = 2 mA, VCC = 5 V 0.4 V
VOH1O utput High Volta ge IOH = –2 mA, VCC = 5V 0.8V
CC V
M95640, M95320
24/39
Table 14. DC Characteristics (M95xxx, temperature range 3)
No te : 1. For all 5V range device s, the device meets the output requ i rem ents f or both TT L and CMOS standa rds.
2. Current product: identified by Process Identification letter S.
3. New product : id entified by Process Iden t ifi cation l et ter B.
Table 15. DC Characteristics (M95xxx-W, temperature ran ge 6)
Note: 1. Current product: identified by Process Identification letter S.
2. New product : id entified by Process Iden t ifi cation l et ter V.
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leak age Curren t S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Curre nt
C=0.1V
CC/0.9VCC at 2 MHz,
VCC = 5 V, Q = open, Current Product 2 2mA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 5 V, Q = open, New Product 3 4mA
ICC1 Supply Curre nt
(Stand-by)
S = VCC , VCC = 5 V,
VIN = VSS or VCC, Current Product 2 20 µA
S = VCC , VCC = 5 V,
VIN = VSS or VCC, New Product 3 5µA
VIL Input Low Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC+1 V
VOL1Output Low Voltage IOL = 2 mA, VCC = 5 V 0.4 V
VOH1O utput High Volta ge IOH = –2 mA, VCC = 5V 0.8V
CC V
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leak age Curren t S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Curre nt
C=0.1V
CC/0.9VCC at 2 MHz,
VCC = 2.5 V, Q = open, Current Product 1 2mA
C=0.1V
CC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open, New Product 2 3mA
ICC1 Supply Curre nt
(Stand-by)
S = VCC , VCC = 2.5 V,
VIN = VSS or VCC, Current Product 1 2µA
S
= VCC , VCC = 2.5 V
VIN = VSS or VCC, New Product 2 1µA
VIL Input Low Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC+1 V
VOL Output Low Vo ltage IOL = 1.5 mA, VCC = 2.5 V 0.4 V
VOH O utput High Volta ge IOH = –0.4 mA, VCC = 2.5 V 0.8 VCC V
25/39
M95640, M95320
Table 16. DC Characteristics (M95 xxx-W, temperatu re rang e 3)
Note: New product: identified by Process Identification letter B.
Table 17. DC Characteristics (M95xxx-R)
Not e: 1. This product is under qualification. For more infomation, please contact your nearest ST sales office.
2. P relimin ary data.
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leak age Curren t S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Curre nt C=0.1V
CC/0.9VCC at 5 MHz,
VCC= 2.5 V, Q = o pen 3mA
ICC1 Supply Curre nt
(Stand-by) S = VCC , VCC = 2.5 V, VIN = VSS or VCC 2µA
VIL Input Low Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC+1 V
VOL Output Low Vo ltage IOL = 1.5 mA, VCC = 2.5 V 0.4 V
VOH O utput High Volta ge IOH = –0.4 mA, VCC = 2.5 V 0.8 VCC V
Symbol Parameter Test Condition1Min.2Max.2Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leak age Curren t S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Curre nt C = 0.1VCC/0.9VCC at 2 MHz,
VCC= 1.8 V, Q = o pen 1mA
ICC1 Supply Curre nt
(Stand-by) S = VCC, VIN = VSS or VCC , VCC = 1.8 V 1µA
V
IL Input Low Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC+1 V
VOL Output Low Vo ltage IOL = 0.15 mA, VCC = 1.8 V 0.3 V
VOH Output High Voltage IOH = –0.1 mA, VCC = 1.8 V 0.8 VCC V
M95640, M95320
26/39
Table 18. AC Characteristics (M95xxx, temperature range 6)
Note: 1. tCH + tCL ≥ 1 / fC.
2. Value guaranteed by charact erization, not 100% tested in production.
3. Current product: identified by Process Identification letter S.
4. New product : id entified by Process Iden t ifi cation l et ter V .
Test conditions specified in Table 11 and Table 8
Symbol Alt. Parameter Min.3Max.3Min.4Max.4Unit
fCfSCK Clock Frequency D.C. 5 D.C. 10 MHz
tSLCH tCSS1 S Active Setup Time 90 15 ns
tSHCH tCSS2 S Not Active Setup Time 90 15 ns
tSHSL tCS S Deselect Time 100 40 ns
tCHSH tCSH S Active Hold Time 90 25 ns
tCHSL S Not Active Hold Time 90 15 ns
tCH 1tCLH Clock High Time 90 40 ns
tCL 1tCLL Clock Low Time 90 40 ns
tCLCH 2tRC Clock Rise Time 1 1 µs
tCHCL 2tFC Clock Fall Time 1 1 µs
tDVCH tDSU Data In Setup Time 20 15 ns
tCHDX tDH Data In Hold Time 30 15 ns
tHHCH Clock Low Hold Time after HOLD not Active 70 15 ns
tHLCH Clock Low Hold Time after HOLD Active 40 20 ns
tCHHL Clock High Set-up Time before HOLD Active 60 30 ns
tCHHH Clock High Set-up Time before HOLD not
Active 60 30 ns
tSHQZ 2tDIS Output Disable Time 100 25 ns
tCLQV tVClock Low to Output Valid 60 25 ns
tCLQX tHO Output Hold Time 0 0 ns
tQLQH 2tRO Output Rise Time 50 20 ns
tQHQL 2tFO Output Fall Time 50 20 ns
tHHQX 2tLZ HOLD High to Output Low-Z 50 25 ns
tHLQZ 2tHZ HOLD Low to Output High-Z 100 25 ns
tWtWC Write Time 10 5 ms
27/39
M95640, M95320
Table 19. AC Characteristics (M95xxx, temperature range 3)
Note: 1. tCH + tCL ≥ 1 / fC.
2. Value guaranteed by charact erization, not 100% tested in production.
3. Current product: identified by Process Identification letter S.
4. New product : id entified by Process Iden t ifi cation l et ter B .
Test conditions specified in Table 11 and Table 8
Symbol Alt. Parameter Min.3Max.3Min.4Max.4Unit
fCfSCK Clock Frequency D.C. 2 D.C. 5 MHz
tSLCH tCSS1 S Active Setup Time 200 90 ns
tSHCH tCSS2 S Not Active Setup Time 200 90 ns
tSHSL tCS S Deselect Time 200 100 ns
tCHSH tCSH S Active Hold Time 200 90 ns
tCHSL S Not Active Hold Time 200 90 ns
tCH 1tCLH Clock High Time 200 90 ns
tCL 1tCLL Clock Low Time 200 90 ns
tCLCH 2tRC Clock Rise Time 1 1 µs
tCHCL 2tFC Clock Fall Time 1 1 µs
tDVCH tDSU Data In Setup Time 40 20 ns
tCHDX tDH Data In Hold Time 50 30 ns
tHHCH Clock Low Hold Time after HOLD not Active 140 70 ns
tHLCH Clock Low Hold Time after HOLD Active 90 40 ns
tCHHL Clock High Set-up Time before HOLD Active 120 70 ns
tCHHH Clock High Set-up Time before HOLD not
Active 120 70 ns
tSHQZ 2tDIS Output Disable Time 250 100 ns
tCLQV tVClock Low to Output Valid 150 60 ns
tCLQX tHO Output Hold Time 0 0 ns
tQLQH 2tRO Output Rise Time 100 50 ns
tQHQL 2tFO Output Fall Time 100 50 ns
tHHQX 2tLZ HOLD High to Output Low-Z 100 50 ns
tHLQZ 2tHZ HOLD Low to Output High-Z 250 100 ns
tWtWC Write Time 10 5 ms
M95640, M95320
28/39
Table 20. AC Characteristics (M95xxx-W, temperature range 6)
Note: 1. tCH + tCL ≥ 1 / fC.
2. Value guaranteed by charact erization, not 100% tested in production.
3. Current product: identified by Process Identification letter S.
4. New product : id entified by Process Iden t ifi cation l et ter V .
Test conditions specified in Table 11 and Table 9
Symbol Alt. Parameter Min.3Max.3Min.4Max.4Unit
fCfSCK Clock Frequency D.C. 2 D.C. 5 MHz
tSLCH tCSS1 S Active Setup Time 200 90 ns
tSHCH tCSS2 S Not Active Setup Time 200 90 ns
tSHSL tCS S Deselect Time 200 100 ns
tCHSH tCSH S Active Hold Time 200 90 ns
tCHSL S Not Active Hold Time 200 90 ns
tCH 1tCLH Clock High Time 200 90 ns
tCL 1tCLL Clock Low Time 200 90 ns
tCLCH 2tRC Clock Rise Time 1 1 µs
tCHCL 2tFC Clock Fall Time 1 1 µs
tDVCH tDSU Data In Setup Time 40 20 ns
tCHDX tDH Data In Hold Time 50 30 ns
tHHCH Clock Low Hold Time after HOLD not Active 140 70 ns
tHLCH Clock Low Hold Time after HOLD Active 90 40 ns
tCHHL Clock High Set-up Time before HOLD Active 120 60 ns
tCHHH Clock High Set-up Time before HOLD not
Active 120 60 ns
tSHQZ 2tDIS Output Disable Time 250 100 ns
tCLQV tVClock Low to Output Valid 150 60 ns
tCLQX tHO Output Hold Time 0 0 ns
tQLQH 2tRO Output Rise Time 100 50 ns
tQHQL 2tFO Output Fall Time 100 50 ns
tHHQX 2tLZ HOLD High to Output Low-Z 100 50 ns
tHLQZ 2tHZ HOLD Low to Output High-Z 250 100 ns
tWtWC Write Time 10 5 ms
29/39
M95640, M95320
Table 21. AC Characteristics (M95xxx-W, temperature range 3)
Note: 1. tCH + tCL ≥ 1 / fC.
2. Value guaranteed by charact erization, not 100% tested in production.
3. New product : id entified by Process Iden t ifi cation l et ter B.
Test conditions specified in Table 11 and Table 9
Symbol Alt. Parameter Min. Max. Unit
fCfSCK Cl ock Frequen cy D.C. 5 MHz
tSLCH tCSS1 S Active Setup Time 90 ns
tSHCH tCSS2 S Not Active Setup Time 90 ns
tSHSL tCS S Deselect Time 100 ns
tCHSH tCSH S Active Hold Time 90 ns
tCHSL S Not Active Hold Time 90 ns
tCH 1tCLH Clock High Time 90 ns
tCL 1tCLL Clock Low Time 90 ns
tCLCH 2tRC Clock Rise Time 1 µs
tCHCL 2tFC Clock Fall Time 1 µs
tDVCH tDSU Data In Setup Time 20 ns
tCHDX tDH Data In Hold Time 30 ns
tHHCH Clock Low Hold Time after HOLD not Active 70 ns
tHLCH Clock Low Hold Time after HOLD Active 40 ns
tCHHL Clock High Set-up Time before HOLD Active 60 ns
tCHHH Clock High Set-up Time before HOLD not Active 60 ns
tSHQZ 2tDIS Output Disable Time 100 ns
tCLQV tVClock Low to Output Valid 60 ns
tCLQX tHO O utput Hold Time 0 ns
tQLQH 2tRO O utput Rise Time 50 ns
tQHQL 2tFO O utput Fall Time 50 ns
tHHQX 2tLZ HOLD High to Output Low-Z 50 ns
tHLQZ 2tHZ HOLD Low to Output High-Z 100 ns
tWtWC Write Time 5 ms
M95640, M95320
30/39
Table 22. AC Characteristics (M95xxx-R)
Note: 1. tCH + tCL ≥ 1 / fC.
2. Value guaranteed by charact erization, not 100% tested in production.
3. Prelimi nary dat a: this product is un der q ualific ation. For more infom ation, please contact your nearest ST sales off i ce.
Test conditions specified in Table 11 and Table 10
Symbol Alt. Parameter Min.3Max.3Unit
fCfSCK Cl ock Frequen cy D.C. 2 MHz
tSLCH tCSS1 S Active Setup Time 200 ns
tSHCH tCSS2 S Not Active Setup Time 200 ns
tSHSL tCS S Deselect Time 200 ns
tCHSH tCSH S Active Hold Time 200 ns
tCHSL S Not Active Hold Time 200 ns
tCH 1tCLH Clock High Time 200 ns
tCL 1tCLL Clock Low Time 200 ns
tCLCH 2tRC Clock Rise Time 1 µs
tCHCL 2tFC Clock Fall Time 1 µs
tDVCH tDSU Data In Setup Time 40 ns
tCHDX tDH Data In Hold Time 50 ns
tHHCH Clock Low Hold Time after HOLD not Active 140 ns
tHLCH Clock Low Hold Time after HOLD Active 90 ns
tCHHL Clock High Set-up Time before HOLD Active 120 ns
tCHHH Clock High Set-up Time before HOLD not Active 120 ns
tSHQZ 2tDIS Output Disable Time 250 ns
tCLQV tVClock Low to Output Valid 150 ns
tCLQX tHO O utput Hold Time 0 ns
tQLQH 2tRO O utput Rise Time 100 ns
tQHQL 2tFO O utput Fall Time 100 ns
tHHQX 2tLZ HOLD High to Output Low-Z 100 ns
tHLQZ 2tHZ HOLD Low to Output High-Z 250 ns
tWtWC Write Time 10 ms
31/39
M95640, M95320
Figure 17. S erial Input Timing
Figu re 18 . H ol d Timing
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
Q
AI02032
S
D
HOLD
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
M95640, M95320
32/39
Figure 19. Output Timing
C
Q
AI01449D
S
LSB OUT
DADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
33/39
M95640, M95320
PACKAGE MECHANICAL
Figure 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead fram e, Packag e Outline
No te s: 1. Drawing is not to scal e.
Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package M ech ani cal Data
PDIP-B
A2
A1
A
L
be
D
E1
8
1
c
eA
b2
eB
E
Symb. mm inches
Typ. Min. Max. Typ. Min. Max.
A 5.33 0.210
A1 0.38 0.015
A2 3.30 2.92 4.95 0.130 0.115 0.195
b 0.46 0.36 0.56 0.018 0.014 0.022
b2 1.52 1.14 1.78 0.060 0.045 0.070
c 0.25 0.20 0.36 0.010 0.008 0.014
D 9.27 9.02 10.16 0.365 0.355 0.400
E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7.11 0.250 0.240 0.280
e 2.54 – – 0.100 – –
eA 7.62 – – 0.300 – –
eB 10.92 0.430
L 3.30 2.92 3.81 0.130 0.115 0.150
M95640, M95320
34/39
Figure 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body wi dth , Packag e Outline
Not e: Drawing is not to scale.
Table 24. SO8 narrow – 8 l ead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Symb. mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α0° 8° 0° 8°
N8 8
CP 0.10 0.004
SO-a
E
N
CP
Be
A
D
C
LA1 α
1H
h x 45˚
35/39
M95640, M95320
Figure 22. TSSOP8 – 8 lead Thin Shrink Sm all Outline, Package Ou tline
No te s: 1. Drawing is not to scal e.
Table 25. TSSOP8 – 8 lead Thin Sh rink Small Outline, Package Mechanical Data
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
Symbol mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α0° 8° 0° 8°
M95640, M95320
36/39
Figure 23. TS SOP 14 - 14 lead Thin Shri nk Small Outli ne, Pack age Ou tline
No te s: 1. Drawing is not to scal e.
Table 26. TS SO P 14 - 14 lead Thin Shrink Small Outline, Packag e Mechani cal D ata
TSSOP14-M
1
14
CP
c
L
EE1
D
A2A
α
eb
7
8
A1
L1
Symbol mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 5.000 4.900 5.100 0.1969 0.1929 0.2008
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.500 0.750 0.0236 0.0197 0.0295
L1 1.000 0.0394
α0° 8° 0° 8°
37/39
M95640, M95320
PAR T NUMBERING
Table 27. Ordering Information Scheme
Not e: 1. Devices bearing the process identification letter “B” or “V” in the package marking (on the top side of the package, on the right side),
guarantee more than 1 million E rase/Writ e cycle endurance (see Table 28, below). For more information about these dev ices, and
their device i dentification, please contact your n earest ST sales off i ce, and ask for the Product C hange Not i ce.
For a list of available options (speed, package,
etc.) or for further information on any aspect of this device, please con tact your nearest ST Sales O f-
fice.
Table 28. How to Identify Current and Forthcomin g Products by the Pr ocess Identificati on Letter
Note: 1. For furth er informati on, please ask your S T Sales Of fice f or Pr ocess Change Not i ce PC N MPG/EE/0 053 (PCEE0053) and M PG/
EE/0054 (PC EE005 4).
Example: M95320 – W MN 6 T P
Device Type
M95 = SPI serial access EEPROM
Device Function 1
640 = 64 Kbit (8192 x 8)
320 = 32 Kbit (4096 x 8)
Operating Voltage
blank = VCC = 4.5 to 5.5V
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
DL = TSSOP14 (169 mil width)
Temperature Range
6 = –40 to 85 °C
3 = –40 to 125 °C
Option
blank = Standard Packing
T = Tape & Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Pb-free plating
G = Green pack
Markings on Current Products1Markings on New Products1
95640 6 (or 95640W6)
xxxxS95640 6 (or 95640W6)
xxxxV
95640 3
xxxxS95640 3 (or 95640W3)
xxxxB
M95640, M95320
38/39
RE VISION HISTORY
Table 29. D ocum ent Revision History
Date Rev. Description of Revision
13-Jul-2000 1.2 Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp 1,11,15. New clause
on p7. Addition of TSSOP8 package on pp 1, 2, Ordering Info, Mechanical Data
16-Mar-2001 1.3
Test condition added ILI and ILO, and specification of tDLDH and tDHDL removed.
tCLCH, tCHCL, tDLDH and tDHDL changed to 50ns for the -V range.
“-V” Voltage range changed to “2.7V to 3.6V” throughout.
Maximum lead soldering time and temperature conditions updated.
Instruction sequence illustrations updated.
“Bus Master and Memory Devices on the SPI bus” illustration updated.
Package Mechanical data updated.
19-Jul-2001 1.4 M95160 and M95080 devices removed to their own data sheet
06-Dec-2001 1.5 Endurance increased to 1M write/erase cycles
Instruction sequence illustrations updated
18-Dec-2001 2.0 Document reformatted using the new template. No parameters changed.
08-Feb-2002 2.1 Announcement made of planned upgrade to 10 MHz clock for the 5V, –40 to 85°C, range.
Endurance set to 100K write/erase cycles
18-Dec-2002 2.2 10MHz, 5MHz, 2MHz clock; 5ms, 10ms Write Time; 100K, 1M erase/write cycles distinguished
on front page, and in the DC and AC Characteristics tables
26-Mar-2003 2.3 Process indentification letter corrected in f ootnote to AC Char acteristics tab le for temp. range 3
26-Jun-2003 2.4 -S voltage range upgraded by removing it and inserting -R voltage range in its place
15-Oct-2003 3.0 Table of contents, and Pb-free options added. VIL(min) improved to -0.45V.
21-Nov-2003 3.1 VI(min) and VO(min) corrected (improved) to -0.45V.
39/39
M95640, M95320
Info rm atio n fur ni shed is bel i eved to be accurate an d rel i able. However, STMicro el ectro ni cs assumes no resp onsib ility for the cons equences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by i m pl i cation or oth erwise under any pat ent or paten t rights of STMi croel ectroni cs. Specificat i ons me ntioned i n this publ ication are subj ect
to change without notice. This publication supersedes and replaces all information previously s upplied. STMicroelectronics products are not
authorized for u se as c ri tical components in lif e support devices or systems without express writ ten approval of STM i croelectronics.
The ST l ogo is a registered tra dem ark of STM i croel ectron ics.
All other names are th e prope rt y of their respectiv e owners
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