Description
Available in PGA (Puma 2), and JLCC (Puma 67)
footprints, the Puma **E4001 is a 4 Mbit EEPROM
module user configurable as 128K x 32, 256K x 16
or 512K x 8. Available with access times of 120, 150
and 200ns, the device features hardware and software
data protection, 10,000 cycle Write/Erase capability
and 10 year data retention time.
Several pinout variants of the PUMA67 are available
including single and multiple WE variants.
Parts may be screened in accordance with MIL-STD-
883
Pin Functions
A0~A16 Address Input D0~D31 Data Inputs/Outputs
CS1~4 Chip Select WE1~4 Write Enables
OE Output Enable Vcc Power (+5V)
GND Ground
Features
• 4 Megabit EEPROM module.
• Access Times of 120/150/200 ns.
• Output Configurable as 32/ 16/ 8 bit wide.
• Upgradeable footprint
• Operating Power 1600/ 830/ 445 mW (Max).
Low Power Standby 2.2 mW (Max).
• Byte and Page Write (128 Bytes) in 5ms typical with
DATA Polling and Toggle bit indication of end of
Write.
• Hardware and Software Data Protection.
• Puma 2 - 66 pin Ceramic PGA.
• Puma 67 - 68 Lead Ceramic JLCC.
• May be screened in accordance with MIL-STD-883.
• 100,000 W/E cycle endurance option
Block Diagram
PUMA 67E4001A/B
Block Diagram
PUMA 2E4001, 67E4001A and 67E4001B
128K x 32 EEPROM Module
PUMA 2/67E4001/A/B -12/15/20
Issue 4.3 : January 2001
D16~23
D0~7
D8~15
D24~31
CS1
CS2
CS3
CS4
OE
WE
A0~A16
128K x 8
EEPROM 128K x 8
EEPROM 128K x 8
EEPROM 128K x 8
EEPROM
D16~23
D0~7
D8~15
D24~31
CS1
CS2
CS3
CS4
OE
WE1
A0~A16
128K x 8
EEPROM 128K x 8
EEPROM 128K x 8
EEPROM 128K x 8
EEPROM
WE2
WE3
WE4
Elm Road, West Chirton, North Shields, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A /B- 12/15/20
2
Recommended Operating Conditions
min typ max
DC Power Supply Voltage VCC 4.5 5.0 5.5 V
Input Low Voltage VIL -1.0 - 0.8 V
Input High Voltage VIH 2.0 - VCC+1 V
Operating Temp Range TA0-70
°C
TAI -40 - 85 °C (I Suffix)
TAM -55 - 125 °C (M, MB Suffix)
Absolute Maximum Ratings (1)
Operating Temperature TOPR -55 to +125 °C
Storage Temperature TSTG -65 to +150 °C
Input voltages (including N.C. pins) with Respect to GND VIN -0.6 to +6.25 V
Output voltages with respect to GND VOUT -0.6 to VCC+0.6 V
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Capacitance (TA=25°C,ƒ=1MHz) Note: These parameters are calculated, not measured.
Parameter Symbol Test Condition typ max Unit
Input Capacitance CS1~4, WE1~4(1) CIN1 VIN=0V - 20 pF
Other Inputs CIN2 VIN=0V - 22 pF
Output Capacitance COUT VOUT=0V - 22 pF
Notes: (1) On the PUMA 2E4001, 67E4001A/B versions only.
DC OPERATING CONDITIONS
DC Electrical Characteristics (TA=-55°C to +125°C,VCC=5V ± 10%)
Parameter Symbol Test Condition min max Unit
Input Leakage Current ILI1 VIN = GND to VCC +1 -40µA
Output Leakage Current 32 bit ILO VI/O = GND to VCC, CS(1)=VIH -40µA
Operating Supply Current 32 bit ICC32 CS(1)=OE=VIL, WE=VIH, IOUT=0mA, ƒ=5MHz(2) - 320 mA
16 bit ICC16 As above - 166 mA
8 bit ICC8 As above -89mA
Standby Supply Current TTL levels ISB1 CS(1) = 2.0V to VCC+1V -12mA
CMOS levels ISB2 CS(1) = VCC-0.3V to VCC+1V - 1.2 mA
Output Low Voltage VOL IOL = 2.1mA. -0.45V
Output High Voltage VOH IOH = -400µA. 2.4 - V
Notes (1) CS above are accessed through CS1~4. These inputs must be operated simultaneously for 32 bit operation, in
pairs in 16 bit mode and singly for 8 bit mode.
(2) Also for WE1~4 on the PUMA 2E4001, 67E4001A/B versions. Additionally, WE1~4 are accessed as in note (1)
above.
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A/B - 12/15/20
3
AC Test Conditions Output Test Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 10ns
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* VCC=5V±10%
Write Cycle
Parameter Symbol min typ max Unit
Write Cycle Time tWC --10 ms
Address Set-up Time tAS 0--ns
Address Hold Time tAH 50 - - ns
Output Enable Set-up Time tOES 0--ns
Output Enable Hold Time tOEH 0--ns
Chip Select Set-up Time tCS 0--ns
Chip Select Hold Time tCH 0--ns
Write Pulse Width tWP 100 - - ns
Write Enable High Recovery tWPH 50 - - ns
Data Set-up Time tDS 50 - - ns
Data Hold Time tDH 0--ns
Byte Load Cycle tBLC - - 150 µs
AC OPERATING CONDITIONS
Read Cycle
12 15 20
Parameter Symnbol min max min max min max Unit
Read Cycle Time tRC 120 - 150 - 200 - ns
Address Access Time tAA - 120 - 150 - 200 ns
Chip Select Access Time tCS - 120 - 150 - 200 ns
Output Enable Access Time tOE 0 600700 80ns
CS or OE to Output Float (2) tDF 0 600700 80ns
Output Hold from Address Change tOH 0-0-0-ns
Notes:(1) tHZ max. and tOLZ max. are measured with CL = 5pF, from the point when Chip Select or Output Enable return high
(whichever occurs first) to the time when the outputs are no longer driven. tHZ and tOHZ are shown for reference only:
they are characterized and not tested.
(2) This parameter is characterised and is not 100% tested.
645
100pF
I/O P in
1.76V
Ω
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A /B- 12/15/20
4
Toggle Bit Characteristics (1)
Parameter Symbol min typ max Unit
Data Hold Time tDH 10 - - ns
OE Hold Time tOEH 10 - - ns
OE to Output Delay (2) tOE ---ns
OE High Pulse tOEHP 150 - - ns
Write Recovery Time tWR 0--ns
Notes:(1) These parameter are characterised and is not 100% tested.
(2) See AC Read Characteristics.
Data Polling Characterisitics (1)
Parameter Symbol min typ max Unit
Data Hold Time tDH 10 - - ns
OE Hold Time tOEH 10 - - ns
OE to Output Delay (2) tOE ---ns
Write Recovery Time tWR 0--ns
Notes:(1) These parameter are characterised and is not 100% tested.
(2) See AC Read Characteristics.
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A/B - 12/15/20
5
AC Write Waveform - WE Controlled
AC Write Waveform - CS Controlled
tWC
tAS tAH
tWP
tCS
tOES
tDS tDH
tOEH
tCH
tWPH
Address
WE
OE
CS1~4
DATA
tWC
tAS tAH
tWP
tCS
tOES
tDS tDH
tOEH
tCH
tWPH
Address
WE
CS1~4
OE
DATA
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A /B- 12/15/20
6
Page Mode Write Waveform
Note: A8 through A16 must specify the page address during each high to low transition of Write Enable (or Chip select).
Output Enable must be high only when Write Enable and Chip Select are both low.
Read Cycle Timing Waveform
OE
CS1~4
WE
A0-A16
Data
tWP tWPH tBLC
tAS tAH tDH
tDS
tWC
Valid
Add
Valid
Data
Byte 0 Byte 1 Byte 2 Byte 3 Byte 126 Byte 127
A0~A16
CS1~4
OE
Data HIGH Z
tCS
tOE
tACC
tOHZ
tOH
tRC
Output
Valid
Ad dr es s Va lid
tCLZ
tOLZ
tOHZ
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A/B - 12/15/20
7
Software Protected Write Waveform
OE
CS1~4
WE/WE1~4
A0~A6
tWP
tAS tAH
tDH
Data
tDS tWC
Byte 0 Byte 126 Byte 127
05555 02AAA 05555
AA 55 A0
A7~A16
BYTE ADDRESS
PAGE ADDR ESS
tWPH
BLC
t
Toggle Bit Waveform
CS1~4
WE/WE1~4
OE tOE
tOEH
tDH tWR
D6,D14,
D22,D30 HIGH Z
WE/WE1~4
CS1~4
OE
D7,D15,
D23,D31
A0-A16
tOE
tOEH
tDH tWR
An
AnAnAnAn
High Z
DATA Polling Waveform
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A /B- 12/15/20
8
Device Operation
The following description deals with the device, with the references to WE meaning WE1~4 on the 'A' parts.
Read
The device read operations are initiated by both Output Enable and Chip Select LOW. The read operation is
terminated by either Chip Select or Output Enable returning HIGH. This 2-line control architecture elimanates bus
contention in a system environment. The data bus will be in a high impendence state when either Output Enable
or Chip Select is HIGH.
Write
Write operations are initated when both Chip Select and Write Enable are LOW and Output Enable is HIGH. The
device supports both a Chip Select and Write Enable controlled write cycle. That is, the address is latched by the
falling edge of either Chip Select or Write Enable, whichever occurs last. Similarly, the data is latched internally
by the rising edge of either Chip Select or Write Enable, whichever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within 5 ms.
Page Mode Write
The page write feature of the device allows the entire memory to be written in 5 seconds. Page Write allows 128
bytes of data to be written prior to the internal programming cycle. The host can fetch data from another location
within the system during a page write operation (change the source address), but the page address (A8 through
A16) for each subsequent valid write cycle to the part during this operation must be the same as the initial page
address.
The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can
write up to 128 bytes in the same manner as the first byte written. Each successive byte load cycle, started by the
Write Enable HIGH to LOW transition, must begin within 150 µs of the falling edge of the preceding Write Enable.
If a subsequent Write Enable HIGH to LOW transition is not detected within 150 µs, the internal automatic
programming cycle will commence.
DATA Polling
The device features DATA Polling to indicate if the write cycle is completed. During the internal programming cycle,
any attempt to read the last byte written will produce the compliment of that data on D7. Once the programming
is complete, D7 will refect the true data. Note: If the the device is in a protected state and an illegal write operation
is attempted DATA Polling will not operate.
TOGGLE bit
In addition to DATA polling, another method is provided to determine the end of a Write Cycle. During a write
operation successive attempts to read data will result in D6 toggling between 1 and 0. Once a write is complete,
this toggling will stop and valid data will be read.
Hardware Data Protection
The device provides three harware features to protect nonvololitile data from inadvertent writes.
•Noise Protection - A Write Enable pulse less than 15 ns will not inditiate a write cycle.
•Default VCC Sence - All functions are inhabited when VCC < 3.6 V.
•Write Inhibit - Holding either Output Enable LOW, Write Enable HIGH or Chip Select HIGH will prevent an
inadvertent write cycle during power on or power off, maintaining data integrity.
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A/B - 12/15/20
9
MODE CS1~4 OE OUTPUTS
Read
Write
Standby
Write Inhibit
WE
0
0
1
X
X
1
0
X
1
X
0
I
X
X
0
Data Out
Data in
Floating
Software Data Protection
The device can be automatically protected during power-up and power-down without the need for external circuits
by employing the software data protect feature. The internal software data protection circuit is enabled after the
first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the
device unless the reset command is issued.
Once the software protection is enabled, the device is also protected against inadvertent and accidental writes in
that, the software algorithm must be issued prior to writing additional data to the device.
Operating Modes
The table below shows the logic inputs required to control the operation of the device.
0 = VIL : 1 = VIH : X = VIH or VIL
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A /B- 12/15/20
10
Notes:
(1) Data Format I/O7-I/O0 (Hex);
Once initiated, this sequence of write operations should not be interrupted.
(2) Enable Write Protect state will be initiated at end of write even if no other data is loaded.
(3) Disable Write Protect state will be initiated at end of write period even if no other data is loaded.
(4) 1 to 128 bytes of data may be loaded.
Software Algorithms
Selecting the software data protection mode requires the host system to precede datawrite operations by a series
of three write operations to three specfic addresses. The three byte sequence opens the page write window
enabling the host to write from from 1 to 128 bytes of data. Once the page load cycle has been completed, the device
will automatically be returned to the data protected state
Software Data Protection Algorithm
Regardless of wheather the device has been protected or not, once the software data protected aglorithm is used
and the data is written, the device will automatically disable further writes unless another command is issued to
cancel it. If no further commands are issued the device will be write protected during power-down and any
subsequent power-up.
LOAD DAT A A0
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2A AA
LOAD DAT A AA
TO
ADDRESS 5555
LAST BYTE / WORD
TO
LAST ADDRESS
LOAD DAT A XX
TO
ANY ADDRESS(4)
WRITES
ENABLED (2)
ENTE R DATA
PROTECT
STATE
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A/B - 12/15/20
11
Software Data Protect Disable
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an
E2PROM programmer. The following six step algorithm will reset the internal protection circuit. After tWC, the device
will be in standard operating mode.
LAST BYTE / WORD
TO
LAST ADDRESS
LOAD DATA XX
TO
ANY ADDRES S
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA AA
TO
ADDRESS 5555
(4)
EXIT DATA
PROTECT
STATE (3)
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A /B- 12/15/20
12
Package Details
PUMA 67E4001
24.99 (0.984) sq.
24.89 (0.980) sq.
(0.202) max R=0.76 (0.030) typ.
1.27
(0.050) typ.
0.64
(0.025) min
21.08 (0.830)
0.43
(0.017) typ.
0.10 (0.004)
25.40 (1.000) sq.
24.49 (0.964) sq.
1.35 (0.053)
0.94 (0.037) 5.13
20.57 (0.810) sq.
20.07 (0.790) sq.
24.13 (0.950) sq.
23.11 (0.910) sq.
21.37 (0.840)
PUMA 2E4001
1 5.24 (0 .60 ) ty p
27.5 8 (1 .086) SQ 4.83 (0.19 0)
4.32 (0.170)
1.40 (0.055)
1.52 (0.060)
8.13 (0.320) max
0.66 (0.026)
1.27 (0.050)
2.54 (0.010) typ
2.54 (0.010) t
y
p
1.02 (0.040)
0.53 (0.021)
0.38 (0.015)
1.15 (0.045)
2 7.08 (1 .06 6 ) SQ
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A/B - 12/15/20
13
Pin Definitions
112 23
VIEW
FRO M
ABOVE
21324
314 25
415 26
516 27
617 28
718 29
819 30
920 31
10 21 32
11 22 33
34 45 56
35 46 57
36 47 58
37 48 59
38 49 60
39 50 61
40 51 62
41 52 63
42 53 64
43 54 65
44 55 66
D8 WE2 D15
D9 CS2 D14
D10 GND D13
A13 D11 D12
A14 A10 OE
A11 NC
A12 WE1
NC VCC D7
D0 CS1 D6
D1 NC D5
D2 D3 D4
D24 VCC D31
D25 CS4 D30
D26 WE4 D29
A6 D27 D28
A7 A3 A0
NC A4 A1
A8 A5 A2
A9 WE3 D23
D16 CS3 D22
D17 GND D21
D18 D19 D20
A15
A16
NC
A0
A1
A2
A3
A4
A5
CS3
GN
D
CS4
WE1
A6
A7
A8
A9
A10
VCC
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
9 8 7 6 5 4 3 2 16867 66 65 64 63 62 61
27 28 2930 31 32 33 34 3536 37 3839 4041 42 43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
PUMA 67E4001A
VIEW
FROM
ABOVE
Vcc
A11
A12
A13
A14
A15
A16
CS1
OE
CS2
NC
WE2
WE3
WE4
NC
GND
NC
OE
CS1
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE
A6
A7
A8
A9
A10
VCC
D0
D1
D2
D3
D4
D5
D6
D7
G
ND
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
9 8 7 6 5 4 3 2 1 68 67 66 6564 63 6261
27 28 2930 31 32 33 34 3536 37 3839 4041 42 43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
PUMA 67E4001
VIEW
FROM
ABOVE
Vcc
A11
A12
A13
A14
A15
A16
CS2
NC
NC
NC
NC
NC
GND
NC
PUMA 67E4001 PUMA 67E4001A
PUMA 2E4001
PUMA 67E4001B
NC
A0
A1
A2
A3
A4
A5
CS3
GN
D
CS4
WE1
A6
A7
A8
A9
A10
A11
D0
D1
D2
D3
D4
D5
D6
D7
G
ND
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
PUM A 67E400 1B
VIEW
FROM
ABOVE
Vcc
A11
A12
A13
A14
A15
A16
CS1
OE
CS2
NC
WE2
WE3
WE4
NC
NC
NC
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A /B- 12/15/20
14
MB MULTICHIP MODULE SCREENING FLOW
SCREEN TEST METHOD LEVEL
Visual and Mechanical
Internal visual 2010 Condition B or manufacturers equivalent 100%
Temperature cycle 1010 Condition C (10 Cycles,-65oC to +150oC) 100%
Constant acceleration 2001 Condition B (Y1 & Y2) (10,000g) 100%
Endurance
Write Cycle endurance and As per Internal Specification.
Data Retention performance
Burn-In
Pre-Burn-in electrical Per applicable device specifications at TA=+25oC 100%
Burn-in TA=+125oC,160hrs min 100%
Final Electrical Tests Per applicable Device Specification
Static (DC) a) @ TA=+25oC and power supply extremes 100%
b) @ temperature and power supply extremes 100%
Functional a) @ TA=+25oC and power supply extremes 100%
b) @ temperature and power supply extremes 100%
Switching (AC) a) @ TA=+25oC and power supply extremes 100%
b) @ temperature and power supply extremes 100%
Percent Defective allowable (PDA) Calculated at post-burn-in at TA=+25oC 10%
Hermeticity 1014
Fine Condition A 100%
Gross Condition C 100%
Quality Conformance Per Applicable Device Specification Sample
External Visual 2009 Per vendor or customer specification 100%
Military Screening Procedure
MultiChip Screening Flow for high reliability product is in accordance with Mil-883 method 5004 .
ISSUE 4.3 : January 2001 PUMA 2/67E4001/A/B - 12/15/20
15
PUMA 2E4001AMB-12E
Blank = 10,000 W/E cycle endurance
E = 100,000 W/E cycle endurance
Speed 12 = 120 ns
15 = 150 ns
20 = 200 ns
Temp. range/screening Blank = Commercial Temperature
I = Industrial Temperature
M = Military Temperature
MB = Processed in accordance with
MIL-STD-883
WE Option Blank = Single WE (PUMA 67 only)
WE1~4 (PUMA 2 only)
A = WE1~4 (PUMA 67 only)
B = PUMA67 pinout variant
Organisation 4001 = 128Kx 32, user confiurable as
256K x 16 and 512K x 8
Technology E = EEPROM MEMORY
Package PUMA 2 = JEDEC 66 Pin Ceramic PGA package
PUMA 67 = JEDEC 68 J-Leaded Ceramic Surface
Mount package
Ordering Information
Note :
Although this data is believed to be accurate, the information contained herein is not intended to and does not create any
warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of a
company director.
