ASM5I9352G-32-ET - Alliance Semiconductor

July 2005 ASM5I9352

rev 0.2

Alliance Semiconductor

2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855 .4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer

Features

 Output frequency range: 25MHz to 200MHz

 Output frequency range: 16.67MHz to 200MHz

 Input frequency range: 16.67MHz to 200MHz

 2.5V or 3.3V operation

 Split 2.5V/3.3V outputs

 ± 2% max Output duty cycle variation

 11 Clock outputs: Drive up to 22 clock lines

 LVCMOS reference clock input

 125-pS max output-output skew

 PLL bypass mode

 Spread AwareTM

 Output enable/disable

 Pin compatible with MPC9352 and MPC952

 Industrial temperature range: –40°C to +85°C

 32-Pin 1.0mm TQFP & LQFP Packages

Functional Description

The ASM5I9352 is a low voltage high performance

200MHz PLL-based zero delay buffer designed for high

speed clock distribution applications.

The ASM5I9352 features an LVCMOS reference clock

input and provides 11 outputs partitioned in 3 banks of 5, 4,

and 2 outputs. Bank A divides the VCO output by 4 or 6

while Bank B divides by 4 and 2 and Bank C divides by 2

and 4 per SEL(A:C) settings, see Table 2. These dividers

allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and

1:3. Each LVCMOS compatible output can drive 50Ω series

or parallel terminated transmission lines. For series

terminated transmission lines, each output can drive one or

two traces giving the device an effective fanout of 1:22.

The PLL is ensured stable given that the VCO is configured

to run between 200 MHz to 500 MHz. This allows a wide

range of output frequencies from 16.67 MHz to 200 MHz.

For normal operation, the external feedback input, FB_IN,

is connected to one of the outputs. The internal VCO is

running at multiples of the input reference clock set by the

feedback divider, see Table 1.

When PLL_EN# is HIGH, PLL is bypassed and the

reference clock directly feeds the output dividers. This

mode is fully static and the minimum input clock frequency

specification does not apply.

July 2005 ASM5I9352

rev 0.2

2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer 2 of 12

Notice: The information in this document is subject to change without notice.

Block Diagram

Pin Configuration

Q

A0

QA1

QA2

QA3

QB0

QB1

Q

B2

QB3

PLL

_

EN#

+2

QA4

QC0

QC1

+4/

+

6

+4/

+2

+2/

+4

VCO

200-500MHz

Phase

Detector

LPF

REFCL

K

FB_IN

VCO_SEL

SEL

A

SELB

SELC

MR/OE#

QA0

QA1

VDDQA

VSS

QB3

1

2

3

4

5

6

7

8

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

24

23

22

21

20

19

18

17

SELC

SELB

SELA

MR/OE#

REFCLK

AVSS

FB_IN

VCO_SEL

VDDQC

QC0

VSS

QB2

VDDQB

PLL_EN#

AVDD

VDD

VSS

QA2

QA4

VDDQA

VDDQB

QB0

QB1

VSS

QA3

VSS

ASM5I9352

QC1

July 2005 ASM5I9352

rev 0.2

2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer 3 of 12

Notice: The information in this document is subject to change without notice.

Pin Configuration1

Pin Name I/O Type Description

6 REFCLK I, PD LVCMOS

Reference clock input.

12, 14,

15, 18, 19 QA(0:4) O LVCMOS

Clock output bank A.

22, 23,

26, 27 QB(0:3) O LVCMOS

Clock output bank B.

30, 31 QC(0,1) O LVCMOS Clock output bank C.

8 FB_IN I, PD LVCMOS

Feedback clock input. Connect to an output for normal operation.

This input should be at the same voltage rail as input reference

clock. See Table 1.

1 VCO_SEL I, PD LVCMOS

VCO divider select input. See Table 2.

5 MR/OE# I, PD LVCMOS

Master reset/output enable/d isab le input. See Table 2.

9 PLL_EN# I, PD LVCMOS

PLL enable/disable input. See Table 2.

2, 3, 4 SEL(A:C) I, PD LVCMOS Frequency select input, Bank (A:C). See Table 2.

16, 20 VDDQA Supply VDD 2.5V or 3.3V power supply for bank A output clocks2,3.

21, 25 VDDQB Supply VDD 2.5V or 3.3V power supply for bank B output clocks.2,3

32 VDDQC Supply VDD 2.5V or 3.3V power supply for bank C output clocks. 2,3

10 AVDD Supply VDD 2.5V or 3.3V power supply for PLL. 2,3

11 VDD Supply VDD 2.5V or 3.3V power suppl y for core an d inputs. 2,3

7 AVSS Supply Ground

Analog ground.

13, 17,

24, 28, 29 VSS Supply Ground

Common ground.

Note: 1. PD = Internal pull-down.

2.A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins

their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.

3.AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output

supply pins.

July 2005 ASM5I9352

rev 0.2

2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer 4 of 12

Notice: The information in this document is subject to change without notice.

Table 1: Frequency Table

VCO_SEL Feedback

Output Divider VCO Input Frequency Range

(AVDD = 3.3V) Input Frequency

Range (AVDD = 2.5V)

0 ÷2 Input Clock * 2 100 MHz to 200 MHz 100 MHz to 200 MHz

0 ÷4 Input Clock * 4 50 MHz to 125 MHz 50 MHz to 100 MHz

0 ÷6 Input Clock * 6 33.33 MHz to 83.33 MHz 33.33 MHz to 66.67 MHz

1 ÷2 Input Clock * 4 50 MHz to 125 MHz 50 MHz to 100 MHz

1 ÷4 Input Clock * 8 25 MHz to 62.5 MHz 25 MHz to 50 MHz

1 ÷6 Input Clock * 12 16.67 MHz to 41.67 MHz 16.67 MHz to 33.33 MHz

Table 2: Function Table

Control Default 0 1

VCO_SEL 0 VCO VCO ÷ 2

PLL_EN# 0 PLL enabled. The VCO output

connects to the output dividers

Bypass mode, PLL disabled. The input clock

connects to the output dividers

MR/OE# 0 Outputs enabled Outputs disabled (three-state), VCO running

at its minimum frequency

SELA 0 QA = VCO÷4 QA = VCO÷6

SELB 0 QB = VCO ÷4 QB = VCO÷2

SELC 0 QC = VCO÷2 QC = VCO÷4

Absolute Maximum Ratings

Parameter Description Condition Min Max Unit

VDD DC Supply Voltage –0.3 5.5 V

VDD DC Operating Voltage Functional 2.375 3.465 V

VIN DC Input Voltage Relative to VSS –0.3 VDD+ 0.3 V

VOUT DC Output Voltage Relative to VSS –0.3 VDD+ 0.3 V

VTT Output termination Voltage

VDD ÷2 V

LU Latch Up Immunity Functional 200 mA

RPS Power Supply Ripple Ripple Frequency < 100 kHz 150 mVp-p

TS Temperature, Storage Non Functional –65 +150 °C

TA Temperature, Operating Ambient Functional –40 +85 °C

TJ Temperature, Junction Functional 155 °C

ØJC Dissipation, Junction to Case Functional 42 °C/W

ØJA Dissipation, Junction to Ambient Functional 105 °C/W

ESDH ESD Protection (Human Body Model) 2000 Volts

FIT Failure in Time Manufacturing test 10 ppm

Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device

reliability.

July 2005 ASM5I9352

rev 0.2

2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer 5 of 12

Notice: The information in this document is subject to change without notice.

DC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C)

Parameter Description Condition Min Typ Max Unit

VIL Input Voltage, Low LVCMOS

0.7 V

VIH Input Voltage, High LVCMOS 1.7 VDD+ 0.3 V

VOL Output Voltage, Low1 IOL= 15 mA

0.6 V

VOH Output Voltage, High1 IOH= –15 mA 1.8

V

IIL Input Current, Low VIL= VSS

–10 µA

IIH Input Current, High2 VIL= VDD

100 µA

IDDA PLL Supply Current AVDD only 5 10 mA

IDDQ Quiescent Supply Current All VDD pins except AVDD 3 5 mA

IDD Dynamic Supply Current

170 mA

CIN Input Pin Capacitance

4 pF

ZOUT Output Impedance

17 – 20 Ω

Note:1.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated

transmission lines.

2.Inputs have pull-down resistors that affect the input current.

DC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C)

Parameter Description Condition Min Typ Max Unit

VIL Input Voltage, Low LVCMOS

0.8 V

VIH Input Voltage, High LVCMOS 2.0 VDD + 0.3 V

IOL= 24 mA

0.55

VOL Output Voltage, Low1 IOL= 12 mA

0.30 V

VOH Output Voltage, High1 IOH= –24 mA 2.4

V

IIL Input Current, Low VIL= VSS

–10 µA

IIH Input Current, High2 VIL= VDD

100 µA

IDDA PLL Supply Current AVDD only 5 10 mA

IDDQ Quiescent Supply Current All VDD pins except AVDD 3 5 mA

IDD Dynamic Supply Current

240 mA

CIN Input Pin Capacitance

4 pF

ZOUT Output Impedance

14 – 17 Ω

Note:1.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated

transmission lines.

2.Inputs have pull-down resistors that affect the input current.

July 2005 ASM5I9352

rev 0.2

2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer 6 of 12

Notice: The information in this document is subject to change without notice.

AC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C) 1

Parameter Description Condition Min Typ Max Unit

fVCO VCO Frequency 200 400 MHz

÷2 Feedback 100 200

÷4 Feedback 50 100

÷6 Feedback 33.33 66.67

÷8 Feedback 25 50

÷12 Feedback 16.67 33.33

fin Input Frequency

Bypass mode

(PLL_EN# = 1) 0 200

MHz

frefDC Input Duty Cycle 25 75 %

tr, tf TCLK Input Rise/FallTime 0.7V to 1.7V

1.0 nS

÷2 Output 100 200

÷4 Output 50 100

÷6 Output 33.33 66.67

÷8 Output 25 50

fMAX Maximum Output Frequency

÷12 Output 16.67 33.33

MHz

fMAX< 100 MHz 47 53

DC Output Duty Cycle fMAX > 100 MHz 44 56 %

tr, tf Output Rise/Fall times 0.6V to 1.8V 0.1 1.0 nS

t(φ) Propagation Delay (static phase

offset)

TCLK to FB_IN, same VDD,

does not include jitter -100 100 pS

tsk(O) Output-to-Output Skew Skew within Bank

125 pS

Banks at same voltage,

same frequency

175

tsk(B) Bank-to-Bank Skew Banks at same voltage,

different frequency

225

pS

tPLZ, HZ Output Disable Time

8 nS

tPZL, ZH Output Enable Time

10 nS

÷2 Feedback 2

÷4 Feedback 1 - 1.5

÷6 Feedback 0.6

÷8 Feedback 0.75

BW PLL Closed Loop Bandwidth (-

3dB)

÷12 Feedback 0.5

MHz

Same frequency

100

tJIT(CC) Cycle-to-Cycle Jitter Multiple frequencies

300 pS

Same frequency

100

tJIT(PER) Period Jitter Multiple frequencies

150 pS

VCO < 300 MHz 150

tJIT(φ) I/O Phase Jitter VCO > 300 MHz 100 pS

tLOCK Maximum PLL Lock Time

1 mS

Note:1.AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.

July 2005 ASM5I9352

rev 0.2

2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer 7 of 12

Notice: The information in this document is subject to change without notice.

AC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C)1

Parameter Description Condition Min Typ Max Unit

fVCO VCO Frequency 200 500 MHz

÷2 Feedback 100 200

÷4 Feedback 50 125

÷6 Feedback 33.33 83.33

÷8 Feedback 25 62.5

÷12 Feedback 16.67 41.67

fin Input Frequency

Bypass mode (PLL_EN# = 1) 0 200

MHz

frefDC Input Duty Cycle 25 75 %

tr, tf TCLK Input Rise/FallTime 0.8V to 2.0V

1.0 nS

÷2 Output 100 200

÷4 Output 50 125

÷6 Output 33.33 83.33

÷8 Output 25 62.5

fMAX Maximum Output Frequency

÷12 Output 16.67 41.67

MHz

fMAX< 100 MHz 48 52

DC Output Duty Cycle fMAX > 100 MHz 44 56 %

tr, tf Output Rise/Fall times 0.55V to 2.4V 0.1 1.0 nS

t(φ) Propagation Delay

(static phase offset)

TCLK to FB_IN, same VDD,

does not include jitter –100 200 pS

tsk(O) Output-to-Output Skew Skew within each Bank

125 pS

Banks at same voltage,

same frequency

175

Banks at same voltage,

different frequency

235

tsk(B) Bank-to-Bank Skew

Banks at different voltage

425

pS

tPLZ, HZ Output Disable Time

8 nS

tPZL, ZH Output Enable Time

10 nS

÷2 Feedback 2

÷4 Feedback 1 – 1.5

÷6 Feedback 0.6

÷8 Feedback 0.75

BW PLL Closed Loop Bandwidth

(-3dB)

÷12 Feedback 0.5

MHz

Same frequency

100

tJIT(CC) Cycle-to-Cycle Jitter Multiple frequencies

275 pS

Same frequency

100

tJIT(PER) Period Jitter Multiple frequencies

150 pS

VCO < 300 MHz 150

tJIT(φ) I/O Phase Jitter VCO > 300 MHz 100 pS

tLOCK Maximum PLL Lock Time

1 mS

Note:1.AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.

July 2005 ASM5I9352

rev 0.2

2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer 8 of 12

Notice: The information in this document is subject to change without notice.

Figure 1. AC Test Reference for VDD = 3.3V / 2.5V

Figure 2. LVCMOS Propagation Delay t(φ), Static Phase Offset

DC = tP / T0 x 100%

Figure 3. Output Duty Cycle (DC)

Figure 4. Output-to-Output Skew , tsk(O)

LVCMOS_CLK

VDD

VDD/2

GND

tP

T0

tSK(0)

VDD

VDD/2

GND

VDD

VDD/2

GND

Pulse

Generator

Z = 50 ohm

Zo = 50 ohm

RT = 50 ohm

V

TT

V

TT

RT = 50 ohm

Zo = 50 ohm

LVCMOS_CLK

VDD

VDD/2

GND

t(

φ

)

FB_IN

July 2005 ASM5I9352

rev 0.2

2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer 9 of 12

Notice: The information in this document is subject to change without notice.

Package Diagram

32-lead TQFP Package

SECTION A- A

Dimensions

Inches Millimeters

Symbol

Min Max Min Max

A …. 0.0472 … 1.2

A1 0.0020 0.0059 0.05 0.15

A2 0.0374 0.0413 0.95 1.05

D 0.3465 0.3622 8.8 9.2

D1 0.2717 0.2795 6.9 7.1

E 0.3465 0.3622 8.8 9.2

E1 0.2717 0.2795 6.9 7.1

L 0.0177 0.0295 0.45 0.75

L1 0.03937 REF 1.00 REF

T 0.0035 0.0079 0.09 0.2

T1 0.0038 0.0062 0.097 0.157

b 0.0118 0.0177 0.30 0.45

b1 0.0118 0.0157 0.30 0.40

R0 0.0031 0.0079 0.08 0.2

a 0° 7° 0° 7°

e 0.031 BASE 0.8 BASE

July 2005 ASM5I9352

rev 0.2

2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer 10 of 12

Notice: The information in this document is subject to change without notice.

32-lead LQFP Package

SECTION A-A

Dimensions

Inches Millimeters

Symbol

Min Max Min Max

A …. 0.0630 … 1.6

A1 0.0020 0.0059 0.05 0.15

A2 0.0531 0.0571 1.35 1.45

D 0.3465 0.3622 8.8 9.2

D1 0.2717 0.2795 6.9 7.1

E 0.3465 0.3622 8.8 9.2

E1 0.2717 0.2795 6.9 7.1

L 0.0177 0.0295 0.45 0.75

L1 0.03937 REF 1.00 REF

T 0.0035 0.0079 0.09 0.2

T1 0.0038 0.0062 0.097 0.157

b 0.0118 0.0177 0.30 0.45

b1 0.0118 0.0157 0.30 0.40

R0 0.0031 0.0079 0.08 0.20

e 0.031 BASE 0.8 BASE

a 0° 7° 0° 7°

July 2005 ASM5I9352

rev 0.2

2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer 11 of 12

Notice: The information in this document is subject to change without notice.

Ordering Information

Part Number Marking Package Type Temperature

ASM5I9352-32-ET ASM5I9352 32-pin TQFP Industrial

ASM5I9352-32-LT ASM5I9352 32-pin LQFP –Tape and Reel Industrial

ASM5I9352G-32-ET ASM5I9352G 32-pin TQFP, Green Industrial

ASM5I9352G-32-LT ASM5I9352G 32-pin LQFP –Tape and Reel, Green Industrial

Device Ordering Information

ASM 5I9352 F-32-LT

Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.

O = SOT U = MSOP

S = SOIC E = TQFP

T = TSSOP L = LQFP

A = SSOP U = MSOP

V = TVSOP P = PDIP

B = BGA D = QSOP

Q

=

QFN

X

=

SC

-

70

DEVICE PIN COUNT

X= Automotive I= Industrial P or n/c = Commercial

(-40C to +125C) (-40C to +85C) (0C to +70C)

1 = Reserved 6 = Power Management

2 = Non PLL based 7 = Power Management

3 = EMI Reduction 8 = Power Management

4 = DDR support products 9 = Hi Performance

5 = STD Zero Dela

y

Buffe

r

0 = Reserved

ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT

PART NUMBER

F = LEAD FREE AND RoHS COMPLIANT PART

G = GREEN PACKAGE

R = Tape & reel, T = Tube or Tray

July 2005 ASM5I9352

rev 0.2

2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer 12 of 12

Notice: The information in this document is subject to change without notice.

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respective companies. Alliance reserves the right to make changes to this document and its products at any time without

notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein

represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this

data at any time, without notice. If the product described herein is under development, significant changes to these

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Alliance Semiconductor Corporation

2575, Augustine Drive,

Santa Clara, CA 95054

Tel# 408-855-4900

Fax: 408-855-4999

www.alsc.com

Part Number: ASM5I9352

Document Version: 0.2

Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003