Freescale Semiconductor
Data Sheet: Documen t Nu mber: MSC8144E
Rev. 14, 5/2010
© 2007–2010 Freescale Semiconductor, Inc.
MSC8144E
FC-PBGA–783
29 mm ×29 mm
• Four StarCore® SC3400 DSP subsystems , each with an SC3400
DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,
memory management unit (MMU), extended prog r a mmable
interrupt controller (EPIC), two general-purpose 32-bit timers,
debug an d pro filin g sup po rt, an d low-p ower Wait and Stop
processing modes.
• Chip-level arbitration and system (CLASS) that provides full
fabric non-blocking arbitration between the processing el ements
and other initia tors and the M2 memory, DDR SRAM controller,
device configuration control and status registers, and ot her
targets.
• 128 Kbyte L2 shared instruction cache.
• 512 Kbyte M2 memory for critical data and temporary data
buffering.
• 10 Mbyte 128-bit wide M3 memory.
• 96 Kbyte boot ROM.
• Three input cloc ks (shared, global, and differentia l).
• Four PLLs (system, core, global, and serial RapidIO).
• Security Engine (SEC0 optimized to process all the algorithms
associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP
using 4 crypto-channels with multi-command chains, integrated
controller for assignment of the six execution units (PKEU, DEU,
AESU, AFEU, MDEU, and KEU0) and the random number
generator (RNG), and XOR engine to accelerate parity checking
for RAID storage appl ications.
• DDR controller with up to a 200 MHz clock (400 MHz data rate),
16/32 bit data bus, support ing up t o 1 Gbyte in up to two ba nks
and support for DDR1 and DDR2.
• DMA controller with 16 bidirectional channels with up to 1024
buffer descri ptors, and progra mmable prior ity, buffer, and
multip lexin g co nf igu r atio n.
• Up to e ight inde pendent TDM modules with progra mmable word
size (2, 4, 8, or 16-bi t), hardware-base A-law/μ-law conve rs i on ,
up to 128 M bps data ra te for all c hann els, with glu e less inte rfac e
to E1 or T1 framers, and can in t erface wi th H-MVIP/H.110
devices, T SI, and codecs such as AC-97.
• QUICC Engine™ technolo gy subsystem with dual RISC
processors, 48 Kbyte multi-master RAM, 48 Kbyte instru ction
RAM, supporting three communication controllers with one ATM
and tw o Gigabit E thernet interfaces, to offload scheduling task s
from the DSP cores.
– The two Ethernet controllers support 10/100/1000 Mbps
operations via MII/RMII/S MII/RGMII/SGMII and the SGMII
protocol using a 4-pin SerDes interface at 1000 Mbps data rate
only.
– The ATM controller su pports UTOPIA level II 8/16 bit s a t
25/50 MHz in UTOPIA/POS mode with adaptation layer
support AAL0, AAL2, and AAL5.
• PCI designed to comply with the PCI specifica tion revision 2.2 at
33 MHz or 66 M Hz with access to all PCI address spaces.
• Serial RapidIO® 1x/4x endpoint corresponds to Specification 1.2
of the RapidIO trade association, and supports read, write,
messa ges, doorbe lls, and mai ntenance a ccesses in inbound mod e,
and messages and doorbells in outbound mode.
• I/O interrupt concentrator consolidates all chip maskable interrupt
and non-maskable interrupt sources and routes them to
INT_OUT, NMI_OUT, and the cores.
• UART that permits full-duplex operation with a bit rate of up to
6.25 Mbps.
• Serial peripheral interface (SPI).
• Four ti mer modules, each with four configurable16-bit timers.
• Four software watchdog timer (SWT) modules.
• Up to 32 general-purpose input/output (GPIO) ports, 16 of which
can be configur ed as maska b le int err up t inputs.
•I
2C interface that allows booting from EEPROM devices.
• Eigh t programmable hard war e semaphores.
• Thirty two virtual maskable interru pts and one vi r tual NMI that
can be generated b y a simple write access.
• Optional booting via serial Rapid IO port, PCI, I2C, SPI, or
Ethernet i nterfaces.
Note: This document supports mask set M31H.
Quad Core Digital Signal
Processor
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor2
Table of Conte nts
1 Pin Assignments and Reset States. . . . . . . . . . . . . . . . . . . . . .4
1.1 FC-PBGA Ba ll La yout Diagrams. . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location . . . . . . . . . . . . . . . . . . . . . . .6
2 Ele ctrica l C h a r a cteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.1 Max imum Ra ting s . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .27
2.3 Default Ou tpu t Driver Characte ristics . . . . . . . . . . . . . .28
2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28
2.5 DC Electrical Chara c te ristics . . . . . . . . . . . . . . . . . . . .29
2.6 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3 Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . .64
3.1 Start-up Sequencing Recommendations . . . . . . . . . . .64
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .65
3.3 Clock and Timing Signal Board Layout Considerations66
3.4 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .66
4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6 Product D o c u menta ti o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7 Revis io n Histor y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
List of Figures
Figure 1. MSC8144E Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram 3
Figure 3. MSC8144E FC-PB GA Pac kage, Top View. . . . . . . . . . . 4
Figure 4. MSC8144E FC-PB G A Pac kage, Bo ttom View . . . . . . . . 5
Figure 5. SerDes Reference Clocks Input St age . . . . . . . . . . . . . 31
Figure 6. Start-Up Sequence with VDD Raised Before VDDIO with
CLKIN Started with VDDIO. . . . . . . . . . . . . . . . . . . . . . . 3 5
Figure 7. Timing for a Reset Configuration Write. . . . . . . . . . . . . 38
Figure 8. Timing for tDDKHMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 9. DDR SDRAM Output Timing. . . . . . . . . . . . . . . . . . . . . 41
Figure 10.DDR AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 11.Differential VPP of Trans mi tter or R e c e i ve r . . . . . . . . . . 42
Figure 12.Transmitter Output Complia n ce Mask. . . . . . . . . . . . . . 46
Figure 13.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 48
Figure 14.Receiver Input Compliance Mask . . . . . . . . . . . . . . . . . 49
Figure 15.PCI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 16.PCI Input AC Ti ming Measurement Conditions. . . . . . . 51
Figure 17.PCI Output AC Timing Measurement Condition . . . . . . 51
Figure 18.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 20.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 21.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 22.UART Ou tp u t Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 23.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 24.MII Management Interface Timing. . . . . . . . . . . . . . . . . 55
Figure 25.MII Transmit AC Timing. . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 26.AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 27.MII Receive AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 28.RMII Transmit and Receive AC T iming . . . . . . . . . . . . . 57
Figure 29.AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 30.SMII Mode Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 31.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . . 59
Figure 32.ATM/UTOPIA/POS AC Test Load . . . . . . . . . . . . . . . . . 60
Figure 33.ATM/UTOPIAPOS AC Timing (External Clock). . . . . . . 60
Figure 34.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 35.SPI AC Timing in Slave Mode (External Clock). . . . . . . 61
Figure 36.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 62
Figure 37.Asynchronous Signal Timing. . . . . . . . . . . . . . . . . . . . . 62
Figure 38.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 39.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 63
Figure 40.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 41.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 42.VDDM3, VDDM3IO and V25M3 Power-on Sequence . . . . . 65
Figure 44.MSC8144E Mechanical Information, 783-ball FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 3
Figure 1. MSC8144E Block Diagram
Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram
JTAG
RMU SRIO
Note: The arrow direction indicat es m aster or slav e.
128-bit at
DDR Interface 16/32- bit at 400 MHz data rat e
8 TDMs
DMA
I/O-Interrupt
Concentrator
UART
Clocks
Timers
Reset
Semaphores
Other
DDR
10 Mby tes
M3
Memory
512 Kbytes
M2
Memory
CLASS
128 Kbyt e
L2
ICache
PCI
PCI 32-bit
Ser. Rapi dIO
Subsystem
Modules
QUICC Engine™
Ether-
Dual RISC
ATM
16-bit/8-bit
10/100/ 1000 Mbps
10/100/ 1000 Mbps
Subsystem
400 MHz
Processors
Eight TDMs 33/66 MHz
1x/4x
256-Channels each
Four DSP
Subsystems
Ether- Boot ROM
I2C
Virtual
Interrupts
Controller
UTOPIA
SPI
SPI
net
net
Security
Engine Core
Instruction
Cache Address
Translation
Task
Protection
Data
Cache
(WTB) (WBB)
EPIC
Interrupts
P-bus
Xa-bus
Xb-bus
DQBus
Debug Support
OCE30
Bus Interface
MMU
Timer
Two Internal Buses
(128 bits wide each)
IQBus
DPU
SC3400
Core
TWB
Write-
Through
Buffer
Write-
Back
Buffer
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Pin Assignments and Reset States
Freesca le Sem ico nd uctor4
1 Pin Assignments and Reset States
This section includes diagrams of the MSC8144E package ball grid array layouts and tables showing how the pinouts are
allocated for the package.
1.1 FC-PBGA Ball Layout Diagrams
Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers.
Figure 3. MSC8144E FC-PBGA Package, Top View
MSC8144E
Top View
1342 5678 10 151312119
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
14 16 17 18 19 20 21 22 23 24 25 26 27 28
AH
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 5
Figure 4. MSC8144E FC-PBGA Package, Bottom View
1342567810 151312119
Bottom View
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
14 16 17 18 19 20 21 22 23 24 25 26 27
AH
28
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor6
1.2 Signal List By Ball Location
Table 1 presents the signal list sorted by ball number. The functionality of multi-functional (multiplexed) pins is separated for
each mode. When designing a board, make sure that the reference supply for each signal is appropriately considered. The
specified reference s upply m ust be tied to the voltage level specified in this documen t if any of the related s ignal f unction s are
used (active).
Table 1. Signal List by Ball Number
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
A2 GND GND
A3 GE2_RX_ER /PCI_AD31 Ethernet 2 PCI Ethernet 2 VDDGE2
A4 VDDGE2 VDDGE2
A5 GE2_RX_DV/PCI_AD30 Ethernet 2 PCI Ethernet 2 VDDGE2
A6 GE2_TD0/PCI_CBE0 Ethernet 2 PCI Ethernet 2 VDDGE2
A7 SRIO_IMP_CAL_RX VDDSXC
A8 Reserved1—
A9 Reserved1—
A10 Reserved1—
A11 Reserved1—
A12 SRIO_RXD0 VDDSXC
A13 VDDSXC VDDSXC
A14 SRIO_RXD1 VDDSXC
A15 VDDSXC VDDSXC
A16 SRIO_REF_CLK VDDSXC
A17 VDDRIOPLL GNDRIOPLL
A18 GNDSXC GNDSXC
A19 SRIO_RXD2/
GE1_SGMII_RX SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC
A20 VDDSXC VDDSXC
A21 SRIO_RXD3/
GE2_SGMII_RX SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC
A22 VDDSXC VDDSXC
A23 SRIO_IMP_CAL_TX VDDSXP
A24 MDQ28 VDDDDR
A25 MDQ29 VDDDDR
A26 MDQ30 VDDDDR
A27 MDQ31 VDDDDR
A28 MDQS3 VDDDDR
B1 Reserved1—
B2 GE2_TD1/PCI_CBE1 Ethernet 2 PCI Ethernet 2 VDDGE2
B3 GE2_TX_EN/PCI_CBE2 Ethernet 2 PCI Ethernet 2 VDDGE2
B4 GE_MDIO Ethernet VDDGE2
B5 GND GND
B6 GE_MDC Ethernet VDDGE2
B7 GNDSXC GNDSXC
B8 Reserved1—
B9 Reserved1—
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 7
B10 Reserved1—
B11 Reserved1—
B12 SRIO_RXD0 VDDSXC
B13 GNDSXC GNDSXC
B14 SRIO_RXD1 VDDSXC
B15 GNDSXC GNDSXC
B16 SRIO_REF_CLK VDDSXC
B17 Reserved1—
B18 VDDSXC VDDSXC
B19 SRIO_RXD2/
GE1_SGMII_RX SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC
B20 GNDSXC GNDSXC
B21 SRIO_RXD3/
GE2_SGMII_RX SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC
B22 GNDSXC GNDSXC
B23 GNDSXP GNDSXP
B24 MDQ27 VDDDDR
B25 VDDDDR VDDDDR
B26 GND GND
B27 VDDDDR VDDDDR
B28 MDQS3 VDDDDR
C1 Reserved1—
C2 GE2_RX_CLK/PCI_AD29 Ethernet 2 PCI Ethernet 2 VDDGE2
C3 VDDGE2 VDDGE2
C4 TDM7RSYN/GE2_TD2/
PCI_AD2/UTP_TER TDM PCI Ethernet 2 UTOPIA VDDGE2
C5 TDM7RCLK/GE2_RD2/
PCI_AD0/UTP_RVL TDM PCI Ethernet 2 UTOPIA VDDGE2
C6 VDDGE2 VDDGE2
C7 GE2_RD0/PCI_AD27 Ethernet 2 PCI Ethernet 2 VDDGE2
C8 Reserved1—
C9 Reserved1—
C10 Reserved1—
C11 Reserved1—
C12 VDDSXP VDDSXP
C13 SRIO_TXD0 VDDSXP
C14 VDDSXP VDDSXP
C15 SRIO_TXD1 VDDSXP
C16 GNDSXC GNDSXC
C17 GNDRIOPLL GNDRIOPLL
C18 Reserved1—
C19 VDDSXP VDDSXP
C20 SRIO_TXD2/GE1_SGMII_T
XSGMII support on SERDES is enabled by Reset Configuration Word VDDSXP
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor8
C21 VDDSXP VDDSXP
C22 SRIO_TXD3/GE2_SGMII_T
XSGMII support on SERDES is enabled by Reset Configuration Word VDDSXP
C23 VDDSXP VDDSXP
C24 MDQ26 VDDDDR
C25 MDQ25 VDDDDR
C26 MDM3 VDDDDR
C27 GND GND
C28 MDQ24 VDDDDR
D1 Reserved1—
D2 GE2_RD1/PCI_AD28 Ethernet 2 PCI Ethernet 2 VDDGE2
D3 GND GND
D4 TDM7TDAT/GE2_TD3/
PCI_AD3/UTP_TMD TDM PCI Ethernet 2 UTOPIA VDDGE2
D5 TDM7RDAT/GE2_RD3/
PCI_AD1/UTP_STA TDM PCI Ethernet 2 UTOPIA VDDGE2
D6 GE1_RD0/UTP_RD2/
PCI_CBE2 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1
D7 TDM7TCLK/GE2_TCK/
PCI_IDS/UTP_RER TDM PCI Ethernet 2 UTOPIA VDDGE2
D8 Reserved1—
D9 Reserved1—
D10 Reserved1—
D11 Reserved1—
D12 GNDSXP GNDSXP
D13 SRIO_TXD0 VDDSXP
D14 GNDSXP GNDSXP
D15 SRIO_TXD1 VDDSXP
D16 VDDSXC VDDSXC
D17 Reserved1—
D18 Reserved1—
D19 GNDSXP GNDSXP
D20 SRIO_TXD2/GE1_SGMII_T
XSGMII support on SERDES is enabled by Reset Configuration Word VDDSXP
D21 GNDSXP GNDSXP
D22 SRIO_TXD3/GE2_SGMII_T
XSGMII support on SERDES is enabled by Reset Configuration Word VDDSXP
D23 GNDSXP GNDSXP
D24 MDQ23 VDDDDR
D25 VDDDDR VDDDDR
D26 MDQ22 VDDDDR
D27 MDQ21 VDDDDR
D28 MDQS2 VDDDDR
E1 Reserved1—
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 9
E2 GE1_RX_CLK/UTP_RD6/
PCI_PAR UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UT O PIA VDDGE1
E3 GE1_RD2/UTP_RD4/
PCI_FRAME UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1
E4 GE1_RD1/UTP_RD3/
PCI_CBE3 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1
E5 GE1_RD3/UTP_RD5/
PCI_IRDY UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1
E6 VDDGE1 VDDGE1
E7 GE1_TX_EN/UTP_TD6/
PCI_CBE0 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPI A VDDGE1
E8 Reserved1—
E9 Reserved1—
E10 GND GND
E11 VDD VDD
E12 GND GND
E13 VDD VDD
E14 GND GND
E15 VDD VDD
E16 GND GND
E17 VDD VDD
E18 GND GND
E19 VDD VDD
E20 GND GND
E21 VDD VDD
E22 GND GND
E23 VDDDDR VDDDDR
E24 MDQ20 VDDDDR
E25 GND GND
E26 VDDDDR VDDDDR
E27 GND GND
E28 MDQS2 VDDDDR
F1 Reserved1—
F2 GE1_TX_CLK/UTP_RD0/
PCI_AD31 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1
F3 VDDGE1 VDDGE1
F4 GE1_TD3/UTP_TD5/
PCI_AD30 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1
F5 GE1_TD1/UTP_TD3/
PCI_AD28 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1
F6 GND GND
F7 GE1_TD0/UTP_TD2/
PCI_AD27 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1
F8 VDDGE1 VDDGE1
F9 GND GND
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor10
F10 VDD VDD
F11 GND GND
F12 VDD VDD
F13 GND GND
F14 VDD VDD
F15 GND GND
F16 VDD VDD
F17 GND GND
F18 VDD VDD
F19 GND GND
F20 VDD VDD
F21 Reserved1—
F22 VDDDDR VDDDDR
F23 GND GND
F24 MDQ19 VDDDDR
F25 MDQ18 VDDDDR
F26 MDM2 VDDDDR
F27 MDQ17 VDDDDR
F28 MDQ16 VDDDDR
G1 Reserved1—
G2 SRESET4VDDIO
G3 GND GND
G4 PORESET4VDDIO
G5 GE1_COL/UTP_RD1 UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA VDDIO
G6 GE1_TD2/UTP_TD4/
PCI_AD29 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1
G7 GE1_RX_DV/UTP_RD7 UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA VDDGE1
G8 GE1_TX_ER/UTP_TD7/
PCI_CBE1 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPI A VDDGE1
G9 VDD VDD
G10 GND GND
G11 VDD VDD
G12 GND GND
G13 VDD VDD
G14 GND GND
G15 VDD VDD
G16 GND GND
G17 VDD VDD
G18 GND GND
G19 VDD VDD
G20 GND GND
G21 Reserved1— —
G22 GND GND
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 11
G23 MBA1 VDDDDR
G24 MA3 VDDDDR
G25 MA8 VDDDDR
G26 VDDDDR VDDDDR
G27 GND GND
G28 MCK0 VDDDDR
H1 Reserved1—
H2 CLKIN VDDIO
H3 HRESET VDDIO
H4 PCI_CLK_IN VDDIO
H5 NMI VDDIO
H6 URXD/GPIO14/IRQ8/
RC_LDF3, 6 RC_LDF UART/GPIO/IRQ VDDIO
H7 GE1_RX_ER/PCI_AD6/
GPIO25/IRQ153, 6 GPIO/
IRQ Ethernet
1PCI GPIO/
IRQ Ethernet 1 VDDIO
H8 GE1_CRS/PCI_AD5 PCI Ethernet
1PCI Ethernet 1 VDDIO
H9 GND GND
H10 VDD VDD
H11 GND GND
H12 VDD VDD
H13 GND GND
H14 VDD VDD
H15 VDD VDD
H16 VDD VDD
H17 GND GND
H18 VDD VDD
H19 GND GND
H20 VDD VDD
H21 VDD VDD
H22 VDDDDR VDDDDR
H23 MBA0 VDDDDR
H24 MA15 VDDDDR
H25 VDDDDR VDDDDR
H26 MA9 VDDDDR
H27 MA7 VDDDDR
H28 MCK0 VDDDDR
J1 Reserved1—
J2 GND GND
J3 VDDIO VDDIO
J4 STOP_BS VDDIO
J5 NMI_OUT4VDDIO
J6 INT_OUT4VDDIO
J7 SDA/GPIO273, 4, 6 I2C/GPIO VDDIO
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor12
J8 VDDIO VDDIO
J9 VDD VDD
J10 GND GND
J11 VDD VDD
J12 GND GND
J13 VDD VDD
J14 GND GND
J15 GND GND
J16 GND GND
J17 VDD VDD
J18 GND GND
J19 VDD VDD
J20 GND GND
J21 GND GND
J22 GND GND
J23 GND GND
J24 VDDDDR VDDDDR
J25 GND GND
J26 VDDDDR VDDDDR
J27 GND GND
J28 VDDDDR VDDDDR
K1 Reserved1—
K2 Reserved1—
K3 Reserved1—
K4 Reserved1—
K5 VDDPLL2A VDDPLL2A
K6 GND GND
K7 VDDPLL0A VDDPLL0A
K8 VDDPLL1A VDDPLL1A
K9 VDD VDD
K10 GND GND
K11 VDD VDD
K12 GND GND
K13 VDD VDD
K14 VDD VDD
K15 VDD VDD
K16 VDD VDD
K17 VDD VDD
K18 GND GND
K19 VDD VDD
K20 GND GND
K21 VDD VDD
K22 VDDDDR VDDDDR
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 13
K23 MBA2 VDDDDR
K24 MA10 VDDDDR
K25 MA12 VDDDDR
K26 MA14 VDDDDR
K27 MA4 VDDDDR
K28 MVREF VDDDDR
L1 Reserved1—
L2 CLKOUT VDDIO
L3 TMR1/UTP_IR/PCI_CBE3/
GPIO173, 6 UTOPIA TMR/
GPIO UTOPIA PCI UTOPIA VDDIO
L4 TMR4/PCI_PAR/GPIO203,
6/ UTP_REOP TIMER/GPIO PCI TIMER/GPIO VDDIO
L5 GND GND
L6 TMR2/PCI_FRAME/
GPIO183, 6 TIMER/GPIO PCI TIMER/GPIO UTOPIA VDDIO
L7 SCL/GPIO263, 4, 6 I2C/GPIO VDDIO
L8 UTXD/GPIO15/IRQ93, 6 UART/GPIO/IRQ VDDIO
L9 GND GND
L10 VDD VDD
L11 GND GND
L12 VDD VDD
L13 GND GND
L14 VDD VDD
L15 Reserved1GND
L16 VDD VDD
L17 GND GND
L18 VDD VDD
L19 GND GND
L20 VDD VDD
L21 GND GND
L22 GND GND
L23 MCKE1 VDDDDR
L24 MA1 VDDDDR
L25 VDDDDR VDDDDR
L26 GND GND
L27 VDDDDR VDDDDR
L28 MCK1 VDDDDR
M1 Reserved1—
M2 TRST VDDIO
M3 EE0 VDDIO
M4 EE1 VDDIO
M5 UTP_RCLK/PCI_AD13 UTOPIA PCI UTOPIA VDDIO
M6 UTP_RADDR0/PCI_AD7 UTOPIA PCI UTOPIA VDDIO
M7 UTP_TD8/PCI_AD30 UTOPIA PCI UTOPIA VDDIO
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor14
M8 VDDIO VDDIO
M9 VDD VDD
M10 GND GND
M11 VDD VDD
M12 GND GND
M13 VDD VDD
M14 GND GND
M15 VDD VDD
M16 GND GND
M17 VDD VDD
M18 GND GND
M19 VDD VDD
M20 GND GND
M21 VDD VDD
M22 VDDDDR VDDDDR
M23 MCS1 VDDDDR
M24 MA13 VDDDDR
M25 MA2 VDDDDR
M26 MA0 VDDDDR
M27 GND GND
M28 MCK1 VDDDDR
N1 Reserved1—
N2 VDDIO VDDIO
N3 TMS VDDIO
N4 UTP_RD10/PCI_AD145UTOPIA PCI UTOPIA VDDIO
N5 VDDIO Power VDDIO
N6 UTP_RADDR1/PCI_AD8 UTOPIA PCI UTOPIA VDDIO
N7 UTP_TD9/PCI_AD31 UTOPIA PCI UTOPIA VDDIO
N8 TMR3/PCI_IRDY/GPIO193,
6/ UTP_TEOP TIMER/GPIO PCI TIMER/GPIO UTOPIA VDDIO
N9 GND GND
N10 VDDM3 VDDM3
N11 VDD VDD
N12 VDDM3 VDDM3
N13 VDD VDD
N14 VDDM3 VDDM3
N15 VDD VDD
N16 VDDM3 VDDM3
N17 VDD VDD
N18 VDDM3 VDDM3
N19 VDD VDD
N20 VDDM3 VDDM3
N21 GND GND
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 15
N22 GND GND
N23 MODT1 VDDDDR
N24 MCKE0 VDDDDR
N25 VDDDDR VDDDDR
N26 MA5 VDDDDR
N27 MA6 VDDDDR
N28 MA11 VDDDDR
P1 Reserved1—
P2 TDI5VDDIO
P3 UTP_RD11/PCI_AD15 UTOPIA PCI UTOPIA VDDIO
P4 GND GND
P5 UTP_RADDR3/PCI_AD10 UTOPIA PCI UTOPIA VDDIO
P6 UTP_RADDR2/PCI_AD9 UTOPIA PCI UTOPIA VDDIO
P7 PCI_GNT/GPIO29/IRQ73. 6 GPIO/IRQ PCI GPIO/IRQ VDDIO
P8 PCI_STOP/GPIO30/IRQ23,
6GPIO/IRQ PCI GPIO/IRQ VDDIO
P9 GND GND
P10 GND GND
P11 VDDM3 VDDM3
P12 GND GND
P13 VDDM3 VDDM3
P14 GND GND
P15 VDDM3 VDDM3
P16 GND GND
P17 VDDM3 VDDM3
P18 GND GND
P19 VDDM3 VDDM3
P20 GND GND
P21 GND GND
P22 VDDDDR VDDDDR
P23 MCS0 VDDDDR
P24 MRAS VDDDDR
P25 GND GND
P26 VDDDDR VDDDDR
P27 GND GND
P28 MCK2 VDDDDR
R1 Reserved1—
R2 TCK VDDIO
R3 TDO VDDIO
R4 UTP_RD12/PCI_AD16 UTOPIA PCI UTOPIA VDDIO
R5 UTP_RCLAV_PDRPA/
PCI_AD12 UTOPIA PCI UTOPIA VDDIO
R6 UTP_RADDR4/PCI_AD11 UTOPIA PCI UTOPIA VDDIO
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor16
R7 VDDIO VDDIO
R8 PCI_REQ PCI VDDIO
R9 GND GND
R10 GND GND
R11 GND GND
R12 GND GND
R13 GND GND
R14 GND GND
R15 GND GND
R16 GND GND
R17 GND GND
R18 GND GND
R19 GND GND
R20 GND GND
R21 GND GND
R22 GND GND
R23 MODT0 VDDDDR
R24 MDIC1 VDDDDR
R25 MDIC0 VDDDDR
R26 MCAS VDDDDR
R27 MWE VDDDDR
R28 MCK2 VDDDDR
T1 Reserved1—
T2 UTP_RPRTY/PCI_AD21 UTOPIA PCI UTOPIA VDDIO
T3 UTP_RD13/PCI_AD17 UTOPIA PCI UTOPIA VDDIO
T4 VDDIO VDDIO
T5 UTP_RD14/PCI_AD18 UTOPIA PCI UTOPIA VDDIO
T6 UTP_RD15/PCI_AD19 UTOPIA PCI UTOPIA VDDIO
T7 PCI_TRDY PCI VDDIO
T8 PCI_DEVSEL/GPIO31/
IRQ33, 6 GPIO/IRQ PCI GPIO/IRQ VDDIO
T9 GND GND
T10 GND GND
T11 GND GND
T12 GND GND
T13 GND GND
T14 GND GND
T15 GND GND
T16 GND GND
T17 GND GND
T18 GND GND
T19 GND GND
T20 GND GND
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 17
T21 GND GND
T22 VDDDDR VDDDDR
T23 GND GND
T24 VDDDDR VDDDDR
T25 GND GND
T26 VDDDDR VDDDDR
T27 GND GND
T28 VDDDDR VDDDDR
U1 Reserved1—
U2 UTP_TCLK/PCI_AD29 UTOPIA PCI UTOPIA VDDIO
U3 UTP_TADDR4/PCI_AD27 UTOPIA PCI UTOPIA VDDIO
U4 UTP_TADDR2 UTOPIA VDDIO
U5 GND GND
U6 UTP_REN/PCI_AD20 UTOPIA PCI UTOPIA VDDIO
U7 PCI_AD26 PCI VDDIO
U8 PCI_AD25 PCI VDDIO
U9 Reserved1VDDIO
U10 VDDM3 VDDM3
U11 GND GND
U12 VDDM3 VDDM3
U13 GND GND
U14 VDDM3 VDDM3
U15 GND GND
U16 VDDM3 VDDM3
U17 GND GND
U18 VDDM3 VDDM3
U19 GND GND
U20 VDDM3 VDDM3
U21 GND GND
U22 GND GND
U23 MDQ7 VDDDDR
U24 MDQ3 VDDDDR
U25 MDQ4 VDDDDR
U26 MDQ5 VDDDDR
U27 MDQ1 VDDDDR
U28 MDQ0 VDDDDR
V1 Reserved1—
V2 UTP_TD10/PCI_CBE0 UTOPIA PCI UTOPIA VDDIO
V3 UTP_TADDR3 UTOPIA VDDIO
V4 UTP_TD1/PCI_PERR UTOPIA PCI UTOPIA VDDIO
V5 UTP_TADDR0/PCI_AD23 UTOPIA PCI UTOPIA VDDIO
V6 UTP_TADDR1/PCI_AD24 UTOPIA PCI UTOPIA VDDIO
V7 UTP_TCLAV/PCI_AD28 UTOPIA PCI UTOPIA VDDIO
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor18
V8 VDDIO VDDIO
V9 Reserved1VDDIO
V10 GND GND
V11 VDDM3 VDDM3
V12 GND GND
V13 VDDM3 VDDM3
V14 GND GND
V15 VDDM3 VDDM3
V16 GND GND
V17 VDDM3 VDDM3
V18 GND GND
V19 VDDM3 VDDM3
V20 GND GND
V21 GND GND
V22 VDDDDR VDDDDR
V23 MDQ2 VDDDDR
V24 VDDDDR VDDDDR
V25 MDQ6 VDDDDR
V26 GND GND
V27 VDDDDR VDDDDR
V28 MDQS0 VDDDDR
W1 Reserved1—
W2 UTP_TD12/PCI_CBE2 UTOPIA PCI UTOPIA VDDIO
W3 UTP_TD11/PCI_CBE1 UTOPIA PCI UTOPIA VDDIO
W4 VDDIO VDDIO
W5 GND GND
W6 UTP_TD15/PCI_IRDY UTOPIA PCI UTOPIA VDDIO
W7 UTP_TD0/PCI_SERR UTOPIA PCI UTOPIA VDDIO
W8 UTP_RSOC/PCI_AD22 UTOPIA PCI UTOPIA VDDIO
W9 Reserved1VDDIO
W10 VDDM3 VDDM3
W11 GND GND
W12 V25M3 V25M3
W13 GND GND
W14 VDDM3 VDDM3
W15 V25M3 V25M3
W16 VDDM3 VDDM3
W17 GND GND
W18 V25M3 V25M3
W19 GND GND
W20 VDDM3 VDDM3
W21 GND GND
W22 GND GND
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 19
W23 MDQ10 VDDDDR
W24 GND GND
W25 MDQ11 VDDDDR
W26 MDM0 VDDDDR
W27 GND GND
W28 MDQS0 VDDDDR
Y1 Reserved1-
Y2 UTP_TD14/PCI_FRAME UTOPIA PCI UTOPIA VDDIO
Y3 TDM5TSYN/ PCI_AD18/
GPIO123, 6 TDM/GPIO PCI TDM/GPIO VDDIO
Y4 TDM5TCLK/PCI_AD16 TDM PCI TDM VDDIO
Y5 TDM4RCLK/PCI_AD7 TDM PCI TDM VDDIO
Y6 TDM4TSYN/PCI_AD12 TDM PCI TDM VDDIO
Y7 UTP_TPRTY/RC14 RC14 UTOPIA VDDIO
Y8 UTP_TEN/PCI_PAR UTOPIA PCI UTOPIA VDDIO
Y9 Reserved1VDDIO
Y10 GND GND
Y11 VDDM3 VDDM3
Y12 GND GND
Y13 VDDM3 VDDM3
Y14 GND GND
Y15 VDDM3 VDDM3
Y16 GND GND
Y17 VDDM3 VDDM3
Y18 GND GND
Y19 VDDM3 VDDM3
Y20 GND GND
Y21 GND GND
Y22 VDDDDR VDDDDR
Y23 MDQ13 VDDDDR
Y24 VDDDDR VDDDDR
Y25 GND GND
Y26 MDQ9 VDDDDR
Y27 VDDDDR VDDDDR
Y28 MDQ8 VDDDDR
AA1 Reserved1—
AA2 UTP_TD13/PCI_CBE3 UTOPIA PCI UTOPIA VDDIO
AA3 TDM5RSYN /PCI_AD15/
GPIO103, 6 TDM/GPIO PCI TDM/GPIO VDDIO
AA4 TDM5TDAT, AT/PCI_AD17/
GPIO116TDM/GPIO PCI TDM/GPIO VDDIO
AA5 TDM5RCLK/PCI_AD13/
GPIO283, 6 TDM/GPIO PCI TDM/GPIO VDDIO
AA6 GND GND
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor20
AA7 TDM4TCLK/PCI_AD10 TDM PCI TDM VDDIO
AA8 TDM4TDAT/PCI_AD11 TDM PCI TDM VDDIO
AA9 VDDIO VDDIO
AA10 VDDM3 VDDM3
AA11 GND GND
AA12 VDDM3 VDDM3
AA13 GND GND
AA14 VDDM3 VDDM3
AA15 GND GND
AA16 VDDM3 VDDM3
AA17 GND GND
AA18 VDDM3 VDDM3
AA19 GND GND
AA20 VDDM3 VDDM3
AA21 GND GND
AA22 GND GND
AA23 MDQ15 VDDDDR
AA24 MDQ14 VDDDDR
AA25 MDM1 VDDDDR
AA26 MDQ12 VDDDDR
AA27 MDQS1 VDDDDR
AA28 MDQS1 VDDDDR
AB1 Reserved1-
AB2 UTP_TSOC/RC15 RC15 UTOPIA VDDIO
AB3 VDDIO VDDIO
AB4 TDM6RDAT/PCI_A D 20/
GPIO5/IRQ113, 6 TDM/GPIO/ IRQ PCI TDM/GPIO/ IRQ VDDIO
AB5 TDM5RDAT/PCI_A D 14/
GPIO93, 6 TDM/GPIO PCI TDM/GPIO VDDIO
AB6 TDM6TSYN/ PCI_AD24/
GPIO8/ IRQ143, 6 TDM/GPIO/IRQ PCI TDM/GPIO/IRQ VDDIO
AB7 TDM6RCLK/PCI_AD19/
GPIO4/IRQ103, 6 TDM/GPIO/IRQ PCI TDM/GPIO/IRQ VDDIO
AB8 TDM4RSYN/PCI_AD9 TDM PCI TDM VDDIO
AB9 TDM4RDAT/PCI_AD8 TDM PCI TDM VDDIO
AB10 GND GND
AB11 VDDM3 VDDM3
AB12 GND GND
AB13 VDDM3 VDDM3
AB14 GND GND
AB15 VDDM3 VDDM3
AB16 GND GND
AB17 VDDM3 VDDM3
AB18 GND GND
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 21
AB19 VDDM3 VDDM3
AB20 GND GND
AB21 GND GND
AB22 VDDDDR VDDDDR
AB23 MECC7 VDDDDR
AB24 MECC1 VDDDDR
AB25 MECC4 VDDDDR
AB26 MECC5 VDDDDR
AB27 MECC2 VDDDDR
AB28 ECC_MDQS VDDDDR
AC1 Reserved1—
AC2 UTP_RD9/RC13 RC13 UTOPIA VDDIO
AC3 UTP_RD8/RC12 RC12 UTOPIA VDDIO
AC4 TDM6TCLK/PCI_AD22 TDM PCI TDM VDDIO
AC5 TDM6RSYN/PCI_AD21/
GPIO6/ IRQ123, 6 TDM/GPIO/IRQ PCI TDM/GPIO/IRQ VDDIO
AC6 VDDIO VDDIO
AC7 TDM3TSYN/RC11 RC11 TDM VDDIO
AC8 PCI_AD23/GPIO7/IRQ13/
TDM6TDAT3, 6/UTP_RMOD TDM/GPIO/IRQ PCI TDM/GPIO/IRQ UTOPIA VDDIO
AC9 TDM7TSYN/ PCI_AD4 TDM PCI rese rved VDDIO
AC10 VDDM3IO VDDM3IO
AC11 GND GND
AC12 VDDM3 VDDM3
AC13 GND GND
AC14 VDDM3 VDDM3
AC15 GND GND
AC16 VDDM3 VDDM3
AC17 GND GND
AC18 VDDM3 VDDM3
AC19 GND GND
AC20 VDDM3IO VDDM3IO
AC21 Reserved1—
AC22 MECC6 VDDDDR
AC23 MECC3 VDDDDR
AC24 ECC_MDM VDDDDR
AC25 VDDDDR VDDDDR
AC26 MECC0 VDDDDR
AC27 VDDDDR VDDDDR
AC28 ECC_MDQS VDDDDR
AD1 Reserved1—
AD2 GPIO13, 6 GPIO VDDIO
AD3 TMR0/GPIO13 TIMER/GPIO VDDIO
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor22
AD4 GPIO23, 6 GPIO VDDIO
AD5 GND GND
AD6 TDM1TCLK TDM VDDIO
AD7 TDM3TDAT/RC10 RC10 TDM VDDIO
AD8 TDM3RSYN/RC9 RC9 TDM VDDIO
AD9 TDM3RDAT/RC8 RC8 TDM VDDIO
AD10 GND GND
AD11 V25M3 V25M3
AD12 GND GND
AD13 VDDM3 VDDM3
AD14 GND GND
AD15 V25M3 V25M3
AD16 GND GND
AD17 VDDM3 VDDM3
AD18 GND GND
AD19 V25M3 V25M3
AD20 GND GND
AD21 Reserved1—
AD22 VDDDDR VDDDDR
AD23 GND GND
AD24 VDDDDR VDDDDR
AD25 GND GND
AD26 VDDDDR VDDDDR
AD27 GND GND
AD28 VDDDDR VDDDDR
AE1 Reserved1—
AE2 GPIO03, 6 GPIO VDDIO
AE3 GPIO33, 6 GPIO VDDIO
AE4 TDM1RCLK TDM VDDIO
AE5 TDM1TSYN/RC3 RC3 TDM VDDIO
AE6 TDM1TDAT/RC2 RC2 TDM VDDIO
AE7 TDM1RSYN/RC1 RC1 TDM VDDIO
AE8 TDM3RCLK/RC16 RC16 TDM VDDIO
AE9 TDM3TCLK TDM VDDIO
AE10 TDM2TDAT/RC6 RC6 TDM VDDIO
AE11 GPIO21/IRQ13. 6/SPICLK GPIO/IRQ/SPI VDDIO
AE12 GND GND
AE13 Reserved1—
AE14 GND GND
AE15 Reserved1—
AE16 Reserved1—
AE17 Reserved1—
AE18 GND GND
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 23
AE19 GND GND
AE20 VDDM3IO VDDM3IO
AE21 Reserved1—
AE22 GND GND
AE23 GND GND
AE24 GND GND
AE25 VDDDDR VDDDDR
AE26 GND GND
AE27 VDDDDR VDDDDR
AE28 GND GND
AF1 Reserved1—
AF2 VDDIO VDDIO
AF3 GND GND
AF4 TDM0RDAT/
RCFG_CLKIN_RNG RCFG_
CLKIN_
RNG
TDM VDDIO
AF5 TDM0TSYN/RCW_SRC2 RCW_
SRC2 TDM VDDIO
AF6 TDM1RDAT/RC0 RC0 TDM VDDIO
AF7 VDDIO VDDIO
AF8 GND GND
AF9 TDM2RDAT/RC4 RC4 TDM VDDIO
AF10 TDM2TCLK TDM VDDIO
AF11 GPIO22/IRQ43, 6/SPIMOSI GPIO/IRQ/SPI VDDIO
AF12 GND GND
AF13 GND GND
AF14 VDDM3IO VDDM3IO
AF15 GND GND
AF16 GND GND
AF17 Reserved1—
AF18 VDDM3IO VDDM3IO
AF19 GND GND
AF20 Reserved1—
AF21 Reserved1—
AF22 M3_RESET VDDM3IO
AF23 GND GND
AF24 VDDDDR VDDDDR
AF25 GND GND
AF26 VDDDDR VDDDDR
AF27 GND GND
AF28 VDDDDR VDDDDR
AG1 Reserved1—
AG2 GPIO16/IRQ03, 6 GPIO/IRQ VDDIO
AG3 TDM0TCLK TDM VDDIO
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor24
AG4 TDM0RSYN/RCW_S RC0 RCW_
SRC0 TDM VDDIO
AG5 TDM0RCLK TDM VDDIO
AG6 TDM0TDAT/RCW_SRC1 RCW_
SRC1 TDM VDDIO
AG7 TDM2TSYN/RC7 RC7 TDM VDDIO
AG8 TDM2RCLK TDM VDDIO
AG9 TDM2RSYN/RC5 RC5 TDM VDDIO
AG10 GPIO24/IRQ63, 6/SPISEL GPIO/IRQ/SPI VDDIO
AG11 GPIO23/IRQ53, 6/SPIMISO GPIO/IRQ/SPI VDDIO
AG12 Reserved1—
AG13 GND GND
AG14 GND GND
AG15 GND GND
AG16 GND GND
AG17 Reserved1—
AG18 Reserved1—
AG19 GND GND
AG20 GND GND
AG21 VDDM3IO VDDM3IO
AG22 GND GND
AG23 GND GND
AG24 GND GND
AG25 VDDDDR VDDDDR
AG26 GND GND
AG27 VDDDDR VDDDDR
AG28 GND GND
AH1 Reserved1—
AH2 Reserved1—
AH3 Reserved1—
AH4 Reserved1—
AH5 Reserved1—
AH6 Reserved1—
AH7 Reserved1—
AH8 Reserved1—
AH9 Reserved1—
AH10 Reserved1—
AH11 Reserved1—
AH12 Reserved1—
AH13 Reserved1—
AH14 Reserved1—
AH15 Reserved1—
AH16 Reserved1—
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 25
AH17 Reserved1—
AH18 Reserved1—
AH19 Reserved1—
AH20 Reserved1—
AH21 Reserved1—
AH22 Reserved1—
AH23 Reserved1—
AH24 Reserved1—
AH25 Reserved1—
AH26 Reserved1—
AH27 Reserved1—
AH28 Reserved1—
Notes: 1. Res e rved signals should be disconnected for compatibility with future revisions of the device.
2. For signals with same functionality in all modes the appropriate cells are empty.
3. The choice between GPIO function and other function is by GPIO registers setup. For configuration details, see Chapter 23,
GPIO in the MSC8144E Reference Manual.
4. Open-drain signal.
5. Internal 20 KΩ pull-up resistor.
6. For signals with GPIO functionality, the open-drain and internal 20 KΩ pull-up resistor can be configured by GPIO register
programming. See Chapter 23, GPIO of the MSC 8144E Reference Manual for configurat ion details.
Table 1. Signal List by Ball Number (continued)
Ball
Number Signal Name
Power-
On
Reset
Value
I/O Mult iplexing Mode2
Ref.
Supply
0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor26
2 Electrica l Characteristics
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications. For additional information, see the MSC8144E Reference Manual.
2.1 Maximum Ratings
In calculat ing timi ng requir ements, adding a maximu m value o f one specification to a minimu m value of anoth er specification
does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values
in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction.
Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another
specification; adding a maximum to a minimum represents a condition that can never exist.
Table 2 describes the maximum electrical ratings for the MSC8144E.
CAUTION
This device contains circuitry protecting against damage
due to high static voltage or electrical fields; however,
normal precautions should be taken to avoid exceeding
maximum voltage ratings. Reliability is enhanced if unused
inputs are tied to an appropriate logic voltage level (for
example, either GND or VDD).
Table 2. Absolute Maximum Ratings
Rating Symbol Value Unit
Core supply voltage Vdd –0.3 to 1 .1 V
PLL supply voltage3VDDPLL0
VDDPLL1
VDDPLL2
–0 .3 to 1 .1 V
M3 memory Internal voltage VDDM3 –0.3 to 1.32 V
DDR memory supply voltage
• DDR mode
• DDR2 mode
DDR reference voltage
Input DDR voltage
VDDDDR
MVREF
VINDDR
–0.3 to 2.75
–0.3 to 1.98
–0.3 to 0.51 × VDDDDR
–0.3 to VDDDDR + 0.3
V
V
V
V
Ethernet 1 I/O voltage
Input Ethernet 1 I/O voltage
VDDGE1
VINGE1
–0.3 to 3.465
–0.3 to VDDGE1 + 0.3
V
V
Ethernet 2 I/O voltage
Input Ethernet 2I/O voltage
VDDGE2
VINGE2
–0.3 to 3.465
–0.3 to VDDGE2 + 0.3
V
V
I/O voltage excluding Ethernet, DDR, M3, and RapidIO lines
Input I/O voltage
VDDIO
VINIO
–0.3 to 3.465
–0 .3 to VDDIO + 0.3
V
V
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 27
2.2 Recommended Operating Conditions
Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.
M3 memory I/O and M3 memory char ge pump voltage
Input M3 memory I/O voltage
VDDM3IO
V25M3
VINM3IO
–0.3 to 2.75
–0.3 to VDDM3IO + 0.3
V
V
Rapid I/O C voltage VDDSXC –0.3 to 1.21 V
Rapid I/O P voltage VDDSXP –0.3 to 1.26 V
Rapid I/O PLL voltage VDDRIOPLL –0.3 to 1.21 V
Operating temperature TJ–40 to 105 °C
Storage temperature range TSTG –55 to +150 °C
Notes: 1. Functional operating conditions are given in Table 3.
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the listed limits may affect device reliability or cause permane nt damage.
3. PLL supply voltage is specified at input of the fil ter and not at pin of the MSC8144E (see Figure 43)
Table 3. Recommended Operating Conditions
Rating Symbol Min Nominal Max Unit
Core supply voltage
• 800 MHz (VT, SVT, TVT) and
1000 MHz (VT)
• 1000 MHz (SVT, TVT)
VDD 0.97
0.97
1.0
1.0
1.05
1.03
V
V
PLL supply voltage
• 800 MHz (VT, SVT, TVT) and
1000 MHz (VT)
• 1000 MHz (SVT, TVT)
VDDPLL0
VDDPLL1
VDDPLL2
0.97
0.97
1.0
1.0
1.05
1.03
V
V
M3 memory Internal voltage VDDM3 1.213 1.25 1.313 V
DDR memory supply voltage
• DDR mode
• DDR2 mode
DDR reference voltage
VDDDDR
MVREF
2.375
1.71
0.49 × VDDDDR (nom)
2.5
1.8
0.5 × VDDDDR (nom )
2.625
1.89
0.51 × VDDDDR (nom)
V
V
V
Ethernet 1 I/O voltage
• 2.5 V mode
• 3.3 V mode
VDDGE1 2.375
3.135 2.5
3.3 2.625
3.465 V
V
Ethernet 2 I/O voltage
• 2.5 V mode
• 3.3 V mode
VDDGE2 2.375
3.135 2.5
3.3 2.625
3.465 V
V
I/O voltage excluding Ethernet,
DDR, M3, and RapidIO lines VDDIO 3.135 3.3 3.465 V
M3 memory I/O and M3 charge
pump voltage VDDM3IO
V25M3
2.375 2.5 2.625 V
Rapid I/O C voltage VDDSXC 0.97 1.0 1.05 V
Rapid I/O P voltage
• Short run (haul) mode
• Long run (haul) mode
VDDSXP 0.97
1.14 1.0
1.2 1.05
1.26 V
V
Rapid I/O PLL voltage VDDRIOPLL 0.97 1.0 1.05 V
Operating temperature range:
• Standard (VT)
• Intermediate (SVT)
• Extended (TVT)
TJ
TJ
TA
TJ
0
0
–40
—
90
105
—
105
°C
°C
°C
°C
Note: PLL supply voltage is specified at input of the filter and not at pin of the MSC8144E (see Figure 43).
Table 2. Absolute Maximum Ratings
Rating Symbol Value Unit
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor28
2.3 Default Output Driver Characteristics
Table 4 provides information on the characteristics of the output driver strengths.
2.4 Thermal Characteristics
Table 5 describes thermal characteristics of the MSC8144E for the FC-PBGA packages.
Table 4. Output Drive Impedance
Driver Ty pe Output Impedance (Ω)
DDR signal 18
DDR2 signal 18
35 (half strength mode)
Table 5. Thermal Characteristics for the MSC8144E
Characteristic Symbol
FC-PBGA
29 × 29 mm5Unit
Natural
Convection 200 ft/min
(1 m/s) airflow
Junction-to-ambient1, 2 RθJA 20 15 °C/W
Junction-to-ambient , four-layer board1, 3 RθJA 15 12 °C/W
Junction-to-board (bottom)4RθJB 7°C/W
Junction-to-case5RθJC 0.8 °C/W
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mount ing site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JES D51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JES D51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL
SPEC-883 Method 1012.1) with the calculated case temperature.
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 29
2.5 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC8144E.
2.5.1 DDR SDRAM DC Electrical Characteristics
This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8144E.
Note: DDR SDRAM uses VDDDDR(typ) = 2.5 V and DDR2 SDRAM us es VDDDDR(typ) = 1.8 V.
2.5.1.1 DDR2 (1.8 V) SDRAM DC Electrical Characteristics
Table 6 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MSC8144E when
VDDDDR(typ) = 1.8 V.
Table 6. DDR2 SDRAM DC Electrical Characteristics for VDDDDR (typ) = 1.8 V
Parameter/Condition Symbol Min Max Unit
I/O supply voltage1VDDDDR 1.7 1.9 V
I/O reference voltage2MVREF 0.49 × VDDDDR 0.51 × VDDDDR V
I/O termination voltage3VTT MVREF –0.04 MV
REF + 0.04 V
Input high voltage VIH MVREF + 0.125 VDDDDR +0.3 V
Input low voltage VIL –0.3 MVREF – 0.125 V
Output leakage current4IOZ –50 50 μA
Output high current (VOUT = 1.420 V) IOH –13.4 — mA
Output low current (VOUT = 0.280 V) IOL 13.4 — mA
Notes: 1. VDDDDR is expected to be within 50 mV of the DRAM VDD at all times.
2. MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of VDDDDR.
4. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR.
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor30
2.5.1.2 DDR (2.5V) SDRAM DC Electrical Characteristics
Table 7 provides the recommended operating conditions for the DDR SDRAM component(s) of the MSC8144E when
VDDDDR(typ) = 2.5 V.
Table 8 lists the current draw characteristics for MVREF.
Table 7. DDR SDRAM DC Electrical Characteristics for VDDDDR (typ) = 2.5 V
Parameter/Condition Symbol Min Max Unit
I/O supply voltage1VDDDDR 2.3 2.7 V
I/O reference voltage2MVREF 0.49 × VDDDDR 0.51 × VDDDDR V
I/O termination voltage3VTT MVREF – 0.04 MVREF + 0.04 V
Input high voltage VIH MVREF + 0.15 V DDDDR + 0.3 V
Input low voltage VIL –0.3 MVREF – 0.15 V
Output leakage current4IOZ –50 50 μA
Output high current (VOUT = 1.95 V) IOH –16.2 — mA
Output low current (VOUT = 0.35 V) IOL 16.2 — mA
Notes: 1. VDDDDR is expected to be within 50 mV of the DRAM VDD at all times.
2. MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of VDDDDR.
4. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR.
Table 8. Current Draw Characteristics for MVREF
Parameter / Condition Symbol Min Max Unit
Current draw for MVREF IMVREF — 500 μA
Note: The voltage regulator for MVREF must be able to supply up to 500 μA current.
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 31
2.5.2 Serial RapidIO DC Electrical Cha racteristics
DC receiver logic levels are not defined since the receiver is AC-coupled.
2.5.2.1 DC Requirements for SerDes Reference Clocks
The SerDes reference clocks SRIO_REF_CLK and SRIO_REF_CLK are AC-coupled differential inputs. Each differential
clock input has an intern al 50 Ω termin ation to GNDSXC. The reference clock must be able to drive this ter m ination. The
recommended minimum operating voltage is –0.4 V; the recommended maximum operating voltage is 1.32 V; and the
maximum absolute voltag e is 1.72 V.
The maximum average current allowed in each input is 8 mA. This current limitation sets the maximum common mode input
voltage to be less than 0.4 V (0.4 V/50 Ω = 8 mA) while the minimum commo n mo de in put lev e l is GNDSXC. For example, a
clock with a 50 /50 duty cycle can be driven by a current s ource ou tput that ranges from 0 mA to 16 mA (0–0.8 V). The input is
AC-coupled internally, so, therefore, the exact common mode input voltage is not critical.
Note: This internal AC-couple network does not function correctly with reference clock frequencies below 90 MHz.
If the device driving the SRIO_REF_CLK inputs cannot drive 50 Ω to GNDSXC, or if it exceeds the maximum input current
limitations, then it must use external AC-coupling. The minimum differential peak-to-peak amplitude of the input clock is 0.4 V
(0.2 V peak-to-peak per phase). T he maximum differential peak-to-peak amplitude of the input clock is 1.6 V peak-to-peak (see
Figure 5. The termination to GNDSXC allows compatibility with HCSL type reference clocks specified for PCI-Express
applications. Many other low voltage differential type outputs can be used b ut will probably need to be AC-coupled due to the
limited commo n mode input range. LVPECL outputs can produce too lar ge an amplitude and may need to be source terminated
with a d ivider networ k to r educe the ampl itude. Th e amplitude of the clock mus t be at least a 400 mV d ifferential p eak-peak for
single-ended clock. If driven differentially, each signal wire needs to drive 100 mV around common mode voltage. The
differential reference clock (SRIO_REF_CLK/ SRIO_REF_CLK) input is HCSL-compatible DC coupled or LVDS-compatible
with AC-coupling.
Figure 5. SerDes Reference Clocks Input Sta ge
SRIO_REF_CLK
SRIO_REF_CLK
50 Ω
50 Ω
GNDSXC
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor32
2.5.2.2 Spread Spectrum Clock
SRIO_REF_CLK/ SRIO_REF_CLK is designed to work with a spread spectrum clock (0 to 0.5% spreading at 3033 kHz rate
is allowed), assuming both ends have same reference clock. For better r esults use a source without significant unintended
modulation.
2.5.3 PCI DC Electrical Characteristics
2.5.4 TDM DC Electrical Characteristics
Table 9. PCI DC Electrical Characteristics
Characteristic Symbol Min Max Unit
Supply voltage 3.3 V VDDPCI 3.135 3.465 V
Inp u t h igh volta g e VIH 0.5 × VDDPCI 3.465 V
Inp u t lo w vol ta g e VIL –0.5 0.3 × VDDPCI V
Input Pull-up voltage2VIPU 0.7 × VDDPCI
Input leakage current, 0<VIN <VDDPCI IIN –30 30 μA
Tri-state (high impedance off state) leakage current, 0<VIN <VDDPCI IOZ –30 30 μA
Signal low input current, VIL = 0.4 V1IL–30 30 μA
Signal high input current, VIH = 2.0 V1IH–30 30 μA
Output high voltage, IOH = –0.5 mA, except open drain pins VOH 0.9 × VDDPCI —V
Output low voltage, IOL= 1.5 mA VOL —0.1 × VDDPCI V
Inp ut Pi n C a paci tance2CIN 10 pF
Notes: 1. Not tested. Guaranteed by design.
Table 10. TDM DC Electrical Characteristics
Characteristic Symbol Min Max Unit
Supply voltage 3.3 V VDDTDM 3.135 3.465 V
Input high voltage VIH 2.0 3.465 V
Input low voltage VIL –0.3 0.8 V
Input leakage current 0<VIN <VDDTDM IIN –30 30 μA
Tri-state (high impedance off state) leakage current IOZ –30 30 μA
Output high voltage, IOH = –1.6 mA VOH 2.4 — V
Output low voltage, IOL= 0.4mA VOL —0.4V
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 33
2.5.5 Ethernet DC Electrical Character istics
2.5.5.1 MII, SMII and RMII DC Electrical Characteristics
2.5.5.2 RGMII DC Electrical Characteristics
Table 11. MII, SMII and RMII DC Electrical Characteristics
Characteristic Symbol Min Max Unit
Supply voltage 3.3 V VDDGE1
VDDGE2
3.135 3.465 V
Input high voltage VIH 2.0 3.465 V
Input low voltage VIL –0.3 0.8 V
Input leakage current, VIN = supply voltage IIN –30 30 μA
Signal low input current, VIL = 0.4 V1IL–30 30 μA
Signal high input current, VIH = 2.4 V1IH–30 30 μA
Output high voltage, IOH = –4 mA VOH 2.4 3.465 V
Output low voltage, IOL= 4mA VOL —0.4V
Input Pin Capacitance1CIN 8pF
Note: 1. Not tested. Guaranteed by design.
Table 12. RGMII DC Electrical Characteristics
Characteristic Symbol Min Max Unit
Supply voltage 2.5 V VDDGE1
VDDGE2
2.375 2.625 V
Input high voltage VIH 1.7 2.625 V
Input low voltage VIL –0.3 0.7 V
Input leakage current, VIN = supply voltage IIN –30 30 μA
Output high voltage, IOH = –1 mA VOH 2.0 2.625 V
Output low voltage, IOL= 1 mA VOL —0.4V
Input Pin Capacitance1CIN 8pF
Note: 1. Not tested. Guaranteed by design.
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor34
2.5.6 ATM/UTOPIA/POS DC Electri cal Characteristi cs
2.5.7 SP I DC Electrical Characteristics
Table 14 provides the SPI DC electrical characteristics.
2.5.8 GPIO, UART, TIMER, EE, STOP_BS, I2C, IRQn, NMI_OU T, INT_OUT,
CLKIN, JTAG Ports DC Electrical Characteristics
Table 13. ATM/UTOPIA/POS DC Electrical Characteristics
Characteristic Symbol Min Max Unit
Supply voltage 3.3 V VDDIO 3.135 3.465 V
Input high voltage VIH 2.0 3.465 V
Input low voltage VIL –0.3 0.8 V
Input leakage current, VIN = supply voltage I IN –30 30 μA
Signal low input current, VIL = 0.4 V1IL–30 30 μA
Signal high input current, VIH = 2.4 V1IH–30 30 μA
Output high voltage, IOH = –4 mA VOH 2.4 3.465 V
Output low voltage, IOL= 4 mA VOL —0.5V
Notes: 1. Not tested. Guaranteed by design.
Table 14. SPI DC Electrical Characteristics
Characteristic Symbol Min Max Unit
Input high voltage VIH 2.0 3.465 V
Input low voltage VIL –0.3 0.8 V
Input current IIN 30 μA
Output high voltage, IOH = –4.0 mA VOH 2.4 — V
Output low voltage, IOL = 4.0 mA VOL —0.5V
Table 15. GPIO, UART, Timer, EE, STOP_BS, I2C, IRQn, NMI_OUT, INT_OUT, CLKIN, and JTAG Port1
DC Electrical Characteristics
Characteristic Symbol Min Max Unit
Supply voltage 3.3 V VDDIO 3.135 3.465 V
Input high voltage VIH 2.0 3.465 V
Input low voltage VIL –0.3 0.8 V
Input leakage current, VIN = supply voltage IIN –30 30 μA
Tri-state (high impedance off state) leakage current, VIN = supply voltage IOZ –30 30 μA
Signal low input current, VIL = 0.4 V2IL–30 30 μA
Signal high input current, VIH = 2.0 V2IH–30 30 μA
Output high voltage, IOH = –2 mA,
except open drain pins VOH 2.4 3.465 V
Output low voltage, IOL= 3.2 mA VOL —0.4V
Notes: 1. This does not include TDI and TMS, which have internal pullup resistors.
2. Not tested. Guaranteed by design.
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 35
2.6 AC Timings
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs.
2.6.1 Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.6.2
describes the clocking characteristics. Section 2.6.3 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8144E device:
• PORESET and TRST mu st be as sert ed ex ternally f or the d uration of the power-up sequence using the VDDIO (3.3 V)
supply. See Table 19 for timing. TR ST must be deasserted before normal operation begins to ensure correct
initialization of the Security Engine .
Note: For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the
VDDM3IO (2.5 V) supply. See Section 3.1.1, Power-on Sequence for additional design information.
•CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee co rrect device operatio n
(see Figure 6). 32 cycles should be accounted only after VDDIO reaches its nominal value.
• CLKIN and PCI_CLK_IN shou ld either be stable low during the power -up of VDDIO supply and start their swings after
power-up or should swing within VDDIO range during VDDIO power-up., so their amplitude grows as VDDIO grows
during power-up.
Figure 6 shows a sequence in which VDDIO is raised after VDD and CLKIN begins to tog gle wi th the raise of VDDIO supply.
2.6.2 Clock and Timing Signals
The followin g sections include a des cription of clock signal characteristics. Table 16 shows the maximu m frequency v alues fo r
CLKIN and PCI_CLK_IN. The user must ensure that maximum frequency values are not exceeded.
Figure 6. Start-Up Sequence with VDD Raised Before VDDIO with CLKIN Started with VDDIO
Table 16. Clock Frequencies
Characteristic Symbol Min Max Unit
CLKIN frequency FCLKIN 33 133 MHz
PCI_CLK_IN frequency FPCI_CLK_IN 33 133 MHz
CLKIN duty cycle DCLKIN 40 60 %
PCI_CLK_IN duty c ycle DPCI_CLK_IN 40 60 %
Voltage
Time
3.3 V
V
DDIO
Nominal
PORESET/TRST asserted
V
DD
Nominal
CLKIN start s toggling
V
DD
applie d PORESET
1
V
DDIO
applied
1.0 V
V
DDIO
= Nominal
V
DD
= Nominal
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor36
2.6.3 Reset Timing
The MSC8144E has several in puts to the reset logic:
• Power-on reset (PORESET)
• E xternal hard reset (HRESET)
• External soft reset (SRESET)
• Software watchdog reset
•JTAG reset
• RapidIO reset
• Software hard reset
• Software soft reset
All MSC8144E reset sources are fed into the reset controller , which takes different actions depending on the source of the reset.
The reset status register indicates the most recent sources to cause a reset. Table 17 de scribes the reset sources.
Table 17. Reset Sources
Table 18 summarizes the reset actions that occur as a result of the different reset sources.
Name Direction Description
Power-on reset
(PORESET)Input Initiates the power-on reset flow that resets the MSC8144E and configures various attributes of the
MSC8144E. On PORESET, the entire MSC8144E device is reset. All PLLs states is reset, HRESET
and SRESET are driven, the extended cores are reset, and system configuration is sampled. The
reset source and word are configured only when PORESET is asserted.
External hard
reset (HRESET)Input/ Output Initiates the hard reset flow that configures various attributes of the MSC8144E. While HRESET is
asserted, S RES ET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the extended cores are reset, and system configuration is sampled. Note that
the RCW (reset Configuration Word) is not reloaded during HRESET assertion after out of power on
reset sequence. The reset configuration word is described in the Reset chapter in the MSC8144E
Reference Manual.
External soft reset
(SRESET)Input/ Output Initiates the soft reset flow. The MSC8144E detects an external assertion of SRESET only if it occurs
while the MSC8144E is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET
is driven, the extended cores are reset, and system configuration is maintained.
Host reset
command through
the TAP
Internal When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
Software
watchdog reset Internal When the MSC8144E watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
RapidIO reset Internal When the RapidIO logic asserts the RapidIO hard reset signal, it generates an internal hard reset
sequence.
Software hard
reset Internal A hard reset sequence can be initialized by writing to a memory mapped register (RCR)
Software soft reset Internal A soft reset sequence can be initialized by writing to a memory mapped register (RCR)
Table 18. Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On Reset
(PORESET)Hard Reset (HRESET) Soft Reset (SRESET)
External only External or Internal
(Software Watch dog ,
Software or RapidIO)
External or
internal
Software
JTAG Command:
EXTEST, CLAMP, or
HIGHZ
Configuration pins sampled (Refer to
Section 2.6.3.2 for details).Yes NoNoNo
PLL state reset Yes No No No
Select reset configuration source Yes No No No
System reset configuration write Yes No No No
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 37
2.6.3.1 Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 3 2 CLKIN cycles after
VDD and VDDIO are both at their nominal levels.
2.6.3.2 Reset Configuration
The MSC8144E has two mechanis ms for wri ting the reset configuration:
• Through the I2C port
• Through exte rnal pi ns
• Through internal hard coded
Twenty-three signals (see Section 1 for signal description details) are sampled during the power-on reset sequence to define the
Reset Word Configuration Source and operating conditions:
• RCW_SRC[2–0]
• RC[16–0]
The RCFG_CLKIN_RNG pin must be valid during power-on or hard reset sequence. The STOP_BS pin must be always valid
and is also sampled during power-on reset sequence for RCW loading from an I2C EEPROM.
2.6.3.3 Reset Timing Tables
Table 19 and Figure 7 describe the reset timing for a reset configuration.
HRESET driven Yes Yes No No
IPBus modules reset (TDM, UART, SWT ,
DDRC, IPBus master, GIC, HS, and GPIO) Yes Yes Yes Yes
SRESET driven Yes Yes Yes Depends on command
Extended cores reset Yes Yes Yes Yes
CLASS registers reset Yes Yes Some
registers Some registers
Timers, Performance Monitor Yes Yes No No
QUICC Engine Subsystem, PCI, DMA Yes Yes Most
registers Most registers
Table 19. Timing for a Reset Configuration Write
No. Characteristics Expression Max Min Unit
1 Required external PORESET duration minimum
• 33 MHz <= CLKIN < 44 MHz
• 44 MHz <= CLKIN < 66 MHz
• 66 MHz <= CLKIN < 100 MHz
• 100 MHz <= CLKIN < 133 MHz
32/CLKIN 1280
728
485
320
727
484
320
241
ns
ns
ns
ns
Table 18. Reset Actions for Each Reset Source (continued)
Reset Action/Reset Source
Power-On Reset
(PORESET)Hard Reset (HRESET) Soft Reset (SRESET)
External only External or Internal
(Software Watch dog ,
Software or RapidIO)
External or
internal
Software
JTAG Command:
EXTEST, CLAMP, or
HIGHZ
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor38
See also Reset Errata for PLL lock and reset duration.
2 Delay from de-assertion of external PORESET to HRESET deassertion for
external pins and hard coded RCW
• 33 MHz <= CLKIN < 66 MHz
• 66 MHz <= CLKIN <= 133 MHz
Delay from de-assertion of external PORESET to HRESET deassertion for
loading RCW the I2C interface
• 33 MHz <= CLKIN < 44 MHz
• 44 MHz <= CLKIN < 66 MHz
• 66 MHz <= CLKIN < 100 MHz
• 100 MHz <= CLKIN < 133 MHz
15369/CLKIN
34825/CLKIN
92545/CLKIN
107435/CLKIN
124208/CLKIN
157880/CLKIN
615
528
3702
2441
1882
1579
233
262
2103
1627
1242
1187
μs
μs
μs
μs
μs
μs
3 Delay from H R ES ET deassertion to SRESET deassertion
• REFCLK = 33 MHz to 133 MHz 16/CLKIN 640 120 ns
Note: Timings are not tested, but are guaranteed by design.
Figure 7. Timing for a Reset Configuration Write
Table 19. Timing for a Reset Configura tion Write (continued)
No. Characteristics Expression Max Min Unit
PORESET
HRESET
Input
Output (I/O)
SRESET
Output (I/O)
RCW_SRC2,RCW_SRC1, RCW _SRC 0,STOP_BS and RCFG_CLKIN_RNG
pins must be valid
1
2
3
Reset configuration write
sequence during this
period.
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 39
2.6.4 DDR SDRAM AC Timing Specifications
This section describes the AC electrical characteristics for the DDR SDRAM interface.
2.6.4.1 DDR SDRAM Input Timings
Table 20 provides th e input AC timing specifications for the DDR SDRAM when VDDDDR (typ) = 2.5 V.
Table 21 provides th e input AC timing specifications for the DDR SDRAM when VDDDDR (typ) = 1.8 V.
Table 22 provides the input AC timing specifications for the DDR SDRAM interface.
Table 20. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
Parameter Symbol Min Max Unit
AC input low voltage VIL —MV
REF – 0.31 V
AC input high voltage VIH MVREF + 0.31 — V
Note: At recommended operating conditions with VDDDDR of 2.5 ± 5%.
Table 21. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Parameter Symbol Min Max Unit
AC input low voltage VIL —MV
REF – 0.25 V
AC input high voltage VIH MVREF + 0.25 — V
Note: At recommended operating conditions with VDDDDR of 1.8 ± 5%.
Table 22. DDR SDRAM Input AC Timing Specifications
Parameter Symbol Min Max Unit
Controller Skew for MDQS—MDQ/MECC/MDM1
•400 MHz
•333 MHz
•266 MHz
•200 MHz
tCISKEW –365
–390
–428
–490
365
390
428
490
ps
ps
ps
ps
Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. Subtract this value from the total timing budget.
2. At recommended operating conditions with VDDDDR (1.8 V or 2.5 V) ± 5%
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor40
2.6.4.2 DDR SDRAM Output AC Timing Specifications
Table 23 provides the output AC timing specifications for the DDR SDRAM interface.
Table 23. DDR SDRAM Output AC Timing Specifications
Parameter Symbol 1Min Max Unit
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)2tMCK 510ns
ADDR/CMD output setup with respect to MCK3
•400 MHz
•333 MHz
•266 MHz
•200 MHz
tDDKHAS 1.95
2.40
3.15
4.20
—
—
—
—
ns
ns
ns
ns
ADDR/CMD output hold with respect to MCK3
•400 MHz
•333 MHz
•266 MHz
•200 MHz
tDDKHAX 1.85
2.40
3.15
4.20
—
—
—
—
ns
ns
ns
ns
MCSn output setup with respect to MCK3
•400 MHz
•333 MHz
•266 MHz
•200 MHz
tDDKHCS 1.95
2.40
3.15
4.20
—
—
—
—
ns
ns
ns
ns
MCSn output hold with respect to MCK3
•400 MHz
•333 MHz
•266 MHz
•200 MHz
tDDKHCX 1.95
2.40
3.15
4.20
—
—
—
—
ns
ns
ns
ns
MCK to MDQS Skew4tDDKHMH –0.6 0.6 ns
MDQ/MECC /MDM output setup with respect to MDQS5
•400 MHz
•333 MHz
•266 MHz
•200 MHz
tDDKHDS,
tDDKLDS 700
900
1100
1200
—
—
—
—
ps
ps
ps
ps
MDQ/MECC /MDM output hold with respect to MDQS5
•400 MHz
•333 MHz
•266 MHz
•200 MHz
tDDKHDX,
tDDKLDX 700
900
1100
1200
—
—
—
—
ps
ps
ps
ps
MDQS preamble start6tDDKHMP –0.5 × tMCK – 0.6 –0.5 × tMCK +0.6 ns
MDQS epilogue end6tDDKHME –0.6 0.6 ns
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK mem o ry clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust t he memory clocks by
1/2 applied cycle.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MSC8144 Reference Manual for a description and understanding of the timing modifications
enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MD M). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
7. At recommended operating conditions with VDDDDR (1.8 V or 2.5 V) ± 5%.
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 41
Figure 8 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
Figure 9 shows the DDR SDRAM output timing diagram.
Figure 8. Timing for tDDKHMH
Figure 9. DDR SDRAM Output Timing
MDQS
MCK[n]
MCK[n] tMCK
tDDKH M Hmax ) = 0. 6 ns
tDDKHMH(min) = –0. 6 ns
MDQS
ADDR/CMD
tDDKHAS, tDDKHCS
tDDKHMH
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK[n]
MCK[n] tMCK
tDDKLDX
tDDKHDX
D1D0
tDDKHAX ,tDDKHCX
Write A0 NOOP
tDDKHME
tDDKHMP
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor42
Figure 10 provides the AC test load for the DDR bus.
2.6.5 Serial RapidIO Timing and SGMI I Timing
2.6.5.1 AC Requirements for SRIO_REF_CLK and SRIO_REF_CLK
Table 24 lists AC signal specifications.
2.6.5.2 Signal Definitions
LP-Serial links use differential signalin g. This section defines terms used in the des cri ption and specification of differential
signals. Figure 1 1 shows how the signals are defined. The figure shows waveforms for either a transmitter output (TD and TD)
or a recei ver in put (RD and RD). Each signal swings between voltage levels A and B, where A > B.
Note: This explanation uses generic TD/TD/RD/RD signal names. These correspond to SRIO_TXD/SRIO_TXD/
SRIO_RXD/SRIO_RXD respectively.
Figure 10. DDR AC Test Load
Table 24. SDn_REF_CLK and SDn_REF_CLK AC Signal Specifications
Parameter Description Symbol Min Typical M a x Units Comments
REFC LK cyc le time tREF — 10 (8, 6.4) — ns 8 ns applies only to serial RapidIO system
with 125-MHz reference clock. 6.4 ns
applies only to serial RapidIO systems with
a 156.25 MHz reference clock.
Note: SGMII uses the 8 ns (125 MHz)
value only.
Figure 11. Differential VPP of Transmitter or Receiver
Output Z0 = 50 ΩRL = 50 Ω
VDDDDR/2
Differen tial Peak-Peak = 2
×
(A – B)
A TD or RD
TD or RD
B
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 43
Using these waveforms, the definitions are as follows:
1. The transmitter output signal s and th e receiver input signals TD, TD, RD and RD each have a peak-to-peak voltage
(VPP) swing of A – B.
2. The differential output signal of the transmitter, VOD, is defined as VTD – VTD.
3. The differential input signal of the receiver, VID, is defined as VRD – VRD.
4. The differential output s ignal of the transmitter and the d ifferential input s ignal of the receiver each range fro m A – B
to –(A – B).
5. The peak value of the differential transmitter output signal and the differential receiver input signal is A – B.
6. The value of the differential transmitter output signal and the differential receiver input signal is 2 ×(A – B) VPP.
T o illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common
mode voltage of 2 .25 V and each of its outputs, TD and TD , has a s wing that goes between 2.5 V and 2.0 V. Using these va lues,
the peak-to-peak vo ltag e swing of the signals TD and TD is 500 mVPP. The differential output signal ranges between 500 mV
and –500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mVPP.
Note: AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud
rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI
electrical interface specified in Clause 47 of IEEE™ Std 802.3ae-2002™. XAUI has similar application goals to
serial RapidIO. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs for
XAUI, suitably modified for applications at the baud intervals and reaches described herein.
2.6.5.3 Equalization
W ith the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such
as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye
opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be
used. The most common equalization techniques that can be used are:
• A passive high pass filter network placed at the receiver. This is often referred to as passive equalization.
• The use of active circuits in the receiver. This is often referred to as adaptive equalization.
2.6.5.4 Transmitter Specifications
LP-Serial transmitter electrical and timing sp ecifications are stated in the text an d tab les of th is section. The differential return
loss, S11, of the transmitter in each case shall be better than
• –10 dB for (baud frequency)/10 < freq(f) < 625 MHz, and
• –10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ freq(f) ≤ baud frequency
The reference impedance for the differential return loss measurements is 1 00 Ω resistive. Differential return loss includes
contributions from internal circuitry, packaging, and any external components related to the driver. The output impedance
requirement applies to all valid output levels. It is recommended that the 20–80% rise/fall time of the transmitter, as measured
at the transmitter output, have a minimum value 60 ps in each case. It is also recommended that the timing skew at the output
of an LP-Serial transmitter between the two signals comprising a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50
GB, and 15 ps at 3.125 GB.
Table 25. Short Run Transmitter AC Timing Specifications—1.25 GBaud
Characteristic Symbol Range Unit Notes
Min Max
Output Voltage VO–0.40 2.30 V Voltage relative to COMMON of either signal
comprising a differential pair
Differential Output Voltage V DIFFPP 500 1000 mVPP
Determ inis tic Jit ter JD0.17 UIPP
Total Jitt e r JT0.35 UIPP
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor44
Multiple output skew SMO 1000 ps Skew at the transmitter output between lanes of a
multilane link
Unit Interval UI 800 800 ps ±100 ppm
Table 26. Short Run Transmitter AC Timing Specifications—2.5 GBaud
Characteristic Symbol Range Unit Notes
Min Max
Output Voltage VO–0.40 2.30 V Voltage relative to COMMON of either signal
comprising a differential pair
Differential Output Voltage V DIFFPP 500 1000 mVPP
Determ inis tic Jit ter JD0.17 UIPP
Total Jitt e r JT0.35 UIPP
Multiple Output skew SMO 1000 ps Skew at the transmitter output between lanes of a
multilane link
Unit Interval UI 400 400 ps ±100 ppm
Table 27. Short Run Transmitter AC Timing Specifications—3.125 GBaud
Characteristic Symbol Range Unit Notes
Min Max
Output Voltage VO-0.40 2.30 V Voltage relative to COMMON of either signal
comprising a differential pair
Differential Output Voltage V DIFFPP 500 1000 mVPP
Determ inis tic Jit ter JD0.17 UIPP
Total Jitt e r JT0.35 UIPP
Multiple output skew SMO 1000 ps Skew at the transmitter output between lanes of a
multilane link
Unit Interval UI 320 320 ps ±100 ppm
Table 28. Long Run Transmitter AC Timing Speci fications—1.25 GBaud
Characteristic Symbol Range Unit Notes
Min Max
Output Voltage VO-0.40 2.30 V Voltage relative to COMMON of either signal
comprising a differential pair
Differential Output Voltage V DIFFPP 800 1600 mVPP
Determ inis tic Jit ter JD0.17 UIPP
Total Jitt e r JT0.35 UIPP
Multiple output skew SMO 1000 ps Skew at the transmitter output between lanes of a
multilane link
Unit Interval UI 800 800 ps ±100 ppm
Table 25. Short Run Tra nsmit ter AC Timing Specifications—1.25 GBaud (continued)
Characteristic Symbol Range Unit Notes
Min Max
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 45
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall
entirely within the unsha ded portion of the transmitter outp ut compliance mask shown in Figure 12 with the parameters
specified in Table 31 when measured at the o utput pins of the dev ice and th e device is driving a 100 Ω ±5% dif ferential resistive
load. The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce
inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or
minimized.
Table 29. Long Run Transmitter AC Timing Specifications—2.5 GBaud
Characteristic Symbol Range Unit Notes
Min Max
Output Voltage VO-0.40 2.30 V Voltage relative to COMMON of either signal
comprising a differential pair
Differential Output Voltage V DIFFPP 800 1600 mVPP
Determ inis tic Jit ter JD0.17 UIPP
Total Jitt e r JT0.35 UIPP
Multiple output skew SMO 1000 ps Skew at the transmitter output between lanes of a
multilane link
Unit Interval UI 400 400 ps ±100 ppm
Table 30. Long Run Transmitter AC Timing Specifications—3.125 GBaud
Characteristic Symbol Range Unit Notes
Min Max
Output Voltage VO-0.40 2.30 V Voltage relative to COMMON of either signal
comprising a differential pair
Differential Output Voltage V DIFFPP 800 1600 mVPP
Determ inis tic Jit ter JD0.17 UIPP
Total Jitt e r JT0.35 UIPP
Multiple output skew SMO 1000 ps Skew at the transmitter output between lanes of a
multilane link
Unit Interval UI 320 320 ps ±100 ppm
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor46
Figure 12. Transmitter Output Complia nce M ask
Table 31. Transmitter Differential Output Eye Diagram Parameters
Transmitter Type VDIFFmin (mV) VDIFFmax (m V) A (UI) B (UI)
1.25 GBaud short range 250 500 0.175 0.39
1.25 GBaud long range 400 800 0.175 0.39
2.5 GBaud short range 250 500 0.175 0.39
2.5 GBaud long range 400 800 0.175 0.39
3.125 GBaud short range 250 500 0.175 0.39
3.125 GBaud long range 400 800 0.175 0.39
0
VDIFF min
VDIFF max
-VDIFF min
-VDIFF max
0B1-B1
Time in UI
Transmitter Differential Output Voltage
A1-A
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 47
2.6.5.5 Receiver Specifications
LP-Serial receiver electrical and timing specifications are stated in the text and tab les of this section. Rec eiver input impedance
shall result in a differential return loss better that 10 dB and a common mode return loss better than 6 dB from 100 MHz to 0.8
× baud frequency. This includes contributions from internal circuitry, the package, and any extern al components related to the
receiver. AC coupling components are included in this requirement. The reference impedance for return loss measurements is
100 Ω resistive for differential return loss and 25 Ω resistive for common mode.
Table 32. Receiver AC Timing Specifications—1.25 GBa ud
Characteristic Symbol Range Unit Notes
Min Max
Differential Input Voltage VIN 200 1600 mVPP Measured at receiver
Deterministic Jit ter Tolerance JD0.37 UIPP Measured at receiver
Combined Deterministic and Random
Jitter Tolerance JDR 0.55 UIPP Measured at receiver
Total Jitt e r Tolera n ce JT0.65 UIPP Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 13. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew SMI 24 ns Skew at the receiver input between lanes of a
multilane link
Bit Error Rate BER 10–12
Unit Interval UI 800 800 ps ±100 ppm
Table 33. Receiver AC Timing Specifications—2.5 GBaud
Characteristic Symbol Range Unit Notes
Min Max
Differential Input Voltage VIN 200 1600 mVPP Measured at receiver
Deterministic Jit ter Tolerance JD0.37 UIPP Measured at receiver
Combined Deterministic and Random
Jitter Tolerance JDR 0.55 UIPP Measured at receiver
Total Jitt e r Tolera n ce JT0.65 UIPP Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 13. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew SMI 24 ns Skew at the receiver input between lanes of a
multilane link
Bit Error Rate BER 10–12
Unit Interval UI 400 400 ps ±100 ppm
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor48
Table 34. Receiver AC Timing Specifications—3.125 GBaud
Characteristic Symbol Range Unit Notes
Min Max
Differential Input Voltage VIN 200 1600 mVPP Measured at receiver
Deterministic Jit ter Tolerance JD0.37 UIPP Measured at receiver
Combined Deterministic and Random
Jitter Tolerance JDR 0.55 UIPP Measured at receiver
Total Jitt e r Tolera n ce JT0.65 UIPP Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 13. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew SMI 22 ns Skew at the receiver input between lanes of a
multilane link
Bit Error Rate BER 10–12
Unit Interval UI 320 320 ps ±100 ppm
Figure 13. Single Frequency Sinusoidal Jitter Limit s
8.5 UI p-p
0.10 UI p-p
Sinusoidal
Jitter
Amplitude
22.1 kHz 1.875 MHz 20 MHzFrequency
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 49
2.6.5.6 Receiver Eye Diagrams
For each bau d rate at which an LP-Serial receiv er is specified to oper ate, the receiver shall meet the correspondin g bit error rate
specification (Table 32, Table 33, and Table 34) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter)
falls entirely within the unshaded portion of the receiver input compliance mask shown in Figure 14 with the parameters
specified in Table 35. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the
device replaced with a 100 Ω ±5% differential resistive load.
2.6.5.7 Measurement and Test Requirements
Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE Std.
802.3ae-20 02™, the measurement and tes t requirements defined her e are similarly guided by C lause 47. In addition, the CJPAT
test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter
measurements. Annex 48B of IEEE Std. 802.3ae-2002 is recommended as a reference for additional information on jitter test
methods.
Figure 14. Receiver Input Compliance Mask
Table 35. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
Receiver Type V DIFFmin (mV) VDIFFmax (mV) A (UI) B (UI)
1.25 GBaud 100 800 0.275 0.400
2.5 GBaud 100 800 0.275 0.400
3.125 GBaud 100 800 0.275 0.400
10
VDIFF max
–VDIFF max
VDIFF min
–VDIFF min
Time (UI)
Receiver Differential Input Voltage
0
A B 1 – B 1 – A
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor50
2.6.5.8 Eye Template Measurements
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point at (baud
frequency)/1667 is applied to the jitter . The data pattern for template measurements is the continuous jitter test pattern (CJPAT)
defined in Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive
directions , and oppo site ends of the l inks shall us e asynchronou s clocks . Four lan e implementat ions shall u se CJPAT as defined
in Annex 48 A. Sing le lan e impl ementa ti ons sh al l use the CJ PAT sequence speci fied i n Annex 48A for trans mi ssi on on la ne 0.
The amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10–12. The eye pattern
shall be measured with AC couplin g and the compliance template centered at 0 Volts differential. The left and right edges of
the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100 Ω
resistive ±5% differential to 2.5 GHz.
2.6.5.9 Jitter Test Measurements
For the purpo se of jitter measurement , the effects of a sing le-pole high pass filter with a 3 dB point at (baud frequency)/16 67 is
applied to the jitter. The data pattern for jitter measurements is the Con tinuous Jitter Test Pattern (CJPAT) pattern defined in
Annex 48A of IEEE Std. 802.3 ae. All lanes of the LP-Serial link shall be active in both th e transmit and receive directions, and
opposi te ends of the link s shall use asynchron ous cloc ks. Four lane impl ementations shall use CJPAT as define d in Annex 48 A.
Single lane implementat ions shall use the CJPAT sequ ence specif ied in Annex 48A for transmis sion on lane 0. Jitter shall be
measured with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance
setup) shall be performed with a test procedure result ing in a BER curve such as that described in Annex 48B of IEEE Std.
802.3ae.
2.6.5.10 Transmit Jitter
Transmit jitter is measured at the driver output wh en terminated into a load of 100 Ω resistive ±5% differential to 2.5 GHz.
2.6.5.11 Jitter Tolerance
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum
of deterministic and random jitter defined in Section 2.6.5.9 and then adjusting the signal amplitude until the data eye contacts
the 6 points of the minimum eye opening of the receive template shown in Figure 14 and Table 35. Note that for this to occur,
the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)
about the mean zero crossing. Eye template measurement requ irements are as defined above. Random jitter is calibrated using
a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter
specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.
2.6.6 PCI Timing
This section describes th e gene r a l AC timing parameters of the PC I bus . Table 36 provides the PCI AC timing specifications.
Table 36. PCI AC Timing Specifications
Parameter Symbol 33 MHz 66 MHz Unit
Min Max Min Max
Output delay tPCVAL 2.0 11.0 1.0 6.0 ns
High-Z to Valid Output delay tPCON 2.0 — 1.0 — ns
Valid to High-Z Output delay tPCOFF — 28 — 14 ns
Input setup tPCSU 7.0 — 3.0 — ns
Input hold tPCH 0—0—ns
Electrical Characteri stics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 51
Figure 15 provides the AC test load for the PCI.
Figure 16 shows the PCI input AC timing cond itions.
Figure 17 shows the PCI output AC timing conditions.
Notes: 1. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
2. All PCI signals are measured from 0.5 × VDDIO of the rising edge of PCI_CLK_IN to 0.4 × VDDIO of the signal in question for
3.3-V PCI signaling levels.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. The reset assertion timing requirement for HRESET is in Table 19 and Figure 7
Figure 15. PCI AC Test L oad
Figure 16. PCI Input AC Timing Measurement Conditions
Figure 17. PCI Output AC Timing Measurement Condition
Table 36. PCI AC Timing Specifications (continued)
Parameter Symbol 33 MHz 66 MHz Unit
Min Max Min Max
Output Z0 = 50 ΩVDD/2
RL = 50 Ω
tPCSU
CLK
Input
tPCH
CLK
Output Delay
tPCVAL
High-Impedance
tPCOFF
Output
tPCON
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freesca le Sem ico nd uctor52
2.6.7 TDM Timing
Figure 18 shows the TDM input AC timing.
Note: For some TDM modes, receive data and receive sync are input on other pins. This timing is also valid for them. See
the MSC8144E Reference Manual.
Figure 19 shows TDMxTSYN AC timing in TSO=0 mode.
Figure 20 shows the TDM Output AC timing
Table 37. TDM Timing
Characteristic Symbol Expression Min Max Units
TDMxRCLK/TDMxTCLK tTDMC TC116 — ns
TDMxRCLK/TDMxTCLK high pulse width t TDMCH (0.5 ± 0.1) × TC47—ns
TDMxRCLK/TDMxTCLK low pulse width tTDMCL (0.5 ± 0.1) × TC47—ns
TDM receive all input setup time related to TDMxRCLK
TDMxTSYN inpu t setup time related to TDMxTCLK in TSO=0 mode tTDMVKH 3.6 — ns
TDM receive all input hold time related to TDMxRCLK
TDMxTSYN input hold time related to TDMxTCLK in TSO=0 mode tTDMXKH 1.9 — ns
TDMxTCLK high to TDMxTDA T output active2tTDMDHOX 2.5 — ns
TDMxTCLK high to TDMxTDA T output valid2tTDMDHOV —9.8ns
All output hold time (except TDMxTSYN) 3tTDMHOX 2.5 — ns
TDMxTCLK high to TDMxTDAT output high impedance2tTDMDHOZ —9.8ns
TDMxTCLK high to TDMxTSYN output valid2tTDMSHOV —9.25ns
TDMxTSYN output hold time3tTDMSHOX 2.0 — ns
Notes: 1. Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.
2. Values are based on 20 pF capacitive load.
3. Values are based on 10 pF capacitive load.
4. The expression is for common calculations only.
Figure 18. TDM Inputs Signals
Figure 19. TDMxTSYN in TSO=0 mode
TDMxRCLK
TDMxRDAT
TDMxRSYN
tTDMC
tTDMCH tTDMCL
tTDMVKH
tTDMVKH tTDMXKH
tTDMXKH
TDMxTCLK
TDMxTSYN
tTDMVKH tTDMXKH
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 53
Note: For some TDM modes, transmit data is output on other pins. This timing is also valid for those pins. See the
MSC8144E Reference Manual
2.6.8 UART Timing
Figure 21 shows the UART input AC timin g
Figure 22 shows the UART output AC tim ing
Figure 20. TDM Output Signals
Table 38. UART Timing
Characteristics Symbol Expression Min Max Unit
URXD and UTXD inputs high/low duration TUREFCLK 16 × TREFCLK 160 — ns
Note: TUREFCLK = TREFCLK is guaranteed by design.
Figure 21. UART Input Timing
Figure 22. UART Output Timing
TDMxTCLK
TDMxTDAT
~
~
TDMxTSYN
~
~
tTDMDHOX
tTDMDHOV tTDMDHOZ
tTDMHOX
tTDMC
tTDMCH tTDMCL
tTDMSHOX
tTDMSHOV
UTXD, URXD
TUREFCLK
inputs
TUREFCLK
UTXD output
TUREFCLK TUREFCLK
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor54
2.6.9 Timer Timing
Figure 23 shows the timer input AC timing
2.6.10 Ethernet Timing
This section describes the AC electrical characteristics for the Ethernet interface.
There are programmable delay units (PDU) that should be programmed dif ferently for each Interface to meet timing. There is
a general configuration register 4 (GCR4) used to configure the timing. For additi onal in for m ation, see the MSC8144E
Reference Manual .
2.6.10.1 Management Interface Timing
Table 39. Timer Timing
Characteristics Symbol Min Unit
TIMERx frequency TTMREFCLK 10.0 ns
TIMERx Input high phase TTMCH 4.0 ns
TIMERx Output low phase TTMCL 4.0 ns
Figure 23. Timer Timing
Table 40. Ethernet Controller Management Interface Timing
Characteristics Symbol Min Max Unit
ETHMDC to ETHMDIO delay2tMDKHDX 10 70 ns
ETHMDIO to ETHMDC rising edge setup time tMDDVKH 7—ns
ETHMDC rising edge to ETHMDIO hold time tMDDXKH 0—ns
Notes: 1. Program the ETHMDC frequency (fMDC) to a maximum value of 2.5 MHz (400 ns period for tMDC). The value depends on the
source clock and configuration of MIIMCFG[MCS] and UPSM R[MDCP] . For example, for a source clock of 400 MHz, to
achieve fMDC = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8144E Reference Manual for
configuration details.
2. The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of
333 MHz, the delay is 58 ns.
TTMREFCLK
TTMCL
T
TMCH
TIMERx (Input)
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 55
2.6.10.2 MII Transmit AC Timing Specifications
Table 41 provides the MII transmit AC timing specifications.
Figure 25 shows the MII transmit AC timing diagram .
2.6.10.3 MII Receive AC Timing Specifications
Table 42 provides the MII receive AC timing specifications.
Figure 24. MII Management Interface Timing
Table 41. MII Transmit AC Timing Specifications
Parameter/Condition Symbol 1Min Max Unit
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 025ns
Notes: 1. Typical TX_CLK period (tMTX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.
2. Program GCR4 as 0x00030CC3.
Figure 25. MII Transmit AC Timing
Table 42. MII Receive AC Timing Specifications
Parameter/Condition Symbol 1Min Max Unit
RXD[3:0], RX_DV, RX_ER set up time to RX_CLK tMRDVKH 10.0 — ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 2—ns
Notes: 1. Typical RX_CLK period (tMRX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.
2. Program GCR4 as 0x00030CC3.
ETHMDC
ETHMDIO
ETHMDIO
(Input)
(Output)
t
MDC
tMDDXKH
tMDDVKH
tMDKHDX
TX_CLK
TXD[3:0]
tMTKHDX
TX_EN
TX_ER
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor56
Figure 26 provides the AC test load.
Figure 27 shows the MII receive AC timing diagram.
2.6.10.4 RMII Transmit and Receive AC Timing Specifications
Table 43 provides the RMII transmit and receive AC timing specifications.
Figure 26. AC Test Load
Figure 27. MII Receive AC Timing
Table 43. RMII Transmit and Receive AC Timing Specifications
Parameter/Condition Symbol 1Min Max Unit
REF_CLK duty cycle tRMXH/tRMX 35 65 %
REF_CLK to RMII data TXD[1–0], TX_EN delay tRMTKHDX 210ns
RXD[1–0], CRS_DV, RX_ER setup time to REF_CLK tRMRDVKH 4.0 — ns
RXD[1–0], CRS_DV, RX_ER hold time to REF_CLK tRMRDXKH 2.0 — ns
REF_CLK data clock rise tRMXR 1.0 4.0 ns
REF_CLK data clock fall tRMXF 1.0 4.0 ns
Typical REF_CLK clock period (tRMX) is 20 ns
Notes: 1. Ty pical REF_CLK clock period (t RMX) is 20 ns
2. Program GCR4 as 0x00001405
Output Z0 = 50 ΩVDDGE/2
RL = 50 Ω
RX_CLK
RXD[3:0]
tMRDXKH
RX_DV
RX_ER tMRDVKH
Valid Data
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 57
Figure 28 shows the RMII transmit and receive AC timing diagram.
Figure 29 provides the AC test load.
2.6.10.5 SMII AC Timing Specification
Figure 30 shows the SMII Mode signal timing.
Figure 28. RMII Transmit and Receive AC Timing
Figure 29. AC Test Load
Table 44. SMII Mode Signal Timing
Characteristics Symbol Min Max Unit
ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge setup time tSMDVKH 1.5 — ns
ETHCLOCK rising edge to ETHSYNC_IN, ETHRX D hold time tSMDXKH 1.0 — ns
ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay tSMXR 1.5 5.0 ns
Notes: 1. Typical REF_CLK clock period is 8ns
2. Measured using a 5 pF load.
3. Measured using a 15 pF load
4. Program GCR4 as 0x00002008
REF_CLK
TXD[1–0]
tRMTKHDX
tRMX
tRMXH
tRMXR
tRMXF
TX_EN
RXD[1–0]
tRMRDXKH
CRS_DV
RX_ER tRMRDVKH
Valid Data
Output Z0 = 50 ΩVDDGE/2
RL = 50 Ω
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor58
Figure 30. SMII Mode Signal Timing
2.6.10.6 RGMII AC T iming Specifications
Table 45 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.
Table 46 presents the RGMII AC timing specification for applications required non-delayed clock on board.
Table 45. RGMII with On-Board Delay AC Timing Specifications
Parameter/Condition Symbol Min Typ Max Unit
Data to clock output skew (at transmitter) tSKEWT -0.5 — 0.5 ns
Data to clock input skew (at receiver) 2tSKEWR 0.9 — 2.6 ns
Clock cycle duration 3tRGT 7.2 8.0 8.8 ns
Duty cycle for 1000Base-T 4, 5 tRGTH/tRGT 45 50 55 %
Duty cycle for 10BASE-T and 100BASE-TX 3, 5 tRGTH/tRGT 40 50 60 %
Rise time (20%–80%) tRGTR — — 0.75 ns
Fall time (20%–80%) tRGTF — — 0.75 ns
GTX_CL K125 reference clock period tG12 6—8.0—ns
GTX_C LK125 ref erence clock duty cycle tG125H/tG125 45 — 55 %
Notes: 1. At recommended operating conditions with LVDD of 2.5 V +/- 5%.
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will
be added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned
between.
5. Duty cycle reference is LVdd/2.
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7. GCR4 should be programmed as 0x00001004.
Table 46. RGMII with No On-Board Delay AC Timing Specifications
Parameter/Condition Symbol Min Typ Max Unit
Data to clock output skew (at transmitter) tSKEWT –2.6 — –0.9 ns
Data to clock input skew (at receiver) 2tSKEWR –0.5 — 0.5 ns
Notes: 1. At recommended operating conditions with LVDD of 2.5 V +/- 5%.
2. This implies that PC board design will require clocks to be routed with no additional trace delay
3. GCR4 should be programmed as 0x0004C130.
Valid
ETHCLOCK
ETHSYNC_IN
ETHRXD
ETHSYNC
ETHTXD Valid Valid
tSMXR
tSMDXKH
tSMDVKH
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 59
Figure 31 shows the RGMII AC timing and multiplexing diagrams.
Figure 31. RGMII AC Timing and Multiplexing
GTX_CLK
tSKEWT
TX_CTL
TXD[8:5]
TXD[7:4]
TXD[9]
TXERR
TXD[4]
TXEN
TXD[3:0]
(At DSP)
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CLK
(At PHY)
RX_CTL
RXD[8:5]
RXD[7:4]
RXD[9]
RXERR
RXD[4]
RXDV
RXD[3:0]
RXD[8:5][3:0]
RXD[7:4][3:0]
RX_CLK
(At DSP)
tSKEWR
tSKEWR
tSKEWT
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor60
2.6.11 ATM/UTOPIA/POS Timing
Table 47 provides th e ATM/UTOPIA/POS input and outp ut AC tim ing specifications.
Figure 32 provides the AC test load for the ATM/UTOPIA/PO S.
Figure 33 shows the ATM/UTOPIA/UTOPIA timing with external clock.
Table 47. ATM/UTOPIA/POS AC Timing (External Clock) Specifications
Characteristic Symbol Min Max Unit
Outputs—External clock delay tUEKHOV 19ns
Outputs—External clock High Impedance1tUEKHOX 19ns
Inputs—External clock input setup time tUEIVKH 4ns
Inputs—External clock input hold time tUEIXKH 1ns
Notes: 1. Not tested. Guaranteed by design.
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin. Although the specifications generally reference the rising edge of the clock, these AC timing diagrams
also apply when the falling edge is the active edge.
Figure 32. ATM/UT OPIA/POS AC Test Load
Figure 33. ATM/UTOPIAPOS AC Timing (External Clock)
Output Z0 = 50 ΩVDD/2
RL = 50 Ω
CLK (input)
tUEIXKH
tUEIVKH
tUEKHOV
Input Signals:
Output Signals:
t
UEKHOX
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 61
2.6.12 SPI Timing
Table 48 lists the SPI input and output AC timing specifications.
Figure 34 provides the AC test load for the SPI.
Figure 34. SPI AC Test Load
Figure 35 and Figure 36 represent the AC timings from Table 48. Note that althoug h th e s pecifications g enerally reference the
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 35 shows the SPI timings in slave mode (external clock).
Figure 35. SPI AC Timing in Slave Mode (External Clock)
Figure 36 shows the SPI timings in master mode (internal clock).
Table 48. SPI AC Timing Specifications 1
Characteristic Symbol
2Min Max Unit
SPI outputs valid—Master mode (internal clock) delay tNIKHOV 6ns
SPI outputs hold—Master mode (internal clock) delay tNIKHOX 0.5 ns
SPI outputs valid—Slave mode (external clock) delay tNEKHOV 8ns
SPI outputs hold—Slave mode (external clock) delay tNEKHOX 2ns
SPI inputs—Master mode (internal clock) input setup time tNIIVKH 4ns
SPI inputs—Master mode (internal clock) input hold time tNIIXKH 0ns
SPI inputs—Slave mode (external clock) input setup time tNEIVKH 4ns
SPI inputs—Slave mode (external clock) input hold time tNEIXKH 2ns
Notes: 1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.
Timings are measured at the pin.
2. The symbols for timing specifications follow the pattern of t(first two lett ers of fun ctional blo ck) (si g na l)(state) (reference)( sta te) f or inputs and
t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing (NI) for
the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
Output Z0 = 50 ΩOVDD/
2
RL = 50 Ω
SPICLK (Input)
tNEIXKH
tNEIVKH
tNEKHOX
Input Signals:
SPIMOSI
(See Note)
Output Sign als :
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor62
Figure 36. SPI AC Timing in Master Mode (Internal Clock)
2.6.13 Asynchro nous Si gnal Timing
The following interfaces use the specified asynchronous signals:
•GPIO. Signals GPIO[31–0], when used as GPIO signals, that is, when the alternate multiplexed special functions are
not selected.
Note: When used as a GPI, the input should be driven until it is acknowledged by the device; the GPIO input status is read
from a register.
•EE port. Signals EE0, EE1, EE2_0, EE2_1, EE2_2, and EE2_3.
•Boot function. Signal STOP_BS.
•I2C interface. Signals I2C_SCL and I2C_SDA.
•Interru pt inputs. Signals IRQ[15–0] and NMI.
•Interr upt outputs. Signals INT_OUT and NMI_OUT (pulse width is 10 ns).
Figure 37 shows the behavior of the asynchronous signals.
Table 49. Signal Timing
Characteristics Symbol Type Min
Input tIN Asynchronous One CLKIN cycle1
Output tOUT Asynchronous A pplication dependent
Note: 1. Relevant for EE0, IRQ[15–0], and NMI only.
Figure 37. Asynchronous Signal Timing
SPICLK (Output)
tNIIXKH
tNIKHOX
Input Signals:
SPIMISO
(See Note)
Output Sign als :
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
tNIIVKH
Output
tIN
Input
tOUT
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 63
2.6.14 JTAG Signals
Figure 38 Shows the Test Clock Input Timing Diagram
Figure 39 Shows the boundary scan (JTAG) timing diagram.
Table 50. JTAG Timing
Characteristics Symbol All frequenci e s Unit
Min Max
TCK cycle time tTCKX 36.0 — ns
TCK clock high phase measured at VM = 1.6 V tTCKH 15.0 — ns
TCK rise and fall times tTCKR —3.0ns
Boundary scan input data setup time tBSVKH 0.0 — ns
Boundary scan input data hold time tBSXKH 15.0 — ns
TCK fall to output data valid tTCKHOV — 20.0 ns
TCK fall to output high impedance tTCKHOZ — 24.0 ns
TMS, TDI data setup time tTDIVKH 0.0 — ns
TMS, TDI data hold time tTDIXKH 5.0 — ns
TCK fall to TDO data valid tTDOHOV — 10.0 ns
TCK fall to TDO high impedance tTDOHOZ — 12.0 ns
TRST assert time tTRST 100.0 — ns
Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.
Figure 38. Test Clock Input Timing
Figure 39. Boundary Scan (JTAG) Timing
TCK
(Input)
VMVM
t
TCKX
tTCKH
tTCKR
tTCKR
TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
Input Data Valid
Output Data Valid
tBSXKH
tBSVKH
tTCKHOV
tTCKHOZ
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freesca le Sem ico nd uctor64
Figure 40 Shows the test access port timing diagram
Figure 41 Shows the TRST timing diagram.
3 Hardware Des ign Considerations
The following sections discuss areas to consider when the MSC8144E device is designed into a system.
3.1 Start-up Sequencing Recommendations
3.1.1 Power-on Sequence
Use the following guidelines for power-on sequencing:
• There are no dependencies in power-on/power-off sequence between VDDM3 and VDD supplies.
• There are no dependencies in power-on/power-off sequence between RapidIO supplies: VDDSXC, VDDSXP,
VDDRIOPLL and other MSC8144E supplies.
•V
DDPLL should be coupled with the VDD power rail with extremely low impedance path.
External voltage applied to any input line must not exceed the related to this port I/O supply by more than 0.6 V at any time,
including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for
configuration purposes. This is an acceptable exception to the rule during start-up. However , each such input can draw up to 80
mA per input pin per MSC8144E device in the system during start-up. An assertion of the inputs to the high voltage level before
power-up should be with slew rate less than 4V/ns.
Figure 40. Test Access Port Timing
Figure 41. TRST Timing
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
Input Data Valid
Output Data Va lid
TMS
tTDIVKH tTDIXKH
tTDOHOV
tTDOHOZ
TRST
(Input) tTRST
Hardware Design Considerations
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 65
The following supplies should rise before any other supplies in any sequence
•V
DD and VDDPLL coupled together
•V
DDM3
After the ab ove supplies rise to 90 % of their nominal value the fo llowing I/ O supplies ma y rise in any sequen ce (see Figure 42):
•V
DDGE1
•V
DDGE2
•V
DDIO
•VDDDDR and MVREF coupled one to another. MVREF should be either at same time or after VDDDDR.
•V
DDM3IO
•V
25M3
Note: 1. This recommended power sequencing is different from the MSC8122/MSC8126.
2. If no pins that require VDDGE1 as a reference supply are used (see Table 1), VDDGE1 can be tied to GND.
3. If no pins that require VDDGE2 as a reference supply are used (see Table 1), VDDGE2 can be tied to GND.
4. If the DDR interface is not used, VDDDDR and MVREF can be tied to GND.
5. If the M3 memory is not used, VDDM3, VDDM3IO, and V25M3 can be tied to GND.
6. If the RapidIO interface is not used, VDDSX, VDDSXP, and VDDRIOPLL can be tied to GND.
3.1.2 Start-Up Timing
Section 2.6.1 describes the start-up tim ing.
3.2 Power Supply Design Considerations
Each PLL supply must have an external RC filter for the VDDPLL input. The filter is a 10 Ω resistor in series with two 2.2 μF,
low ESL (<0.5 nH) and low ESR capacitors. All three PLLs can connect to a single supply voltage source (such as a voltage
regulator) as long as the external RC filter is app lied to each PLL separately (see Fi gu re 43). For op timal noise filtering, place
the circuit as close as possible to its VDDPLL inputs. These traces should be short and direct.
Figure 42. VDDM3, VDDM3IO and V25M3 Power-on Sequence
VDDM3, VDD, and VDDPLL
90%
I/O supplies
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Hardware Design Considerations
Freesca le Sem ico nd uctor66
Figure 43. PLL Supplies
3.3 Clock and Timing Signal Board Layout Considerations
When laying out the system board, use the following guidelines:
• Keep clock and timing signal paths as short as possible and route with 50 Ω impedance.
• Use a serial termination resistor placed close to the clock buffer to minimize signal reflection. Use the following
equation to compute the resist or value:
Rterm = Rim – Rbuf
where Rim = trace characteristic impedance
Rbuf = clock buffer internal impedance.
Note: See MSC8144 CLKIN and PCI_CLK_IN Board Layout (AN3440) for an example layout.
3.4 Connectivity Guidelines
Note: Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal
connections in this discussion.
First, select the pin multiplexing mode to allocate the requir e d I/O signals. Then use the guidelin es p resented in the following
subsection s for board design a nd conn ections . The fo llowing convent ions ar e used in descr ibing the co nnectivity requiremen ts:
1. GND indicates using a 10 kΩ pull-down resistor (recommended) or a direct connection to the ground plane. Direct
connection s to t he gr oun d plane may yield DC current up to 50 mA th rou gh t he I/O su ppl y t hat add s to ov eral l pow er
consumption.
2. VDD indicates using a 10 kΩ pull-up resistor (recommended) or a direct connection to the appropriate power supply.
Direct connections to the supply may y ield DC cur rent u p to 5 0mA t h rou gh the I/O su ppl y t hat ad ds t o over a ll po wer
consumption.
3. Mandatory use of a pull-up or pull-down resistor it is clearly indicated as “pull-up/pull-down”.
MSC8144E
VDDPLL0
10 Ω
2.2 μF2.2 μF
VDDPLL0
10 Ω
2.2 μF2.2 μF
VDDPLL0
10 Ω
2.2 μF2.2 μF
Voltage Regulator
Hardware Design Considerations
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 67
4. NC indicates “not connected” and means do not connect anything to the pin.
5. The phrase “in use” indicates a typical pin connection for the required function.
Note: Please see recommendations #1 and #2 as mandatory pull-down or pull-up connection for unused pins in case of
subset interface connection.
3.4.1 DDR Memory Related Pins
This section discusses the various scenarios that can be used with DDR1 and DDR2 memory.
Note: For information about unused differential/non-differential pins in DDR1/DDR2 modes (that is, unused negative lines
of strobes in DDR1), please refer to Table 51.
3.4.1.1 DDR Interface Is Not Used
Table 51. Connectivity of DDR Related Pins When the DDR Interface Is Not Used
Signal Name Pin Connection
MDQ[0–31] NC
MDQS[0–3] NC
MDQS[0–3] NC
MA[0–15] NC
MCK[0–2] NC
MCK[0–2] NC
MCS[0–1] NC
MDM[0–3] NC
MBA[0–2] NC
MCAS NC
MCKE[0–1] NC
MODT[0–1] NC
MDIC[0–1] NC
MRAS NC
MWE NC
MECC[0–7] NC
ECC_MDM NC
ECC_MDQS NC
ECC_MDQS NC
MVREF GND
VDDDDR GND
Note: If the DDR controller is not used, disable the internal DDR clock by writing a 1 to the CLK11DIS bit in the System Clock Control
Register (SCCR[CLK!11DIS]). See Cha pter 7, Clocks, in the M SC 8144E Reference Man ual for details.
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Hardware Design Considerations
Freesca le Sem ico nd uctor68
3.4.1.2 16-Bit DDR Memory Only
Table 52 lists unused pin connection when using 16-bit DDR me m ory. The 16 most significant data lines are not used.
3.4.1.3 ECC Unused Pin Connections
When the error code corrected mechanism is not used i n any 32- or 16-bit DDR configuration, refer to Table 53 to determine
the correct pin connections.
Table 52. Connectivity of DDR Related Pins When Using 16-bit DDR Memory Only
Signal Name Pin connection
MDQ[0–15] in use
MDQ[16–31] pull-up to VDDDDR
MDQS[0–1] in use
MDQS[2–3] pull-down to GND
MDQS[0–1] in use
MDQS[2–3]pull-up to VDDDDR
MA[0–15] in use
MCK[0–2] in use
MCK[0–2] in use
MCS[0–1]in use
MDM[0–1] in use
MDM[2–3] NC
MBA[0–2] in use
MCAS in use
MCKE[0–1] in use
MODT[0–1] in use
MDIC[0–1] in use
MRAS in use
MWE in use
MVREF 1/2*VDDDDR
VDDDDR 2.5 V or 1.8 V
Table 53. Connectivity of Unused ECC Mechanism Pins
Signal Name Pin connection
MECC[0–7] pull-up to VDDDDR
ECC_MDM NC
ECC_MDQS pull-down to GND
ECC_MDQS pull-up to VDDDDR
Hardware Design Considerations
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 69
3.4.2 Serial RapidIO Interface Related Pins
3.4.2.1 Serial RapidIO interface Is Not Used
3.4.2.2 Serial RapidIO Specific Lane Is Not Used
Table 54. Connectivity of Serial RapidIO Interface Related Pins When the RapidIO Interface Is Not Used
Signal Name Pin Connection
SRIO_IMP_CAL_RX GND
SRIO_IMP_CAL_TX GND
SRIO_REF_CLK GND
SRIO_REF_CLK GND
SRIO_RXD[0–3] GND
SRIO_RXD[0–3] GND
SRIO_TXD[0–3] NC
SRIO_TXD[0–3] NC
VDDRIOPLL GND
GNDRIOPLL GND
GNDSXP GND
GNDSXC GND
VDDSXP GND
VDDSXC GND
Table 55. Connectivity of Serial RapidIO Related Pins When Specific Lane Is Not Used
Signal Name Pin Connection
SRIO_IMP_CAL_RX in use
SRIO_IMP_CAL_TX in use
SRIO_REF_CLK in use
SRIO_REF_CLK in use
SRIO_RXDxGNDSXC
SRIO_RXDxGNDSXC
SRIO_TXDxNC
SRIO_TXDxNC
VDDRIOPLL in use
GNDRIOPLL in use
GNDSXP GNDSXP
GNDSXC GNDSXC
VDDSXP 1.0 V
VDDSXC 1.0 V
Note: The x indicates the lane number {0,1,2,3} for all unused lanes.
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Hardware Design Considerations
Freesca le Sem ico nd uctor70
3.4.3 M3 Memory Related Pins
3.4.4 Ethernet Related Pins
3.4.4.1 Ethernet Controller 1 (GE1) Related Pins
Note: Table 57 and Table 58 assume that the alternate function of the specified pin is not used. If the alternate function is
used, connect the pin as required to support that function.
3.4.4.1.1 GE1 Interface Is Not Used
Table 57 assumes that the GE1 signals are not used for any purpos e (includin g any multiplexed fu nction s) and that VDDGE1 is
tied to GND.
Table 56. Connectivity of M3 Related Pins When M3 Memory Is Not Used
Signal Name Pin Connection
M3_RESET NC
V25M3 GND
VDDM3 GND
VDDM3IO GND
Table 57. Connectivity of GE1 Related Pins When the GE1 Interface Is Not Used
Signal Name Pin Connection
GE1_COL NC
GE1_CRS NC
GE1_RD[0–4] NC
GE1_RX_ER NC
GE1_RX_CLK NC
GE1_RX_DV NC
GE1_SGMII_RX GNDSXC
GE1_SGMII_RX GNDSXC
GE1_SGMII_TX NC
GE1_SGMII_TX NC
GE1_TD[0–4] NC
GE1_TX_CLK NC
GE1_TX_EN NC
GE1_TX_ER NC
Hardware Design Considerations
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 71
3.4.4.1.2 Subset of GE1 Pins Required
When only a subset of the whole GE1 interface is used, such as for RMII, the unused GE1 pins should be connected as described
in Table 58. This table assumes that the unused GE1 pins are not used for any purpose (including any multiplexed function) and
that VDDGE1 is tied to either 2.5 V or 3.3 V.
3.4.4.2 Ethernet Controller 2 (GE2) Related Pins
Note: Table 59 thro ugh Table 61 assume that the alternate function of the specified pin is not used. If the alternate function
is used, connect the pin as required to support that function.
3.4.4.2.1 GE2 interface Is Not Used
Table 59 assumes that the GE2 pins are not used for any purpose (including any multiplexed function) and that VDDGE2 is tied
to GND.
Table 58. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required
Signal Name Pin Connection
GE1_COL GND
GE1_CRS GND
GE1_RD[0–3] GND
GE1_RX_ER GND
GE1_RX_CLK GND
GE1_RX_DV GND
GE1_SGMII_RX GNDSXC
GE1_SGMII_RX GNDSXC
GE1_SGMII_TX NC
GE1_SGMII_TX NC
GE1_TD[0-3] NC
GE1_TX_CLK GND
GE1_TX_EN NC
GE1_TX_ER NC
Table 59. Connectivity of GE2 Related Pins When the GE2 Interface Is Not Used
Signal Name Pin Connection
GE2_RD[0-3] NC
GE2_RX_CLK NC
GE2_RX_DV NC
GE2_RX_ER NC
GE2_SGMII_RX GNDSXC
GE2_SGMII_RX GNDSXC
GE2_SGMII_TX NC
GE2_SGMII_TX NC
GE2_TCK Nc
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Hardware Design Considerations
Freesca le Sem ico nd uctor72
3.4.4.2.2 Subset of GE2 Pins Required
When only a subset of the whole GE2 interface is used, such as for RMII, th e unused GE2 pins should be connected as described
in Table 60. The table assumes that the unused GE2 pins are not used for any purpose (including any multiplexed functions)
and that VDDGE2 is tied to either 2.5 V or 3.3 V.
3.4.4.3 GE1 and GE2 Management Pins
GE_MDC and GE_MDIO pins should be connect ed as required by the specified pro tocol. If neither GE1 nor GE2 is used (that
is, VDDGE2 is connected to GND), Table 61 lists the recommended management pin connections.
GE2_TD[0–3] Nc
GE2_TX_EN NC
Table 60. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required
Signal Name Pin Connection
GE2_RD[0-3] GND
GE2_RX_CLK GND
GE2_RX_DV GND
GE2_RX_ER GND
GE2_SGMII_RX GNDSXC
GE2_SGMII_RX GNDSXC
GE2_SGMII_TX NC
GE2_SGMII_TX NC
GE2_TCK NC
GE2_TD[0–3] NC
GE2_TX_EN NC
Table 61. Connectivity of GE Manageme nt Pins When GE1 and GE2 Are Not Used
Signal Name Pin Connection
GE_MDC NC
GE_MDIO NC
Table 59. Connectivity of GE2 Related Pins When the GE2 Interface Is Not Used (continued)
Signal Name Pin Connection
Hardware Design Considerations
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 73
3.4.5 UTOPIA/POS Related Pi ns
Table 62 lists the board connections of the UTOPIA/POS pins when the entire UTOPIA/POS interface is not us ed o r subs et o f
UTOPIA/POS interface is used. For multiplexing options that select a subset of the UTOPIA/POS interface, use the connections
described in Table 62 for those signals that are not selected. Table 62 assumes that the altern ate fu nction of the specified pin is
not used. If the alternate function is used, connect that pin as required to support the selected function.
3.4.6 TDM Interface Related Pins
Table 63 lists the board connections of the TDM pins when an entire specific TDM is not used. For multiplexi ng optio ns that
select a subset of a TDM interface, use the connections described in Table 63 for those signals that are not selected. Table 63
assumes that the alternate f unction of the specifi ed pin is no t used. If the alternate f unction is used, connect that p in as r equired
to support the selected function.
Table 62. Connectivity of UTOPIA/POS Related Pins When UTOPIA/POS Interface Is Not Used
Signal Name Pin Connection
UTP_IR GND
UTP_RADDR[0–4] VDDIO
UTP_RCLAV_PDRPA NC
UTP_RCLK GND
UTP_RD[0–15] GND
UTP_REN VDDIO
UTP_RPRTY GND
UTP_RSOC GND
UTP_TADDR[0–4] VDDIO
UTP_TCLAV NC
UTP_TCLK GND
UTP_TD[0–15] NC
UTP_TEN VDDIO
UTP_TPRTY NC
UTP_TSOC NC
VDDIO 3.3 V
Table 63. Connectivity of TDM Related Pins When TDM Interface Is Not Used
Signal Name Pin Connection
TDMxRCLK GND
TDMxRDAT GND
TDMxRSYN GND
TDMxTCLK GND
TDMTxDAT GND
TDMxTSYN GND
VDDIO 3.3 V
Notes: 1. x = {0, 1, 2,3, 4, 5, 6, 7}
2. In case of subset of TDM interface usage please make sure to disable unused TDM modules. See Chapter 20, TDM, in the
MSC8144E Reference Man ual for details.
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Hardware Design Considerations
Freesca le Sem ico nd uctor74
3.4.7 PCI Related Pins
Table 64 lists the board connections of the pins when PCI is not used. Table 64 assumes that the alternate function of the
specified pin is not used. If the alternate function is used, connect that pin as required to support the selected function.
3.4.8 Mi scellaneous Pins
Table 65 lists the board connections for the pins if they are not required by the system design. Table 65 assumes that the altern ate
function of the specified pin is not used. If the alternate function is used, connect that pin as required to support the selected
function.
Table 64. Connectivity of PCI Related Pins When PCI Is Not Used
Signal Name Pin Connection
PCI_AD[0–31] GND
PCI_CBE[0–3] GND
PCI_CLK_IN GND
PCI_DEVSEL VDDIO
PCI_FRAME VDDIO
PCI_GNT VDDIO
PCI_IDS GND
PCI_IRDY VDDIO
PCI_PAR GND
PCI_PERR VDDIO
PCI_REQ NC
PCI_SERR VDDIO
PCI_STOP VDDIO
PCI_TRDY VDDIO
VDDIO 3.3 V
Table 65. Connectivity of Individual Pins When They Are Not Required
Signal Name Pin Connection
CLKOUT NC
EE0 GND
EE1 NC
GPIO[0–31] GND
SCL See the GPIO connectivity guidelines in this table.
SDA See the GPIO connectivity guidelines in this table.
INT_OUT NC
IRQ[0–15] See the GPIO connectivity guidelines in this table.
NMI VDDIO
NMI_OUT NC
RC[0–16] GND
RC_LDF NC
STOP_BS GND
Ordering Information
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 75
Note: For details on configuration, see the MSC8144E Reference Manual . For additional information, refer to the MSC8144
Design Checklist (AN3202).
4 Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
TCK GND
TDI GND
TDO NC
TMR[0–4] See the GPIO connectivity guidelines in this table.
TMS GND
TRST GND
URXD See the GPIO connectivity guidelines in this table.
UTXD See the GPIO connectivity guidelines in this table.
VDDIO 3.3 V
Note: When using I/O multiplexing mode 5 or 6, tie the TDM7TSYN/PCI_AD4 signal (ball number AC9) to GND.
Part Package Type Spheres Mask # Core Voltage Operating
Temperature
Core
Frequency
(MHz) Order Number
MSC8144E Flip Chip Plastic Ball Grid Array
(FC-PBGA) Lead-free 0M31H 1.0 V 0° to 90°C 800 MSC8144EVT800A
0° to 105°C 800 MSC8144ESVT800A
–40° to 105°C 800 MSC8144ETVT800A
0° to 90°C 1000 MSC8144EVT1000A
0° to 105°C 1000 MSC8144ESVT1000A
–40° to 105°C 1000 MSC8144ETVT1000A
1M31H 1.0 V 0° to 90°C 800 MSC8144EVT800B
0° to 105°C 800 MSC8144ESVT800B
–40° to 105°C 800 MSC8144ETVT800B
0° to 90°C 1000 MSC8144EVT1000B
0° to 105°C 1000 MSC8144ESVT1000B
–40° to 105°C 1000 MSC8144ETVT1000B
Note: See Table 3 for Core Voltage tolerance limits.
Table 65. Connectivity of Individual Pins When They Are Not Required (continued)
Signal Name Pin Connection
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Package Information
Freesca le Sem ico nd uctor76
5 Package Information
6 Product Documentation
•MSC8144E Technical Data Sheet (MSC8144E). Details the signals, AC/DC characteristics, clock signal
characteristics, package and pinout, and electrical design considerations of the MSC8144E device.
•MSC8144E Reference Manual (MSC8144ERM). Includ es functional descriptions of the extended cores and all the
internal subsystems including configuration and programming information.
•Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8144E device.
•SC3400 DS P Cor e Refer ence Manual. Covers the SC3400 core architecture, control registers, clock registers, program
control, and in st ru ctio n set.
•MSC8144 SC3400 DSP Core Subsystem Reference Manual. Covers core subsystem architecture, functionality, and
registers.
Figure 44. MSC8144E Mechanical Information, 783-ball FC-PBGA Package
Notes:
1. All dimensions in millimeters.
2. Dimensioning and tolerancing
per ASME Y14.5M–1994.
3. Maximum solder ball diamete
r
measured parallel to Datum A
.
4. Datum A, the seating plane, is
determined by the spherical
crowns of the solder balls.
5. Parallelism measurement
should exclude any effect of
marking.
6. Capacitors may not be presen
t
on all devices.
7. Caution must be taken not to
short exposed metal capacito
r
pads on package top.
CASE NO. 1842-04
Revision History
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 77
7 Revision History
Table 66 provides a revision history for this data sheet.
Table 66. Document Revision History
Revision Date Description
0 June. 2007 • In itial pu blic release.
1 Sep 2007 • Updated M3 voltage range in Table 3.
• Changed not e in Table 7 for PLL power supplies.
• DDR volt age designator changed from VDD to VDDDDR in Table 8, Table 10, Sect ion 2.7.4 .1, Section
2.7.4.2, and Figure 11. Changed range on IOZ in Table 8 and Table 10.
• Deleted text before Table 13 and added note 2 to in put pin cap acitance.
• Deleted text before Table 14, added a 1 to th e note, and added note 1 to input pin capacit a nce.
• Deleted Section 2.6.5 on page 32 and r enumbered subsequent subsections.
• Deleted text before new Sect ion 2.6.5.1.
• Added a 1 to the note in Table 15 an d added note 1 to input pin capa citance.
• Deleted ac voltage rows from Table 16. Adde d no te 1 to inpu t pi n ca p aci t an c e.
• Changed output high and l ow voltage l evels in Table 17 and Table 18.
• Deleted text before Table 19.
• Added clock skew ranges i n percent in Table 21.
•Changed V
REF to MVREF in Table 26 .
•Changed V
DD to VDDIO in Table 36 Updated note 2.
• Added note 4 to Table 42. Changed tTDMSHOX value.
•Changed V
DD to VDDGE in Figure 27 and Figure 30.
• Changed the value of the data to clock out skew in Table 51.
• Changed EE pin timing in Table 55.
• Changed the head for the JTAG timing section, now Section 2.7.14.
• Updated JTAG timing for TCK cycle time, TCK high phase, and boundary scan input data hold time in
Table 55.
•Added new Section 3.3 with guidelines for board layout for clock and timing signals. Renumbered
subse qu e nt se c tio ns .
2 Sep 2007 • Changed leakage current values in Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, and Table 19
from –10 and 10 μa to –3 0 and 30 μa.
• Change the minimum value of tMDDVKH in Table 45 from 5 ns t o 7 ns.
• Updat ed note 1 in Table 45.
3 Oct 2007 • Corrected column numbering in Figure 3 and Figure 4.
• Updated SPI signal names in Table 1.
4 Oct 2007 • Updated SPI signal names in Table 1.
5 Dec 2007 • Change d mi nimum voltage level for VDDM3 t o 1.213 (1.25 – 3%) in Table 3.
• Added POS to titles in Section 2.6.6.
• Added additional signals to titles in Section 2.6.8. Added high and low voltage ranges to Table 19.
• Added ATM an d POS to headings in Section 2.7.11. Change d ch a r acte ri s t ics to ge ne ri c inp ut/output in
Table 52, Figure 33, and Figure 34.
• Replaced Sections 2.7.13 and 2.7.14 with new Section 2.7.13. Renumb er ed subsequ ent sections, tables,
and figures.
• Added POS to all UTOPIA references in Section 3.4.5.
6 Dec 2007 • Changed GCR4 program value to 0x0004C130 in Note 7 in Table 51.
7 Mar 200 8 • Changed description of Table 16 in Section 2. 7.2.
8 Apr 2008 •Added
3 to the PLL supply voltage row in Table 2.
• Changed t he fi rst s ent ence in Secti on 3.4.8 to reflect that Table 70 indicates what to do with pins if they
are “not” required by the d esign. Changed the Pin Connection for GPIO[0–31] to GND.
• Updat ed ordering information in S ecti on 4.
• Multiple corrections of minor punctuation errors.
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Revision History
Freesca le Sem ico nd uctor78
9 Aug 2008 • Removed th e comment about preliminary est i mates before Table 4 and removed non-DDR rows in the
table.
• Table 9 and Table 11 for DDR and DDR2 SDRAM capacitance removed and subsequent tables
renumbered.
• Changed units for IOH and IOL to mA in Table 9.
• Removed signal low and high input current from Table 12.
• Added a note to Table 15 to exclude TDM and TMS. Removed reference to overshoot and undershoot and
associated figure.
•Changed TRST
deassertion description in Section 3.1.
• Changed minimu m clock fre quency to 33 MHz and ma ximum clock frequency to 133 MHz in Table 16.
• Changed minimu m input clock frequency to 33 MHz in Table 19.
•Changed the t
DDKHAX min imum value in Table 23 to 1.85 ns.
• Removed tREFPJ and tREFCJ from Table 24 b ecause the specificat ions are not required or tested.
• Removed tPCRSTCLK, tPCRSTOFF, tPCRST, and tPCRHFA from Table 36 be ca u se the sp ecifi catio n s are not
required or tested.
• Removed tUAVKH and tUAVXH from Table 38 because the specifications are not required or tested.
• The parameters tMDCH, tMDCR, an d tMDHF were removed from Table 40 because the specifications are not
required or tested.
• The pa rameters tMTXH/tMTX, tMTXR, and tMTXF were removed from Table 41 because the specifications
are not required or tested.
• The pa rameters tMRXH/tMRX, tMRXR, and tMRXF were removed from Table 42 because the specifi cations
are not required or tested.
• The pa rameters tRMXH/tRMX, tRMXR, and tRMXF were removed from Table 43 because the specifications
are not required or tested.
• Changed the GTX_CLK125 ref e rence clock duty cycle to 45% –55% in Table 45 and Table 46 and the
paramet e r s tRGT, tRGTH/tRGT (1000Base-T), t RGTH/tRGT (10B ase-T), tRGTR, tRGTF, tG12, and tG125H/tG125
were removed because the specificati ons are not requir ed or tested.
•Changed t
UEKHOX to guaranteed by d esign in Table 47.
• Updated ordera ble part numbers in Section 4.
10 Aug 2008 • Changed b8t to bit in the M3 memory description on the first page.
• Changed maximum input high voltage (VIH) for SPI to 3.465 in the first row of Table 14.
• Changed packet processor t o QUICC Engine Subsystem in the last row of Table 18.
11 Feb 2009 •In Figure 31, for GTX_CLK, changed (at t ransm itter) to (a t DSP ) and for RX_ CLK, c h anged (a t PHY) to
(at DSP).
• Updated package drawing to the latest revision, Case No. 1842-04 in Figure 44.
12 Jul 2009 • Updated MVREF equ ations and t emperature ranges in Table 3.
• Updated ordera ble part numbers in Section 4.
13 Nov 2009 • Updated Core and PLL input voltage tolerance in Table 3.
14 May 2010 • Corrected typo in Table 23. Changed MCLK minimum time to 5 ns.
Table 66. Document Revision History (continued)
Revision Date Description
Revision History
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semicond uc tor 79
Document Number: MSC8144E
Rev. 14
5/2010
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