5962-0824504HYC - Micross Components, Inc.

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

FIGURE 1: PIN ASSIGNMENT

(Top View)

Hermetic, Multi-Chip Module

(MCM)

64Mb, 2M x 32, 3.3Volt Boot Block FLASH Array

Available via Applicable Speciﬁ cations:

• MIL-PRF-38534, Class H

• DSCC SMD 5962-08245

FEATURES

• 64Mb device, total density, organized as 2M x 32

• Bottom Boot Block (Sector) Architecture

(Contact factory for top boot)

• Operation with single 3.0V Supply

• Available in multiple Access time variations

• Individual byte control via individual byte selects (CSx\)

• Low Power CMOS

• 1,000,000 Erase/Program Cycles

• Minimum 1,000,000 Program/Erase Cycles per sector

guaranteed

• Sector Architecture:

• One 16K byte, two 8K byte, one 32K byte and

thirty-one 64Kbyte sectors (byte mode)

• Any combination of sectors can be concurrently erased

• MCM supports full array (multi-chip) Erase

• Embedded Erase and Program Algorithms

• Erase Suspend/Resume; Supports reading data from or

programming data to a sector not being Erased

• TTL Compatible Inputs and Outputs

• Military and Industrial operating temperature ranges

OPTION MARKING

Access Speed

70ns* -70

90ns -90

100ns -100

120ns -120

*Contact Factory

Package

Ceramic Quad Flat Pack Q

Ceramic Hex Inline Pack P

Temperature Range

Full Mil (MIL-PRF-38534, Class H /Q

Military Temp (-55oC to +125oC) /XT

Industrial (-40oC to +85oC) /IT

GENERAL DESCRIPTION

The AS8FLC2M32B is a 64Mb FLASH Multi-Chip Module

organized as 2M x 32 bits. The module achieves high speed

access, low power consumption and high reliability by employ-

ing advanced CMOS memory technology. The military grade

product is manufactured in compliance to the MIL-PRF-38534

speciﬁ cations, making the AS8FLC2M32B ideally suited for

military or space applications. The module is offered in a

68-lead 0.990 inch square ceramic quad ﬂ at pack or 66-lead

1.185inch square ceramic Hex In-line Package (HIP). The

CQFP package design is targeted for those applications, which

require low proﬁ le SMT Packaging.

For more products and information

please visit our web site at

www.micross.com

I/O0

I/O1

I/02

I/O5

I/O6

I/O7

GND

I/O10

I/O11

I/O17

I/O18

I/O21

I/O22

I/O23

GND

I/O26

I/O27

I/O16

I/O19

I/O25

I/O20

I/O24

I/O28

I/O30

I/O29

I/O 3

I/O 9

I/O4

I/O8

I/012

I/O 14

I/O13

VCC

A10

WE1\

CS4\

GND

CS3\

RESET\VCC

A11

A12

A13

A14

A15

CS1\

OE\

CS2\

A17

WE2\

WE3\

WE4\

A18

A19

A16

26 44

I/O 15 I/O31

[Package Designator QT]

I/O2

I/O1

I/O0

I/O8

I/O9

I/O10

I/O4I/O3

I/O5

I/O6

I/O7

I/O11 I/O12

I/O13

I/O14

I/O15

I/O16

I/O17

I/O18 I/O19 I/O20

I/O21

I/O22

I/O23

I/O24

I/O25

I/O26

I/O27 I/O28

I/O29

I/O30

I/O31

A18

A11

A16

A14

A15

A10

A17

A12

A13

CS3\

CS2\

CS1\

CS4\

A19

VCC

GND

Reset\

OE\

WE\

66 HIP

Pin Assignment

[Package Designator H]

(Top View)

DQ8

DQ9

DQ10

DQ0

DQ1

DQ2

DQ11

DQ3

DQ15

DQ14

DQ13

A20

DQ12

DQ7

DQ6

DQ5

DQ4

DQ24

DQ25

DQ26

DQ27

DQ31

DQ30

DQ29

DQ19

DQ28

DQ23

DQ22

DQ21

DQ20

DQ16

DQ17

DQ18

DQ25

DQ24

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

A20

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

The device requires only a single 3.3volt power supply for

both READ and WRITE operations. Internally generated and

regulated voltages are provided for the program and erase

functions.

The device is entirely command set compatible with the

JEDEC SINGLE POWER FLASH STANDARD. Com-

mands are written to the command register using standard

microprocessor write timings. Register contents serve as

input to an internal state-machine that controls the erase and

programming circuitry. Write cycles also internally latch

addresses and data required for the programming or erase

function(s). Reading data out of the array is similar to reading

from other electrically programmable devices.

Device programming occurs by executing the program

command sequence. This initiates the EMBEDDED

PROGRAM algorithm that automatically times the WRITE

PULSE widths and cycle and veriﬁ es each cell for proper

cell margins. The UNLOCK BYPASS mode facilitates faster

programming times by requiring only two WRITE cycles to

program data instead of four.

Device erasure occurs by executing the erase command

sequence. This initiates the Embedded Erase algorithm, an

internal algorithm that automatically pre-programs the array

before executing the erase operation. During erasure, the

device automatically times the erase pulse widths and veriﬁ es

proper cell margin.

The host system can detect whether a program or erase

operation is complete by reading the DQ7 (Data\ Polling) and

DQ6 (toggle) STATUS BITS. After a program or erase cycle

has been completed, the device is ready to read array data or

accept another command.

The SECTOR ERASE ARCHITECTURE allows memory

sectors to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully erased when

shipped from Micross.

Hardware data protection measures include a low VCC

detector that automatically inhibits WRITE operations during

power transitions. The hardware sector protection features

disables both program and erase operation in any combination

of the sectors of memory. This can be achieved in-system or

via specially adapted commercial programming equipment.

The ERASE SUSPEND feature enables the user to put erase

on hold for any period of time to read data from, or program

data to, any sector which is not selected for erasure. True

BACKGROUND ERASE can thus be achieved.

The HARDWARE RESET\ PIN terminates any operation

in progress and resets the internal state machine to a READ

operation. The RESET\ pin may be tied to the system reset

circuitry.

LOGIC DIAGRAM (Byte)

1M x 8 1M x 8 1M x 8 1M x 8

RESET\

OE\

A0-Ax

WE1\ WE2\ WE3\ WE4\

CS1\ CS2\ CS3\ CS4\

BLOCK DIAGRAM

I/O0-7 I/O8-15 I/O16-23 I/O24-31

68-Ld. CQFP, Package "QT"

1M x 8 1M x 8 1M x 8 1M x 8

RESET\

OE\

A0-Ax

WE\

CS1\ CS2\ CS3\ CS4\

BLOCK DIAGRAM

I/O0-7 I/O8-15 I/O16-23 I/O24-31

66-Ld. HIP, Package "H"

2 2 2 2

DQ DQ DQ DQ

DQ DQ

GND

VCC

RESET\

WEx\

RY/BY\

CSx\

X-Decoder

DQ (byte)

OE\

A0-Ax

Y-Decoder

Address Latch

State

Control

Command

VCC Detector Timer

PGM Voltage

Generator

Chip E nable

Output Enable

Logic

Y-Gating

Cell Ma tr ix

I/O Buffers

Data Latch

Erase Voltage

Generator

Sector

Switches

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

A system reset would then also reset the FLASH device,

enabling the system microprocessor to read the boot-up

ﬁ rmware from the FLASH memory array . The device of fers two

power-saving features. When addresses have been stable for a

speciﬁ ed amount of time, the device enters the AUTOMATIC

SLEEP MODE. The system can also place the device into the

STANDBY mode. Power consumption is greatly reduced in

both these modes.

Device Bus Operations

This section describes the use of the command register for setting

and controlling the bus operations. The command register itself

does not occupy any addressable memory locations. The register

is composed of a series of latches that store the commands,

addresses and data information needed to execute the indicated

command. The contents of the register serve as the input to the

internal state machine. The state machine output dictates the

function of the device. Table 1 lists the device bus operations,

the inputs and control/stimulus levels they require, and the

resulting output. The following subsections describe each of

these operations in further detail.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the

CSx\ and OE\ pins to VIL. Chip Select CSx\ is the power and

chip select control of the byte or bytes targeted by the system

(user). Output Enable [OE\] is the output control and gates array

data to the output pins. Write (byte) Enables [WEx\] should

remain at VIH levels.

The internal state machine is set for reading array data upon

device power-up, or after a HARDWARE RESET . This ensures

that no spurious alteration of the memory content occurs

during

Table 1

the power transition. No command is necessary in this mode to

obtain array data. Standard microprocessor read cycles that

assert valid data on the device address inputs produce valid

data on the data outputs. The device remains enabled for read

access until the command register contents are altered.

See READING ARRAY DATA for more information. Refer

to AC Read Operations table data for timing speciﬁ cations

relevant to this operational mode.

Writing Commands/Command Sequences

T o WRITE a command or command sequence, the system must

drive CSx\, WEx\ to VIL and OE\ to VIH.

An ERASE command operation can erase one sector , multiple

sectors, or the entire array. Table 2 indicates the address

space contained within each sector within the array. A sector

address

consists of the address bits required to uniquely select a

sector.

The “Command Deﬁ nitions” section has details on erasure

of a single, multiple sectors, the entire array or suspending/

resuming the erase operation.

After the system writes the autoselect command sequence, the

device enters the autoselect mode. The system can then read

autoselect codes from the internal register (which is separate

from the memory array) on each of the Data input/output bits

within each byte of the MCM FLASH array. Standard read

cycle timings apply in this mode. Refer to the Autoselect

Mode and Autoselect Command Sequence sections for more

information.

ICC2 in the DC Characteristics table represents that active

current specification for the WRITE mode. The AC

Characteristics section contains timing speciﬁ cations for Write

Operations.

RESET\ CS1\ CS2\ CS3\ CS4\ WE1\ WE2\ WE3\ WE4\ OE\ OPERATION ADDRESSES DATA BUS (DQ0-DQX)

LHHH D0-D7 Out

HLHH D8-D15 Out

HHLH D16-D31 Out

HHHL D24-D31 Out

LLLL D0-D31 Out

LHHHLHHH D0-D7 In

H L H H H L H H D8-D15 In

H H L H H H L H D16-D31 In

H H H L H H H L D24-D31 In

LLLLLLLL D0-D31 In

VCC +/- 0.3VVCC +/- 0.3VVCC +/- 0.3VVCC +/- 0.3VVCC +/- 0.3VXXXXX Standby X

X L L L L HHHHH Output Diable X

LXXXXXXXXX Reset X

VID L L L L LLLLH Sector Protect SECTOR ADDRESS

A7=L, A2=H, A1=L D

, D

OUT

VIDLLLLLLLLH Sector Unprotect SECTOR ADDRESS

A7=L, A2=H, A1=L D

, D

OUT

VIDXXXXXXXXXTemporary Sector Unprotect A

Legend L=Logic=VIL, H=Logic High=VIH, VID=12.0 +/-0.5V, X= Don't Care, A

=Address In, D

OUT

=Data Out

Notes

H WRITE A0-Ax InH

H L READ A0-Ax InHHHH

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

The AUTOMATIC SLEEP mode is independent of the CSx\,

WEx\ and OE\ control signals. Standard address access

timings provide new data when addresses are changed. While

in sleep mode, output data is latched and always available to

the system. ICC5 in the “DC Characteristics Table represents

the AUTOMATIC SLEEP mode current usage.

RESET\: Hardware Reset Pin

The RESET\ pin provides a hardware method of resetting

the device to reading array data. When the RESET\ pin is

driven low for at least a period of tRP, the device immediately

terminates any operation in progress, tristates all output pins,

and ignores all READ/WRITE commands for the duration of the

RESET\ pulse. The device also resets the internal state machine

to reading array data. The operation that was interrupted

should be reinitiated once the device is ready to accept another

command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET\ pulse.

When RESET\ is held at VSS+/-0.3v, the device draws CMOS

STANDBY current (ICC4). If RESET\ is held at VIL but not

within the limits of VCC +/- 0.3v, the MCM Array will be in

STANDBY, but current limits will be higher than those listed

under ICC4.

The RESET\ pin may be tied to the system reset circuitry. A

system reset would thus also reset the FLASH array, enabling

the system to read the boot-up ﬁ rmware code from the boot

block area of the memory.

Program and Erase Operation Status

During an ERASE or PROGRAM operation, the system may

check the status of the operation by reading the status bits on

each of the seven data I/O bits within each byte of the MCM

FLASH array. Standard READ cycle timings and ICC read

speciﬁ cations apply. Refer to “Write Operation Status” for

more information, and to “AC Characteristics” for timing

speciﬁ cations.

Standby Mode

When the system is not READING or WRITING to the device,

it can place the device in the standby mode to save on power

consumption.

The device enters the CMOS STANDBY mode when the CSx\

and RESET\ pins are held at VCC+/-0.3v . If CSx\ and RESET\

are held at VIH, but not within VCC+/-0.3v, the device will

be in STANDBY mode but at levels higher than achievable in

full CMOS STANDBY. The device requires standard access

time (tCE) for read access when the device is in either of these

STANDBY modes, before it is ready to READ data.

If the device is deselected during ERASURE or

PROGRAMMING, the device draws active current until the

operation is completed.

In the DC Characteristics table, ICC3 and ICC4 represent the

STANDBY MODE currents.

Automatic Sleep Mode

The AUTOMATIC SLEEP mode minimizes FLASH device

energy consumption. The device automatically enables this

mode when addresses remain stable for tACC + 30ns.

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Autoselect Code Table

PROGRAM or ERASE operation is not executing, the RESET

operation is completed within a time of tREADY. The system

can read data tRH after the RESET\ pin returns to VIH.

Refer to the “AC Characteristics” tables for RESET\

parameters.

Output Disable Mode

When the OE\ input is at VIH, output from the device is

disabled. The output pins are placed in the high Impedance

State.

Autoselect Mode

The autoselect mode provides manufacturer and device

identiﬁ cation, and sector protection veriﬁ cation through

identiﬁ er codes output via the appropriate Byte DQ’s. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However, the

autoselect codes can also be accessed in-system through the

command register.

When using programming equipment (modiﬁ ed to support

multi-byte devices, or supplied from the programming

equipment provider as such), the autoselect mode requires

VID (11.5v to 12.5v) on address pin A9. Address pins A6,

A1, and A0 must be as shown in the Autoselect Table below.

In addtion, when verifying sector protection, the sector address

must appear on the appropriate highest order address bits. When

all necessary bits have been set as required, the programming

equipment may then read the corresponding identiﬁ er code on

the appropriate Byte DQ’s.

To access the autoselect codes in-system, the host system can

issue the autoselect command via the command register.

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

SA0 0000000X 16/8 000000-003FFF

SA1 00000010 8/4 004000-005FFF

SA2 00000011 8/4 006000-007FFF

SA3 000001XX 32/16 008000-00FFFF

SA4 0 0 0 0 1 X X X 64/32 010000-01FFFF

SA5 0 0 0 1 0 X X X 64/32 020000-02FFFF

SA6 0 0 0 1 1 X X X 64/32 030000-03FFFF

SA7 0 0 1 0 0 X X X 64/32 040000-04FFFF

SA8 0 0 1 0 1 X X X 64/32 050000-05FFFF

SA9 0 0 1 1 0 X X X 64/32 060000-06FFFF

SA1000111XXX 64/32 070000-07FFFF

SA1101000XXX 64/32 080000-08FFFF

SA1201001XXX 64/32 090000-09FFFF

SA1301010XXX 64/32 0A0000-0AFFFF

SA1401011XXX 64/32 0B0000-0BFFFF

SA1501100XXX 64/32 0C0000-0CFFFF

SA1601101XXX 64/32 0D0000-0DFFFF

SA1701110XXX 64/32 0E0000-0EFFFF

SA1801111XXX 64/32 0F0000-0FFFFF

SA1910000XXX 64/32 100000-10FFFF

SA2010001XXX 64/32 110000-11FFFF

SA2110010XXX 64/32 120000-12FFFF

SA2210011XXX 64/32 130000-13FFFF

SA2310100XXX 64/32 140000-14FFFF

SA2410101XXX 64/32 150000-15FFFF

SA2510110XXX 64/32 160000-16FFFF

SA2610111XXX 64/32 170000-17FFFF

SA2711000XXX 64/32 180000-18FFFF

SA2811001XXX 64/32 190000-19FFFF

SA2911010XXX 64/32 1A0000-1AFFFF

SA3011011XXX 64/32 1B0000-1BFFFF

SA3111100XXX 64/32 1C0000-1CFFFF

SA3211101XXX 64/32 1D0000-1DFFFF

SA3311110XXX 64/32 1E0000-1EFFFF

SA3411111XXX 64/32 1F0000-1FFFFF

A15 A14 A13 Sector Size

(Kbytes / Kwords) Address Range (in

hexadecimal)

A17 A16

Sector A20 A19 A18

Sector Addr ess Table

Note: Address range is A19:A-1 in byte mode

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Sector Protect:

Write 60h to sector

address with

A7 = 0, A2 = 1,

A1 = 0

Set up sector

address

Wait 150 μs

Verify Sector

Protect: Write 40h

to sector address

with A7 = 0,

A2 = 1, A1 = 0

Read from

sector address

with A7 = 0,

A2 = 1, A1 = 0

START

PLSCNT = 1

RESET# = V

Wait 1 ms

First Write

Cycle = 60h?

Data = 01h?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Ye s

PLSCNT

= 25?

Ye s

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

Ye s

Sector Protect

Algorithm

Protect another

sector?

Reset

PLSCNT = 1

Sector Protect Algorithm Flow

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Sector Un-Protect Algorithm Flow

Sector Unprotect:

Write 60h to sector

address with

A7 = 1, A2 = 1,

A1 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A7 = 1, A2 = 1,

A1 = 0

Read from

sector address

with A7 = 1,

A2 = 1, A1 = 0

START

PLSCNT = 1

RESET# = V

Wait 1 ms

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Write reset

command

Sector Unprotect

complete

Ye s

PLSCNT

= 1000?

Ye s

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

All sectors

protected?

Ye s

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Ye s

Sector Unprotect

Algorithm

First Write

Cycle = 60h?

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Temporary Sector Unprotect

This feature allows temporary un-protection of previously

protected sectors to change data in-system. Setting the RESET\

pin to VID activates the sector Unprotect mode. During this

mode, formerly protected sectors can be programmed or erased

by selecting the sector addresses. Once VID is removed

from the RESET\ pin, all the previously protected sectors are

protected again. The diagram below depicts the algorithm ﬂ ow

for this operation.

Temporary Sector Unprotect Diagram

Hardware Data Protection

The command sequence requirements of UNLOCK cycles

for PROGRAMMING or ERASING provides data protection

against inadvertent WRITES. In addition, the following

hardware data protection measures prevent accidental

ERASURE or PROGRAMMING, which might otherwise be

caused by spurious system level signals during VCC power-up

and power-down transitions, or from system noise.

Low VCC WRITE Inhibit

When VCC is less than VLKO, the device does not accept any

WRITE cycles. This protects data during VCC power-up and

power-down. The system must provide the proper signals to

the control pins to prevent unintentional WRITES when VCC

is greater than VLKO.

Write Pulse “GLITCH” Protection

Noise pulses of less than 5ns (typical) on OE\, CSx\ or WEx\

do not initiate a WRITE cycle.

Logical Inhibit

WRITE cycles are inhibited by holding any one of OE\=VIL,

CSx\=VIH or WEx\=VIH. To initiate a WRITE cycle, CSx\

and WEx\ must be a logical zero while OE\ is a logical one.

Power -Up WRITE Inhibit

If WEx\=CSx\=VIL and OE\=VIH during power-up, the device

does not accept commands on the rising edge of WEx\. The

internal state machine is automatically reset to READING array

data on power-up.

Command Deﬁ nitions

Writing speciﬁ c address and data commands or sequences

into the command register initiates device operations. The

COMMAND REGISTER TABLE deﬁ nes the valid register

command sequences for this device Module. WRITING

incorrect address and data values or WRITING them in the

improper sequence resets the device to READING array

data.

All addresses are latched on the falling edge of WEx\ or CSx\,

whichever happens later . All data is latched on the rising edge of

WEx\ or CSx\, whichever happens ﬁ rst. Refer to the AC timing

references for correct timings of the appropriate signals.

Reading Array Data

The device is automatically set to READING Array data after

device power-up. No commands are required to retrieve data.

The device is also ready to READ data after completing an

Embedded Program or Embedded Erase operation.

After the device accepts an ERASE Suspend command, the

device enters the ERASE Suspend Mode. The system can

read array data using the standard READ timings, except that

if it READS at an address within Erase-Suspended sectors, the

device outputs status data. After completing a programming

operation in the Erase Suspend Mode, the system may once

again READ array data with the same exception.

The system must issue the reset command to re-enable the

device for reading array data if DQ5, DQ13, DQ21 and DQ29

goes high, or while in the autoselect mode.

NOTES:

1. All protected sectors unprotected

2. All previously protected sectors are

protected once again

RESET\ = VID

(Note 1)

Perform Erase or

Program

Operations

RESET\ = VIH

Start

Temporary Sector

Unprotect

Completed

(Note 2)

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Reset Command

WRITING the reset command to the device resets the device

to reading array data. Address bits are don’t care for this

command.

The RESET command may be WRITTEN between the sequence

cycles in an ERASE command sequence before ERASING

begins. This resets the device to READING array data. Once

ERASURE begins, the device ignores RESET command requests

until the ﬁ rst initiation of the operation has completed.

The RESET command may be WRITTEN between the sequence

cycles in a program command sequence and before programming

begins. This RESETS the device to READING Array data.

Once programming begins, the device ignores additional RESET

command requests until the current operation has completed.

The RESET command may be written between the sequence

cycles in an Autoselect command sequence. Once in the

Autoselect Mode, the reset command must be WRITTEN to

return to READING Array data.

Autoselect Command Sequence

The Autoselect command sequence allows the host system to

access the manufacturer and device codes, allowing the user

determination as to whether or not a Sector is protected. This

method is an alternative to DEVICE PROGRAMMERS but

requires VID on Address bit 9 (A9).

The Autoselect command sequence is initiated by WRITING

two UNLOCK cycles, followed by the AUTOSELECT

COMMAMD. The device then enters the AUTOSELECT mode,

and the system may read at any address, any number of times,

without initiating another command.

A READ cycle at Address XX00h retrieves the manufacturer

code. A READ cycle at Address XX01h returns the device

code. A READ cycle containing a Sector Address (SA) and the

address 02h returns 01h if that sector is protected, or 00h if it

is un-protected.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock WRITE cycles,

followed by the PROGRAM set-up command. The program

address and data are WRITTEN next, which in turn initiates the

Embedded Program algorithm. The system is not required to

provide further controls or timings. The device automatically

provides internally generated PROGRAM pulses and veriﬁ es

the programmed cell margin.

When the Embedded Program algorithm is complete, the device

then returns to READING array data and addresses are no longer

latched. The system can determine the status of the program

operation by using DQ31, DQ30, DQ23, DQ22, DQ15. DQ14,

DQ7, DQ6.

Any commands WRITTEN to the device during the Embedded

Program algorithm are ignored. Note that a HARDWARE

RESET immediately terminates the programming operation.

The Byte Program command sequence should be reinitiated

once the device has reset to READING Array data, to ensure

data integrity.

PROGRAMMING is allowed in any sequence and across Sector

Boundaries. A bit cannot be PROGRAMMED from a “0” back to

a “1”, this can only be accomplished via an ERASE operation.

Unlock Bypass Command Sequence

The UNLOCK BYPASS feature allows the system to program

bytes to the device faster than using the standard program

command sequence. The UNLOCK BYPASS command

sequence is initiated by ﬁ rst WRITING two UNLOCK cycles.

This is followed by a third WRITE cycle containing the

UNLOCK BYPASS command, 20h. The device then enters the

UNLOCK BYPASS mode. A two-cycle UNLOCK BYPASS

command operation is all that is required to PROGRAM in this

mode. The ﬁ rst cycle in this sequence contains the UNLOCK

BYPASS program command, A0h; the second cycle contains the

program address and data. Additional data is PROGRAMMED

in the same manner. This mode dispenses with the initial two

UNLOCK cycles required in the standard PROGRAM command

sequence. The ﬁ rst cycle must contain the data 90h; the second

cycle the data 00h. Addresses are don’t care fore both cycles.

The device then returns to READING Array data.

Chip Erase Command Sequence

CHIP ERASE is a six-bus cycle operation. The CHIP ERASE

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional UNLOCK

WRITE cycles are then followed by the chip ERASE command,

which in turn invokes the Embedded ERASE algorithm. The

device does not require the system to PRE-PROGRAM prior to

ERASE. The Embedded ERASE algorithm automatically PRE-

PROGRAMS and VERIFIES the entire Array for an all Zero data

pattern prior to electrical ERASE. The system is not required to

provide any controls or timing during these operations.

Any commands WRITTEN to the chip during the Embedded

ERASE operation are ignored. Note that a HARDWARE

RESET

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

When the Embedded Erase Algorithm is complete, the device

returns to READING Array data and addresses are no longer

latched. The system can determine the status of the ERASE

operation by using DQ2, DQ6, and DQ7 of Byte 1; DQ10, DQ14

and DQ15 of Byte 2; DQ18, DQ22 and DQ23 of Byte 3 as well

as DQ26, DQ30 and DQ31 of Byte 4.

Erase Suspend/Erase Resume Commands

The ERASE SUSPEND command allows the system to interrupt

a SECTOR ERASE operation and then READ data from, or

PROGRAM data to, any sector not selected for ERASURE. This

command is valid only during the SECTOR ERASE command

sequence. The ERASE SUSPEND command is ignored if

WRITTEN during the CHIP ERASE operation or Embedded

Program algorithm. WRITING the ERASE SUSPEND

command during the SECTOR ERASE time-out immediately

terminates the time-out period and SUSPENDS the ERASE

operation. Addresses are “don’t-cares” when WRITING the

ERASE SUSPEND command.

When the ERASE command is WRITTEN during a SECTOR

ERASE operation, the device requires a maximum of 20us to

SUSPEND the ERASE operation. However , when the ERASE

SUSPEND command is WRITTEN during the SECTOR ERASE

time-out, the device immediately terminates the time-out period

and SUSPENDS the ERASE operation.

After the ERASE operation has been SUSPENDED, the system

can READ Array data from or PROGRAM data to any sector not

selected for ERASURE. Normal READ and WRITE timings and

command deﬁ nitions apply. READING at any Address within

ERASE-SUSPENDED sectors produces status data on three DQ

pins within each Byte. DQ2, DQ6, and DQ7 of Byte 1; DQ10,

DQ14 and DQ15 of Byte 2; DQ18, DQ22 and DQ23 of Byte 3

as well as DQ26, DQ30 and DQ31 of Byte 4 to determine if a

sector is actively ERASING or is ERASE-SUSPENDED.

After and ERASE-SUSPENDED program operation is complete,

the system can once again READ from or WRITE to within non-

suspended sectors. The system can determine the status of the

PROGRAM operation using the DQ6, 7 bits of Byte 1; DQ14,

15 of Byte 2; DQ22, 23 of Byte 3 and DQ30, 31 of Byte 4; just

as in the standard PROGRAM operation.

The system may also write the auto select command sequence

when the device is in the ERASE SUSPEND mode. The device

allows READING autoselect codes even at addresses within

Any commands WRITTEN to the chip during the Embedded

ERASE operation are ignored. Note that a HARDWARE

RESET during the chip erase operation immediately terminates

the operation. The CHIP ERASE command sequence should

be reinitiated once the device has returned to READING Array

data, to ensure data integrity.

The system can determine the status of the erase operation

by using byte data from each of the four bytes. When the

Embedded ERASE Algorithm is complete, the device returns to

READING Array data and Addresses are no longer latched.

Sector Erase Command Sequence

SECTOR ERASE is a six-bus cycle operation. The SECTOR

ERASE command sequence is initiated by WRITING two

UNLOCK cycles, followed by a SET-UP command. Two

additional UNLOCK WRITE cycles are then followed by the

address of the sector to be ERASED, and the SECTOR ERASE

command.

The device does not require the system to PREPROGRAM the

memory prior to ERASE. The Embedded ERASE Algorithm

automatically PROGRAMS and veriﬁ es the sector for an all

zero data pattern prior to electrical ERASE. The system is

not required to provide any controls or timings during these

operations.

After the command sequence is WRITTEN, a SECTOR ERASE

time-out of 50uS begins. During the time-out period, additional

Sector Addresses and SECTOR ERASE commands may be

WRITTEN. Loading the SECTOR ERASE buffer may be

done in any sequence and the number of sectors may be from

one sector to all sectors. The time between these additional

cycles must be less than 50uS, otherwise the last address and

command might not be accepted, and erasure may begin. It

is recommended that processor interrupts be disabled during

this time to ensure all commands are accepted. The interrupts

can be re-enabled after the last SECTOR ERASE command is

WRITTEN. If the time between additional SECTOR ERASE

commands can be assumed to be less than 50uS, the system

need not monitor DQ3, DQ11, DQ19 or DQ27 to determine

if the SECTOR ERASE has timed out. The time-out begins

from the rising edge of the ﬁ nal WEx\ pulse in the command

sequence.

Once the SECTOR ERASE operation has begun, only the

ERASE SUSPEND command is valid. All other commands

are ignored. Note that a HARDWARE RESET during the

SECTOR ERASE operation immediately terminates the op-

eration. The SECT OR ERASE command sequence should be

reinitiated once

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

ERASING sectors, since the codes are not stored in the memory

Array. When the device exits the Autoselect mode, the device

reverts to the ERASE SUSPEND mode, and is ready for another

valid operation.

The system must WRITE the ERASE RESUME command to

exit the ERASE SUSPEND mode and continue the SECTOR

ERASE operation. Further WRITES of the RESUME com-

mand are ignored. Another ERASE SUSPEND command can

be WRITTEN after the device has resumed ERASING.

Erase Operation Diagram

Write Operation Status

The device provides several bits to determine the status of a

write operation: DQ2, DQ3, DQ5, DQ6 and DQ7 of Byte 1;

DQ10, DQ11, DQ13, DQ14 and DQ15 of Byte 2; DQ18, DQ19,

DQ21, DQ22 and DQ23 of Byte 3; as well as, DQ26, DQ27,

DQ29, DQ30 and DQ31 of Byte 4.

DQ7, DQ15, DQ23 and DQ31: Data\ Polling

The Data\ Polling bit per byte, indicates to the host system

whether an Embedded Algorithm is in progress or completed,

or whether the device is in ERASE SUSPEND. Data\ Polling

is valid after the rising edge of the ﬁ nal WEx\ pulse in the

PROGRAM or ERASE command sequence.

During the Embedded Program Algorithm, the device outputs on

DQ7 for Byte 1, DQ15 for Byte 2, DQ23 for Byte 3, and DQ31

for Byte 4, the complement of the datum programmed to each

of these bits. This status also applies to the PROGRAMMING

during ERASE SUSPEND. When the Embedded Program

Algorithm is complete, the device outputs the datum

PROGRAMMED into each of these status bits. The system

must provide the PROGRAM address to READ valid status

information. If a PROGRAM address fails within a protected

sector, Data\ Polling is active for approximately 1uS, then the

device returns to reading array data.

During the Embedded Erase Algorithm, Data\ Polling produces

a “0” on the Data\ Polling Status bits. When the Embedded

ERASE Algorithm is complete, or if the device enters the

ERASE SUSPEND mode, Data\ Polling produces a “1” on

each of the Data\ Polling status bits. This is analogous to the

complement/true data output described for the Embedded

Program Algorithm: the ERASE function changes all the

bits in a sector to “1”; prior to this, the device outputs the

“compliment”, or “0”. The system must provide an address

within any of the sectors selected for ERASURE to READ

valid status information.

After an ERASE Command sequence is WRITTEN, if all

s4ctors selected for erasing are protected, Data\ Polling is

active for approximately 100uS, then the device returns to

READING array data. If not all selected sectors are protected,

the Embedded ERASE Algorithm ERASES the unprotected

sectors, and ignores the selected sectors that are protected.

When the system detects a Data\ Polling status bit has changed

from the complement to true data, it can READ valid data

at each of the Bytes on the following READ cycles. This is

because

Data\ Polling Algorithm Diagram

READ Byte Data

Address = VA

Start

DQ5, DQ13,

DQ21,

DQ29=1?

YES

DQ7, DQ15,

DQ23, DQ31=

Data?

YES

READ Byte Data

Address = VA

DQ7, DQ15,

DQ23, DQ31=

Data?

YES

PASSFAIL

Write ERASE

Command

Sequence

Data Poll from

System

ERASURE

Completed

Start

Data = FFh?

YES

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Command Deﬁ nition Table

*Data is for single byte.

BYTE 1 = DQ0 - DQ7

BYTE 2 = DQ8 - DQ15

BYTE 3 = DQ16 - DQ23

BYTE 4 = DQ24 - DQ31

Add

Data Add

Data

Read (Note 5) 1RA RD

Reset (Note 6) 1 XXX F0

Manufacturer ID 4 AAA AA 555 55 AAA 90 X00 1

Device ID, Btm. Boot 4 AAA AA 555 55 AAA 90 X01 37

Sector Protect Verify 4 AAA AA 555 55 AAA 90 (SA) 0

(Note 8) X04 1

4 AAA AA 555 55 AAA A0 PA PD

3 AAA AA 555 55 AAA 20

2 XXX A0 PA PD

2 XXX 90 XXX 0

6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30

1 XXX B0

1 XXX 30

Legend:

X= Don't Care

RA = Address of the memory location to be read

RD = Data read from location RA during read operation

PA = Address of the memory location to be programmed. Addresses latched on the falling edge of the Wex\ or Cex\ pulse, whichever occurs later.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever occurs later.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20-A13 uniquely select any sector.

Notes:

1.See Table 1 for Valid Bus Operations.

2.All values in hexadecimal.

3.Except when reading array or autoselect data, all bus cycles are write operations

4.Data bits A20-A11 are don’t cares for unlock and command cycles

5.No unlock or command cycles required when reading array data.

6.The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ% goes high (while the device is providing status data).

7.The fourth cycle of the autoselect command sequence is a read cycle

8.The data is 00h for an unprotected sector and 01h for a protected sector.

9.The Unlock Bypass command is required prior to the Unlock Bypass Program command.

10.The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.

11. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase operation.

12. The Erase Resume command is valid only during the Erase Suspend mode.

Bus Cycles (Notes 2-4)

(Note 9)

Cycles

Command Sequence

(

Note 1

)

First Second Third Fourth Fifth Sixth

Erase Suspend (Note 11)

Erase Resume (Note 12)

Auto-Select

(Note 7)

Unlock Bypass Reset

(Note 10)

Chip Erase

Sector Erase

Program

Unlock Bypass

Unlock Bypass Program

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

DQ7, DQ15, DQ23 and DQ31 may change asynchronously

with the 7 lower order bits within each Byte, while the OEx\

pins are asserted Low.

DQ6, DQ14, DQ22 and DQ30: Toggle Bit 1

T oggle Bit 1 indicates whether an Embedded Program or Erase

Algorithm is in progress, complete, or has entered the ERASE

SUSPEND mode. Toggle Bit 1 may be read at any address

and is valid after the rising edge of the ﬁ nal WEx\ pulse in

the command sequence as well as during the sector ERASE

time-out.

During an Embedded Program or Erase Algorithm operation,

successive READ cycles that access any address will cause this

status indicator to toggle. When the operation is complete, the

status bit will stop toggling.

After an ERASE command sequence is WRITTEN, if all

sectors selected for ERASING are protected, the toggle bit(s)

will toggle for approximately 100uS, then will become steady

state as the device returns to READING array data. If not all

selected sectors are protected, the Embedded Erase Algorithm

will cause ERASURE of unprotected sectors, ignoring the

selected sectors that are protected.

The System can use DQ2, DQ6 of Byte 1; DQ10, DQ14 of Byte

2; DQ18, DQ22 of Byte 3; DQ26, DQ30 of Byte 4 together to

determine whether a sector is actively ERASING or is ERASE

SUSPENDED. When the device is actively ERASING the DQ6

of Byte 1; DQ14 of Byte 2; DQ22 of Byte 3 and DQ30 of Byte

4 toggles and when the devices enters ERASE SUSPEND, the

status bit returns to a steady state. However, the system must

also use DQ2 of Byte 1; DQ10 of Byte 2, DQ18 of Byte 3 and

DQ26 of Byte 4 to determine which sectors are ERASING or

ERASE SUSPENDED in each of the Bytes contained in the

Module. Alternatively DQ7, DQ15, DQ23 and DQ31 can be

used (see DQ7, DQ15, DQ23, DQ31 Data\ Polling).

If a program address falls within a protected sector, DQ6, 14,

22, and or DQ30 will toggle for approximately 1us after the

PROGRAM command sequence is WRITTEN, then returns to

READING Array data.

DQ6, 14, 22, and or DQ30 also toggles during the ERASE

SUSPEND program mode, stops toggling once the operation

is complete.

DQ2, DQ10, DQ18 and DQ26: Toggle Bit II

The “Toggle Bit II” on each of the Bytes, when used with

DQ6, 14, 22, and DQ30 indicates whether a particular sector

is actively ERASING or whether that sector is ERASE-

SUSPENDED. Toggle Bit II is valid after the rising edge of

the ﬁ nal WEx\ pulse in the command sequence.

DQ2, 10, 18 and or DQ26 toggles when the system READS

at addresses within those sectors that have been selected for

ERASURE, but does not indicate when a sector is being

ERASED. DQ6, 14, 22 and DQ30 by comparison indicates

that a device is actively ERASING or in ERASE SUSPEND,

but cannot distinguish which sectors are selected for the

operation, therefore both status bits are required for sector and

mode information.

Reading Toggle Bits I/II

Whenever the system initially begins READING toggle bit

statuses, it must READ Byte data (ie…DQ0-7, DQ8-15,

DQ16-23 and or DQ24-31) at least twice in a row to determine

whether a Toggle Bit is toggling. Typically, the system would

note and store the value of the toggle bit after the ﬁ rst READ.

After the second READ, the system would compare the new

value of the Toggle Bit with the ﬁ rst. If the toggle bit is not

toggling the device has completed the PROGRAM or ERASE

operation. The system can READ array data on each Byte

during the next READ cycle.

If after the initial two READ cycles, the system determines

that the toggle bit is still toggling, the system also should note

whether the value of DQ5, 13, 21 and or DQ29 is High. If

High, the system should then determine again whether the

toggle bit(s) are again toggling, since the toggle bit may have

indeed stop toggling just as DQ5, 13, 21 and or DQ29 went

High. If the toggle bit is no longer toggling, the device has

successfully completed the operation. If the toggle bit is still

active (toggling), the device has not successfully completed the

operation and the system must WRITE the RESET command

to return to READING array data.

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

The remaining scenario is that the system initially determines

that the toggle bit is toggling and DQ5, 13, 21, and or DQ29

has not gone High. The system may continue to monitor the

toggle bit and DQ5, 13, 21, and or DQ29 through successive

READ cycles, determining the status as described in the

previous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start at the

beginning of the Algorithm when it returns to determine the

status of the operation.

READ(#1) Byte

Data from Byte1, 2,

3 and or 4

Start

Toggle Bit =

Toggle?

YES

READ(#2) Byte

Data from Byte1, 2,

3 and or 4

DQ5, 13, 21

and or DQ29 =

"1"

YES

READ(#1) Byte

Data from Byte1, 2,

3 and or 4

READ(#2) Byte

Data from Byte1, 2,

3 and or 4

Toggle Bit =

Toggle?

Operation Not

Complete, WRITE

RESET Command

PROGRAM/

ERASE Complete

YES

Toggle Bit Algorithm Diagram

DQ5,13,21,and or DQ29: Exceeding Timing

Limits

DQ5, 13, 21, and or DQ29 indicates whether the PROGRAM

or ERASE time has exceeded a speciﬁ ed internal pulse count

limit. Under these conditions this will produce a logic level “1”

High. This is a failure condition that indicates the PROGRAM

or ERASE cycle was not successfully completed.

The DQ5, 13, 21 and or DQ29 failure condition may appear

if the system tries to PROGRAM a “1” to a location that was

previously PROGRAMMED to a logic level “0” Low . Only an

ERASE operation can change a logic level “0” back to a Logic

Level “1”. Under this condition, the device halts operation and

when the operation has exceeded the timing limits, DQ5, 13,

21, and or DQ29 will produce a logic level “1”.

Under both of these conditions, the system must issue the

RESET command to return to reading array data.

DQ3, 11, 19, and or DQ27: Sector Erase Timer

After WRITING a Sector Erase command sequence, the

system may read this status bit or bits to determine whether or

not an ERASE operation has begun. If additional sectors are

selected for ERASURE, the entire time-out also applies after

each additional Sector Erase command. When the time-out

is complete, this status bit or bits changes from a logic level

“0” to “1”. The system may ignore this status bit if the system

can guarantee that the time between additional Sector Erase

command will always be less than 50us.

After the Sector Erase command sequence is WRITTEN, the

system should read the status on DQ7, 15, 23 and or DQ31

(Data\ Polling) or DQ6, 14, 22, and or DQ30 (Toggle Bit I) to

ensure the device has accepted the command sequence. Then

READ DQ3, 1 1, 19 and or DQ27, looking for this bit or bits to

be a logic level “1”. If this bit is a logic level “1”, the internally

controlled ERASE cycle has begun; all further commands are

ignored until the ERASE operation is complete. If this bit is a

logic level “0”, the device will accept additional Sector Erase

commands. To ensure the command has been accepted, the

system software should check the status of DQ3, 1 1, 19 and or

DQ27 prior to and following each subsequent Sector Erase com-

mand. If this bit or bits is a logic level “1” on the second status

check, the last command might not have been accepted.

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Pin Description/Assignment Table

Signal Name Symbol Type Pin DEF/Package=QT Symbol Pin DEF/Package=H Description

Address A0, A1, A2. A3, Input 8, 7, 6, 5, A0, A1, A2. A3, 7, 60, 61, 62, 49, 50, Address Inputs

A4, A5, A6, A7 4, 3, 66, 65, A4, A5, A6, A7 51, 37, 41, 17, 16, 6,

A8, A9, A10, A11 64, 63, 62, 28,A8, A9, A10, A11 38, 40, 4, 18, 5, 28,

A12,A13,A14,A15 29,30,31,32, A12,A13,A14,A15 8, 21

A16,A17,A18,A19 33,37,41,42 A16,A17,A18,A19

Chip Selects CS1\, CS2

Input 34, 36, CS1\, CS2

20, 13, 53, 46 Active Low True Chip Selects (Enables)

CS3\, CS4\ 2, 68CS3\, CS4\

Write Enables WE1\, WE2

Input 67, 38,WE

29 Active Low True Write Enable(s)

WE3\, WE4

39, 40

Output Enable OE

Input 35 OE

27 Active Low True Output Enable (x32)

Reset RESET

Input 9 RESET

12 Active Low True Reset

Power Supply VCC Input 61,27 VCC 19, 45 Power for Core and I/O

Ground [Core] VSS Input 1,52,18VSS 14, 54 Digital GND

Data Input, Output I/O0,I/O1,I/O2 Input/ 10,11,12,13,14,15, I/O0,I/O1,I/O2 9, 10, 11, 22, 33, 32, Data Input, Output

I/O3,I/O4,I/O5 Output 16,17,19,20,21,22, I/O3,I/O4,I/O5 31, 30, 1, 2, 3, 15

I/O6,I/O7,1/O823,24,25,26,60,59, I/O6,I/O7,1/O826, 25, 24, 23, 42, 43

I/O9,I/O10,I/O11 58,57,56,55,54,53, I/O9,I/O10,I/O11 44, 55, 66, 65, 65, 63

I/O12,I/O13,I/O14 51,50,49,48,47,46, I/O12,I/O13,I/O14 34, 35, 36, 42, 43, 44,

I/O15,I/O16,I/O17 45,44 I/O15,I/O16,I/O17 55, 66, 65, 64, 63,

I/O18,I/O19,I/O20 I/O18,I/O19,I/O20 34, 35, 48, 59, 58,

I/O21,I/O22,I/O23 I/O21,I/O22,I/O23 57, 56

I/O24,I/O25,I/O26 I/O24,I/O25,I/O26

I/O27,I/O28,I/O29 I/O27,I/O28,I/O29

I/O30,I/O31 I/O30,I/O31

No Connection NC OPEN 43 NC 47, 52, 39 No internal connection

Absolute Maximum Ratings*

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units

Voltage on VDD Pin (Note 1) VCC

-0.5 4 V

Voltage on A9, OE\,

-0.5 12.5 V

and RESET\ (Note 2)

Voltage on Input Pins VIN

-0.5 VCC+0.5 V

Voltage on I/O Pins VIO

-0.5 VDDQ+0.5 V

Output Short Circuit Current ISC

200 mA

(Note 3)

Storage Temperature tSTG

-65 150

Operating Temperatures

-40 85

[Screenin

Levels]

-55 125

VCNTL

1. Minimum DC voltage on any Input or Input/Output pin is

–0.5v. During voltage transitions, input or input/output

pins may undershoot VSS to –2.0v for periods of up to

20ns.

2. Minimum DC input/output voltage on pins A9, OE\, and

RESET\ is-0.5v. During voltage transitions, A9, OE\, and

RESET\ may undershoot VSS to –2.0v for periods of up to

20ns. Maximum DC input voltage on pin A9 is +12.5v

which may overshoot to 14.0v for periods up to 20ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one (1) second.

*Stress greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other conditions

greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum conditions for any duration or segment of time

may affect device reliability.

Test Conditions

Test Specifications

Parameter -70/-90 -100/-120 Units

Output Load 1 TTL Gate

Output Load Capacitance,

CL (including Jig)

Input Rise and Fall Times

5ns

Input Pulse Levels

0.0-3.0 V

Input timing measurement

reference levels

Output timing measurement

reference levels

1.5

30 100

1.5

Test Set-Up

Device

Under

Test

3.3v

6.2K

ohm

1N3064

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

DC Electrical Characteristics

Symbol Parameter Test Conditions Min Max Units Notes

ILI Input Load Current

Vin=Vss to Vcc, Vcc=Vcc MAX

+/- 5.0 uA

ILIT A9 Input Load Current

Vcc=Vcc Ma,; A9=12.5v

160.0 uA

ILO Output Leakage Current

VOUT=VSS to VCC, VCC=VCC MAX

+/-5.0 uA

14Mhz 120 mA 1,2

8Mhz 70 mA 1,2

VCC Standby Current During

Reset

IL Input Low Voltage -0.5 0.8 V

IH Input High Voltage 0.7xVCC VCC+0.3 V

Voltage for Autoselect and

Temporary Sector Unprotect

OL Output Low Voltage

IOL=4.0mA, VCC=VCC MIN

0.45 V

OH1

IOH=-2.0mA, VCC=VCC MIN

2.4

OH2

IOH=-100uA, VCC=VCC MIN

VCC-0.4

LKO Low VCC Lock-Out Voltage 2.3 2.5 V 4

Notes:

[1] The ICC current listed is typically less than 8mA/Mhz, with OE\ at VIH

[2] Maximum ICC specifications are tested with VCC=VCC MAX

[3] ICC active while Embedded Program or Embedded Erase Algorithm is in progress

[4] Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns

[5] Not 100% Tested

VID 11.5 12.5 V

RESET\=VCC +/- 0.3v

VIH=VCC +/- 0.3v, VIL=VSS +/- 0.3v

Automatic Sleep Mode

2,3,5

2,4

ICC2

ICC3

ICC4

ICC5

ICC1

CE\=VIL, OE\=VIH

Vcc Active Read Current

Ouput High Voltage

VCC Standby Current

140

150

VCC=3.3v

CE\=VIL, OE\=VIH

VCC Active Write Current

CE\, RESET\=VCC +/- 0.3V

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

JEDEC Std 70 90 100 120

tAVAV tRC Min 70 90 100 120

tAVQV tACC

CE# = VIL

OE# = VIL Max 70 90 100 120

tELQV tCE OE# = VIL Max 70 90 100 120

tGLQV tOE Max 30353540

tEHQZ tDF Max

tGHQZ tDF Max

tSR/W Min

Read Min

Toggle and Data# Polling Min

tAXQX tOH Min

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First1

Read Cycle Time1

Address to Output Delay

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High Z1

Output Enable to Output High Z1

Latency Between Read and Write Operations

Speed Options UnitTest Setup

Paramete

tOEH Output Enable Hold Time1

Description

READ Operations

Notes:

1. Not 100% Tested

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output Valid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

RESET#

tDF

tSR/W

tOH

READ Operations Timing

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Erase / Program Operations

Program Operation Timings

Notes:

1. Not 100% Tested

2. See Erase and Programming Performance for more information

Notes

1. PA = program address, PD = program data, DOUT is the true data at the program address.

VCC

tVCS

OE#

WE#

CE#

Data

Addresses

tDS

tAH

tWP

tWHWH1

tWC tAS

tWPH

555h PA PA

Read Status Data (last two cycles)

A0h

tCS

Status DOUT

Program Command Sequence (last two cycles)

tCH

JEDEC Std 70 90 100 120

tAVAV tWC 70 90 100 120

tAVWL tAS

tWLAX tAH

tDVWH tDS 35 40 45 45

tWHDX tDH

tOES

tGHWL tGHWL

tELWL tCS

tWHEH tCH

tWLWH tWP

tWHWL tWPH

tSR/W ns

tWHWH1 tWHWH1 Programming Operation2Byte Typ μs

tWHWH2 tWHWH2 sec

tVCS Min μs

0.7

Write Pulse Width High

Latency Between Read and Write Operations

Sector Erase Operation2

Address Hold Time

Data Setup Time

Data Hold Time

Vcc Setup Time1

Paramete

Write Pulse Width

Write Cycle Time1

Address Setup Time

Min

CE# Setup Time

CE# Hold Time

Output Enable Setup Time

Read Recovery Time Before Write

(OE# High to WE# Low)

Unit

Description

Speed Options

AAAH

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Chip / Sector Erase Operation Timings

OE#

CE#

Addresses

WE#

Data

2AAh SA

tAH

tWP

tWC

tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

Notes:

1. SA=Sector Address (for Sector Erase), VA= Valid Address for reading status data.

Micross Package Designator Q Micross Package Designator P

Back to Back Read / Write Cycle Timing

Valid In

Valid In Valid Out

Valid Out

PA PARA

ACC

WDH

CPH

GHWL

SR/W

Addresses

Data

WE#

OE#

CE#

VCC

tVCS

555h

AAAh for Chip Erase

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Data# Polling TImings (During Embedded Algorithms)

Toggle Bit Timings (During Embedded Algorithms)

Note

VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUS

Complement Tr u e

Addresses VA

tOEH

tCE

tCH

tOH

tDF

Status Data

Complement

Status Data Tr u e

Valid Data

tACC

tRC

Note

VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array

data read cycle.

WE#

CE#

OE#

High Z

tOE

DQ6/DQ2

RY/BY#

tBUS

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

tACC

tRC

Valid Data

Valid Status

(first read) (second read) (stops toggling)

Valid Status

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Note

The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

DQ2 vs. DQ6

JEDEC Std

VIDR

Rise and Fall Time

Min ns

RSP

RESET# Setup Time for

Temporary Sector Unprotect Min μs

UnitAll Speed OptionsDescription

500

Parameter

Temporary Sector Unprotect

Temporary Sector Unprotect Timing Diagram

RESET#

tVIDR

12 V

0 or 3 V

CE#

WE#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 3 V

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Sector Protect: 150 μs

Sector Unprotect: 15 ms

1 μs

RESET#

SA, A6,

A1, A0

Data

CE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Protect/Unprotect Verify

VID

VIH

Sector Protect / Unprotect Timing Diagram

Alternate CE# Controlled Erase/Program Operations

JEDEC Std 70 90 100 120

AVAV

70 90 100 120 ns

AVEL

ELAX

DVEH

35 40 45 45 ns

EHDX

OES

GHEL

WLEL

EHWH

ELEH

EHEL

CPH

SR/W

Latency Between Read and Write Operations ns

WHWH1

Programming Operation

Byte μs

WHWH2

sec

Notes:

1. Not 100% Tested

2. See Erase and Programming Performance

Data Setup Time

Unit

Typ

Paramete

Min

Read Recovery Time Before Write (OE#

High to WE# Low)

Write Cycle Time

Address Setup Time

Address Hold Time

Description Speed Options

Data Hold Time

Output Enable Setup Time

WE# Setup Time

WE# Hold Time

CE# Pulse Width

CE# Pulse Width High

Sector Erase Operation

0.7

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Erase and Programming Performance

Typ1Max2Unit Comments

0.5 10 s

16 s

6 150 μsExcludessystemleveloverhead5

Parameter

SectorEraseTime

ChipEraseTime

ByteProgrammingTime

Excludes00hprogrammingprior

toerasure4

NOTES

1.Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles, checkerboard data

pattern.

2.Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.

3.The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4.In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5.System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.

6.The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.

Hardware Reset (RESET\)

JEDEC Std

tREADY 20 μs

READY

500

max

All Speed Options

RESET# Pin Low (During Embedded Algorithms) to

Read or Write (See Note)

RESET# Pin Low (NOT During Embedded Algorithms)

UnitTest Setup

Paramete

Description

READY

500

tRP 500

tRH 50

tRPD 20 μs

min

(g g)

to Read or Write (See Note)

RESET# Pulse Width

RESET# High Time Before Read (See Note)

RESET# Low to Standby Mode

Note:

Not 100% Tested

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Mechanical Drawings

Micross Components

[Package Designator Q]

Detail A

Package Specifications

Symbol Max

Dimensions in Inches

Min

0.120 0.140

0.005 0.015

0.010 REF

0.800 BSC

0.050 BSC

0.010 TYP

0.013 0.017

0.870 0.890

0.980

0.936

1.000

0.956

0.035 0.045

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

4 x ob1

EE1

Package Specifications

Symbol Max

ob1

ob2

D/E

D1/E1

Min

0.210 0.245

0.025 0.035

1.000 BSC

0.600 BSC

0.016 0.020

0.065 0.075

1.170

1.140

1.200

0.145 0.155

Dimensions in Inches

0.100 BSC

1.150

0.045 0.055

0.135 0.145

66 x ob

65 x ob2

Pin 1: SQ. Pad

Micross Components

[Package Designator P]

Mechanical Drawings

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Ordering Information

*Consult Factory for Top Boot

Ceramic Quad Flat Pack Speed Pkg.

Micross Part Numbe

Configuration (ns)

Industrial Operating Range (-400C to +850C)

AS8FLC2M32BQ-70/IT* 2Mx32, 3.3v,Flash Bottom Boot Block 70 CQFP-68

AS8FLC2M32BQ-90/IT 2Mx32, 3.3v,Flash Bottom Boot Block 90 CQFP-68

AS8FLC2M32BQ-100/IT 2Mx32, 3.3v,Flash Bottom Boot Block 100 CQFP-68

AS8FLC2M32BQ-120/IT 2Mx32, 3.3v,Flash Bottom Boot Block 120 CQFP-68

Extended Operating Range (-550C to +1250C)

AS8FLC2M32BQ-70/XT* 2Mx32, 3.3v,Flash Bottom Boot Block 70 CQFP-68

AS8FLC2M32BQ-90/X

2Mx32, 3.3v,Flash Bottom Boot Block 90 CQFP-68

AS8FLC2M32BQ-100/X

2Mx32, 3.3v,Flash Bottom Boot Block 100 CQFP-68

AS8FLC2M32BQ-120/X

2Mx32, 3.3v,Flash Bottom Boot Block 120 CQFP-68

MIL-PRF-38534, CLASS H

AS8FLC2M32BQ-70/Q* 2Mx32, 3.3v,Flash Bottom Boot Block 70 CQFP-68

AS8FLC2M32BQ-90/Q 2Mx32, 3.3v,Flash Bottom Boot Block 90 CQFP-68

AS8FLC2M32BQ-100/Q 2Mx32, 3.3v,Flash Bottom Boot Block 100 CQFP-68

AS8FLC2M32BQ-120/Q 2Mx32, 3.3v,Flash Bottom Boot Block 120 CQFP-68

Hex Inline Package Speed Pkg.

Micross Part Numbe

Configuration (ns)

Industrial Operating Range (-400C to +850C)

AS8FLC2M32BP-70/IT* 2Mx32, 3.3v,Flash Bottom Boot Block 70 HIP-66

AS8FLC2M32BP-90/I

2Mx32, 3.3v,Flash Bottom Boot Block 90 HIP-66

AS8FLC2M32BP-100/I

2Mx32, 3.3v,Flash Bottom Boot Block 100 HIP-66

AS8FLC2M32BP-120/I

2Mx32, 3.3v,Flash Bottom Boot Block 120 HIP-66

Extended Operating Range (-550C to +1250C)

AS8FLC2M32BP-70/XT

2Mx32, 3.3v,Flash Bottom Boot Block 70 HIP-66

AS8FLC2M32BP-90/X

2Mx32, 3.3v,Flash Bottom Boot Block 90 HIP-66

AS8FLC2M32BP-100/X

2Mx32, 3.3v,Flash Bottom Boot Block 100 HIP-66

AS8FLC2M32BP-120/X

2Mx32, 3.3v,Flash Bottom Boot Block 120 HIP-66

MIL-PRF-38534, CLASS H

AS8FLC2M32BP-70/Q* 2Mx32, 3.3v,Flash Bottom Boot Block 70 HIP-66

AS8FLC2M32BP-90/

2Mx32, 3.3v,Flash Bottom Boot Block 90 HIP-66

AS8FLC2M32BP-100/

2Mx32, 3.3v,Flash Bottom Boot Block 100 HIP-66

AS8FLC2M32BP-120/

2Mx32, 3.3v,Flash Bottom Boot Block 120 HIP-66

*Contact Factor

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

Micross Package Designator Q Micross Package Designator P

Micross Part Number SMD Part Number Micross Part Number SMD Part Number

AS8FLC2M32BQ-70/Q 5962-0824504HXA AS8FLC2M32BP-70/Q 5962-0824504HYA

AS8FLC2M32BQ-70/Q 5962-0824504HXC AS8FLC2M32BP-70/Q 5962-0824504HYC

AS8FLC2M32BQ-90/Q 5962-0824503HXA AS8FLC2M32BP-90/Q 5962-0824503HYA

AS8FLC2M32BQ-90/Q 5962-0824503HXC AS8FLC2M32BP-90/Q 5962-0824503HYC

AS8FLC2M32BQ-100/Q 5962-0824502HXA AS8FLC2M32BP-100/Q 5962-0824502HYA

AS8FLC2M32BQ-100/Q 5962-0824502HXC AS8FLC2M32BP-100/Q 5962-0824502HYC

AS8FLC2M32BQ-120/Q 5962-0824501HXA AS8FLC2M32BP-120/Q 5962-0824501HYA

AS8FLC2M32BQ-120/Q 5962-0824501HXC AS8FLC2M32BP-120/Q 5962-0824501HYC

MICROSS TO DSCC PART NUMBER CROSS REFERENCE

FOR 5962-08245*

* Micross part number is for reference only. Orders received referencing the SMD part number will be

processed per the SMD.

FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or speciﬁ cations without notice.

DOCUMENT TITLE

64Mb, 2M x 32, 3.3Volt Boot Block FLASH Array

REVISION HISTORY

Rev # History Release Date Status

1.1 Updated Package Information May 2008 Release

1.2 Updated Order Chart (QT to Q) May 2009 Release

1.3 Updated Micross Information January 2010 Release

1.4 Removed all "word" references February 2010 Release

Added DSCC SMD number for cross reference

1.5 Added "Contact Factory" note for -70 February 2010 Release

1.6 Corrected Micross to DSCC p/n cross May 2011 Release

reference, page 28. (QT package corrected

to Q package)