SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 D Very Low Power . . . 200 W Typ at 5 V D Fast Response Time . . . 2.5 s Typ With D, J, N, OR PW PACKAGE (TOP VIEW) 5-mV Overdrive 1OUT 2OUT VDD 2IN - 2IN + 1IN - 1IN + D Single Supply Operation: D 14 2 13 3 12 4 11 5 10 6 9 7 8 3OUT 4OUT GND 4IN + 4IN - 3IN + 3IN - FK PACKAGE (TOP VIEW) 2OUT 1OUT NC 3OUT 3OUT D D TLC139M . . . 4 V to 16 V TLC339M . . . 4 V to 16 V TLC339C . . . 3 V to 16 V TLC339I . . . 3 V to 16 V High Input Impedance . . . 1012 Typ Input Offset Voltage Change at Worst Case Input at Condition Typically 0.23 V/Month Including the First 30 Days On-Chip ESD Protection 1 description VDD NC 2IN - NC 2IN + The Texas Instruments LinCMOS process offers superior analog performance to standard CMOS processes. Along with the standard CMOS advantages of low power without sacrificing speed, high input impedance, and low bias currents, the LinCMOS process offers extremely stable input offset voltages, even with differential input stresses of several volts. This characteristic makes it possible to build reliable CMOS comparators. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 GND NC 4IN + NC 4IN - 1IN - 1IN + NC 3IN - 3IN + The TLC139/TLC339 consists of four independent differential-voltage comparators designed to operate from a single supply. It is functionally similar to the LM139/LM339 family but uses 1/20th the power for similar response times. The open-drain MOS output stage interfaces to a variety of leads and supplies, as well as wired logic functions. For a similar device with a push-pull output configuration, see the TLC3704 data sheet. NC - No internal connection symbol (each comparator) IN + OUT IN - AVAILABLE OPTIONS PACKAGE TA VIO max AT 25C SMALL OUTLINE (D) CHIP CARRIER (FK) CERAMIC DIP (J) PLASTIC DIP (P) TSSOP (PW) 0C to 70C 5 mV TLC339CD -- -- TLC339CN -40C to 85C 5 mV TLC339ID -- -- TLC339IN TLC339CPW -- -40C to 125C 5 mV TLC339QD -- -- TLC339QN -- -55C to 125C 5 mV TLC339MD TLC139MFK TLC139MJ TLC339MN -- The D and PW packages are available taped and reeled. Add the suffix R to the device type (e.g., TLC339CDR or TLC339CPWR). LinCMOS is a trademark of Texas Instruments Incorporated. Copyright 1991-2004, Texas Instruments Incorporated ! "#$ %!& % "! "! '! ! !( ! %% ) *& % "! + %! !!$* $%! ! + $$ "!!& WWW.TI.COM 1 SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 description (continued) The TLC139M and TLC339M are characterized for operation over the full military temperature range of -55C to 125C. The TLC339C is characterized for operation over the commercial temperature range of 0C to 70C. The TLC339I is characterized for operation over the industrial temperature range of - 40C to 85C. The TLC339Q is characterized for operation over the extended industrial temperature range of - 40C to 125C. output schematic OPEN-DRAIN CMOS OUTPUT Output absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Total supply current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: TLC139M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C TLC339C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLC339I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C TLC339M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C TLC339Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to network ground. 2. Differential voltages are at IN+ with respect to IN -. DISSIPATION RATING TABLE 2 PACKAGE TA 25 25C C POWER RATING D FK J N PW 950 mW 1375 mW 1375 mW 1150 mW 700 mW DERATING FACTOR ABOVE TA = 25 25C C TA = 70 70C C POWER RATING TA = 85 85C C POWER RATING TA = 125 125C C POWER RATING 608 mW 880 mW 880 mW 736 mW 448 mW 494 mW 715 mW 715 mW 598 mW 364 mW 190 mW 275 mW 275 mW 230 mW 140 mW 7.6 mW/ mW/C C 11.0 mW/C mW/ C 11.0 mW/C mW/C 9.2 mW/ C 5.6 mW/C WWW.TI.COM SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 recommended operating conditions TLC139M, TLC339M UNIT MIN NOM MAX Supply voltage, VDD 4 5 16 V Common-mode input voltage, VIC 0 VDD -1.5 20 mA 125 C Low-level output current, IOL Operating free-air temperature, TA -55 V electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC139M, TLC339M MIN TYP MAX 25C VIO Input offset voltage VIC = VICRmin, See Note 3 IIO Input offset current VIC = 2.5 V 125C IIB Input bias current VIC = 2.5 V 125C VDD = 5 V to 10 V, 1.4 -55C to 125C 1 CMRR kSVR Common-mode input voltage range Common-mode rejection ratio Supply-voltage rejection ratio VIC = VICRmin VDD = 5 V to 10 V VOL Low-level output voltage VID = - 1 V, IOL = 6 mA IOH High-level output current VID = - 1 V, VO = 5 V -55C to 125C 0 to VDD -1.5 Supply current (four comparators) Outputs low, No load 84 125C 84 -55C 84 25C 85 125C 84 -55C 84 25C 300 125C dB dB 400 800 mV 0.8 40 nA 1 A 44 80 125C -55C to 125C nA V 25C 25C nA pA 30 25C 25C IDD 5 0 to VDD -1 mV pA 15 25C VICR 5 10 25C UNIT 175 A All characteristics are measured with zero common-mode voltage unless otherwise noted. NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V with a 2.5-k load to VDD. WWW.TI.COM 3 SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 recommended operating conditions TLC339C Supply voltage, VDD Common-mode input voltage, VIC NOM 3 5 16 V 8 VDD -1.5 20 mA 70 C -0.2 Low-level output current, IOL Operating free-air temperature,TA UNIT MIN MAX 0 V electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VIO Input offset voltage VIC = VICRmin, See Note 3 IIO Input offset current VIC = 2.5 V IIB Input bias current VIC = 2.5 V VDD = 5 V to 10 V, TA MIN TLC339C TYP MAX 1.4 5 25C 0C to 70C 6.5 25C 1 70C VICR CMRR kSVR Common-mode input voltage range Common-mode rejection ratio Supply-voltage rejection ratio VIC = VICRmin VDD = 5 V to 10 V VOL Low-level output voltage VID = - 1 V, IOL = 6 mA IOH High-level output current VID = - 1 V, VO = 5 V IDD Supply current (four comparators) 25C 0C to 70C 0 to VDD -1.5 No load 84 70C 84 0C 84 25C 85 70C 85 0C 85 25C 300 70C dB dB 400 650 mV 0.8 40 nA 1 A 44 80 70C 0C to 70C nA V 25C 25C nA pA 0.6 0 to VDD -1 25C Outputs low, 5 70C mV pA 0.3 25C UNIT 100 A All characteristics are measured with zero common-mode voltage unless otherwise noted. NOTE 4: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V with a 2.5-k load to VDD. 4 WWW.TI.COM SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 recommended operating conditions TLC339I Supply voltage, VDD Common-mode input voltage, VIC MIN NOM 3 5 -0.2 Low-level output current, IOL 8 Operating free-air temperature,TA UNIT MAX 16 V VDD -1.5 20 0 V mA C 70 electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VIO Input offset voltage VIC = VICRmin, See Note 3 IIO Input offset current VIC = 2.5 V IIB Input bias current VIC = 2.5 V VDD = 5 V to 10 V, TA MIN TLC339I TYP MAX 1.4 5 25C -40C to 85C 7 25C 1 85C VICR CMRR kSVR Common-mode input voltage range Common-mode rejection ratio Supply-voltage rejection ratio VIC = VICRmin VDD = 5 V to 10 V VOL Low-level output voltage VID = - 1 V, IOL = 6 mA IOH High-level output current VID = - 1 V, VO = 5 V IDD Supply current (four comparators) 25C -40C to 85C 0 to VDD -1.5 No load 84 85C 84 -40C 84 25C 85 85C 85 -40C 84 25C 300 85C dB dB 400 700 mV 0.8 40 nA 1 A 44 80 85C -40C to 85C nA V 25C 25C nA pA 2 0 to VDD -1 25C Outputs low, 5 85C mV pA 1 25C UNIT 125 A All characteristics are measured with zero common-mode voltage unless otherwise noted. NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V with a 2.5-k load to VDD. WWW.TI.COM 5 SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 recommended operating conditions TLC339Q UNIT MIN NOM MAX Supply voltage, VDD 4 5 16 V Common-mode input voltage, VIC 0 VDD -1.5 20 mA 125 C Low-level output current, IOL Operating free-air temperature,TA - 40 V electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VIO Input offset voltage VIC = VICRmin, See Note 3 IIO Input offset current VIC = 2.5 V VDD = 5 V to 10 V, TA MIN TLC339Q TYP MAX 1.4 5 25C -40C to 125C 10 25C 1 125C IIB Input bias current VICR Common-mode input voltage range CMRR kSVR Common-mode rejection ratio Supply-voltage rejection ratio VIC = 2.5 V 5 125C VIC = VICRmin VDD = 5 V to 10 V 0 to VDD -1 -40C to 125C 0 to VDD -1.5 25C 84 84 -40C 84 25C 85 125C 84 -40C 84 25C 300 Low-level output voltage VID = - 1 V, IOL = 6 mA 125C IOH High-level output current VID = - 1 V, VO = 5 V 125C IDD Supply current (four comparators) Outputs low, No load 25C 25C -40C to 125C nA V 125C VOL nA pA 30 25C mV pA 15 25C UNIT dB dB 400 800 0.8 44 mV 40 nA 1 A 80 125 A All characteristics are measured with zero common-mode voltage unless otherwise noted. NOTE 4: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V with a 2.5-k load to VDD. 6 WWW.TI.COM SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 switching characteristics, VDD = 5 V, TA = 25C (see Figure 3) PARAMETER TLC139M, TLC339C TLC339I, TLC339M TLC339Q TEST CONDITIONS MIN tPLH tPHL Propagation delay time, low-to-high output Propagation delay time, high-to-low level output f = 10 kHz, CL = 15 pF 4.5 Overdrive = 5 mV 2.5 Overdrive = 10 mV 1.7 Overdrive = 20 mV 1.2 Overdrive = 40 mV 1.0 VI = 1.4 V step at IN+ Overdrive = 2 mV 1.1 Overdrive = 5 mV 2.1 f = 10 kHz, CL = 15 pF f = 10 kHz, CL = 15pF Transition time, high-to-low level output MAX ss 3.6 Overdrive = 10 mV 1.3 Overdrive = 20 mV 0.85 Overdrive = 40 mV 0.55 VI = 1.4 V step at IN+ tTHL TYP Overdrive = 2 mV UNIT ss 0.10 Overdrive = 50 mV 20 ns PARAMETER MEASUREMENT INFORMATION The TLC139 and TLC339 contain a digital output stage that, if held in the linear region of the transfer curve, can cause damage to the device. Conventional operational amplifier/comparator testing incorporates the use of a servo-loop that is designed to force the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the following alternatives for testing parameters such as input offset voltage, common-mode rejection, etc., are suggested. To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With the input polarity reversed, the output should be low. A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater accuracy. 5V 1V 5.1 k 5.1 k Applied VIO Limit VO Applied VIO Limit VO -4V (a) VIO WITH VIC = 0 V (b) VIO WITH VIC = 4 V Figure 1. Method for Verifying That Input Offset Voltage Is Within Specified Limits WWW.TI.COM 7 SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 PARAMETER MEASUREMENT INFORMATION A close approximation of the input offset voltage can be obtained by using a binary search method to vary the differential input voltage while monitoring the output state. When the applied input voltage differential is equal but opposite in polarity to the input offset voltage, the output changes state. Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the comparator into the linear region. The circuit consists of a switching mode servo loop in which U1A generates a triangular waveform of approximately 20-mV amplitude. U1B acts as a buffer, with C2 and R4 removing any residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input is driven by the output of the integrator formed by U1C through the voltage divider formed by R9 and R10. The loop reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input exactly equals the input offset voltage. Voltage divider R9 and R10 provides a step-up of the input offset voltage by a factor of 100 to make measurement easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is suggested that their tolerance level be 1% or lower. VDD U1B 1/4 TLC274CN Buffer + C2 1 F R3 5.1 k - Dut R4 47 k R1 240 k - C1 0.1 F R5 1.8 k, 1% C3 0.68 F U1C 1/4 TLC274CN - R7 1 M R8 1.8 k, 1% + VIO (X100) Integrator C4 0.1 F U1A 1/4 TLC274CN + R2 10 k Triangle Generator R10 100 , 1% R9 10 k, 1% R3 100 k Figure 2. Circuit for Input Offset Voltage Measurement Measuring the extremely low values of input current requires isolation from all other sources of leakage current and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage can be measured with no device in the socket. Subsequently, this open socket leakage value can be subtracted from the measurement obtained, with a device in the socket to obtain the actual input current of the device. 8 WWW.TI.COM SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 PARAMETER MEASUREMENT INFORMATION Propagation delay time is defined as the interval between the application of an input step function and the instant when the output reaches 50% of its maximum value. Propagation delay time, low-to-high-level output, is measured from the leading edge of the input pulse, while propagation delay time, high-to-low-level output, is measured from the trailing edge of the input pulse. Propagation delay time measurement at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 3, so that the circuit is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change state. VDD Pulse Generator 1 F 5.1 k 50 DUT 1V 10 10 Turn Input Offset Voltage Compensation Adjustment CL (see Note A) 1 k -1 V 0.1 F TEST CIRCUIT Overdrive Overdrive Input Low-to-High-Level Output 100 mV Input 100 mV High-to-Low-Level Output 50% 90% 50% 10% tTHL tPLH tPHL VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance. Figure 3. Propagation Delay, Rise, and Fall Times Test Circuit and Voltage Waveforms WWW.TI.COM 9 SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO IIB Input offset voltage Distribution 4 Input bias current vs Free-air temperature 5 CMRR Common-mode rejection ratio vs Free-air temperature 6 kSVR Supply-voltage rejection ratio vs Free-air temperature 7 IOH High-level output current vs High-level output voltage vs Free-air temperature 8 9 VOL Low-level output voltage vs Low-level output current vs Free-air temperature 10 11 IDD Supply current vs Supply voltage vs Free-air temperature 12 13 tPLH tPHL Low-to-high level output propagation delay time vs Supply voltage 14 Low-to-high level output propagation delay time vs Supply voltage 15 Overdrive voltage vs Low-to-high-level output propagation delay time 16 Output fall time vs Supply voltage 17 Overdrive voltage vs High-to-low-level output propagation delay time 18 tf 10 WWW.TI.COM SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE DISTRIBUTION OF INPUT OFFSET VOLTAGE 100 90 10 VDD = 5 V VIC = 2.5 V TA = 25C VDD = 5 V VIC = 2.5 V IIIB IB - Input Bias Current - nA 80 Number of Units 70 60 50 40 30 20 1 0 0.01 10 0 -5 -4 -3 -2 -1 0 1 2 3 4 0.001 25 5 50 VIO - Input Offset Voltage - mV COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE 90 VDD = 5 V 88 87 86 85 84 83 82 81 80 - 75 - 50 125 SUPPLY-VOLTAGE REJECTION RATIO vs FREE-AIR TEMPERATURE k SVR - Supply-Voltage Rejection Ratio - dB kSVR CMMR - Common-Mode Rejection Ratio - dB 89 100 Figure 5 Figure 4 90 75 TA - Free-Air Temperature - C 89 VDD = 5 V to 10 V 88 87 86 85 84 83 82 81 80 - 25 0 25 50 75 100 - 75 - 50 125 - 25 0 25 50 75 100 125 TA - Free-Air Temperature - C TA - Free-Air Temperature - C Figure 7 Figure 6 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. WWW.TI.COM 11 SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT CURRENT vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 1000 VDD = VOH = 5 V TA = 125C 100 V0H I OH - High-Level Output Current - nA V0H I OH - High-Level Output Current - nA 1000 TA = 85C TA = 70C 10 TA = 25C 1 VOH = VDD 2 10 1 0.1 0.1 0 100 4 6 8 10 12 14 25 16 50 100 125 TA - Free-Air Temperature - C VOH - High-Level Output Voltage - V Figure 8 Figure 9 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 1.5 600 TA = 25C 1.25 4V 1 0.75 5V 10 V 0.5 16 V 0.25 0 0 2 4 VDD = 5 V IOL = 6 mA VDD = 3 V VOL VOL - Low-Level Output Voltage - V VOL VOL - Low-Level Output Voltage - V 75 6 8 10 12 14 16 18 20 IOL - Low-Level Output Current - mA 500 400 300 200 100 0 -75 -50 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C Figure 10 Figure 11 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 12 WWW.TI.COM SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 80 100 Outputs Low No Load 90 70 80 -40C xA A IICC DD - Supply Current - xA A IICC DD - Supply Current - VDD = 5 V No Load TA = - 55C 70 25C 60 50 85C 40 125C 30 20 60 50 Outputs Low 40 30 Outputs High 20 10 10 0 0 2 4 6 8 10 12 14 0 -75 16 -50 25 50 75 100 125 HIGH-TO-LOW-LEVEL OUTPUT RESPONSE TIME vs SUPPLY VOLTAGE LOW-TO-HIGH-LEVEL OUTPUT RESPONSE TIME vs SUPPLY VOLTAGE 5 6 CL = 15 pF RL = 5.1 k (pullup to VDD) TA = 25C CL = 15 pF RL = 5.1 k (pullup to VDD) TA = 25C 4.5 tPHL IDD - HIgh-to-Low-Level Output Propagation Delay Time - s tPLH IDD - Low-to-High-Level Output Propagation Delay Time - s 0 Figure 13 Figure 12 5 -25 TA - Free-Air Temperature - C VDD - Supply Voltage - V Overdrive = 2 mV 4 5 mV 3 10 mV 2 20 mV 40 mV 1 4 3.5 Overdrive = 2 mV 3 2.5 5 mV 2 1.5 10 mV 1 20 mV 0.5 40 mV 0 0 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 VDD - Supply Voltage - V VDD - Supply Voltage - V Figure 14 Figure 15 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. WWW.TI.COM 13 SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS LOW-TO-HIGH-LEVEL OUTPUT PROPAGATION DELAY FOR VARIOUS OVERDRIVE VOLTAGES OUTPUT FALL TIME vs SUPPLY VOLTAGE 5 50 40 mV CL = 100 pF 20 mV 10 mV 5 mV 2 mV 40 t - Time - ns VV) O - Output Voltage - V 60 Differential Input Voltage - mV 0 100 VDD = 5 V CL = 15 pF RL = 5.1 k (pullup to VDD) TA = 25C 0 0 1 2 3 4 50 pF 30 15 pF 20 10 RL = 5.1 k (pullup to VDD) TA = 25C 0 5 0 2 4 tPLH IDD - Low-to-High-Level Output Propagation Delay Time - s 6 Figure 16 Figure 17 VV) O - Output Voltage - V HIGH-TO-LOW-LEVEL OUTPUT PROPAGATION DELAY FOR VARIOUS OVERDRIVE VOLTAGES 5 40 mV 20 mV 10 mV 5 mV 2 mV Differential Input Voltage - mV 0 VDD = 5 V CL = 15 pF RL = 5.1 k (pullup to VDD) TA = 25C 100 0 0 1 2 3 4 tPHL - High-to-Low-Level Output Propagation Delay Time - s Figure 18 14 8 10 12 VDD - Supply Voltage - V WWW.TI.COM 5 14 16 SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 APPLICATION INFORMATION The inputs should always remain within the supply rails in order to avoid forward biasing the diodes in the electrostatic discharge (ESD) protection structure. If either input exceeds this range, the device is not damaged as long as the input current is limited to less than 5 mA. To maintain the expected output state, the inputs must remain within the common-mode range. For example, at 25C with VDD = 5 V, both inputs must remain between - 0.2 V and 4 V to assure proper device operation. To assure reliable operation, the supply should be decoupled with a capacitor (0.1 F) positioned as close to the device as possible. The output and supply currents require close observation since the TLC139/TLC339 does not provide current protection. For example, each output can source or sink a maximum of 20 mA; however, the total current to ground has an absolute maximum of 60 mA. This prohibits sinking 20 mA from each of the four outputs simultaneously since the total current to ground would be 80 mA. The TLC139 and TLC339 have internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, exercise care when handling these devices as exposure to ESD may result in the degradation of the device parametric performance. Table of Applications FIGURE Pulse-width-modulated motor speed controller 19 Enhanced supply supervisor 20 Two-phase nonoverlapping clock generator 21 12 V SN75603 DIR 12 V 5V EN 5.1 k (see Note A) 5.1 k 100 k Half-H Driver 5V 10 k 1/4 TLC139/TLC339 10 k C1 0.01 F (see Note B) 12 V 1/4 TLC139/339 SN75604 Motor Speed Control Potentiometer 5V 10 k Motor 10 k Half-H Driver 5V Direction Control S1 SPDT NOTES: A. The recommended minimum capacitance is 10 F to eliminate common ground switching noise. B. Select C1 for change in oscillator frequency. Figure 19. Pulse-Width-Modulated Motor Speed Controller WWW.TI.COM 15 SLCS119A - DECEMBER 1986 - REVISED APRIL 2004 TYPICAL APPLICATION DATA 5V 5V 12 V 10 k VCC SENSE 5.1 k 12 V Sense RESIN 3.3 k 1 k 1/4 TLC139/TLC339 2.5 V TL7705A REF CT GND 12 V 1 F VUNREG (see Note A) To P Reset RESET 5.1 k To P Interrupt Early Power Fail 1/4 TLC139/TLC339 R1 Ct (see Note B) R2 Monitors 5-V Rail Monitors 12-V Rail Early Power Fail Warning NOTES:A. VUNREG = 2.5 R1 ) R2 R2 B. The value of Ct determines the time delay of reset. Figure 20. Enhanced Supply Supervisor 12 V 12 V R1 100 k (see Note B) 12 V 5.1 k Output 1 R3 5 k (see Note C) 5.1 k 100 k 1/4 TLC139/TLC339 100 k 1/4 TLC139/TLC339 12 V 22 k 100 k 5.1 k C1 0.01 F (see Note A) 12 V Output 2 1/4 TLC139/TLC339 R3 100 k (see Note B) Output 1 NOTES: A. Select C1 for a change in oscillator frequency where: 1/f = 1.85 (100 k)C1 B. Select R1 and R3 to change duty cycle C. Select R2 to change deadtime Output 2 Figure 21. Two-Phase Nonoverlapping Clock Generator 16 WWW.TI.COM PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-87659022A ACTIVE LCCC FK 20 1 None 5962-8765902CA ACTIVE CDIP J 14 1 None 5962-9555001NXDR ACTIVE SOIC D 14 2500 None TLC139MFKB ACTIVE LCCC FK 20 1 None TLC139MJ ACTIVE CDIP J 14 1 None TLC139MJB ACTIVE CDIP J 14 1 TLC339CD ACTIVE SOIC D 14 50 TLC339CDB ACTIVE SSOP DB 14 80 TLC339CDBR ACTIVE SSOP DB 14 TLC339CDR ACTIVE SOIC D TLC339CN ACTIVE PDIP TLC339CN10 OBSOLETE TLC339CNSR ACTIVE Lead/Ball Finish MSL Peak Temp (3) POST-PLATE Level-NC-NC-NC A42 SNPB CU NIPDAU Level-NC-NC-NC Level-1-220C-UNLIM POST-PLATE Level-NC-NC-NC A42 SNPB Level-NC-NC-NC None A42 SNPB Level-NC-NC-NC Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC PDIP N 14 None Call TI SO NS 14 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM 90 None CU NIPDAU Level-1-220C-UNLIM None Call TI Call TI TLC339CPW ACTIVE TSSOP PW 14 TLC339CPWLE OBSOLETE TSSOP PW 14 TLC339CPWR ACTIVE TSSOP PW 14 2000 None CU NIPDAU Level-1-220C-UNLIM TLC339ID ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC339IDR ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC339IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC339MD ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM TLC339MDR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM TLC339MN ACTIVE PDIP N 14 25 None Call TI Call TI Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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