Integrated Device Technology, Inc. HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM IDT7006S/L FEATURES: True Dual-Ported memory cells which allow simulta- neous reads of the same memory location + High-speed access Military: 35/45/55/70ns (max.) Commercial: 25/35/45/55ns (max.) + Low-power operation IDT7006S Active: 750mW (typ.) Standby: 5mW (typ.) IDT7006L Active: 750mW (typ.) Standby: 1mW (typ.) + IDT7006 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than ane device + M/S=H for BUSY output flag on Master M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Devices are capable of withstanding greater than 2001V electrostatic discharge Battery backup operation2V data retention TTL-compatible, single 5V (+10%) pawer supply Available in 68-pin PGA, quad flatpack, and PLCC, a 68- pin fine pitch LCC, and a 64-pin TQFP Industrial temperature range (-40C to +85C) is avail- able, tested to military electrical specifications DESCRIPTION: The IDT7006 is a high-speed 16K x 8 Dual-Port Static FUNCTIONAL BLOCK DIAGRAM RAWAL RAWR CEL CER OE. OER Ai3L A13R A10L A10R VO7L O77 COLUMN COLUMN vO VO WOOL Oar Busy") Busys' Aat ROW ROW Agr Aoi SELECT SELECT Aor NOTES: 1. (MASTER): AtaL Ai3R BUSY is output, AoL ARBITRATION AoR ae. a INTERRUPT oe Boe input = SEMAPHORE 2. BUSY outputs Of OER and INT R/AWL A/We outputs are non-tri-stated push-pull. SEM SEMR, INTL NTR 2739 drw O1 MILITARY AND COMMERCIAL TEMPERATURE RANGES 1993 Integrated Device Technology, Inc NOVEMBER 1993 DSc-1044/2 1IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM RAM. The IDT7006 is designed to be used as a stand-alone 128K-bit Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full- speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low PIN CONFIGURATIONS MILITARY AND COMMERCIAL TEMPERATURE RANGES standby power mode. Fabricated using IDT's CMOS high-performance technol- ogy, these devices typically operate on only 750mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500,.W from a2V battery. The IDT7006 is packaged in a ceramic 68-pin PGA, an 68- pin quad flatpack, a PLCC, a 68-pin fine pitch LCC anda 64- pin thin plastic quad flatpack, TQFP. Military grade product is manufactured in compliance with the latest revision of MIL- STD-883, Class B, making it ideally suited to military tempera- ture applications demanding the highest level of performance and reliability. 5 Some Bas 2esesggeg INDEX OSSme mS Soe elsegE ROO a a a 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 VOa2t Cio 60 [J Ast VOs_ C11 59 7 Aa VOa. Chie 58 [1] Ast VOst C13 57 DAa GND (14 56 CJ AIL VOs. (1s Ona 55 [] AoL vOr7L Che F68-1 54 D INTL VecThi7 L68-1 53 [] BUSYL GND C18 521] GND VOon s 19 PLCC / FLATPACK / LCC 5 EIS _ VO1R CJ20 50 [.] BUSYR TOP VIEW VOe2rn Car 49 [] INTR Vec(C]22 48 1 Aor VOsr Jes 47 DAR VO4R C24 46 [7] Aor VOsR C25 45 [1 A3r VOer (]26 4417] Aan 27 28 29 30 31 32 39 34 35 36 37 38 39 40 41 42 43 O co 2 mGe co x x x x x x x x 2738 drw 02 62KHE BMS S2e EL e2deed Q Isis a Is Vcc - 0.2V isa4 | Full Standby Current One Port CEL or MIL. s| _ 90 260 |mA (One Port All CER > Vcc - 0.2V L _ 90 215 CMOS Level Inputs) SEMR = SEML> Vcc - 0.2V VIN 2 Voc - 0.2V or ViINS 0.2V | COM'L. S | 100 230 90 220 Active Port Outputs Open L | 100 190] 90 180 t = fmax) NOTES: 2739 tbl 08 1. 2. 3. 4. 5. X in part numbers indicates power rating (S or L) Veco = 5V, Ta = +25C. Atf = max, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRc, and using AC Test Conditions of input levels of GND to 3V. f = 0 means no address or control lines change. At Vecs2.0V input leakages are undefined. 6.11IDT7O06S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE")(Continued) (Vcc = 5.0V + 10%) 7006X45 7006X55 7006X70 Test MIL ONLY Symbol Parameter Condition Version |Typ.@ Max. | Typ.2 Max. [Typ.2) Max. funit Iec Dynamic Operating CE Vi, Outputs Open MIL. S | 155 400 150 | 395 | 140 | 390 |mA Current SEM VIH L 155 340 150 335 140 330 (Both Ports Active) f= fmax!?) COML. S$ | 155 340 150 | 335 _ L 155 290 150 285 _ _ IsBt Standby Current CEL = CER VIH MIL. $s 16 85 13 85 10 85 [mA (Both Ports TTL SEMR = SEML ViH L 16 65 13 65 10 65 Level Inputs) f = fMax'9) cOoML. S| 70 13 | 70 f L _ 50 13 50 _ _ IsB2 Standby Current CER or CEL VIH MIL. S$ 90 290 85 290 80 290 [mA (One Port TTL Active Port Outputs Open L 90 250 85 250 80 250 Level Inputs) f = tMax'9) cOML. S| 90 [| 240 85 | 240 [ J SEMR = SEML VIH L 90 210 85 210 _ _ IsB3 Full Standby Current Both Ports CEL and MIL. $8 1.0 30 1.0 30 1.0 30 [mA (Both Ports Ali CER Vcc -0.2V L 0.2 10 0.2 10 0.2 10 CMOS Level Inputs) VIN Voc - 0.2V or COML. 1.0 415 1.0 15 _ Vin 0.2V,f=-04) L | 02 5 02) 5 |- SEMA = SEML Vcc - 0.2V Ise4 Full Standby Current One Port CEL or MIL. $s 85 260 80 260 76 260 [mA (One Port All CER Vcc -0.2V CMOS Level inputs) SEMA = SEML Vcc - 0.2V L 85 215 80 215 75 215 VIN Vcc - 0.2V or COM'L. S$ 85 220 80 220 _ _ VIN 0.2V Active Port Outputs Open, L 85 180 80 180 _ _ f = fMax) NOTES: 2739 thi 08 1. Xin part numbers in of input levels of GND to 3V. . f=0 means no address or control lines change. : dicates power rating (S or L) 2. Veco = SV, Ta = 428C. 3. Atf = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using AC Test Conditions 4 DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only) (Vic = 0.2V, VHC = Vcc - 0.2V) Symbol Parameter Test Condition Min. Typ. Max. | Unit VoR Vcc for Data Retention Vcc = 2V 2.0 _ _ v ICCDR Data Retention Current CE Vuc MIL. _ 100 4000 HA VIN VHC or Vic | COM'L. _ 100 1500 tcor) Chip Deselect to Data Retention Time SEM VHC 0 _ ns trae) Operation Recovery Time tac) _ _ ns NOTES: 2739 th! 09 1. Ta =+25C, Veco = 2V 2. tac = Read Cycle Time 3. This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Vec tCDR VoR 2 2V DATA RETENTION MODE 45V | 2739 drw 05 6.11IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TEST CONDITIONS 5V Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Max. 12500 Input Timing Ref Levels 1.5V Input Timing Reference DATAouT Output Reference Levels 1.5V BUSY Output Load See Figures 1 & 2 INT . 2739 tbl 10 775Q. 30pF 2739 drw 06 Figure 1. Output Load (SpF for tz, tHz, twz, tow) * Including scope and jig. AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE) lOT7006X25 IDT7006X35 COML ONLY Symbol Parameter Min. | Max. Min. [ Max. Unit READ CYCLE tRC Read Cycle Time 25 _ 35 _ ns TAA Address Access Time _ 25 35 ns tACE Chip Enable Access Time) _ 25 _ 35 ns tAOE Output Enable Access Time 13 20 ns tOH Output Hold from Address Change 3 _ 3 _ ns tl2z Output Low-Z Time'! 2) 3 _ 3 _ ns tHZ Output High-Z Time!" 2) 15 15 ns tPU Chip Enable to Power Up Time! 0 0 ns 1PO Chip Disable to Power Down Timel2! _ 50 50 ns 1SOP Semaphore Flag Update Pulse (OE or SEM) 12 _ 16 _ ns 1SAA Semaphore Address Access Time _ 30 _ 40 ns IDT7006X45 IDT7006X55 IDT7006X70 MIL ONLY Symbol Parameter Min. | Max. | Min. | Max. [ Min. | Max. | Unit READ CYCLE tAC Read Cycle Time 45 _ 55 _ 70 _ ns TAA Address Access Time 45 _ 55 _ 70 ns tACE Chip Enable Access Time 45 55 70 ns tAQE Output Enable Access Time _ 25 _ 30 _ 35 ns tOH Output Hold from Address Change 3 _ 3 _ 3 _ ns tLz Output Low-Z Time! ) 3 _ 3 3 ns tHZ Output High-Z Time: _ 20 25 30 | ns tPu Chip Enable to Power Up Timel 0 _ 0 _ 0 _ ns tPD Chip Disable to Power Down Time _ 50 50 _ 50 ns tsoP Semaphore Fiag Update Pulse (OE or SEM) 15 _ 15 _ 15 _ ns TSAA Semaphore Address Access Time 50 _ 60 ~ 75 ns NOTES: 2739 tbl 14 1. Transition is measured +500mvV from low or high impedance voltage with load {Figures 1 and 2). 2. This parameter is guaranteed but not tested. 3. To access RAM, CE=L, SEM =H. 4. Xin part numbers indicates power rating (S or L). 6.11 7IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES WAVEFORM OF READ CYCLES) ADDR DATAout VALID DATA) BUSYouT 2739 drw 07 NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first CE or OE. 3. taco delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last taoe, tace, taa or tapD. 5. SEM = H. TIMING OF POWER-UP POWER-DOWN {Pu ted lec Isp 2739 drw 08 6.11 8IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE) IDT7006X25 IDT7006X35 COM'L ONLY Symbol Parameter Min. | * Max Min. i Max. Unit WRITE CYCLE two Write Cycle Time 25 _ 35 - ns tew Chip Enable to End-of-Write) 20 30 = ns Taw Address Valid to End-of-Write 20 _ 30 _ ns tas Address Set-up Time!) 0 0 ns twPe Write Pulse Width 20 _ 30 _ ns iwR Write Recovery Time a _ 0 _ ns tow Data Valid to End of Write 15 _ 25 - ns5 tHZ Output High-Z Time! _ 15 15 ns 1DH Data Hold Time'4) 0 _ 0 _ ns twz Write Enable to Output in High-2'" ) 15 15 ns tow Output Active from End-of-Write # 0 = 0 ns tswRD SEM Flag Write to Read Time 10 10 _ ns tSPS SEM Flag Contention Window 10 _ 10 _ ns IDT7006X45 IDT7006X55 IDT7006X70 MIL. ONLY Symbol Parameter Min. | Max. | Min. [ Max. | Min. | Max. | Unit WRITE CYCLE two Write Cycle Time 45 _ 55 _ 70 _ ns tew Chip Enable to End-of-Write) 40 _ 45 50 |ons taw Address Valid to End-of-Write 40 _ 45 _ 50 _ ns tas Address Set-up Time) 0 = 0 = 0 ns twe Write Pulse Width 35 _ 40 _ 50 _ ns twR Write Recovery Time 0 _ 0 - 0 _ ns tow Data Valid to End-of-Write 25 _ 30 - 40 ns tHZ Output High-Z Time!" *) 20 25 30 | ns {DH Data Hold Time?) 0 i) - 0 _ ns twz Write Enable to Output in High-Z" 2} _ 20 25 30 ns tow Output Active from End-of-Write 2: 4) 0 _ 0 0 ns tswro SEM Flag Write to Read Time 10 10 _ 10 _ ns tsps SEM Flag Contention Window 40 10 _ 10 _ ns NOTES: 2739 tol 12 1. Transition is measured +500mV from low or high impedance voltage with load (Figures t and 2). 2. This parameter is guaranteed but not tested. 3. To access RAM, CE=L, SEM=H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tew time. 4. The specification for toy must be met by the device supplying write data to the RAM under all operating conditions. Although tbH and tow values will vary over voltage and temperature, the actual tbH will always be smaller than the actual tow. X in part numbers indicates power rating (S or L). a 6.11 9IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, RW CONTROLLED TIMING'35) tWC > ADDRESS x x tHzZ _- OE tAW ce | \ { htas (6 twe pe twa RW t b tw2} DATAoUT + i a + tD>w _ +" DH DATAIN TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING'"35=) oe iwc > ADDRESS y * taw ~ CE f re tact) oy tew 2) mwa?) be RW \ \ \ / tbw r*_ tDH DATAIN 2739 drw 10 NOTES: RAW or CE must be high during all address transitions. . Awrite occurs during the overlap (tew or twp) of a low CE and a low R/W for memory array writing cycle. . WR is measured from the earlier of CE or R/W (or SEM or RAW) going high to the end of write cycle. . During this period, the 1/0 pins are in the output state and input signals must not be applied. If the CE or SEM low transition occurs simultaneously with or after the RAW low transition, the outputs remain in the high impedance state. Timing depends on which enable signal is asserted last, CE, or RAW. . Timing depends on which enable signal is de-asserted first, CE, or RW. If OE is low during R/W contralled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off and data to be placed on the bus for the required tow. If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp. ONOMRwWNM= 6.11 10ID7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE" ht tsaa | toH Ao-A2 XK VALID ADDRESS DK XX OK VALIO ADDRESS K KKK - tAw >+< TWA | wm tACE SEM N/A, ree tow tSoP DATAo DATAN VALID OM heUT _ let TAS I tWP met 1DH RW KWAI at tSWRD &| LACE 0 YLYUILLLLLILLLLLEL LPN | Write Cycle >t Read Cycle ~ 27939 drw 11 NOTE: 1. CE=H for the duration of the above timing (both write and read cycle). TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION *4) c AoA-A2A MATCH x SIDE? "a" < -RAWA SEMA isPs AoB-A2B MATCH x SIDE Br < R/We ra SEMB v CY 2739 drw 12 NOTES: 1. Dor = Dot = L, CEr = CEL = H, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. A may be either left or right port. B is the opposite port from "A". 3. This parameter is measured from R/Wa or SEMA going high to R/We or SEMa going high. 4. If tsps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. 6.11 11IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE) IDT7006X25 IDT7006X35 COM'L ONLY Symbol Parameter Min. | Max. Min. [ Max. Unit BUSY TIMING (M/S = H) 1BAA BUSY Access Time from Address Match 25 35 ns t8DA BUSY Disable Time from Address Not Matched _ 20 30 ns tBAC BUSY Access Time from Chip Enable LOW ~~ 20 30 ns tpoc BUSY Disable Time from Chip Enable HIGH 17 25 ns taps Arbitration Priority Set-up Time? 5 _ 5 _ ns 1B0D BUSY Disable to Valid Data Note 3 ~ Note 3 ns BUSY TIMING (M/S = L) twa BUSY Input to Write!) 0 0 ns twH Write Hold After BUSY) 17 _ 25 ns PORT-TO-PORT DELAY TIMING two0 Write Pulse to Data Delay!) 50 ~ 60 ns tooo Write Data Valid to Read Data Delay? -_ 35 45 ns IDT7006X45 IDT7006X55 IDT7006X70 MIL. ONLY Symbol Parameter Min. | Max. Min. | Max. Min. | Max. | Unit BUSY TIMING (M/5 = H) {BAA BUSY Access Time from Address Match 35 _ 45 _ 45 ns tBDA BUSY Disable Time from Address Not Matched _ 30 _ 40 _ 40 ns tBAG BUSY Access Time from Chip Enable LOW = 30 40 40 ns tBOC BUSY Disable Time from Chip Enable HIGH | 2 | | 35 | 35 | ns tAPS Arbitration Priority Set-up Time(*) 5 5 5 ns tBDD BUSY Disable to Valid Data |Note3 | [Note3] | Note3| ns BUSY TIMING (M/S = L) twe BUSY Input to Write 0 _ 0 0 ns TWH Write Hold After BUSY 2 | |2 | | 2 | |ns PORT-TO-PORT DELAY TIMING twoo Write Pulse to Data Delay") _ 70 _ 80 _ 95 | ns top Write Data Valid to Read Data Delay") ~ 55 65 = 80 | ns NOTES: 2739 tl 13 1. Port-to-port delay through RAM ceils from writing port to reading port, refer to Timing Waveform of Read With BUSY (M/S = H)" or Timing Waveform of Write With Port-To-Port Delay (M/S=L). . To ensure that the earlier of the two ports wins. . tBDD is a calculated parameter and is the greater of 0, (WDD tWP (actual) or (DDD tDW (actual). . To ensure that the write cycle is inhibited during contention. . To ensure that a write cycle is completed after contention. x is part numbers indicates power rating (S or L). ANON 6.11 12IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ WITH BUSY (M/S = H) twe ADDRa MATCH DATAIN R ADDRt BUSYL DATAouTL NOTES: 2739 drw 13 1. To ensure that the earlier of the two ports wins. 2. CE. = CER=L 3. OE = L for the reading port. TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY"2)(M/S = L) twe ADDRRA MATCH RiWA DATAIN A ADDAL DATAOUTL 2739 drw 14 N 1. BUSY input equals H for the writing port. 2. CEL = CER=L TIMING WAVEFORM OF SLAVE WRITE (M/S = L) [=< twp p RW i" twB TWH BUSY 2739 drw 15 6.11 13IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = H) ADDR #" and ** x ADDRESSES MATCH xX CE a 2739 orw 16 WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING M/S = H) ADDR:a: ADDRESS "N" K taps) ADDR:s- MATCHING ADDRESS "N" t BAA }#t BDA BUSY -5 2739 drw 17 NOTES: 1. All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from A. 2. If taps is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE IDT7006X25 IDT7006X35 COML ONLY Symbol! Parameter Min. | Max. Min | Max. Unit INTERRUPT TIMING TAS Address Set-up Time 0 0 _ ns twa Write Recovery Time 0 0 _ ns tINS Interrupt Set Time _ 20 _ 30 ns tINR Interrupt Reset Time _ 20 _ 30 ns IDT7006X45 IDT7006X55 IDT7006X70 MIL. ONLY Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max. | Unit INTERRUPT TIMING tas Address Set-up Time 0 _ 0 _ 0 _ ns twa Write Recovery Time 0 _ 0 _ 0 _ ns tiNS Interrupt Set Time _ 35 _ 40 _ 50 ns TINR Interrupt Reset Time _ 35 _ 40 _ 50 ns NOTE: 2739 tol 14 1. "x" in part numbers indicates power rating (S or L). 6.11 14IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES WAVEFORM OF INTERRUPT TIMING Ie t we: >! ADDR a INTERRUPT SET ADDRESS! t wal4) tas) INT"B 2739 drw 18 Le t RC | ADDR's INTERRUPT CLEAR ADDRESS) XXXK tas@) CEs: OE ve tinr) NT + 2739 drw 19 NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B is the port opposite trom A. 2. See Interrupt truth table. 3. Timing depends on which enable signal is asserted last. 4. Timing depends on which enable signal is de-asserted first. TRUTH TABLES TRUTH TABLE ! INTERRUPT FLAG Left Port Right Port RAL | GEL | OE: |Aot-Aiat! INTL | RAWR | GER | OER {Aon-Ai3R| INTR Function L L X | 3FFF | Xx X Xx X x L' | Set Right INTR Flag Xx X X X X x L L 3FFF | H | Reset Right INTa Flag X Xx x X LW) L L X 3FFE x Set Left INTL Flag x L L | 3FFE | H! X X X x X Reset Left INTL Flag NOTES: 2739 tol 15 1. Assumes BUSYL = BUSYR = H. 2. If BUSYL = L, then no change. 3. If BUSYR =L, then no change. 6.11 15IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TRUTH TABLE Il ADDRESS BUSY ARBITRATION Inputs Outputs AOL-A13L CE. | CER | Aor-Aizn | BUSYL" | BUSYR | Function x X |NOMATCH H H Normal H xX MATCH H H Normal xX H MATCH H H Normal L L MATCH (2) (2) Write Inhibit) NOTES: 2739 thl 16 1. Pins BUSYL and BUSYn are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYx outputs on the IDT7006 are push pull, not open drain outputs. On slaves the BUSYx input internally inhibits writes. 2. simultaneously. Lif the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable inputs of this port. !f tars is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYr outputs cannot be low Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual togic level on the pin. Writes to the right port are internally ignored when BUSYr outputs are driving low regardless of actual logic level on the pin. TRUTH TABLE Ill EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE") Functions Do - D7 Left Do - D7 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0) Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 4 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTE: 2739 tbl 17 1. This table denotes a sequence of events for anly one of the eight semaphores on the IDT7006. FUNCTIONAL DESCRIPTION The IDT7006 provides two parts with separate control, address and |/O pins that permit independent access for reads or writes to any location in memory. The IDT7006 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE high). When a port is enabled, access to the entire memory array is permitted. INTERRUPTS if the user chooses to use the interrupt function, a memory location (mailbox or message center) is assigned to each port. The left port interrupt flag (INTL) is set when the right port writes to memory location 3FFE (HEX). The left port clears the interrupt by reading address location 3FFE. Likewise, the right port interrupt flag (INTR) is set when the left port writes to memory location 3FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 3FFF. The message (8 bits) at 3FFE or 3FFF is user-defined. If the interrupt function is not used, address locations 3FFE and 3FFF are not used as mail boxes, but as part of the random access memory. Referto Table 1 for the interrupt operation. BUSY LOGIC Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is busy. The busy pin can thenbe used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of busy logic is not required or desirable for all applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical 6.11 16IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES Lo t cr MASTER CE SLAVE CE Q Dual Port Dual Port 9 RAM RAM Ms BUSY (L)_ BUSY (R) BUSY (L) BUSY (R) L CL t MASTER = CE SLAVE CE Dual Port Dual Port RAM _ RAM BUSY (L) Te BUSY (R) BUSY (L) BUSY (R) De - S 2739 drw 20 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7006 RAMs. operation. If the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal opera- tion can be programmed by tying the BUSY pins high. If desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. The busy outputs on the IDT 7006 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the busy indication for the resulting array requires the use of an external AND gate. WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS When expanding an IDT7006 RAM array in width while using busy logic, one master part is used to decide which side of the RAMs array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT7006 RAM the busy pin is an output if the part is used as a master (M/S pin = H), and the busy pin is an input if the part used as a slave (M/Spin = L) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The busy arbitration, on a master, is based on the chip enable and address signals only. Itignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. SEMAPHORES The IDT7006 is an extremely fast Dual-Port 16K x 8 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege aver the other processor for functions defined by the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, anan-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table where CE and SEM are both high. Systems which can best use the IDT7006 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7006s hardware semaphores, which pro- vide a lockout mechanism without requiring complex pro- gramming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The 1DT7006 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in 17IOT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. HOW THE SEMAPHORE FLAGS WORK The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called Token Passing Allocation. In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. Ifit was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token andis using the shared resource. The left processor can then either repeatedly request that semaphore's status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active low. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7006 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins AQA2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin Do is used. If a low level is written into an unused semaphore location, that flag willbe set to a zero on that side and a one on the other side (see Table II|}. That semaphore can now only be modified by the side showing the zero. When a oneis written into the same location from the sameside, the flag willbe set to aone farboth sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communica- tions. (A thorough discussing on the use of this feature follows shortly.) A zero written into the same location from the other side willbe stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as ail zeros. The read MILITARY AND COMMERCIAL TEMPERATURE RANGES value is latched into one sides output register when that side's semaphore select (SEM) and output enable (OE) signals ga active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated _read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the sema- phore in order to guarantee that no system jevel contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. ifthe semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table II!). As an example, assume a processor writes a zero to the left port at a free semaphore location. Ona subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understoad by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a sema- phore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. This condition will continue until a one is written to the same semaphore request latch. Should the other side's semaphore request latch have been written to a zera in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first sides requestlatch. The second sides flag will now stay low until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access toa resource is secure. As with any powerful programming tech- nique, if semaphores are misused or misinterpreted, a soft- ware error can easily happen. 6.11IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. USING SEMAPHORESSOME EXAMPLES Perhaps the simplest application of semaphores is their application as resource markers for the IDT7006s Dual-Port RAM. Say the 16K x 8 RAM was to be divided into two 8K x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 8K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore O. if this task were success- fully completed (a zero was read back rather than a one), the left processor would assume control of the lower 8K. Mean- while the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 8K section by writing, then reading azero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still accupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protoccl would allow the two LPORT SEMAPHORE REQUEST FLIP FLOP Do p Q WRITE SEMAPHORE READ MILITARY AND COMMERCIAL TEMPERATURE RANGES processors to swap 8K blocks of Dual-Port RAM with each other. The blacks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port RAM or other shared resources into eight parts. Semaphores can even be as- signed different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the /O device cannot tolerate any wait states. With the use of semaphores, once the twa devices has determined which memory area was off-limits to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory WAIT state is available on one or both sides. Once a semaphore handshake has been performed, both proces- sors can access their assigned RAM segments at full speed. Another application is in the area of complex data struc- tures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. R PORT SEMAPHORE REQUEST FLIP FLOP Do WRITE Q D SEMAPHORE READ 2739 drw 21 Figure 4. IDT7006 Semaphore Logic 6.11 19IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXXX A 999 A A Device Power Speed Package Process/ Type Temperature Range Blank Commercial (0 C to +70 C) B Military (-55 C to +125 C) Compliant to MIL-STD-883, Class B PF 64-pin TQFP (PN64-1) XL 68-pin LCC (L68-1) G 68-pin PGA (G68-1) J 68-pin PLCC (J68-1) F 68-pin Flatpack (F64-1) 25 Commercial Only 35 45 Speed in Nanoseconds 70 Military Only S$ Standard Power L Low Power 17006 128K (16K x 8) Dual-Port RAM 2738 drw 22 6.11 20