CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Function and Pinout Compatible With FCT
and F Logic
D
Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
D
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D
Ioff Supports Partial-Power-Down Mode
Operation
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Matched Rise and Fall Times
D
Fully Compatible With TTL Input and
Output Logic Levels
D
3-State Outputs
D
CY54FCT373T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D
CY74FCT373T
– 64-mA Output Sink Current
– 32-mA Output Source Current
description
The ’FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the
latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup
times are latched when LE transitions from high to low . Data appears on the bus when the output-enable (OE)
input is low . When OE is high, the bus output is in the high-impedance state. In this mode, data can be entered
into the latches.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
O0
D0
D1
O1
O2
D2
D3
O3
GND
VCC
O7
D7
D6
O6
O5
D5
D4
O4
LE
CY54FCT373T ...D PACKAGE
CY74FCT373T ...Q OR SO PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MA Y 1994 REVISED OCT OBER 2001
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
ORDERING INFORMATION
TAPACKAGESPEED
(ns) ORDERABLE
PART NUMBER TOP-SIDE
MARKING
QSOP Q Tape and reel 4.7 CY74FCT373CTQCT FCT373C
SOIC SO
Tube 4.7 CY74FCT373CTSOC
FCT373C
SOIC
SO
Tape and reel 4.7 CY74FCT373CTSOCT
FCT373C
40°Cto85°C
QSOP Q Tape and reel 5.2 CY74FCT373ATQCT FCT373A
40°C
to
85°C
SOIC SO
Tube 5.2 CY74FCT373ATSOC
FCT373
SOIC
SO
Tape and reel 5.2 CY74FCT373ATSOCT
FCT373
SOIC SO
Tube 8 CY74FCT373TSOC
FCT373
SOIC
SO
Tape and reel 8 CY74FCT373TSOCT
FCT373
55°C to 125°C CDIP D Tube 5.6 CY54FCT373ATDMB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS OUTPUT
OE LE D O
L H H H
LHL L
LLX Q
0
H X X Z
H = High logic level, L = Low logic level,
X = Dont care, Z = High-impedance state,
Qn = Previous state of flip flops (Qn1)
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
32
LE
D0
CP
DO0
Q
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MA Y 1994 REVISED OCT OBER 2001
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum rating over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC input voltage range 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output voltage range 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output current (maximum sink current/pin) 120 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1): Q package 68°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient temperature range with power applied, TA 65°C to 135°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
CY54FCT373T CY74FCT373T
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current 12 32 mA
IOL Low-level output current 32 64 mA
TAOperating free-air temperature 55 125 40 85 °C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MA Y 1994 REVISED OCT OBER 2001
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
CY54FCT373T CY74FCT373T
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYPMAX MIN TYPMAX
UNIT
VIK
VCC = 4.5 V, IIN = 18 mA 0.7 1.2
V
V
IK VCC = 4.75 V, IIN = 18 mA 0.7 1.2
V
VCC = 4.5 V, IOH = 12 mA 2.4 3.3
VOH
VCC 475V
IOH = 32 mA 2V
V
CC =
4
.
75
V
IOH = 15 mA 2.4 3.3
VOL
VCC = 4.5 V, IOL = 32 mA 0.3 0.55
V
V
OL VCC = 4.75 V, IOL = 64 mA 0.3 0.55
V
Vhys All inputs 0.2 0.2 V
II
VCC = 5.5 V, VIN = VCC 5
µA
I
IVCC = 5.25 V, VIN = VCC 5µ
A
IIH
VCC = 5.5 V, VIN = 2.7 V ±1
µA
I
IH VCC = 5.25 V, VIN = 2.7 V ±1µ
A
IIL
VCC = 5.5 V, VIN = 0.5 V ±1
µA
I
IL VCC = 5.25 V, VIN = 0.5 V ±1µ
A
IOZH
VCC = 5.5 V, VOUT = 2.7 V 10
µA
I
OZH VCC = 5.25 V, VOUT = 2.7 V 10 µ
A
IOZL
VCC = 5.5 V, VOUT = 0.5 V 10
µA
I
OZL VCC = 5.25 V, VOUT = 0.5 V 10 µ
A
IOS
VCC = 5.5 V, VOUT = 0 V 60 120 225
mA
I
OS
VCC = 5.25 V, VOUT = 0 V 60 120 225
mA
Ioff VCC = 0 V, VOUT = 4.5 V ±1±1µA
ICC
VCC = 5.5 V, VIN 0.2 V, VINVCC 0.2 V 0.1 0.2
mA
I
CC VCC = 5.25 V, VIN 0.2 V, VINVCC 0.2 V 0.1 0.2
mA
ICC
VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.5 2
mA
I
CC VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.5 2
mA
Typical values are at VCC = 5 V, TA = 25°C.
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or
sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, IOS tests should be performed last.
§Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MA Y 1994 REVISED OCT OBER 2001
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
CY54FCT373T CY74FCT373T
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYPMAX MIN TYPMAX
UNIT
ICCD
VCC = 5.5 V, Outputs open,
One input switching at 50% duty cycle, OE = GND,
VIN 0.2 V or VIN VCC 0.2 V 0.06 0.12 mA/
I
CCD
VCC = 5.25 V, Outputs open,
One input switching at 50% duty cycle, OE = GND,
VIN 0.2 V or VIN VCC 0.2 V 0.06 0.12 MHz
#
VCC =55V
One bit switching
at f1 = 10 MHz VIN 0.2 V or
VINVCC 0.2 V 0.7 1.4
#
VCC
=
5
.
5
V
,
Outputs open,
at 50% duty cycle VIN = 3.4 V or GND 1 2.4
#
,
OE = GND,
LE = VCC Eight bits switching
at f1 = 2.5 MHz VIN 0.2 V or
VINVCC 0.2 V 1.3 2.6||
IC#
at 50% duty cycle VIN = 3.4 V or GND 3.3 10.6||
mA
I
C
#
VCC = 5 25 V
One bit switching
at f1 = 10 MHz VIN 0.2 V or
VINVCC 0.2 V 0.7 1.4
mA
VCC
=
5
.
25
V
,
Outputs open,
at 50% duty cycle VIN = 3.4 V or GND 1 2.4
,
OE = GND,
LE = VCC Eight bits switching
at f1 = 2.5 MHz VIN 0.2 V or
VINVCC 0.2 V 1.3 2.6||
at 50% duty cycle VIN = 3.4 V or GND 3.3 10.6||
Ci6 10 6 10 pF
Co8 12 8 12 pF
Typical values are at VCC = 5 V, TA = 25°C.
This parameter is derived for use in total power-supply calculations.
#IC= ICC + ICC × DH × NT + ICCD (f0/2 + f1 × N1)
Where:
IC= Total supply current
ICC = Power-supply current with CMOS input levels
ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH= Duty cycle for TTL inputs high
NT= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MA Y 1994 REVISED OCT OBER 2001
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY54FCT373T CY54FCT373AT
UNIT
MIN MAX MIN MAX
UNIT
twPulse duration, LE high 6 6 ns
tsu Setup time, data before LE2 2 ns
thHold time, data after LE1.5 1.5 ns
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY74FCT373T CY74FCT373AT CY74FCT373CT
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
twPulse duration, LE high 6 5 5 ns
tsu Setup time, data before LE2 2 2 ns
thHold time, data after LE1.5 1.5 1.5 ns
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM TO CY54FCT373AT
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN MAX
UNIT
tPLH
D
O
1.5 5.6
ns
tPHL
D
O
1.5 5.6
ns
tPLH
LE
O
2 9.8
ns
tPHL
LE
O
2 9.8
ns
tPZH
OE
O
1.5 7.5
ns
tPZL
OE
O
1.5 7.5
ns
tPHZ
OE
O
1.5 6.5
ns
tPLZ
OE
O
1.5 6.5
ns
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM TO CY74FCT373T CY74FCT373AT CY74FCT373CT
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX
UNIT
tPLH
D
O
1.5 8 1.5 5.2 1.5 4.7
ns
tPHL
D
O
1.5 8 1.5 5.2 1.5 4.7
ns
tPLH
LE
O
2 13 2 8.5 2 5.5
ns
tPHL
LE
O
2 13 2 8.5 2 5.5
ns
tPZH
OE
O
1.5 12 1.5 6.5 1.5 5.5
ns
tPZL
OE
O
1.5 12 1.5 6.5 1.5 5.5
ns
tPHZ
OE
O
1.5 7.5 1.5 5.5 1.5 5
ns
tPLZ
OE
O
1.5 7.5 1.5 5.5 1.5 5
ns
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B MA Y 1994 REVISED OCT OBER 2001
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
W aveform 1
(see Note B)
Output
W aveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3.5 V
0 V
VOL + 0.3 V
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
S1 7 V
500 GND
From Output
Under Test
CL = 50 pF
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH 0.3 V
500
500
1.5 V1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9221701MRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9221701MR
A
5962-9221702MRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9221702MR
A
CY54FCT373ATDM
B
5962-9221703M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9221703M2A
CY54FCT373ATDMB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9221702MR
A
CY54FCT373ATDM
B
CY74FCT373ATQCT ACTIVE SSOP DBQ 20 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT373A
CY74FCT373ATQCTE4 ACTIVE SSOP DBQ 20 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT373A
CY74FCT373ATQCTG4 ACTIVE SSOP DBQ 20 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT373A
CY74FCT373ATSOC ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT373A
CY74FCT373ATSOCE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT373A
CY74FCT373ATSOCG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT373A
CY74FCT373ATSOCT ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT373A
CY74FCT373ATSOCTE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT373A
CY74FCT373ATSOCTG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT373A
CY74FCT373TSOC ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT373
CY74FCT373TSOCE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT373
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CY74FCT373TSOCG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT373
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CY74FCT373ATQCT SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CY74FCT373ATSOCT SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CY74FCT373ATQCT SSOP DBQ 20 2500 367.0 367.0 38.0
CY74FCT373ATSOCT SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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