July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Am29PL160C
Data Sheet
Publication Number 22143 Revision CAmendment +5 Issue Date June 10, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 22143 Rev: CAmendment/+5
Issue Date: June 10, 2004
Refer to AMD’s Website (www.amd.com) for the latest informa tion.
Am29PL160C
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
■16 Mbit Page Mode device
— Byte (8-bit) or word (16-bit) mode selectable via
BYTE# pin
— Page size of 16 bytes/8 words: Fast page read
access from random locations within the page
■Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors
■5 V-tolerant data, address, and control signals
■High performance read access times
— Page access times as fast as 25 ns at industrial
temperature range
— Random access times as fast as 65 ns
■Power consumption (typical values at 5 MHz)
— 30 mA read current
— 20 mA program/erase current
— 1 µA standby mode current
— 1 µA Automatic Sleep mode current
■Flexible sector architecture
— Sector sizes: One 16 Kbyte, two 8 Kbyte, one
224 Kbyte, and seven sectors of 256 Kbytes
each
— Supports full chip erase
■Bottom boot block configuration only
■Sector Protection
— A hardware method of locking a sector to prevent
any program or erase operations within that
sector
— Sectors can be locked via programming
equipment
— Temporary Sector Unprotect command
sequence allows code changes in previously
locked sectors
■Minimum 1 million write cycles guarantee
per sector
■20-year data retention
■Manufactured on 0.32 µm process technology
■Software command-set compatible with JEDEC
standard
— Backward compatible with Am29F and Am29LV
families
■CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■Package Options
— 44-pin SO (mask-ROM compatible pinout)
— 48-pin TSOP
4 Am29PL160C June 10, 2004
GENERAL DESCRIPTION
The Am29PL160C is a 16 Mbit, 3.0 Volt-only Page
mode Flash memory device organized as 2,097,152
bytes or 1,048,576 words.The device is offered in a
44-pin SO or a 48-pin TSOP package. The word-wide
data (x16) appears on DQ15–DQ0; the byte-wide (x8)
data appears on DQ7–DQ0. This device can be pro-
grammed in-system or with in standard
EPROM programmers. A 12.0 V VPP or 5.0 VCC are
not required for write or erase operations.
The device offers access times of 65, 70, 90, and 120
ns, allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the de-
vice has separate chip enable (CE#), write enable
(WE#), and output enable (OE#) controls.
The sector sizes are as follows: one 16 Kbyte, two
8 Kbyte, one 224 Kbyte and seven sectors of
256 Kbytes each. The device is available in both top
and bottom boot versions.
Page Mode Features
The device is AC timing, pinout, and package compat-
ible with 16 Mbit x 16 page mode Mask ROM. The
page size is 8 words or 16 bytes.
After initial page access is accomplished, the page
mode operation provides fast read access speed of
random locations within that page.
Standard Flash Memory Features
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that
automatically times the program pulse widths and
verifies proper cell margin. The Unlock Bypass mode
facilitates faster programming times by requiring only
two write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. After a
program or erase cycle has been completed, the de-
vice is ready to read array data or accept another
command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via
programming equipment.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
June 10, 2004 Am29PL160C 5
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29PL160C Device Bus Operations ..............................10
Word/Byte Configuration ........................................................ 10
Requirements for Reading Array Data ................................... 10
Read Mode ............................................................................. 10
Random Read (Non-Page Mode Read) ..........................................10
Page Mode Read .................................................................... 11
Table 2. Word Mode ........................................................................11
Table 3. Byte Mode .........................................................................11
Writing Commands/Command Sequences ............................ 12
Program and Erase Operation Status .................................... 12
Standby Mode ........................................................................ 12
Automatic Sleep Mode ........................................................... 12
Output Disable Mode .............................................................. 12
Table 4. Sector Address Table, Bottom Boot (Am29PL160CB) ......13
Autoselect Mode ..................................................................... 14
Table 5. Am29PL160C Autoselect Codes (High Voltage Method) ..14
Sector Protection/Unprotection ............................................... 14
Common Flash Memory Interface (CFI) . . . . . . . 15
Table 6. CFI Query Identification String ..........................................15
Table 7. System Interface String .....................................................16
Table 8. Device Geometry Definition ..............................................16
Table 9. Primary Vendor-Specific Extended Query ........................17
Hardware Data Protection . . . . . . . . . . . . . . . . . . 17
Low VCC Write Inhibit ......................................................................17
Write Pulse “Glitch” Protection ........................................................17
Logical Inhibit ..................................................................................17
Power-Up Write Inhibit ....................................................................17
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 18
Reading Array Data ................................................................ 18
Reset Command ..................................................................... 18
Autoselect Command Sequence ............................................ 18
Word/Byte Program Command Sequence ............................. 18
Unlock Bypass Command Sequence ..............................................19
Figure 1. Program Operation .......................................................... 19
Chip Erase Command Sequence ........................................... 19
Sector Erase Command Sequence ........................................ 20
Erase Suspend/Erase Resume Commands ........................... 20
Temporary Unprotect Enable/Disable Command Sequence .. 21
Figure 2. Erase Operation............................................................... 21
Command Definitions ............................................................. 22
Table 10. Am29PL160C Command Definitions ..............................22
Write Operation Status . . . . . . . . . . . . . . . . . . . . 23
DQ7: Data# Polling ................................................................. 23
Figure 3. Data# Polling Algorithm ................................................... 23
DQ6: Toggle Bit ...................................................................... 24
DQ2: Toggle Bit ...................................................................... 24
Reading Toggle Bits DQ6/DQ2 .............................................. 24
DQ5: Exceeded Timing Limits ................................................ 24
Figure 4. Toggle Bit Algorithm........................................................ 25
DQ3: Sector Erase Timer ....................................................... 25
Table 11. Write Operation Status ................................................... 26
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 27
Figure 5. Maximum Negative Overshoot Waveform ...................... 27
Figure 6. Maximum Positive Overshoot Waveform........................ 27
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 27
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 7. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 29
Figure 8. Typical ICC1 vs. Frequency ............................................. 29
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. Test Setup....................................................................... 30
Table 12. Test Specifications ......................................................... 30
Key to Switching Waveforms . . . . . . . . . . . . . . . 30
Figure 10. Input Waveforms and Measurement Levels ................. 30
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. Conventional Read Operations Timings ....................... 32
Figure 12. Page Read Timings ...................................................... 32
Figure 13. BYTE# Timings for Read Operations............................ 33
Figure 14. BYTE# Timings for Write Operations............................ 33
Figure 15. Program Operation Timings.......................................... 35
Figure 16. AC Waveforms for Chip/Sector Erase Operations ........ 36
Figure 17. Data# Polling Timings (During Embedded Algorithms). 36
Figure 18. Toggle Bit Timings (During Embedded Algorithms)...... 37
Figure 19. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations ............................................................ 37
Figure 20. Alternate CE# Controlled Write Operation Timings ...... 39
Erase and Programming Performance . . . . . . . 40
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 40
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 40
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 41
TS 048—48-Pin Standard Thin Small Outline Package ......... 41
SO 044—44-Pin Small Outline Package, Standard Pinout .... 42
SOR044—44-Pin Small Outline Package, Reverse Pinout .... 43
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44
Revision A (August 1998) ....................................................... 44
Revision A+1 (September 1998) ............................................ 44
Revision B (January 1999) ..................................................... 44
Revision B+1 (February 1999) ................................................ 44
Revision B+2 (March 5, 1999) ................................................ 44
Revision B+3 (May 14, 1999) ................................................. 44
Revision B+4 (June 25, 1999) ................................................ 44
Revision B+5 (July 26, 1999) .................................................. 44
Revision B+6 (September 2, 1999) ........................................ 44
Revision B+7 (February 4, 2000) ............................................ 44
Revision C (February 21, 2000) .............................................. 44
Revision C+1 (June 20, 2000) ................................................ 44
Revision C+2 (June 28, 2000) ................................................ 44
Revision C+3 (November 14, 2000) ....................................... 44
Revision C+4 (June 12, 2002) ................................................ 44
Revision C+5 (June 10, 2004) ................................................ 45
6 Am29PL160C June 10, 2004
PRODUCT SELECTOR GUIDE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
Family Part Number Am29PL160C
Speed Option
Regulated Voltage Range: VCC =3.0–3.6 V -65R -70R
Full Voltage Range: VCC = 2.7–3.6 V -90 -120
Max access time, ns (tACC) 65 70 90 120
Max CE# access time, ns (tCE) 65 70 90 120
Max page access time, ns (tPAC C ) 25253030
Max OE# access time, ns (tOE) 25253030
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0
–
DQ15
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A19
A-1
June 10, 2004 Am29PL160C 7
CONNECTION DIAGRAMS
CE#
BYTE#
A7
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
WE#
NC
A18
A17
A6
A5
A4
A3
A2
A1
A0
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
NC
DQ10
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
NC
DQ12
DQ4
V
CC
V
CC
V
SS
DQ11
DQ3
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
48-pin Standard TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
WE#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
WE#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
44-Pin
Reverse SO
44-Pin
Standard SO
8 Am29PL160C June 10, 2004
PIN CONFIGURATION
A0–A19 = 20 address inputs
DQ0–DQ15 = 16 data inputs/outputs
DQ15/A-1 = In word mode, functions as DQ15
(MSB data input/output)
In byte mode, functions as A-1
(LSB address input)
BYTE# = Byte enable input
When low, enables byte mode
When high, enables word mode
CE# = Chip Enable input
OE# = Output Enable input
WE# = Write Enable input
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS = Device ground
NC = Pin not connected internally
LOGIC SYMBOL
20
16 or 8
DQ0–DQ15
(A-1)
A0–A19
CE#
OE#
WE#
BYTE#
June 10, 2004 Am29PL160C 9
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29PL160C B -65R S I
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
F = Industrial (–40°C to +85°C) with Pb-free package
PACKAGE TYPE
E = 48-Pin Standard Thin Small Outline Package (TS 048)
(bottom boot devices only)
S = 44-Pin Small Outline Package, Standard Pinout (SO 044)
SK = 44-Pin Small Outline Package, Reverse Pinout (SOR044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29PL160C
16 Megabit (1 M x 16-Bit)
CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
Valid Combinations
(Bottom Boot) Voltage Range
AM29PL160CB-65R
EI, SI, SKI,
EF, SF
VCC = 3.0–3.6 V
AM29PL160CB-70R
AM29PL160CB-90
VCC = 2.7–3.6 V
AM29PL160CB-120
10 Am29PL160C June 10, 2004
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory
location. The register is composed of latches that store
the commands, along with the address and data infor-
mation needed to execute the command. The contents
of the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29PL160C Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0
±
0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH. The BYTE# pin determines whether the
device outputs array data in words or bytes.
The internal state machine is set for reading array data
upon device power-up, or after a reset command
(when not executing a program or erase operation).
This ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 11 for the timing diagram. ICC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Read Mode
Random Read (Non-Page Mode Read)
The device has two control functions which must be
satisfied in order to obtain data at the outputs. CE# is
the power control and should be used for device selec-
tion. OE# is the output control and should be used to
gate data to the output pins if the device is selected.
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (tCE) is the delay from the stable ad-
dresses and stable CE# to valid data at the output
pins. The output enable access time is the delay from
the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least
tACC–tOE time).
Operation CE# OE# WE#
Addresses
(Note 1)
DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read L L H AIN DOUT DOUT DQ8–DQ14 = High-Z,
DQ15 = A-1
Write L H L AIN DIN DIN
Standby VCC ±
0.3 V X X X High-Z High-Z High-Z
Output Disable L H H X High-Z High-Z High-Z
June 10, 2004 Am29PL160C 11
Page Mode Read
The Am29PL160C is capable of fast Page mode read
and is compatible with the Page mode Mask ROM
read operation. This mode provides faster read access
speed for random locations within a page. The Page
size of the Am29PL160C device is 8 words, or 16
bytes, with the appropriate Page being selected by the
higher address bits A3–A19 and the LSB bits A0–A2
(in the word mode) and A-1 to A2 (in the byte mode)
determining the specific word/byte within that page.
This is an asynchronous operation with the micropro-
cessor supplying the specific word or byte location.
The random or initial page access is equal to tACC or
tCE and subsequent Page read accesses (as long as
the locations specified by the microprocessor falls
within that Page) is equivalent to tPAC C. When CE# is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Here again, CE# selects
the device and OE# is the output control and should be
used to gate data to the output pins if the device is se-
lected. Fast Page mode accesses are obtained by
keeping A3–A19 constant and changing A0 to A2 to
select the specific word, or changing A-1 to A2 to se-
lect the specific byte, within that page.
The following tables determine the specific word and
byte within the selected page:
Table 2. Word Mode
Table 3. Byte Mode
Word A2 A1 A0
Word 0 000
Word 1 001
Word 2 010
Word 3 011
Word 4 100
Word 5 101
Word 6 110
Word 7 111
Byte A2 A1 A0 A-1
Byte 0 0 0 0 0
Byte 1 0 0 0 1
Byte 2 0 0 1 0
Byte 3 0 0 1 1
Byte 4 0 1 0 0
Byte 5 0 1 0 1
Byte 6 0 1 1 0
Byte 7 0 1 1 1
Byte 8 1 0 0 0
Byte 9 1 0 0 1
Byte 10 1 0 1 0
Byte 11 1 0 1 1
Byte 12 1 1 0 0
Byte 13 1 1 0 1
Byte 14 1 1 1 0
Byte 15 1 1 1 1
12 Am29PL160C June 10, 2004
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes
or words. Refer to “Word/Byte Configuration” for
more information.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required
to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section has
details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 4 indicates the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has de-
tails on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal
register (which is separate from the memory array) on
DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and
ICC read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# pin is both held at VCC ± 0.3 V. (Note that this is a
more restricted voltage range than VIH.) If CE# is held
at VIH, but not within VCC ± 0.3 V, the device will be in
the standby mode, but the standby current will be
greater. The device requires standard access time
(tCE) for read access when the device is in either of
these standby modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables this
mode when addresses remain stable for tACC + 30 ns.
The automatic sleep mode is independent of the CE#,
WE#, and OE# control signals. Standard address access
timings provide new data when addresses are changed.
While in sleep mode, output data is latched and always
available to the system. Note that during Automatic Sleep
mode, OE# must be at VIH before the device reduces
current to the stated sleep mode specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
June 10, 2004 Am29PL160C 13
Table 4. Sector Address Table, Bottom Boot (Am29PL160CB)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Byte Mode (x8) Word Mode (x16)
SA0 0000000X 16/8 000000–003FFF 00000–01FFF
SA1 00000010 8/4 004000–005FFF 02000–02FFF
SA2 00000011 8/4 006000–007FFF 03000–03FFF
SA3 0 0 0 01000–11111 224/112 008000–03FFFF 04000–1FFFF
SA4 001XXXXX 256/128 040000–07FFFF 20000–3FFFF
SA5 010XXXXX 256/128 080000–0BFFFF 40000–5FFFF
SA6 011XXXXX 256/128 0C0000–0FFFFF 60000–7FFFF
SA7 100XXXXX 256/128 100000–13FFFF 80000–9FFFF
SA8 101XXXXX 256/128 140000–17FFFF A0000–BFFFF
SA9 110XXXXX 256/128 180000–1BFFFF C0000–DFFFF
SA10111XXXXX 256/128 1C0000–1FFFFF E0000–FFFFF
14 Am29PL160C June 10, 2004
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed
with its corresponding programming algorithm. How-
ever, the autoselect codes can also be accessed in-
system through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 5. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (Table 4). Table 5 shows the
remaining address bits that are don’t care. When all
necessary bits have been set as required, the pro-
gramming equipment may then read the
corresponding identifier code on DQ7-DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 10. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
Table 5. Am29PL160C Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 10.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector.
The hardware sector unprotection feature re-enables
both program and erase operations in previously
protected sectors.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Sector protection and unprotection must be imple-
mented using programming equipment. The procedure
requires VID on address pin A9 and OE#. Details on
this method are provided in a supplement, publication
number 22239. Contact an AMD representative to re-
quest a copy.
The device features a temporary unprotect command
sequence to allow changing array data in-system. See
“Temporary Unprotect Enable/Disable Command Se-
quence” for more information.
Description Mode CE# OE# WE#
A19
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID XLXLL X 01h
Device ID:
Am29PL160C
(Bottom Boot Block)
Word L L H
XXV
ID XLXLH
22h 45h
Byte L L H X 45h
Sector Protection Verification L L H SA X VID XLXHL
X01h
(protected)
X00h
(unprotected)
June 10, 2004 Am29PL160C 15
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of de-
vices. Software support can then be device-
independent, JEDEC ID-independent, and forward-
and backward-compatible for the specified flash de-
vice families. Flash vendors can standardize their
existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The system
can read CFI information at the addresses given in Ta-
bles 6–9. To terminate reading CFI data, the system
must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 6–9. The
system must write the reset command to return the de-
vice to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD
representative for copies of these documents.
Table 6. CFI Query Identification String
Addresses
(Word Mode)
Addresses
(Byte Mode) Data Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
16 Am29PL160C June 10, 2004
Table 7. System Interface String
Addresses
(Word Mode)
Addresses
(Byte Mode) Data Description
1Bh 36h 0027h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 38h 0036h VCC Max. (write/erase), D7–D4: volt, D3–D0: 100 millivolt
1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs
20h 40h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 42h 000Ah Typical timeout per individual block erase 2N ms
22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 46h 0005h Max. timeout for byte/word write 2N times typical
24h 48h 0000h Max. timeout for buffer write 2N times typical
25h 4Ah 0004h Max. timeout per individual block erase 2N times typical
26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 8. Device Geometry Definition
Addresses
(Word Mode)
Addresses
(Byte Mode) Data Description
27h 4Eh 0015h Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ch 58h 0004h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0000h
0000h
0040h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
0001h
0000h
0020h
0000h
Erase Block Region 2 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0080h
0003h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0006h
0000h
0000h
0004h
Erase Block Region 4 Information
June 10, 2004 Am29PL160C 17
HARDWARE DATA PROTECTION
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored
until VCC is greater than VLKO. The system must pro-
vide the proper signals to the control pins to prevent
unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
Table 9. Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
Addresses
(Byte Mode) Data Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h 86h 0031h Major version number, ASCII
44h 88h 0030h Minor version number, ASCII
45h 8Ah 0000h Address Sensitive Unlock
0 = Required, 1 = Not Required
46h 8Ch 0002h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 8Eh 0001h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 90h 0001h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 92h 0004h
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah 94h 0000h Simultaneous Operation
00 = Not Supported, 01 = Supported
4Bh 96h 0000h
Burst Mode Type
00 = Not Supported, 01 = 4 Word Linear Burst, 02 = 8 Word Linear Burst,
03 = 32 Linear Burst, 04 = 4 Word Interleave Burst
4Ch 98h 0002h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
18 Am29PL160C June 10, 2004
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device
operations. Table 10 defines the valid register com-
mand sequences. Writing incorrect address and
data values or writing them in the improper se-
quence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system
must
issue the reset command to re-en-
able the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 11 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices
codes, and determine whether or not a sector is pro-
tected. Table 10 shows the address and data
requirements. This method is an alternative to that
shown in Table 5, which is intended for PROM pro-
grammers and requires VID on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect mode,
and the system may read at any address any number of
times, without initiating another command sequence.
A read cycle at address XX00h retrieves the
manufacturer code. A read cycle at address XX01h re-
turns the device code. A read cycle containing a sector
address (SA) and the address 02h in word mode (or
04h in byte mode) returns 01h if that sector is pro-
tected, or 00h if it is unprotected. Refer to Table 4 for
valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up com-
mand. The program address and data are written next,
which in turn initiate the Embedded Program algo-
rithm. The system is
not
required to provide further
controls or timings. The device automatically gener-
ates the program pulses and verifies the programmed
cell margin. Table 10 shows the address and data re-
quirements for the byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by using
DQ7 or DQ6. See “Write Operation Status” for informa-
tion on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored.
June 10, 2004 Am29PL160C 19
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may
halt the operation and set DQ5 to “1,” or cause the
Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read will show that
the data is still “0”. Only erase operations can convert
a “0” to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 10 shows the require-
ments for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
Figure 1 illustrates the algorithm for the program oper-
ation. See the Program/Erase Operations table in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.
Note: See Table 10 for program command sequence.
Figure 1. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
20 Am29PL160C June 10, 2004
device returns to reading array data and addresses
are no longer latched.
Figure 2 illustrates the algorithm for the erase opera-
tion. See the Program/Erase Operations tables in “AC
Characteristics” for parameters, and to Figure 16 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 10 shows the address and data
requirements for the sector erase command sequence.
The device does
not
require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector
for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The in-
terrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase Sus-
pend during the time-out period resets the device
to reading array data. The system must rewrite the
command sequence and any additional sector ad-
dresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, or
DQ2. (Refer to “Write Operation Status” for information
on these status bits.)
Figure 2 illustrates the algorithm for the erase opera-
tion. Refer to the Program/Erase Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 16 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maxi-
mum of 20 µs to suspend the erase operation.
However, when the Erase Suspend command is writ-
ten during the sector erase time-out, the device
immediately terminates the time-out period and sus-
pends the erase operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
After an erase-suspended program operation is com-
plete, the system can once again read array data
within non-suspended sectors. The system can deter-
mine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard
program operation. See “Write Operation Status” for
more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase sus-
June 10, 2004 Am29PL160C 21
pend mode and continue the sector erase operation.
Further writes of the Resume command are ignored.
Another Erase Suspend command can be written after
the device has resumed erasing.
Temporary Unprotect Enable/Disable
Command Sequence
The temporary unprotect command sequence is a
four-bus-cycle operation. The sequence is initiated by
writing two unlock write cycles. A third write cycle sets
up the command. The fourth and final write cycle en-
ables or disables the temporary unprotect feature. If
the temporary unprotect feature is enabled, all sectors
are temporarily unprotected. The system may program
or erase data as needed. When the system writes the
temporary unprotect disable command sequence, all
sectors return to their previous protected or unpro-
tected settings. See Table 10 for more information.
Notes:
1. See Table 10 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 2. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
22 Am29PL160C June 10, 2004
Command Definitions
Table 10. Am29PL160C Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command
cycles.
5. Address bits A19–A11 are don’t cares for unlock and command
cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data
when device is in the autoselect mode, or if DQ5 goes high (while
the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read
cycle.
9. The data is 00h for an unprotected sector and 01h for a protected
sector. See “Autoselect Command Sequence” for more
information.
10. Command is valid when device is ready to read array data or
when device is in autoselect mode.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass
mode.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
14. The Erase Resume command is valid only during the Erase Sus-
pend mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Autoselect (Note 8)
Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
Device ID,
Bottom Boot Block
Word 4555 AA 2AA 55 555 90 X01 2245
Byte AAA 555 AAA X02 45
Sector Protect Verify
(Note 9)
Word
4
555
AA
2AA
55
555
90
(SA)
X02
XX00
XX01
Byte AAA 555 AAA (SA)
X04
00
01
CFI Query (Note 10) Word 155 98
Byte AA
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 11) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 12) 2 XXX 90 XXX 00
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 13) 1 XXX B0
Erase Resume (Note 14) 1 XXX 30
Temporary Unprotect Enable Word 4555 AA 2AA 55 555 E0 XXX 01
Byte AAA 555 AAA
Temporary Unprotect
Disable
Word 4555 AA 2AA 55 555 E0 XXX 00
Byte AAA 555 AAA
June 10, 2004 Am29PL160C 23
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 11 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge
of the final WE# pulse in the program or erase com-
mand sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum out-
put described for the Embedded Program algorithm:
the erase function changes all the bits in a sector to
“1”; prior to this, the device outputs the “complement,”
or “0.” The system must provide an address within any
of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the
device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7–DQ0 on the
following
read cycles. This is be-
cause DQ7 may change asynchronously with DQ0–
DQ6 while Output Enable (OE#) is asserted low. See
Figure 16 in the “AC Characteristics” section.
Table 11 shows the outputs for Data# Polling on DQ7.
Figure 3 shows the Data# Polling algorithm.
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5
Figure 3. Data# Polling Algorithm
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
24 Am29PL160C June 10, 2004
DQ6: Toggle Bit
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 11 shows the outputs for Toggle Bit I on DQ6.
Figure 4 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. Figure 18 in the “AC Character-
istics” section shows the toggle bit timing diagrams.
Figure 19 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
“DQ2: Toggle Bit”.
DQ2: Toggle Bit
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for
erasure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 11 to compare outputs
for DQ2 and DQ6.
Figure 4 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. See also the DQ6: Toggle Bit
subsection. Figure 18 shows the toggle bit timing dia-
gram. Figure 19 shows the differences between DQ2
and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 4 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system
must write the reset command to return to reading
array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 4).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
June 10, 2004 Am29PL160C 25
condition that indicates the program or erase cycle
was not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee that the time between ad-
ditional sector erase commands will always be less than
50 µs. See also the “Write Operation Status” section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read
DQ3. If DQ3 is “1”, the internally controlled erase cycle
has begun; all further commands (other than Erase
Suspend) are ignored until the erase operation is com-
plete. If DQ3 is “0”, the device will accept additional
sector erase commands. To ensure the command has
been accepted, the system software should check the
status of DQ3 prior to and following each subsequent
sector erase command. If DQ3 is high on the second
status check, the last command might not have been
accepted. Table 11 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 4. Toggle Bit Algorithm
(Note 1)
(Notes
1, 2)
26 Am29PL160C June 10, 2004
Table 11. Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Operation
DQ7
(Note 2) DQ6
DQ5
(Note 1) DQ3
DQ2
(Note 2)
Standard
Mode
Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle
Embedded Erase Algorithm 0 Toggle 0 1 Toggle
Erase
Suspend
Mode
Reading within Erase
Suspended Sector 1 No toggle 0 N/A Toggle
Reading within Non-Erase
Suspended Sector Data Data Data Data Data
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A
June 10, 2004 Am29PL160C 27
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . -65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9 and OE# (Note 2) . . . . . . . . . .–0.5 V to +13.0 V
All other pins (Note 1). . . . . . . . . . . –0.5 V to +5.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input at I/O pins may overshoot VSS to
-2.0 V for periods of up to 20 ns. Maximum DC voltage on
output and I/O pins is VCC + 0.5 V. During voltage
transitions output pins may overshoot to VCC + 2.0 V for
periods up to 20 ns.
2. Minimum DC input voltage on pins A9 and OE# is –0.5 V.
During voltage transitions, A9 and OE# may overshoot
VSS to -2.0 V for periods of up to 20 ns. Maximum DC
input voltage on pin A9 and OE# is +13.0 V which may
overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
4. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the de-
vice at these or any other conditions above those indi-
cated in the operational sections of this data sheet is not
implied. Exposure of the device to absolute maximum rat-
ing conditions for extended periods may affect device re-
liability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
VCC for regulated voltage range. . . . . . . 3.0 V to 3.6 V
VCC for full voltage range . . . . . . . . . . . . 2.7 V to 3.6 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
Figure 5. Maximum Negative
Overshoot Waveform
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Figure 6. Maximum Positive
Overshoot Waveform
28 Am29PL160C June 10, 2004
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. The Automatic Sleep Mode current is dependent on the state of OE#.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode
current is 200 nA.
6. Not 100% tested.
Parameter
Symbol Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to 5.5 V,
VCC = VCC max
±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to 5.5 V,
VCC = VCC max
±1.0 µA
ICC1
VCC Active Read Current
(Notes 1, 2) CE# = VIL, OE# = VIH 30 50 mA
ICC2
VCC Active Write Current
(Notes 2, 4, 5) CE# = VIL, OE# = VIH 20 30 mA
ICC3 VCC Standby Current (Note 2) CE# = VCC±0.3 V 1 5 µA
ICC4
Automatic Sleep Mode
(Notes 2, 3, 6)
VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V
OE# = VIH 15
µA
OE# = VIL 820
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC 5.5 V
VID
Voltage for Autoselect and
Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage
IOH = –2.0 mA, VCC = VCC min 0.85 x VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4
VLKO
Low VCC Lock-Out Voltage
(Note 4) 2.3 2.5 V
June 10, 2004 Am29PL160C 29
DC CHARACTERISTICS (Continued)
Zero Power Flash
Note: Addresses are switching at 1 MHz
Figure 7. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
25
20
15
10
5
0
0 500 1000 1500 2000 2500 3000 3500 4000
Supply Current in mA
Time in ns
10
8
2
0
1 2345
Frequency in MHz
Supply Current in mA
Note: T = 25
°
C
Figure 8. Typical ICC1 vs. Frequency
2.7 V
3.6 V
4
6
30 Am29PL160C June 10, 2004
TEST CONDITIONS
Table 12. Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
3.3 V
Device
Under
Te s t
Figure 9. Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition -65R
-70R,
-90, -120 Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig capacitance) 30 100 pF
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement
reference levels 1.5 V
Output timing measurement
reference levels 1.5 V
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V 1.5 V OutputMeasurement LevelInput
Figure 10. Input Waveforms and Measurement Levels
June 10, 2004 Am29PL160C 31
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 12 for test specifications.
Parameter
Description Test Setup
Speed Options
UnitJEDEC Std -65R -70R -90 -120
tAVAV tRC Read Cycle Time Min 65 70 90 120 ns
tAVQV tACC Address Access Time CE#=VIL,
OE#=VIL
Max 65 70 90 120 ns
tELQV tCE Chip Enable to Output Delay OE#=VIL Max 65 70 90 120 ns
tPACC Page Access Time Max 25 25 30 30 ns
tGLQV tOE Output Enable to Output Valid Max 25 25 30 30 ns
tEHQZ tDF Chip Enable to Output High Z Max 20 ns
tGHQZ tDF Output Enable to Output High Z Max 20 ns
tOEH
Output Enable
Hold Time (Note 1)
Read 0 ns
Toggle and
Data# Polling 10 ns
tAXQX tOH Output Hold Time from Addresses Min 0 ns
32 Am29PL160C June 10, 2004
AC CHARACTERISTICS
Figure 11. Conventional Read Operations Timings
Note: Word Configuration: Toggle A0, A1, A2. Byte Configuration: Toggle A-1, A0, A1, A2.
Figure 12. Page Read Timings
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
tDF
tOH
A3
-
A19
CE#
OE#
A
-
1
-
A2
Data Bus
Same Page
Aa Ab Ac Ad
Qa Qb Qc Qd
t
ACC
t
PA C C
t
PA C C
t
PA C C
June 10, 2004 Am29PL160C 33
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
Description
Speed Options
UnitJEDEC Std -65R -70R -90 -120
tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns
tFLQZ BYTE# Switching Low to Output HIGH Z Max 25 25 30 30 ns
tFHQV BYTE# Switching High to Output Active Min 65 70 90 120 ns
DQ15
Output
Data Output
(DQ0–DQ7)
CE#
OE#
BYTE#
tELFL
DQ0–DQ14 Data Output
(DQ0–DQ14)
DQ15/A-1 Address
Input
tFLQZ
BYTE#
Switching
from word
to byte
mode
DQ15
Output
Data Output
(DQ0–DQ7)
BYTE#
tELFH
DQ0–DQ14 Data Output
(DQ0–DQ14)
DQ15/A-1 Address
Input
tFHQV
BYTE#
Switching
from byte
to word
mode
Figure 13. BYTE# Timings for Read Operations
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 14. BYTE# Timings for Write Operations
CE#
WE#
BYTE#
The falling edge of the last WE# signal
tHOLD (tAH)
tSET
(tAS)
34 Am29PL160C June 10, 2004
AC CHARACTERISTICS
Program/Erase Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter
Description
Speed Options
Unit
JEDEC Std -65R -70R -90 -120
tAVAV tWC Write Cycle Time (Note 1) Min 65 70 90 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tWLAX tAH Address Hold Time Min 45 45 45 50 ns
tDVWH tDS Data Setup Time Min 35 35 45 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHWL tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 35 35 50 ns
tWHWL tWPH Write Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Programming Operation (Note 2)
Byte Typ 7 µs
Word Typ 9
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 5 sec
tVCS VCC Setup Time (Note 1) Min 50 µs
June 10, 2004 Am29PL160C 35
AC CHARACTERISTICS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 15. Program Operation Timings
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h PA PA
Read Status Data (last two cycles)
A0h
t
GHWL
t
CS
Status D
OUT
Program Command Sequence (last two cycles)
t
CH
PA
36 Am29PL160C June 10, 2004
AC CHARACTERISTICS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 16. AC Waveforms for Chip/Sector Erase Operations
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle
Figure 17. Data# Polling Timings (During Embedded Algorithms)
OE#
CE#
Addresses
VCC
WE#
Data
2AAh SA
tGHWL
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ0–DQ6
Complement Tr u e
Addresses VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
Status Data
Complement
Status Data Tr u e
Valid Data
Valid Data
t
ACC
t
RC
June 10, 2004 Am29PL160C 37
AC CHARACTERISTICS
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 18. Toggle Bit Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
tOE
DQ6/DQ2
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
tACC
tRC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 19. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
38 Am29PL160C June 10, 2004
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter
Description
Speed Options
UnitJEDEC Std -65R -70R -90 -120
tAVAV tWC Write Cycle Time (Note 1) Min 65 70 90 120 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min45454550ns
tDVEH tDS Data Setup Time Min35354550ns
tEHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHEL tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 35 35 35 50 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWH1 tWHWH1
Programming Operation
(Note 2)
Byte Typ 7
µs
Word Typ 9
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 5 sec
June 10, 2004 Am29PL160C 39
AC CHARACTERISTICS
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the
device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
t
GHEL
t
WS
OE#
CE#
WE#
t
DS
Data
t
AH
Addresses
t
DH
t
CP
DQ7# D
OUT
t
WC
t
AS
t
CPH
PA
Data# Polling
A0 for program
55 for erase
t
WHWH1 or 2
t
WH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Figure 20. Alternate CE# Controlled Write Operation Timings
40 Am29PL160C June 10, 2004
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 10 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 5 60 s Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time 40 s
Byte Programming Time 7 300 µs
Excludes system level
overhead (Note 5)
Word Programming Time 9 360 µs
Chip Programming Time
(Note 3)
Byte Mode 14 42 s
Word Mode 9 27 s
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9 and OE#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0
TSOP 7.5 9 pF
SO 8 10 pF
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time
150°C 10 Years
125°C 20 Years
June 10, 2004 Am29PL160C 41
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
42 Am29PL160C June 10, 2004
PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package, Standard Pinout
Dwg rev AC; 10/99
June 10, 2004 Am29PL160C 43
PHYSICAL DIMENSIONS
SOR044—44-Pin Small Outline Package, Reverse Pinout
Dwg rev AC; 10/99
44 Am29PL160C June 10, 2004
REVISION SUMMARY
Revision A (August 1998)
Initial release.
Revision A+1 (September 1998)
Sector Protection/Unprotection
Added reference to Temporary Unprotect Enable/Dis-
able command sequence.
Common Flash Memory Interface (CFI)
Deleted reference to upper address bits in word mode.
Revision B (January 1999)
Ordering Information
Deleted commercial temperature rating.
DC Characteristics
Corrected ICC1 test condition for OE# to VIH.
Revision B+1 (February 1999)
DC Characteristics
Replaced TBDs for ICC4 with specifications.
Revision B+2 (March 5, 1999)
Distinctive Characteristics
In the first subbullet under the Flexible Sector Architec-
ture bullet, deleted the reference to “one 8 Kbyte”
sector.
Revision B+3 (May 14, 1999)
Global
Deleted the 60R speed option and added the 65R
speed option.
Common Flash Memory Interface (CFI)
Corrected the data for the following CFI hex addreses:
38, 39, 3C, 4C.
Absolute Maximum Ratings
Corrected the maximum rating for all other pins to +5.5
V.
Revision B+4 (June 25, 1999)
Changed data sheet status to preliminary. Deleted the
70 ns, full voltage range speed option.
Revision B+5 (July 26, 1999)
Global
Added the reverse pinout SO package. Deleted the
TSOP package.
Physical Dimensions
Restored section.
Revision B+6 (September 2, 1999)
Connection Diagrams
Corrected the pinouts of pins 1, 2, 43, and 44 on the
reverse SO diagram.
Revision B+7 (February 4, 2000)
Global
Added 48-pin TSOP.
Revision C (February 21, 2000)
Global
The “preliminary” designation has been removed from
the document. Parameters are now stable, and only
speed, package, and temperature range combinations
are expected to change in future data sheet revisions.
Added dash to ordering part numbers.
Revision C+1 (June 20, 2000)
Global
Deleted the SOR44 package. Deleted references to
top boot configuration.
Product Selector Guide, Ordering Information
Added -90R speed option.
Revision C+2 (June 28, 2000)
Command Definitions
Command Definitions table: Corrected address in the
sixth cycle of the chip erase command sequence from
2AA to AAA.
Revision C+3 (November 14, 2000)
Added table of contents.
Revision C+4 (June 12, 2002)
Global
Deleted references to hardware reset (RESET#) input.
Added reverse pinout SO package. Deleted 90R
speed option.
TSOP and SO Pin Capacitance
Added TSOP pin capacitance.
June 10, 2004 Am29PL160C 45
Revision C+5 (June 10, 2004)
Ordering Information
Added Pb-free package OPNs
Trademarks
Copyright © 2004 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
