HY57V643220CT(P)
4 Banks x 512K x 32Bit Synchronous DRAM
This document is a general product description and is subje ct to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.9 / Feb. 2004 1
DESCRIPTION
The Hynix HY57V643220CT(P) is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applica-
tions which require wide data I/O and high bandwidth. HY57V643220CT(P) is organized as 4banks of 524,288x32.
HY57V643220CT(P) is offering fully synch ronous operation referenced to a positive edge of the clock. All inputs and
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length o f pip elin e (Read lat ency o f 2 o r 3), the numbe r of conse cuti ve read o r write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interle ave). A burst of read or write cycles in progress ca n be terminated by a burst termi nate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
• JEDEC standard 3.3V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 86pin TSOP-II with 0.5mm of
pin pitc h
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by DQM0,1,2 and 3
• Internal four banks operation
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
• Burst Read Single Write operation
ORDERING INFORMATION
Part No. Clock Frequency Power Organization Interface Package
HY57V643220C(L)T(P)-47 212MHz
Normal/
Low Power
4Banks x
512Kbits x32 LVTTL 400mil 86pin
TSOP II
HY57V643220C(L)T(P)-5 200MHz
HY57V643220C(L)T(P)-55 183MHz
HY57V643220C(L)T(P)-6 166MHz
HY57V643220C(L)T(P)-7 143MHz
HY57V643220C(L)T(P)-8 125MHz
HY57V643220C(L)T(P)-P 100MHz
HY57V643220C(L)T(P)-S 100MHz
NOTE)
Hynix supports lead free part for each speed grade with same specification.