Z9973 Low Voltage Clock Distribution Buffer/Driver Preliminary Product Features * * * * * * * * * * * Frequency Table * VCO_SEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Output Frequency up to 125MHz TM TM Supports PowerPC , and Pentium Processors 12 Clock Outputs: Frequency Configurable Configurable Output Disable Two Reference Clock Inputs for Dynamic Toggling Oscillator or PECL Reference Input +/- 100 ps Cycle-to-Cycle Jitter Glitch-free Output Clocks Transitioning 3.3V Power Supply Pin Compatible with MPC973 52-Pin TQFP Package Block Diagram FVCO 8x 12x 16x 20x 16x 24x 32x 40x 4x 6x 8x 10x 8x 12x 16x 20x 0 1 0 1 VCO Sync Frz QA0 Pin Configuration QA1 LPF SELB1 SELB0 SELA1 SELA0 QA3 VDDC QA2 VSS QA1 VDDC QA0 VSS VCO_SEL Phase Detector QA2 QA3 FB_IN D Q Sync Frz QB0 52 51 50 49 48 47 46 45 44 43 42 41 40 QB1 QB2 FB_SEL2 QB3 MR#/OE D Q Power-On Reset Sync Frz /4, /6, /8, /12 SELA(0,1) 2 SELB(0,1) 2 2 FB_SEL(0,1) 2 QC0 QC1 /4, /6, /8, /10 /2, /4, /6, /8 SELC(0,1) D Q Sync Frz D Q Sync Frz FB_OUT D Q Sync Frz SYNC QC2 QC3 /4, /6, /8, /10 /2 0 1 Sync Pulse Data Generator VSS MR#/OE SCLK SDATA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 PECL_CLK PECL_CLK# VDD Z9973 39 38 37 36 35 34 33 32 31 30 29 28 27 VSS QB0 VDDC QB1 VSS QB2 VDDC QB3 FB_IN VSS FB_OUT VDDC FB_SEL0 12 FB_SEL1 SYNC VSS QC0 VDDC QC1 SELC0 SELC1 QC2 VDDC QC3 VSS INV_CLK Output Disable Circuitry 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 SCLK SDATA FB_SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * x = the reference input frequency, 200MHz < FVCO < 480MHz. D Q TCLK1 TCLK_SEL FB_SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Table 1 PECL_CLK PECL_CLK# VCO_SEL PLL_EN REF_SEL TCLK0 FB_SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 INV_CLK INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 http://www.imicorp.com Rev 1.0 4/20/2000 Page 1 of 11 Z9973 Low Voltage Clock Distribution Buffer/Driver Preliminary Pin Description PIN NAME I/O TYPE 11 12 9 PECL_CLK PECL_CLK# TCLK0 PWR I I I PU PD PU PECL Clock Input. PECL Clock Input. External Reference/Test Clock Input. Description 10 TCLK1 I PU External Reference/Test Clock Input. 44, 46, 48, 50 32, 34, 36, 38 16, 18, 21, 23 QA(3:0) QB(3:0) QC(3:0) VDDC VDDC VDDC O O O 29 FB_OUT VDDC O 25 SYNC VDDC O 42, 43 SELA(1,0) I PU 40, 41 SELB(1,0) I PU 19, 20 SELC(1,0) I PU 5, 26, 27 FB_SEL(2:0) I PU 52 VCO_SEL I PU 31 FB_IN I PU 6 PLL_EN I PU 7 REF_SEL I PU 8 TCLK_SEL I PU 2 MR#/OE I PU 14 INV_CLK I PU 3 SCLK I PU 4 SDATA I PU Clock Outputs. See Table 2 for frequency selections. Clock Outputs. See Table 2 for frequency selections. Clock Outputs. See Table 2 for frequency selections. Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL(0:2). See Frequency Table. A bypass delay capacitor at this output will control Input Reference/ Output Banks phase relationships. Synchronous Pulse Output. This output is used for system synchronization. The rising edge of the output pulse is in sync with both the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios selected. Frequency Select Inputs. These inputs select the divider ratio at QA(0:3) outputs. See Table 2 Frequency Select Inputs. These inputs select the divider ratio at QB(0:3) outputs. See Table 2 Frequency Select Inputs. These inputs select the divider ratio at QC(0:3) outputs. See Table 2 Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1 VCO Divider Select Input. When set low, the VCO output is divided by 2. When set high, the divider is bypassed. See Table 1 Feedback Clock Input. Connect to FB_OUT for accessing the PLL. PLL Enable Input. When asserted high, PLL is enabled. And when low, PLL is bypassed. Reference Select Input. When high, the PECL clock is selected. And when low, TCLK (0,1) is the reference clock. TCLK Select Input. When low, TCLK0 is selected and when high TCLK1 is selected. Master Reset/Output Enable Input. When asserted low, resets all of the internal flip-flops and also disables all of the outputs. When pulled high, releases the internal flip-flops from reset and enables all of the outputs. Inverted Clock Input. When set high, QC(2,3) outputs are inverted. When set low, the inverter is bypassed. Serial Clock Input. Clocks data at SDATA into the internal register. Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 17, 22, 28, 3.3V Power Supply for Output Clock Buffers. VDDC 33,37, 45, 49 13 3.3V Supply for PLL VDD 1, 15, 24, 30, Common Ground VSS 35, 39, 47, 51 A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 http://www.imicorp.com Rev 1.0 4/20/2000 Page 2 of 11 Z9973 Low Voltage Clock Distribution Buffer/Driver Preliminary Maximum Ratings Input Voltage Relative to VSS: VSS-0.3V Input Voltage Relative to VDD: VDD+0.3V Storage Temperature: Operating Temperature: -65C to + 150C 0C to +70C Maximum Power Supply: 5.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters Characteristic Symbol Min Typ Max Units Input Low Voltage VIL VSS - 0.8 V Input High Voltage VIH 2.0 - VDD V Peak-to-Peak Input Voltage PECL_CLK VPP 300 - 1000 mV Common Mode Range PECL_CLK VCMR VDD2.0 - VDD0.6 V Input Low Current ( @ VIL = VSS) IIL -120 A Input High Current ( @ VIH = VDD) Conditions Note 1 Note 3 IIH 120 A Note 3 Output Low Voltage VOL 0.5 V IOL = 20mA, Note 2 Output High Voltage VOH 2.4 V IOH = -20mA, Note 2 Dynamic Supply Current IDDC - PLL Supply Current IDD Input Pin Capacitance Cin - 190 215 mA All VDDC and VDD 15 20 mA VDD only - 4 pF VDD = VDDC =3.3V + 5%, TA = 0C to +70C Note 1: The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the VCMR range and the input lies within the VPP specification. Note 2: Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines. Note 3: Inputs have pull-up/pull-down resistors which affect input current INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 http://www.imicorp.com Rev 1.0 4/20/2000 Page 3 of 11 Z9973 Low Voltage Clock Distribution Buffer/Driver Preliminary AC Parameters1 SYMBOL Tr / Tf Fref FrefDC Fvco Tlock Tr / Tf Fout PARAMETER TCLK Input Rise / Fall Reference Input Frequency Reference Input Duty Cycle PLL VCO Lock Range Maximum PLL lock Time 3 Output Clocks Rise / Fall Time Maximum Output Frequency FoutDC Output Duty Cycle 3 3 MIN TYP Note 2 25 200 0.15 - TCYCLE/2 - 750 2 MAX 3.0 Note 2 75 480 10 1.2 125 120 80 60 TCYCLE/2 + 750 10 UNITS ns MHz % MHz ms ns MHz INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 http://www.imicorp.com 0.8V to 2.0V Q (/2) Q (/4) Q (/6) Q (/8) ps ns Output Enable Time (all outputs) 3 2 8 ns Output Disable Time (all outputs) 3 +/- 100 ps Cycle to Cycle Jitter (peak to peak) 3,4 TSKEW Any Output to Any Output Skew 550 ps 4,5 ps Tpd Propagation Delay PECL_CLK -225 -25 175 TCLK0 -70 130 330 TCLK1 -130 70 270 VDD = VDDC = 3.3V +/- 5%, TA = 0C to +70C Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. Note 2: Maximum and minimum input reference is limited by VCO lock range. Note 3: Outputs loaded with 30pF each. Note 4: 50 transmission line terminated into VDDC/2. Note 5: Tpd is specified for a 50MHz input reference. Tpd does not include jitter. tpZL, tpZH tpLZ, tpHZ TCCJ CONDITIONS Rev 1.0 QFB =(/8) 4/20/2000 Page 4 of 11 Z9973 Low Voltage Clock Distribution Buffer/Driver Preliminary Description The Z9973 has an integrated PLL that provides low skew and low jitter clock outputs for high performance microprocessors. Three independent banks of four outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125MHz. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs, refer to Frequency Table. The VCO frequency is then divided down to provide the required output frequencies. These dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs, see table 2 below. For situations were the VCO needs to run at relatively low frequencies and hence might not be stable, assert VCO_SEL low to divide the VCO frequency by 2. This will maintain the desired output relationships, but will provide an enhanced PLL lock range. The Z9973 is also capable of providing inverted output clocks. When INV_CLK is asserted high, QC2 and QC3 output clocks are inverted. These clocks could be used as feedback outputs to the Z9973 or a second PLL device to generate early or late clocks for a specific design. This inversion does not affect the output to output skew. SELA1 0 0 1 1 SELA0 0 1 0 1 QA /4 /6 /8 /12 SELB1 0 0 1 1 SELB0 0 1 0 1 QB /4 /6 /8 /10 SELC1 0 0 1 1 SELC0 0 1 0 1 QC /2 /4 /6 /8 Table 2 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 http://www.imicorp.com Rev 1.0 4/20/2000 Page 5 of 11 Z9973 Low Voltage Clock Distribution Buffer/Driver Preliminary Zero Delay Buffer When used as a zero delay buffer the Z9973 will likely be in a nested clock tree application. For these applications the Z9973 offers a low voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance. The Z9973 then can lock onto the LVPECL reference and translate with near zero delay to low skew outputs. By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static phase offset is a function of the reference clock the Tpd of the Z9973 is a function of the configuration used. Glitch-Free Output Frequency Transitions Customarily when output buffers have their internal counter's changed "on the fly' their output clock periods will: A. Contain short or "runt" clock periods. These are clock cycles in which the cycle(s) are shorter in period than either the old or new frequency that is being transitioned to. B. Contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old or new frequency that is being transitioned to. This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic levels of any or all of the following pins changed "on the fly" while it is operating: SELA, SELB, SELC, and VCO_SEL. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 http://www.imicorp.com Rev 1.0 4/20/2000 Page 6 of 11 Z9973 Low Voltage Clock Distribution Buffer/Driver Preliminary SYNC Output In situations were output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system synchronization. The Z9973 monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for the SYNC output. Note that the SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal. VCO 1:1 Mode QA QC SYNC 2:1 Mode QA QC SYNC 3:1 Mode QC QA SYNC 3:2 Mode QA QC SYNC 4:1 Mode QC QA SYNC 4:3 Mode QA QC SYNC 6:1 Mode QA QC SYNC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 http://www.imicorp.com Rev 1.0 4/20/2000 Page 7 of 11 Z9973 Low Voltage Clock Distribution Buffer/Driver Preliminary Power Management The individual output enable / freeze control of the Z9973 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic `0' state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs can not be frozen with the serial port, this avoids any potential lock up situation should an error occur in the loading of the serial data. An output is frozen when a logic `0' is programmed and enabled when a logic `1' is written. The enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial "runt" clocks. The serial input register is programmed through the SDATA input by writing a logic `0' start bit followed by 12 NRZ freeze enable bits. The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK. Start Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0-D3 are the control bits for QA0-QA3, respectively D4-D7 are the control bits for QB0-QB3, respectively D8-D10 are the control bits for QC1-QC3, respectively D11 is the control bit for SYNC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 http://www.imicorp.com Rev 1.0 4/20/2000 Page 8 of 11 Z9973 Low Voltage Clock Distribution Buffer/Driver Preliminary Package Drawing and Dimensions (52 TQFP) INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 http://www.imicorp.com Rev 1.0 4/20/2000 Page 9 of 11 Z9973 Low Voltage Clock Distribution Buffer/Driver Preliminary Package Drawing and Dimensions (Cont.) 52 Pin TQFP Dimensions INCHES SYMBOL Notes: 1. All dimensioning and tolerancing conform to ANSI Y14.5-1982. 2. Datum Plane -Hlocated at mold parting line and coincident with lead. Where lead exits plastic body at bottom of parting line. 3. Datums A-B and -Dto be determined at centerline between leads where leads exit plastic body at datum plane. -H4. To be determined at seating plane -C- 5. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254mm on D1 and E1 dimensions. 6. "N" is the total number of terminals (in this case 52). MIN MILLIMETERS NOM MAX MIN NOM MAX A - - 0.047 - - 1.20 A1 0.002 0.004 0.006 0.05 0.10 0.15 A2 0.037 0.039 0.041 0.95 1.00 1.05 e 0.026 BSC 0.65 BSC D 0.472 BSC 12.00 BSC D1 0.394 BSC 10.00 BSC E 0.472 BSC 12.00 BSC E1 0.394 BSC 10.00 BSC L 0.018 0.024 0.030 0.45 0.60 0.75 b 0.009 0.013 0.015 0.22 0.32 0.38 b1 0.009 0.012 0.013 0.22 0.30 0.33 ccc - - 0.004 - - 0.10 ddd - - 0.005 - - 0.13 8. The top of package is smaller than the bottom of package by 0.15mm. 9. A dimension "b" does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess of the "b" dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. 10. Controlling dimension: millimeter. 11. Maximum allowable die thickness to be assembled in this package family is 0.30mm. 12. This outline conforms to Jedec publication 95 registration MS026, variations ACB, ACC, ACD and ACE. 13. A1 is defined as the distance from the seating plane to the lowest point of the package body. 7. These dimensions to be determined at Datum Plane -H- INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 http://www.imicorp.com Rev 1.0 4/20/2000 Page 10 of 11 Z9973 Low Voltage Clock Distribution Buffer/Driver Preliminary Ordering Information Part Number Package Type Production Flow Z9973AA 52 TQFP Commercial, 0C to +70C Note: The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI Z9973AA Date Code, Lot # Z9973AA Package A = TQFP Revision IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 http://www.imicorp.com Rev 1.0 4/20/2000 Page 11 of 11