Philips Components-Signetics DocumentNo. | 853-0086 EGN No. 83082 Bate of Issue April 4, 1986 Status Product Specification Data Communication Products DESCRIPTION The Signetics SCN2661 EPClis a universal synchronous/asynchranous data communications controller chip that is an enhanced version of the SCN2651. it interfaces easily to all 8-bit and 16-bit microprocessors and may be used ina polled or interrupt driven system environment. The SCN2661 accepts programmed instructions from the microprocessor while supporting many serial data communications disciplines synchronous and asynchronous in the full- or half-duplex mode. Special support for BISYNC is provided. The EPCI serializes parallel data characters received from the microprocessor for transmission. Simultaneously, it can receive serial data and convert it into parallel data characters for input to the Microcomputer. The SCN2661 contains a baud rate generator which can be programmed to either accept an external clock or to generate internal transmit or receive clocks. Sixteen different baud rates can be selected under program control when operating in the internal clock mode. Each version of the EPCI(A, B, C) has a different set of baud rates. SCN2661/SCN68661 Enhanced programmable communications FEATURES Synchronous operation 5- to 8-bit characters plus parity Single or doubla SYN operation Internal or external character synchronization Transparent or non-transparent mode Transparent mode DLE stuffing (Tx) and detection (Rx) Automatic SYN or DLE-SYN insertion SYN, DLE and DLESYN stripping Odd, even, or no parity Local or remote maintenance loopback mode Baud rate: DC to 1Mbes (1X clock} Asynchronous operation 5- to 8-bit characters plus parity - 1, 1-1/2 or 2 stop bits transmitted Odd, even, or no parity Parity, overrun and framing error detection Line break detection and generation - False start bit detection Automatic serial echo mode (echoplex) + Local or remote maintenance loopback mode Baud rate: DC to 1Mbps {1X clock) DG to 62.5kbps (16X clock) DG to 15.625kbps (64X clock) 45 interface (EPCI) OTHER FEATURES Internal or external baud rate clock @ 3 baud rate sets 16 internal cates for each set Double-buffered transmitter and receiver * Dynamic character length switching Full- or half-duplex operation TTL compatible inputs and outputs *@ RxC and TxC pins are short-circuit protected * Single +5V power supply # No system clock required APPLICATIONS @ Intelligent terminals Network processors @ Front-end processors @ Remote data concentrators Computer-to-computer links @ Serial peripherals @ BISYNC adaptorsPhilips ComponentsSignetics Data Communication Products Enhanced programmable communications interface (EPCl) SCN2661/SCN68661 PIN CONFIGURATIONS p2 fi] o3 2] axp GB] cnp [4] pe fa bs (| os [7] o7 (@] TxcxsyNne [3] Ar [io] ce i to Rw [3] FRRDY [14] INDEX CORNER NOTE: Pin Functions the same as 28-pin DIP. TOP VIEW ORDERING CODE Voc = +5V 45% PACKAGES Commercial Automotive Military 0C to +70C -40C to +85C -55C to +125C Ceramic DIP SCN2661AC1F28 | SCN2661AA1F28 | SCN2661AM1F28 28-Pin SCN2661BC1F28 | SCN2661BA1F28 | SCN2661BM1F28 0.6" Wide SCN2661CC1F28 | SCN2661CA1F28 | SCN2661CMIF28 Plastic DIP SCN2661AC1N28 2B-Pin SCN2661BC1N28 Contact Factory Not Available 0.6" Wide SCN26610C1N28 SCN2661AC1A28 Plastic LCC SCN2661BC1A28 Contact Factory Not Available SCN2661CC1A28 April 4, 1986 46 Product SpecificationPhilips ComponentsSignetics Data Communication Preducts Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 BLOCK DIAGRAM DATA BUS Do-D7 DATA BUS BUFFER SNE/DLE CONTROL SYN 1 REGISTER RESET Ay --- >] A, > kw _ ct _>< BRCLK -~_ TEAS YNC << RxC/BKDET <__ A SYN 2 REGISTER DLE REGISTER OPERATION CONTROL MODE REGISTER 1 MODE REGISTER? TRANSMITTER = b>-_ TRY" COMMAND REGISTER STATUS REGISTER TRANSMIT DATA HOLDING REGISTER TRANSMIT SHIFT REGISTER pro BAUD RATE f GENERATOR v AND CLOCK CONTROL RECEIVER RECEIVE DATA HOLDING REGISTER MODEM CONTROL RECEIVE SHIFT REGISTER > RxRDY* P< RxD Tb _ TT NOTES: * Opandrain output pin. April 4, 1986 4?Philips ComponentsSignetics Data Communication Products Enhanced programmable communications interface (EPCI) Product Specification SCN2661/SCN68661 ABSOLUTE MAXIMUM RATINGS! PARAMETER RATING UNIT Operating ambient temperature* Note 4 C Storage temperature -65 to +150 C Alt voltages with respect to ground? 0.5 to +6.0 v NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150C maximum function temperature. 3. This product includes circuitry specifically designed for the protection of its intemal devices from the damaging effect of excessive static charge. Nonetheless, itis suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Over recommended free-air operating temperature range and supply voltage range unless otherwise specified. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. DC ELECTRICAL CHARACTERISTICS": 2 3 LIMITS SYMBOL PARAMETER TEST CONDITIONS Min | Typ | Max UNIT Input voltage Vir Low 0.8 Vv Vin High 2.0 Vv Output voltage VoL Low lo. = 2.2mA 0.4 v Vox4 High lou = -400pA 24 Vv fe Input leakage current Vin=O0to5.5V 10 pA 3-State output leakage current lun Data bus high Vo = 4.0V 10 pA lie Data bus low Vo = 0.45V 10 pA lec | Power supply current 150 mA NOTES: 1. Over recommended free-air operating temperature range and supply voltage range unless otherwise specified. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 2. All voltages measurements are referenced to ground. All time measurements are at the 50% level for inputs (except tpan and tga) and at 0.8V and 2.0V for outputs. input levels swing between 0.4V and 2.4V, with a transition time of < 20ns maximum. 3. Typical values are at +25C, typical supply voltages and typical processing parameters. 4. INTR, TRRDY, AxADY and TxEMT/DSCHG outputs are open-drain. CAPACITANCE Ta = 25C, Veco = OV LIMITS SYMBOL PARAMETER TEST CONDITIONS Min | Typ | Max UNIT Capacitance Cin Input 20 pF Gout Output fc = 1MHz 20 pF Cio InpuvOutput Unmeasured pins tied to ground 20 pF April 4, 1986 48Philips ComponentsSignetics Data Communication Products Praduct Specification Enhanced programmable communications interface (EPC!) SCN2661/SCN68661 AC ELECTRICAL CHARACTERISTICS": 2, 3 LIMITS SYMBOL PARAMETER TEST CONDITIONS Min | Typ | Max UNIT Pulse width thes Reset 1000 ns Chip enable 250 ns Setup and hold time tas Address setup 10 : ns tay Address hofd 10 ns fes RW control setup 10 ns fcH FM control hold 10 ns tos Data setup for write 150 ns tou Data hold for write 10 ns taxs RX data setup 300 ns tax RX data hold 350 ns lop Data delay time for read CL = 150pF 200 ns lor Data bus floating time for read C, = 150pF 400 ns tcep CE to CE delay 600 ns Input clock frequency fara Baud rate generator (2661A, B) 1.0 49152 | 4.9202 MHz fg Rg Baud rate generator (2661) 1.0 5.0688 | 5.0738 MHz frat TxT or RxO : dc 1.0 MHz Clock width gay? - Baud rate High (2661A, B) 75 ns tarn Baud rate High (2661C) 70 ns tarn Baud rate Low (2661A, B) 75 ns tan.> Baud rate Low (2661C) 70 ns tavtH Txt or Rxt High 480 ns tar Txt or Rxt Low 480 ns trxp TxD delay frem falling edge of Txt Cy = 150pF 650 ns tres Skew between TxD changing and falling edge C, = 150pF 0 ns of Txt output* NOTES: 1, Over recommended tree-air operating temperature range and supply voltage range unless othenwise specified. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 2. Alt voltages measurements are referenced to ground. All time measurements are at the 50% level for inputs (except tgqy and tgaL) and at 0.8V and 2.0V for outputs. Input levels swing between 0.4V and 2.4V, with a transition time of < 20ns maximum. 3. Typical values are at +25C, typical supply voltages and typical processing parameters. 4. Parameter applies when internal transmitter clock is used. 5. Under test conditions of 5.0688MHZz fgrg (68661) and 4.9152MHz faag (68661A, B), tgny and tgp, measured at Vy, and V,, respectively, 6. In asynchronous local loopback mode, using 1X clock, the following parameters apply: faq = 0.83MHz max and tar, = 700ns min. 7. See AC load conditions. April 4, 1986 49Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 BLOCK DIAGRAM The EPCl consists of six major sections. These are the transmitter, receiver, timing, operation control, modern control and SYN/DLE control. These sections communicate with each other via an internal data bus and an internal control bus. The internal data dus interfaces to the mi- croprocessor data bus via a data bus buffer. Operation Control This functional block stores configuration and operation commands from the CPU andgener- ates appropriate signals to various internal sec- tions to contral the overall device operation. It contains read and write circuits to permit cam- munications with the microprocessor via the data bus and contains mode registers 1 and 2, the command register, and the status register. Details of register addressing and protocol are presented in the EPCI programming section of this data sheet. Timing The EPCI contains a Baud Rate Generator (BRG) which is programmable to accept exter- naltransmit or receive clocks or to divide an ex- ternal clack to perform data communications. The unit can generate 16 commonly used baud rates, any one of which can be seiected for tull-duplex operation. See Table 1. Receiver The receiver accepts serial data on the RxD pin, converts this serial input to parallel format, checks for bits or characters that are unique to the communication technique and sends an assembled character to the CPU. Transmitter The transmitter accepts parallel data from the CPU, converts it to a seriat bit stream, inserts the appropriate characters or bits (basedon the communication technique) and outputs a com- posite serial stream of data on the TxD output pin. Modem Control The modern control section provides interfac- ing for three input signals and three output sig- nals used for handshaking and status indication between the CPU and a modem. SYN/DLE Controi This section contains control circuitry and three 8-bit registers storing the SYN1, SYN2, and DLE characters provided by the CPU. These registers are usedin the synchronous mode of operation to provide the characters required for synchronization, idle fill and data transparency. Table 1. Baud Rate Generator Characteristics 69661A (BRCLK = 4.9152MHz) ACTUAL FREQUENCY PERCENT MR23-20 BAUD RATE 16X CLOCK ERROR DIVISOR 0000 50 0.8kHz _ 6144 0001 75 1.2 _ 4096 0010 110 1.7598 -0.01 2793 0011 134.5 2.152 _ 2284 0100 150 2.4 2048 0101 200 3.2 1536 0110 300 48 1024 0111 600 9.6 512 1000 1050 16.8329 0.196 292 1004 1200 19.2 256 1010 1800 28.7438 0.19 171 1011 2000 31.9168 0.26 154 1100 2400 38.4 128 1101 4800 76.8 64 1110 9600 153.6 32 wi 19200 307.2 16 686618 (BRCLK = 4.9152MHz) ACTUAL FREQUENCY PERCENT MR23-20 BAUD RATE 16X CLOCK ERROR DIVISOR 0000 45.5 0.7279kHz 0.005 6752 0001 50 0.8 6144 0010 75 1.2 4096 0011 110 1.7598 ~0.01 2793 0100 134.5 2.152 2284 0101 150 24 2048 0110 300 48 1024 o1lt 600 96 512 1000 1200 19.2 256 1001 1800 28,7438 -0.19 171 1010 2000 31,9168 0.26 154 1011 2400 38.4 128 1100 4800 76.8 ~ 64 1101 9600 153.6 32 1110 19200 307.2 16 Wi 38400 614.4 8 April 4, 1986 50Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 68661C (BRCLK = 5.0688MHz) ACTUAL FREQUENCY PERCENT MR23-20 BAUD RATE 18X CLOCK ERROR DIVISOR 0000. 50 0.8KHz _ 6336 0001 75 1.2 _ 4224 0010 110 1.76 2880 0011 134.5 2.1523 0.016 2355 0100 150 24 _ 2112 0401 300 48 _ 1056 0110 600 9.6 _ 528 0411 1200 19.2 _ 264 1000 1800 28.8 _ 176 1001 2000 32.081 0.253 158 1010 2400 38.4 _ 132 1011 3600 57.6 88 1100 4800 76.8 66 1101 7200 115.2 _ 44 1119 9600 153.6 _ 33 1441 19200 316.8 3.125 16 NOTE: 16X clock is used in asynchronous mode. In synchronous mode, clock multiplier is 1X and BRG can be used only for TxC. OPERATION The functional operation of the 68661 is pro- grammed by a set of control words supplied by the CPU. These contro! words specity items such as synchronous or asynchronous made, baud rate, number of bits per character, etc. The programming procedure is described in the EPCI programming section of the data sheet. After programming, the EPCI is ready to per- form the desired communications functions. The receiver performs serial to paralle! conver- sion of data received from a modem or equiva- lent device. The transmitter converts parallel data received from the CPU to a serial bit stream. These actions are accomplished with- inthe framework specified by the contral words. Receiver The 6866 1 is conditioned to receiver data when the BCD input is Low and the RxEN bit in the commands register is true. In the asynchro- nous mode, the receiver looks for High-to-Low (mark to space) transition of the start bit on the RxD input line. {fa transition is detected, the state of the RxD line is sampled again after a delay of one-half of a bit-time. If RxD is now high, the search for a valid start bit is begun again. If RxD is still Low, a valid start bit is as- sumed and the receiver continues to sampie the input line at one bit time intervals until the proper number of data bits, the parity bit, and one stop dit have been assembled, The data are then transferred to the receive data halding register, the RxRDY bitin the status register is set, and the RxRDY output is asserted. If the character length is less than 8 bits, the High or- April 4, 1986 der unused bits in the holding register are set to zero. The parity error, framing error, and overrun error status bits are strobed into the status register on the positive going edge of Rx corresponding to the received character boundary. If the stop bitis present, the receiver will immediately begin its search for the next startbit. Ifthe stop bitis absent (framing error), the receiver will interpret a space as a start bit if it persists inta the next bit timer interval. Ifa break condition is detected (RxD is Low for the entire character as well as the stop bit), only one character consisting of all zeros (with the FE status bit SR5 set) will be transferred te the holding register. The RxD input must return to a High condition before a search for the next start bit begins. Pin 25 can be programmed to be a break datect output by appropriate setting of MR27-MR24. Hf so, a detected break will cause that pin to go High. When RxD returns to mark for one RxC time, pin 25 will go low. Refer to the Break De- tection Timing Diagram. When the EPC1 is initialized into the synchro- nous mode, the receiver first enters the hunt mode on a0 to i transition of RNEN (CR2}. In this mode, as data are shifted into the receiver shift register a bit at a time, the contents of the register are compared to the contents of the SYN1 register. If the two are not equal, the next bit is shifted in and the comparison is repeated. When the two registers match, the hunt mode is terminated and character assembly mode begins. If single SYN operation is pro- 51 grammed, the SYN DETECT? status dit is set. \t double SYN operation is programmed, the first character assembled after SYN1 must be SYN2 in order for the SYN DETECT bit to be set. Otherwise, the EPCI returns to the hunt mode. (Note that the sequence SYN1-SYN1-SYN2 will not achieve synchroni- zation.} When synchronization has been achieved, the EPC! continues to assemble characters and transfer then to the holding reg- ister, setting the RxRDY status bit and assert- ing the RxRDY output each time a character is transferred. The PE and OE status bits are set as appropriate. Further receipt of the appropri- ate SYN sequence sets the SYN DETECT sta- tus bit. If the SYN = stripping mode is commanded, SYN characters are not trans- ferredto the holding register. Note thatthe SYN characters used to establish initial synchroni- Zation are nottransferred to the holding register in any case. External jam synchronization can be achieved via pin 9 by appropriate setting of MR27-MR24. When pin 9 is an XSYNC input, the internal SYN1, SYN1I-SYN2, and DLE-SYN1 detec- tionis disabled. Each positive going signal on XSYNC will cause the receiver to establish syn- chronization on the rising edge of the next RxC pulse. Character assembly will start with the RxD input at this edge. XSYNC may be low- eredon the nextrising edge of RxD. This exter- nal synchronization will cause the SYN DETECT status bitto be set until the status reg- ister is read. Refer to XSYNC timing diagram.Philips Components-Signetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 Fable 2. CPU-Related Signals PIN NAME PIN NO. INPUT/ OUTPUT FUNCTION RESET AO, Al Rr CE DOo-D7 TxEMT? DSTAHG 21 12,18 11 27,28,1,2,5-8 18 i4 vO A High on this input performs a master raset on the 68661. This signal asynchronously termi- nates any device activity and clears the mode, command and status registers. The device as- sumes the idle state and remains there until initialized with the appropriate control words. Address lines used to select internal EPC! registers. Read command when Low, write command when High. Chip enable command. When Low, indicates that control and data lines to the EPCI are valid and that the operation specified by the RW, A1 and AO inputs should be performed. When High, places the DCD7 linas in the 3-State condition. 8-bit, 3-State data bus used to transfer commands, data and status between EPCl and the CPU. DO is the least significant bit, D7 the most significant bit. This outputis the complementof status register bitSRO. When Low, itindicates that the transmit data holding register (THR) is ready to accepta data character from the CPU. Itgoes High when the data character is loaded. This output is valid only when the transmitter is enabled. Itis an open-drain output which can be used as an interrupt to the GPU. This output is the complement of status register bit SR1. When Low, it indicates that the receive data holding register (RHR) has a character ready for input to the CPU. !tgaes High when the RHR is read by the CPU, andalso when the receiver is disabled. Itis an open-drain outputwhich can be used as an interrupt to the CPU. This output is the complement of status register bit SR2. When Low, itincicates that the trans- mitter has completed serialization of the last character loaded by the CPU, or that a change of state of the DSA or OCD inputs has occurred. This output goes High when the status register is ready by the CPU, ifthe TxEMT condition does notexist. Otherwise, the THR must be loaded by the CPU for this line to. go high. !tis an open-drain output which can be used as an interrupt to the CPU. See Status Register (SR2) for details. Table 3. Device-Related Signals PIN NAME PIN NO. INPUT; OUTPUT FUNCTION BRCLK RxC/BKDET TxC/XSYNC RxD TxD 20 25 19 22 16 24 23 vo vO Clock input to the interna! baud rate generator {see Table 1). Not required if external receiver and transmitter clocks are used. Receiver clock. If external receiver clock is programmed, this input controls the rate at which the character is to be received. Its frequency is 1X, 16X or 64X the baud rate, as programmed by mode register 1. Data are sampled on the rising edge of the clack. Ifintemal receiver clock is programmed, this pin can be a 1X/16X clock or a break detect output pin. Transmitter clock. !f external transmitter clock is programmed, this input controls the rate at which the character is transmitted. Its frequency is 1X, 16X or 64X the baud rate, as pro- grammed by mode register 1. The transmitted data changes on the falling edge of the clock. Ifinternal transmitter clock is pragrammed, this pin can be a 1X/16X clock outputor an external jam synchronization input. Serial data input to the receiver. Mark is High, space is Low. Serial data output trom the transmitter. *Mark" is High, Space is Low. Held in mark condition when the transmitter is disabled. General purpose input which can be used for data setready or ring indicator condition. Its com- plement appears as status register bit SR7. Causes a Low output on TXEMT/DSCHG when its state changes it CR2 or CRO = 1. Data carrier detect input. Must be Low in order for the receiver to operate. Its complement ap- pears as status register bit SA6. Causes a Low output on Ix when its state changes it CR2 or CRO = 1. !f DCD goes High while receiving, the RxC is internally inhibited. Clear to send input. Must be Low in order for the transmitter to operate. If it goes High during transmission, the character in the transmit shift register will be transmitted before termination. General purpose output which is the complement of command register bitCR1. Normally used to indicate data terminal ready. General purpose output which is the complement of command register bit CR5. Normally used to indicate request to send. See Command Register (CRS) for details. April 4, 1986 52Philips Components-Signetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 Transmitter The EPCiis conditioned to transmit data when the CTS input is Low and the TxEN command register bit is set. The 68661 indicates to the CPU thatitcan accepta character tor transmis- sion by setting the TXRDY status bit and assert- ing the TXRDY output. When the CPU writes acharacter into the transmit data holding regis- ter, these conditions are negated. Data are transferred from the holding register to the transmit shift register when itis idle or has com- pleted transmission of the previous character. The TxADY conditions are then asserted again. Thus, one full character time of buffering is provided. {n the asynchronous mode, the transmitter au- tomatically sends a start bit folowed by the pro- grammed number of data bits, the least significant bit being sent first. It then appends an optional odd or even parity bit and the pro- grammed number of stop bits. If, following transmission of the data bits, a new character is not available in the transmit holding register, the TxD output remains in the marking (High} condition and the TxEMT/DSCHG output and its corresponding status bit are asserted. Transmission resumes when the CPU loads a new character into the holding register. The transmitter can be forced to output a continu- ous Low (BREAK) candition by setting the send break command bit (CR3) High. In the synchronous mode, when the 68661 is initially conditioned to transmit, the TxD output remains High and the TxRDY condition is as- serted until the first character to be transmitted (usually a SYN character) is loaded by the CPU. Subsequentto this, acontinuous stream of characters is transmitted, No extra bits (oth- er than parity, if commanded) are generated by the EPCI unless the CPU fails to send a new character to the EPCI by the time the transmit- ter has completed sending the previous char- acter. Since synchronous communication does not allow gaps between characters, the EPCI asserts TxEMT and automatically fills the gap by transmitting SN1s, SYN1-SYN2 doublets, or OLE-SYN1 doubles, depending on the state of MR16 and MR17. Normal transmission of the message resumes when a new characteris available in the transmit data holding register. Hf the send DLE bitin the commands register is true, the DLE character is automatically trans- April 4, 1986 mitted prior to transmission of the message character in the THR. EPCI PROGRAMMING Prior to initiating data communications, the 68661 operational mode must be programmed by performing write operations to the mode and command registers. In addition, if synchronous operation is programmed, the appropriate SYN/DLE registers must be loaded. The EPC| canbe recontiguredatany time during program execution. A flawchart of the initialization pro- cess appears in Figure 1. The internal registers of the EPCl are accessed by applying specific signals to the TE, R/W, Al and AOinputs. The conditions necessary to.ad- dress each register are shown in Table 4. The SYN1, SYN2, and DLE registers are ac- cessed by performing write operations with the conditions Al = 0, AQ =1,and R/W=1. The first operation loads the SYN1 register. The next loads the DLE register. Reading or loading the mode registers is done ina similar manner. The first write (ar read} operation addresses mode register 1, and a subsequent operation ad- dresses mode register 2. If more than the re- quired number of accesses are made, the internal sequencer recycles to point at the first register. The pointers are reset to SYN 1 regis- ter and mode register 1 by a RESET input or by performing a read command register opera- tion, but are unaffected by any other read or write operation. The 68661 register tormats are summarized in Tables 5,6, 7and8. Made registers 1 and 2 de- fine the general operational characteristics of the EPCI, while the command register controls the operation within this basic framework. The EPCt indicates its status in the status register. These registers are cleared when a RESET in- put is applied. Mode Register 1 (MR1) Table 5 illustrates mode register 1. Bits MR11 and MRi0 select the cammunication format and baud rate multiplier. 00 specifies synchra- nous format. However, the multiplier in asynch- ronous format applies only if the external clock input option is selected by MR24 or MR25. MR13 and MR12 selecta character length of 5, 6, 7or8bits. The character length does notinc- 53 clude the parity bit, if programmed, and does not include the start and stop bits in asynchro- nous made. MR14 controls parity generation. if enabled, a parity bit is added to the transmitted character and the receiver performs a parity check on in- coming data. MR15 selects odd or even parity when parity is enabled by MR14. In asynchro- nous made, MR17 and MR (16 select character framing of 1, 1.5, or 2 stop bits. (If 2X baud rate is programmed, 1.5 stop bits defaults to 1 stop bits on transmit.) In synchronous mode, MA17 controls the number of SYN characters used to establish synchronization and for character fill when the transmitter is idle. SYN1 aloneis used if MR17 = 1, and SYNi-SYN2 is used when MR17 =O. lf the transparent mode is specified by MR16, DLE-SYN1 is used for character fill and SYN detect, but the normal synchroniza- tion sequence is used to establish character sync. When transmitting, a DLE character in the transmit holding register will cause a sec- ond OLE character to be transmitted. This DLE stuffing eliminates the software DLE compare and stuff on each transparent mode data char- acter. Ifthe send DLE cammand (CR3) is active when a DLE is loaded into THR, only one addi- tional DLE will be transmitted. Also, DLE strip- ping and DLE detect (with MR14 = 0) are enabled. The bits in the mode register affecting character assembly and disassembly (MR12-MR16} can be changed dynamically (auring active receive/ transmitoperation). The character mode regis- ter affects both the transmitter and receiver; therefore in synchronous mode, changes should be made only in half-duplex mode (RxEN = 1 or TxEN = 1, but not bath simulta- neously = 1). Inasynchronous mode, character changes should be made when RxEN and TxEN =O orwhen TxEN = 1 and the transmitter is marking in half-duplex mode (RxEN = 0). To effect assembly/disassembly of the next re- ceived/ransmitted character, MR12 - 15 must be changed within n bit times of the active going state of RxADY/TXADY, Transparent and non-transparent mode changes {MR16) must occur within n-1 bit times of the character to be attected when the receiver or transmitter is ac- trve. (n smalier of the new and old character lengths.)Philips CamponentsSignetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 Table 4. 68661 Register Addressing CE A, Ay Riw FUNCTION 1 x xX X 3-Stale data bus 0 9 0 0 Read receive holding register 0 9 0 1 Write transmit holding register 0 9 1 0 Read status register 0 0 1 1 Write SYN1/SYN2/DLE registers 0 1 0 0 Read mode register 1/2 0 1 0 1 Write mode register 1/2 0 1 1 8 Read command register 0 1 1 1 Write command register INITIAL RESET LOA MODE REGISTER 1 LOAD MODE REGISTER 2 D NOTE: Mode Register 1 must be written before 2 can be written. Mode Register 2 need nat be programmed if external clocks are used. NOTE: SYN1 Register must be written betore SYN2 can be written, and SYN2 befora DLE can be written. | LOAD | COMMAND REGISTER | r-- Figure 1. 68661 Initialization Flowchart | OPERATE | Y DISABLE RCVA AND XMTR SF April 4, 1986 54Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications . SCN2661/SCN68661 interface (EPCI) Table 5. Mode Register 1 (MR1) MR17 | MR16 MR15 MR14 MR13 MR12 MR11 MR10 Sync/Asyne Parity Type | Parity Controt Character Length Mode and Baud Rate Factor Asyne: Stop bit length 00 = invalid 0 = Odd 0 = Disabled 00 = 5 bits 00 = Synchronous 1X rate 01= 1 stop bit 1 = Even 1 = Enabled 01 = 6 bits 01 = Asynchronous 1X rate 10 = 1 1/2 stop bits 10 = 7 bits 10 = Asynchronous 16X rate 11 = 2 stop bits 11 =8 bits 11 = Asynchronous 64X rate Sync: Syne: Number of Transparency SYN char control 0 = Double SYN | 0 = Normal 1 = Single SYN 1 = Transparent NOTE: Baud rate factor in asynchronous applies only if externat clock is selected. Factor is 16X if internal clock is selected. Mode must be selected (MR11, MR10) in any case. Table 6. Mode Register 2 (MR2) MR27 - MR24 MR23 - MR20 . . . . Baud Rate Txe RxC Ping Pin 25 Tx RxC Pin 9 Pin 25 Mode Selection 0000 E E Tx RxC 1000 E E XSYNC" RXC/TxC syne 0001 E I Tx 1X 1001 E 1 Tx BKDET async 001d | E 1X Rx 1010 l E XSYNC* RxC sync. 0011 { | 1X 1X 1011 ! | 1X BKDET async | See baud rates 0100 E E Tx RxC 1100 E E XSYNC* -RxC/TxC sync in Table 1. 0101 E | Txt 16X 1104 E | TXC BKDET async 0110 I E 16X AxC 1110 | E XSYNC* Rx syne o1n1 I I 16X 16X iit I | 16X BKDET async NOTES: * When pin Gis programmed as XSYNC input, SYN1, SYN1-SYN2, and DLE-SYN1 detection is disabled. E = External clock | = Internal clock (BRG) 1X and 16X are clock outputs. Table 7. Command Register (CR} CR? | CRE CRS CH4 CR3 CR2 CRi CRO Receive . Transmit Operating Mode Request Reset Error Sync/Async Control Data Terminal Control {RKEN) y (TxEN) 00 = Normal operation O= Force RTS | 0 = Normal Asyne: 0 = Disable 0 = Force DTR | 0 = Disable 01 = Async: OutputHigh | 1= Reseterror | Force Break 1 = Enable output High | 1 = Enable Automatic one clock flags in 0 = Normal 1 = Force DTR Echo mode time after status reg. 1 = Force break output Low Sync: SYN and/or DLE TxSR (FE,OE,PE/ stripping mode senalization DLE detect.) : 10 = Local loopback 1 = Force RTS Syne Not applicable 11 = Remote loopback output Low Send DLE in 0 = Normal 1 = Send DLE April 4, 1986 55Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 Table 8. Status Register (SR) SR7 SR6 SRS SR4 SR3 SR2 SR1 SRo Data Set Data Carrier FE/SYN PE/DLE TxEMT Ready Detect Detect Overrun Detect DSCHG RxRDY TxRDY 0 = DSR input 0 = DCD input Asyne: 0 = Normal Async: 0 = Narmal 0 = Receive 0 = Transmit is High is High 0 = Normal 1 = Overrun 0 = Normal 1 = Change in holding holding 1 = DSR input 1 = DCD input 1 = Framing error 1 = Parity error DSR or register register is Low is Low error DCD, or emply busy transmit 1 = Receive 1 = Transmit Syne: Syne: shift holding holding 0 = Normal 0 = Normai register is register register 1= SYN 1 = Parity error empty has data empty detected or DLE received Mode Register 2 (MR2) Table 6 illustrates mode register 2. MR23, MR22, MR21 and MR20 control the trequency of the internal baud rate generator (BRG). Six- teenrates are selectable for each EPCl version {-1,-2,-3). Versions 1 and 2 specify a 4.9152MHz TTL input at BRCLK (pin 20); ver- sion 3 specifies a 5.0688MHz input which is identical to the Signetics 2651. MR23 - 20 are don't cares if external clocks are selected (MR25 MR24 = 0). The individual rates are given in Table 1. MR24 MR27 select the receive and transmit clock source (either the BRG or an external in- put) and the function at pins 9 and 25. Refer to Table 6. Command Register (CR) Table 7 illustrates the command register. Bits CRO (TxEN)} and CR2(RxEN) enable ordisable the transmitter and receiver respectively. A 0 to1 transition of CR2 forces start bit search (async made} or hunt mode (sync mode) an the second AxCT rising edge. Disabling the receiver causes RxRDY to go High (inactive). {f the transmitter is disabled, it will complete the transmission of the character in the transmit shift register (if any) prior to terminating opera- tion. The TxD output will then remain in the marking state (High) while TXRDY and TxXEMT will go High (inactive}. H the receiver is dis- abled, it will terminate operation immediately. Any character being assembled will be ne- glected. A 0-to-1 transition of CR2 willinitiate start bit search (async) or hunt mode (sync). Bits CRt (DTR) and CRS (ATS) control the DTR and ATS outputs, Data at the outputs are the logical complement of the register data. in asynchronous mode, setting CR3 will force and hold the TxD output Low (spacing condi- tion) at the end of the current transmitted char- acter. Normal operation resumes when CR3is cleared. The TxD line will go High for at least one bit time before beginning transmission of the next character in the transmit data holding register. In synchronous mode, setting CR3 causes the transmission of the DLE register April 4, 1986 contents prior to sending the character in the transmit data holding register. Since this is a one time command, CR3 does not have to be reset by software. CR3 should be setwhen en- tering and exiting transparent mode and for alt DLE-non-DLE character sequences. Setting CR4 causes the error flags in the status register (SA3, SR4, and SRS) to be cleared; this is aone time command. There is no inter- nal latch for this bit. When CRS (RTS) is set, the RTS pin is forced Low. A 1-to-0 transition of CR5 will cause RTS to go High (inactive} one TxC time after the last serial bithas been transmitted. Ifa 1to0 tran- sition of CR5 occurs while data is being trans- mitted, RTS will remain Low (active) until both the THR and the transmit shift register are empty and then go High (inactive) one TxC time later. The EPCl can operate in one of four submodes within each major mode (synchronous or asynchronous). The operational sub-mode is determined by CR7 and CR6. CR7-CR6=00 is the normal mode, with the transmitter and re- ceive operating independently in accordance with the mode and status register instructions. Inasynchronaus mode, CR7-CR6 =01 places the EPCI in the automatic echo mode. Glocked, regenerated received data are auto- matically directed to the TxD line while normal receiver operation continues. The receiver must be enabled (CR2 = 1), but the transmitter need not be enabled. CPU to receiver commu- nication continues normally, but the CPU to transmitter link is disabled. Only the first char- acter of a break condition is echoed. The TxD output will go High until the next valid start is detected. The following conditions are true while in automatic echo mode: 1. Data assembled by the receiver are auto- matically placed in the transmit holding register and retransmitted by the transmit- ter on the TxD output. 2. The transmitter is clocked by the receive clack. 56 3. TxADY output = 4. 4. The TxEMT/DSCHG pin will reflect only the data set change condition. 5. The TxEN command (CAO) is ignored. in synchronous mode, CR7 CRG = 01 places the EPC! in the automatic SYN/DLE stnpping mode. The exact action taken depends on the setting of bits MR17 and MR16: 1. In the non-transparent, single SYN mode (MR17 MR16 = 10), characters in the data stream matching SYNi are not transferred to the Receive Data Holding register (RHR). 2. Inthe non-transparent, double SYN mode (MR17 MR16 = 00), character in the data stream matching SYN1, or SYN2 if immediately preceded by SYN1, are not transferred the RHR. 3. In transparent mode (MR16 = 1), charac- ter in the data stream matching DLE, or SYN1 if immediately preceded by DLE, are not transferred to the RHR. However, only the first DLE of a DLE-DLE pair is stripped. Note thatautomatic stripping mode does not af- fect the setting of the DLE detect and SYN de- tect status bits (SR3 and SR5). Two diagnostic sub-modes can also be canfi- gured. In local loopback mode (CR7 - CRG = 10), the following loops are connected internally: 1. The transmitter output is connected to the receiver input. : 2. DTA is connected to DCD and RTS is connected to CTS. 3. The receiver is clocked by the transmit clock. 4. The DTR, RTS and TxD outputs are held High. 5. The CTS, DCD, DSR and RxD inputs are ignored.Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 Additional requirements to operate in the local loopback mode are that CRO (TXEN}, CR1 (DTR) and CRS (RTS) must be set to 1. CR2 (AxEN) is ignored by the EPCI. The second diagnostic mode is the remote loopback mode (CR7 CRG = 11). In this mode: 1. Data assembled-by the receiver are auto- matically placed in the transmit holding register and retransmitted by the transmit- ter on the TxD output. 2. The transmitter is clacked by the receiver clock. 3. No data are sent to the local CPU, but he error status conditions (PE, FE) are set. 4. The RxADY, TKRDY, and TxEMT/ DSCHE outputs are held High. 5. GRO (TxEN) is ignored. 6. All ather signals operate normally. Status Register The data contained in the status register (as shown in Table 8) indicates receiver and trans- mitter conditions and modem/data set status. SROis the transmitterready (TxRDY) status bit. It, and its corresponding output, are valid only when the transmitter is enabled. if equal to 0-, itindicates that the transmit data holding regis- fer has been loaded by the CPU and the data has not been transferred to the transmit regis- ter. If set equal to 1, itindicates that the holding register is ready to accept data from the CPU. This bitis initially setwhen the transmitter is en- abled by CRG, unless a character has previous- April 4, 1986 ly been loaded into the holding register. Itis not set when the autamatic echo or remote loop- back modes are programmed. When this bit is set, the TxRDY output pin is Low. In the auto- matic echo and remote loopback modes, the output is held High. SR1, the receiver ready (AxRDY) status bit, in- dicates the condition of the receive data holding register. If set, itindicates that a character has been loaded into the holding register from the receive shift register and is ready to be read by the CPU. If equal to zero, there is no new char- acter in the halding register. This bit is cleared when the CPU reads the receive data holding register or when the receiver is disabled by GR2. When set, the RxRDY output is Low. The TXEMT/DSCHG bit, SR2, when set, indi- cates either a change of state of the DSR or DCD inputs (when CR2 or CRO = 1) or that the transmit shift register has completed transmis- sian of a character and no new character has been loaded into the transmit data holding reg- ister. Nate thatin synchronous mode this bit will be set even though the appropriate fill charac- ter is transmitted. TxEMT wil not go active until _ atleast one character has been transmitted. It is cleared by loading the transmit data holding register. The DSCHG conditions is enabled when TxEN = 1 or RxEN = 1. Itis cleared when the status register is readby the CPU. Ifthe sta- tus register is read twice and SR21 while SRE and SR7 remain unchanged, then a TxEMT condition exists. When SR2 is set, the TXEMT/S DSCHG output is Low. SR3, when set, indicates a received parity error when parity is enabled by MR14._ In synchro- 57 nous transparent mode (MR16 = 1), with parity disabled, it indicates that a character matching DLE register was received and the present character is neither SYN2 or DLE. This bit is cleared when the next character following the above sequence is loaded into RHR, when the receiver is disabled, or by a reset error com- mand, CR4. The overrun error status bit, SR4, indicates that the previous character loaded into the receive holding register was not ready the CPU at the time of new received character was transferred into it. This bit is cleared when the receiver is disabled or by the reset error command, CR4. ln asynchronous mode, bit SRS signifies that the received character was not framed by a stop bit; Le., only the first stop bit is checked. if RHR = 0 when SRS = 1, a break condition is present. In synchronous non-transparent mode (MRi6 = 0), it indicates receipt of the SYN1 character in single SYN mode or the SYN1 SYNZ pair in double SYN mode. In synchronous transparent mode (MR16 = 1), this bit is set upon detection of the initial syn- chronizing characters (SYN or SYN1-SYN2} and, after synchronization has been achieved, when a DLE-SYN1 pairis received. The bit is reset when the receiver is disabled, when the reset error command is given in asynchronous mode, orwhen the status register is read by the CPU in the synchronous mode. SR6 and SA? reflect the conditions of the DCD and DSR inputs, respectively. A Low input sets its corresponding status bit, and a High input clears it.Philips CemponentsSignetics Data Communication Products Product Specification Enhanced programmable communications N N68661 interface (EPC!) SCN2661/SCN6866 Table 9. 68661 EPCI vs 2651 PCI FEATURE EPCI Pcl 1. MR2 BIT 6, 7 Control pins 9, 25 Not used 2. DLE detect -SR3 SR3 = 0 for OLE-DLE, DLE -SYN1 SR3 = 1 for DLE-DLE, DLE - SYN1 3. Reset of SR3, DLE detect Second character after DLE, or receiver dis- able, or CR4 = 1 Receiver disable, or CR4 = 1 4. Send DLE - CR3 One time command Reset via CR3 on next TxADY 5. DLE stuffing in transparent mode Automatic DLE stuffing when DLE is loaded except if CR3 = 1 None 6 SYN1 stripping in double sync non-trans- | All SYN1 First SYN1 of pair parent mode 7. Baud rate versions Three One 8. Terminate ASYNC transmission (drop RTS) Reset CRS in response to TxEMT changing from 1to 0 Reset CRG when TXEMT goes from 1 to 0. Then reset CR5 when TXEMT goes from 1tod 9. Break detect Pin 25 FE and null character 10. Stop bit searched One Two 11. External jam syne Pin No 12. Data bus timing Improved over 2651 _ 13. Data bus drivers Sink 2.2mA Sink 1.6mA Source 400,14 Source 1002A NOTES: * Internal BRG used for RxC. * Internal BRG used for TxC. AC LOAD CONDITIONS 2.24 +5V | 7502 2ko OUTPUT jj OUTPUT 150pF NOTES: Open-drain outputs. Te CL. = Load capacitance includes JIG and probe capacitance. T C_ = 5OpF April 4, 1986 58Philips ComponentsSignetics Data Communication Products Enhanced programmable communications interface (EPCI) Product Specification SCN2661/SCN68661 TIMING DIAGRAMS RESET Txt (OUTPUT) TRANSMIT 1 BIT TIME (1, #6, OR 64 CLOCK PERIODS) be (NPUT) Rxt (1X) READ AND WRITE CLOCK ke tgRH >re tBRL hee tapyHeee tal ] BRCLK, h A \ RESET Tx, RxC a 'RES bet. ig. G -_ > fae 1p RECEIVE rn os } pt tH ; _ ewrire) NAN D,-D BUS NOT BUS (READ) __ FLOATING VAUD DATA VALID FLOATING top | oF April 4, 1986 59Philips Components-Signetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 TIMING DIAGRAMS (Continued) TxRDY, TxEMT (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode]) Txt (1X) 17253354 ;545t 1,273 54 55417,253 14 755172 5,3 44 541 1,253 54 515 f TxD DATA 1 DATA 2 DATA 3 SYN DATA 4 | 1 T TxEN 1 | l I i vy | Lo SYNCHRONOUS MODE TE FOR WRITE OF THR ot] DATA 1 DATA 2 ly DATA 3 11,21;3 54 ,5),8 17,2;3154;5,86 1,213 .}415 a2 Tad DATA 1 DATA3 TxEN TROY d DATA2 | | | | | on ASYNCHRONOUS MODE ZC CE FOR i WRITE OF THR 4p DATA 1 DATA 2 DATA 3 NOTES: A = Start bit B = Stop bit 1 C = Stop bit 2 O = TxD marking candition TxEMT goes low at the beginning of the jast data bit, ov. if parity is enabled, at the baginning of the parity bit. DATA 4 DATA 4 April 4, 1986 60Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 TIMING DIAGRAMS (Continued) EXTERNAL SYNCHRONIZATION WITH XSYNC une | L les ~<_ I j fog = XSYNC SETUP TIME = 300ns ty = XSYNC HOLD TIME = ONE Axc XSYNC {oF QOOMOOOEC V CHARACTER ASSEMBLY BREAK DETECTION TIMING Rx CHARACTER = 5 81TS, NO PARITY RxC + 16 OR 64 | bot | pot | | po! 4 | | | | Rxd |} LOOK FOR START BIT = LOW (IF RxD IS HIGH, LOOK FOR HIGH TO LOW TRANSITION) l FALSE START BIT CHECK MADE (RxD LOW) |p ee MISSING STOP BIT DETECTED SET FE BIT* 1st DATA BIT. MISSING STOP BIT DETECTED, SET FE SIT. SAMPLED 0 > RHR, ACTIVATE AxRDY. SET BKDET PIN RxD INPUT RxSR UNTIL A MARK FO SPACE TRANSITION OCCURS. NOTE: * if the stop bit is present, the stad bit search will commence immediately. April 4, 1986 61Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 TIMING DIAGRAMS (Continued) RxRDY (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode) f Ac 47243 74 55515273 74,5 544253 14> 5447 2,5 54,551 72 1/314 ~S5 jt 7-243 14 7S 1 wi RxD SYN1 DATA 1 DATA 2 BATA 3 DATA 4 DATA 5 = | | | IGNORED 3 RxEN ! | | | { | | | & | | | = SYNDET 8 J STaTus BT | J | a | | | RxRDY | TE FoR a6 rao ly AY sy OY ul u READ READ READ RHR READ RHR READ RHR READ RHR STATUS STATUS (DATA 1) (DATA 2) (DATA 3) {DATA 3) f D ~} A112 1;3 14 1|5,;8;C Aji ,21;3 54,5, 8;C;3- ;Di Ayt121;3 14 ;5,8,6 Ayt 2,37 RxD | DATA 1 | | DATA 2 | DATA3 | | DATA 4 wu | | | a | | | T \ = 7 rxen | | | g | > ! 2 | FxRDY = L_ Lo d oS 2 > g OVERRUN STATUS BIT TE FOR A { ms READ Ay hy READ RHR READ RHR (DATA 1) (DATA 3) NOTES: A = Start bit B = Stop bit 1 C= Stop bit2 D = TxD marking condition Only one stop bit is detected April 4, 1986 62Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications interface (EPC) SCN2661/SCN68661 TYPICAL APPLICATIONS ASYNCHRONOUS INTERFACE TO CRT TERMINAL ADDRESS BUS ) ; CONTROL BUS } ( DATA BUS ? oc a rxo1 patoTTL | CONVERT Tp +>] (OPT) SCN2661/68651 L._ J ZY BAUD RATE CLOCK cR BACLK OSCILLATOR TERNAL ASYNCHRONOUS INTERFACE TO TELEPHONE LINES ( ADDRESS BUS ) 4 CONTROL BUS } ( DATA BUS } RxD TaD psa P< PHONE ASYNC LINE DTA MODEM INTERFACE serssens ore be Ws p-> neo p4 BRCLK BAUD RATE CLOCK ] OSCILLATOR TELEPHONE LINE April 4, 1986 63Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications N 1 interface (EPCI) SCN2661/SCN6866 TYPICAL APPLICATIONS (Continued) SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE ADDRESS BUS 4 4 CONTROL BUS | { DATA BUS. } Rud ft TxD _ SYNCHRONOUS TERMINAL OR SCN2661/68561 rat be PERIPHERAL xl DEVICE SYNCHRONOUS INTERFACE TO TELEPHONE LINES ADDRESS BUS ) ; CONTROL BUS ) | ( DATA BUS } RxD FxD PHONE UNE INTERFACE Rxt Txt SCN2661/68661 DCD D< MODEM crs RTS DSR pTR P_ | TELEPHONE LINE April 4, 1986 64