DATA SHEET O K I A S I C P R O D U C T S MSM38S Sea of Gates and MSM98S Customer Structured Arrays 0.8m Mixed 3-V/5-V July 2001 ------------------------------------------------------------------------------------------- CONTENTS Description ................................................................................................................................................................1 Features .....................................................................................................................................................................1 MSM38S/98S Family Listing ..................................................................................................................................2 Array Architecture ...................................................................................................................................................3 MSM98S000 CSA Layout Methodology .........................................................................................................3 Electrical Characteristics .........................................................................................................................................5 Macro Library .........................................................................................................................................................10 Macrocells for Driving Clock Trees .....................................................................................................................11 Output Driver Macrocells for Slew Rate Control ..............................................................................................12 Automatic Test Vector Generation ......................................................................................................................12 Design process ........................................................................................................................................................13 OKI Advanced Design Center CAD Tools .........................................................................................................14 Package Options .....................................................................................................................................................15 0 Oki Semiconductor MSM38S/MSM98S 0.8m Mixed 3-V/5-V Sea of Gates and Customer Structured Arrays DESCRIPTION OKI's 0.8m ASIC products, specially designed for mixed 3-V/5-V applications, are now available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MSM38S Series and the CSA-based MSM98S Series use a three-layer-metal process on 0.8m drawn (0.6m L-effective) CMOS technology. The semiconductor process is adapted from OKI's production-proven 16-Mbit DRAM manufacturing process. Ideal for low-power portable applications, the MSM38S/98S are constructed with separate power busses for internal core logic and configurable I/O functions. Altogether, the architecture provides maximum flexibility, meeting the needs of all 3-V, 5-V, and mixed 3-V/5-V signal requirements. The MSM38S SOG Series is available in seven sizes with up to 420 I/O pads and over 135,000 usable gates. SOG array sizes are designed to fit the most popular quad flat pack (QFP) packages, such as 100-, 136-, 160-, and 208-pin QFPs. MSM38S SOG-based designs are therefore ideal for pad-limited circuits that require rapid prototyping turnaround times. The MSM98S CSA Series is an all-mask-level superset of the SOG series, available in 29 sizes. The CSA offerings combine the SOG architecture's logic flexibility with the higher integration yielded by optimized diffusion for faster and more compact memory blocks. The MSM98S is ideal for core-limited applications or circuits with large and/or multiple memory functions. Customer modification to the structure of any of the 29 predefined masterslices, rather than creation of a new masterslice every time, improves the prototyping turnaround time over cell-based manufacturing techniques. Both product families are supported by OKI's proprietary MEMGEN tool which quickly and easily generates SOG memories (for the MSM38S) as well as optimized memories for the MSM98S Series. The families also feature floorplanning to control pre-layout timing, clock-skew management software that guarantees worst-case clock skew of 1 ns or less, and scan-path design techniques that support ATVG for fault coverage approaching 100%. FEATURES * 0.8m drawn three-layer metal CMOS * Mixed 3-V/5-V operation for low power and high speed * SOG and CSA architecture availability * Clock tree cells with 1.0-ns clock skew, worst-case (fan-out = 2000 at 70 MHz) * Usable density from 6.5k to 135k gates * I/Os may be VSS, 3 V, 5 V, VDD, CMOS, TTL, and 3state, with 2-mA to 48-mA drive * I/O level shifter cells, allowing any buffer (input, output, or bidirectional) to interface with 3 V or 5 V * Slew-rate-controlled outputs for low radiated noise * User-configurable single and multi-port memories * Specialized 3-V and 5-V macrocells, including phaselocked loop, and PCI cells * Floorplanning for front-end simulation and back-end layout controls * JTAG boundary scan and scan-path ATVG Oki Semiconductor 1 MSM38S/MSM98S ---------------------------------------------------------------------------- MSM38S/98S FAMILY LISTING CSA Part # MSM... SOG Part # MSM... I/O Pads Rows[1] Columns Raw Gates Usable Gates [2] 98S020x020 -- 80 44 148 6,512 4,689 98S023x023 -- 92 51 176 8,976 6,463 -- 38S0110 100 56 194 10,752 7,741 98S026x026 -- 104 59 200 11,800 8,496 98S029x029 -- 116 66 228 15,048 10,835 98S032x032 -- 128 74 252 18,648 13,427 -- 38S0210 136 79 270 21,172 15,244 98S035x035 -- 140 81 276 22,356 16,096 98S038x038 -- 152 89 304 27,056 19,480 -- 38S0300 160 94 322 30,080 21,658 98S041x041 -- 164 96 328 31,488 22,671 98S044x044 -- 176 104 356 37,024 25,917 98S047x047 -- 188 111 380 42,180 29,526 98S050x050 -- 200 119 408 48,552 33,986 98S053x053 -- 212 126 432 54,432 38,102 -- 38S0570 216 129 442 56,760 39,732 98S056x056 -- 224 134 456 61,104 42,162 98S059x059 -- 236 141 484 68,244 47,088 98S062x062 -- 248 149 508 75,692 51,471 98S065x065 -- 260 156 536 83,616 56,859 98S068x068 -- 272 164 560 91,840 62,451 -- 38S0980 280 169 580 97,344 66,194 98S071x071 -- 284 171 588 100,548 67,367 98S074x074 -- 296 179 612 109,548 72,302 98S077x077 -- 308 186 636 118,296 75,709 98S080x080 -- 320 194 664 128,816 82,442 98S083x083 -- 332 201 688 138,288 88,504 98S086x086 38S1500 344 209 716 149,644 95,772 98S089x089 -- 356 216 740 159,840 99,101 98S092x092 -- 368 224 768 172,032 103,219 98S095x095 -- 380 231 792 182,952 109,771 98S098x098 -- 392 239 816 195,024 117,014 98S101x101 -- 404 246 844 207,624 124,574 98S104x104 -- 416 254 868 220,472 132,283 -- 38S2250 420 256 880 224,256 134,554 [1] Row and column numbers are used to evaluate the number and size of mega macrocells that may be included into each array. For example, a 7,600-gate mega macrocell with a size and aspect ratio of 36 rows by 245 columns can be used on the MSM98S032x032 or any larger array base, but not on the MSM98S029x029. [2] Usable gate count is design dependent and varies based upon the number of fan-outs per net, internal busses, floor plan, RAM/ROM blocks, etc. 2 Oki Semiconductor --------------------------------------------------------------------------- MSM38S/MSM98S ARRAY ARCHITECTURE The primary components of a 0.8m MSM38S/98S circuit include: * * * * * * * I/O base cells Configurable I/O pads for VDD, VSS, or I/O (I/O in both 3V and 5V) VDD and VSS pads dedicated to wafer probing Separate power bus for output buffers Separate power bus for internal core logic and input buffers Core base cells containing N-channel and P-channel pairs, arranged in column of gates Isolated gate structure for reduced input capacitance and increased routing flexibility Each array has 16 dedicated corner pads for power and ground use during wafer probing, with four pads per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC) and output drive transistors (VDDO for 3 V and VSSO). I/O cells include level shifter Separate power bus for internal core logic Column of Gates Configurable I/O pads for VDD (3.3 V), VDD (5 V), VSS, I/O (3.3 V), or I/O (5 V) Core Area VDD = 3.3 or 5 V Four-transistor basic core cell VDD, VSS pads in each corner for wafer probing only VDDO (5 V) VDDO (3.3 V) VSSO Separate power bus over I/O cell for output buffers (VDDO (3.3 V), VDDO (5 V), VSSO) Figure 1. MSM38S/98S Array Architecture MSM98S000 CSA Layout Methodology The procedure to design, place, and route a CSA follows. 1. Select suitable base array frame from the available predefined sizes. To select an array size: - Identify the macrocell functions required and the minimum array size to hold the macrocell functions. Oki Semiconductor 3 MSM38S/MSM98S ---------------------------------------------------------------------------- - Add together all the area occupied by the required random logic and macrocells and select the optimum array. 2. Make a floor plan for the design's megacells. - OKI Design Center engineers verify the master slice and review simulation. - OKI Design Center engineers floorplan the array using OKI's proprietary floorplanner and customer performance specifications. - Using OKI CAD software, Design Center engineers remove the SOG transistors and replace them with diffused memory macrocells to the customer's specifications. Figure 2 shows an array base after placement of the optimized memory macrocells. Early mask high-density ROM Mega macrocell High-density RAM Multi-port RAM Figure 2. Optimized Memory Macrocell Floor Plan 3. Place and route logic into the array transistors. - OKI Design Center engineers use layout software and customer performance specifications to connect the random logic and optimized memory macrocells. Figure 3 marks the area in which placement and routing is performed with light shading. Figure 3. Random Logic Place and Route 4 Oki Semiconductor --------------------------------------------------------------------------- MSM38S/MSM98S ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Power supply voltage Symbol Conditions [1] Value Unit VDD Tj = 25 C VSS = 0 V -0.5 to +6.5 V -0.5 to VDD+0.5 V Input voltage VI Output voltage VO -0.5 to VDD+0.5 V Output current per I/O base cell IO -24 to + 24 mA Current per power PAD IPAD -90 to +90 mA Storage temperature Tstg -65 to +150 C - [1] Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the other sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (VSS = 0 V) Rated Value Parameter Symbol Min Typ Max Unit VDD 2.7 3.3 3.6 V 4.5 5.0 5.5 V Ta -40 +25 +85 C Input rise/fall time (normal type)[1][2] trA, tfA - 2 500 ns trB, tfB - 2 500 ns Input rise/fall time (Schmitt Trigger type)[3][4] trC, tfC - - 60 s trD, tfD - - 200 s Power supply voltage Operating temperature [1] [2] [3] [4] trA, tfA - TTL interface, normal input buffer. trB, tfB - CMOS interface, normal input buffer. trC, tfC - TTL interface, Schmitt Trigger input buffer. trD, tfD - CMOS interface, Schmitt Trigger input buffer. Operating Range (VSS = 0 V) Parameter Supply voltage Ambient temperature Oscillation frequency [1] Symbol Rated Value VDD 2.7 to 5.5 Unit V Ta -40 to +85 C fOSC 30 k to 50 M Hz [1] 50-MHz oscillator frequency for VDD is 4.5 ~ 5.5 V. Oki Semiconductor 5 MSM38S/MSM98S ---------------------------------------------------------------------------- DC Characteristics (VDD = 4.5 ~ 5.5 V, VSS = 0 V, Tj = -40 C ~ +85 C) Rated Value Parameter High-level input voltage Symbol Conditions Min Typ[1] Max Unit VIH TTL input 2.2 - VDD+0.5 V CMOS input 0.7xVDD - VDD+0.5 V TTL input -0.5 - 0.8 V CMOS input -0.5 - 0.3xVDD V - - 1.7 2.2 V Low-level input voltage VIL TTL-level Schmitt Trigger input threshold voltage Vt+ CMOS-level Schmitt Trigger input threshold voltage Vt- - 0.8 1.3 - V VT Vt+ - Vt- 0.2 0.4 - V Vt+ - - 3.1 0.76xVDD V Vt- - 0.24xVDD 1.8 - V VT Vt+ - Vt- 0.6 1.3 - V High-level output voltage VOH IOH = 2, 4, 8, 12, 16, 24 mA 3.7 - - V Low-level output voltage VOL IOL = 2, 4, 8, 12, 16, 24 mA - - 0.4 V IOL = 48 mA - - 0.5 V VIH = VDD - 0.01 10 A VIH = VDD(50 k pull down) 20 100 250 A High-level input current Low-level input current 3-state output leakage current IIH IIL VIL = VSS -10 -0.01 - A VIL = VSS (50 k pull up) -250 -100 -20 A VIL = VSS (3 k pull up) -5 -1.6 -0.5 mA VOH = VDD - 0.01 10 A IOZH IOZL Stand-by current[2] VOL = VSS -10 -0.01 - A VOL = VSS (50 k pull up) -250 -100 -20 A VOL = VSS (3 k pull up) -5 -1.6 -0.5 mA Output open VIH = VDD, VIL = VSS - 0.1 100 A IDDS [1] Typical condition is VDD = 5.0 V and Tj = 25 C for a typical process. [2] RAM/ROM should be in power-down mode. 6 Oki Semiconductor --------------------------------------------------------------------------- MSM38S/MSM98S DC Characteristics (VDD = 2.7 ~ 3.6 V, VSS = 0 V, Tj = -40 C ~ +85 C) Rated Value Symbol Conditions Min Typ[1] Max Unit High-level input voltage VIH CMOS input 0.7xVDD - VDD+0.5 V Low-level input voltage VIL CMOS input -0.5 - 0.3xVDD V CMOS-level Schmitt Trigger input threshold voltage Vt+ - - 2 0.76xVDD V Parameter Vt- - 0.24xVDD 1 - V VT Vt+ - Vt- 0.1xVDD 1 - V High-level output voltage VOH IOH = 1, 2, 4, 6, 8, 12 mA 2.2 - - V Low-level output voltage VOL IOL = 1, 2, 4, 6, 8, 12, 24 mA - - 0.4 V High-level input current IIH VIH = VDD - 0.01 1 A VIH = VDD (100 k pull down) 5 35 120 A VIL = VSS -1 -0.01 - A VIL = VSS (100 k pull up) -120 -35 -5 A VIL = VSS (6 k pull up) -2 -.55 -.120 mA Low-level input current 3-state output leakage current Stand-by current[2] IIL IOZH VOH = VDD - 0.01 1 A IOZL VOL = VSS -1 -0.01 - A VOL = VSS (100 k pull up) -120 -35 -5 A VOL = VSS (6 k pull up) -2 -.55 -.12 mA Output open VIH = VDD, VIL = VSS - 0.1 10 A IDDS [1] Typical condition is VDD = 3.3 V and Tj = 25 C for a typical process. [2] RAM/ROM should be in power-down mode. Oki Semiconductor 7 MSM38S/MSM98S ---------------------------------------------------------------------------- AC Characteristics (Core VDD = 5 V, VSS = 0 V, Tj = 25 C) Driving Type Conditions Rated Value[1][2] Unit Inverter 2-input NAND 2-input NOR 1x 1x 1x Input tr/tf = VDD /1.0 ns Output loading: FO = 1, L = 0 mm 0.20 0.25 0.28 ns Inverter 1x 2x 4x 0.47 0.35 0.22 ns 0.57 0.36 0.25 ns 0.69 0.53 0.51 ns 1.63 1.5 0.1[3] ns 500 MHz Parameter Internal gate delay times 2-input NAND 1x 2x 4x 2-input NOR Flip-flop (FD1A) Delay time: Set-up time: Hold time: 1x 2x 4x Input tr/tf = VDD /1.0 ns Output loading: FO = 2, L = 2 mm L = Metal length CLK to Q D to CLK CLK to D Toggle frequency of flip-flop FO = 1, L = 0 mm [1] For the purpose of this table, Rated Value is calculated as an average of the LH and HL delay times of each macro type. [2] Characteristics are quoted for a typical process. [3] thL (C,D) 0.1 ns. For I/O information, please refer to the AC Characteristics listed in the I/O table. AC Characteristics (Core VDD = 3.3 V, VSS = 0 V, Tj = 25 C) Driving Type Conditions Rated Value[1][2] Unit Inverter 2-input NAND 2-input NOR 1x 1x 1x Input tr/tf = VDD /1.0 ns Output loading: FO = 1, L = 0 mm 0.31 0.38 0.43 ns Inverter 1x 2x 4x 0.72 0.54 0.34 ns 0.87 0.55 0.38 ns 1.06 0.81 0.78 ns 2.66 2.29 0.15[3] ns 327 MHz Parameter Internal gate delay times 2-input NAND 2-input NOR Flip-flop (FD1A) Delay time: Set-up time: Hold time: Toggle frequency of flip-flop 1x 2x 4x 1x 2x 4x Input tr/tf = VDD /1.0 ns Output loading: FO = 2, L = 2 mm L = Metal length CLK to Q D to CLK CLK to D FO = 1, L = 0 mm [1] For the purpose of this table, Rated Value is calculated as an average of the LH and HL delay times of each macro type [2] Characteristics are quoted for a typical process. [3] thL (C,D) 0.15 ns. For I/O information, please refer to the AC Characteristics listed in the I/O table. 8 Oki Semiconductor --------------------------------------------------------------------------- MSM38S/MSM98S AC Characteristics (I/O VDD = 3.3 V or 5 V, VSS = 0 V, Tj = 25 C) Rated Values For VDD Conditon[1][2] Parameter Input buffer delay times [1] [2] [3] [4] [5] LH 5-V Ext 3-V Core HH 5-V Ext 5-V Core Unit [3] Conditions TTL input Input tr, tf = 0.2 ns/3.3 V FO = 2, L = 2 mm[4] - - - 0.82 ns Input tr, tf = 0.3 ns/5 V (LH, HH) tr, tf = 0.2 ns/3.3 V (LL, HL) FO = 2, L = 2 mm [4] 0.95 1.78 0.96 0.71 ns 4 mA 8 mA 16 mA 24 mA CL = 20 pF CL = 50 pF CL = 100 pF CL = 150 pF - - - - - - - - 2.90 3.86 3.87 3.69 1.39 1.86 2.03 2.51 ns 2 mA 4 mA 8 mA 12 mA CL = 20 pF CL = 50 pF CL = 100 pF CL = 150 pF 2.30 3.11 3.34 3.76 1.53 1.99 2.18 2.58 - - - - - - - - ns - - - - 3.38 (r) 3.59 (f) 2.66 (r) 3.04 (f) ns - - - - 9.20 (r) 7.86 (f) 3.60 (r) 3.62 (f) ns Push-pull for HH & LH (tin = 0.3 ns/5 V for LH & HL or Push-pull for LL tin = 0.2 ns/3.3 & HL V for LL & HL) Output buffer transition time (20-80%) HL 3-V Ext [3] 5-V Core Type CMOS input Output buffer delay times LL 3-V Ext 3-V Core Push-pull Push-pull with slew rate control CL = 150 pF for 24 mA buffer [5] Rated values are calculated as an average of the L-H and the H-L delay times for each macro type. Characteristics are quoted for a typical process. Parameters include level shifter cell where appropriate. For L = 2 mm, metal capacitance value of 0.304 pF has been chosen. Output rising and falling times are specified. Oki Semiconductor 9 MSM38S/MSM98S ---------------------------------------------------------------------------- MACRO LIBRARY Examples Basic macrocells Basic macrocells w/ Scan test NANDs NORs EXORs Latches Flip-flops Combinational logic Flip-flops Clock tree driver macrocells Macrocells Output macrocells MSI macrocells Mega macrocells 3-State outputs Push-pull outputs Open drain outputs Slew rate control outputs PCI Outputs Counters Shift registers RTC SCSI UART, 82Cxx PCI, PCMCIA Inputs Inputs w/pull-ups Inputs w/pull-downs I/O I/O w/pull-ups I/O w/pull-downs PCI I/O Macro Library Input macrofunctions Bi-directional macro-functions Macro-functions MSI macrofunctions Oscillator macrofunctions Memory macrocells 74199 74163 74151 Gated oscillators SOG RAMs (single- and multi-port) SOG ROMs Figure 4. OKI Macro Library 10 Oki Semiconductor Optimized diffused RAMs (Single- and multi-port) Optimized diffused ROMs --------------------------------------------------------------------------- MSM38S/MSM98S MACROCELLS FOR DRIVING CLOCK TREES OKI offers clock-tree drivers that guarantee a skew time of less than 1.0 ns. The advanced layout software uses dynamic driver placement and sub-trunk allocation to optimize the clock-tree implementation for a particular circuit. Features of the clock-tree driver-macrocells include: * * * * * * * * Clock skew 1.0 ns Automatic fan-out balancing Dynamic sub-trunk allocation Single clock tree driver logic symbol Single-level clock drivers Automatic branch length minimization Dynamic driver placement Up to four clock trunks The clock-skew management scheme is described in detail in the 0.8m Technology Clock Skew Management Application Note. Main Trunk Clocked Cell Sub Trunk Branch Clock Drivers Pad Input Buffer Clock Tree Driver Macrocell Figure 5. Clock Tree Structure Oki Semiconductor 11 MSM38S/MSM98S ---------------------------------------------------------------------------- OUTPUT DRIVER MACROCELLS FOR SLEW RATE CONTROL The slew-rate-control output driver macrocells reduce both simultaneous-switching noise and outputringing noise. The output transistors are split into two sets; first, one set of output transistors drive the output pads, then, after the output passes the threshold, the second set of output transistors drive the I/O pads. Figure 6 below shows output drivers configured for slew-rate control. All outputs with a drive of 8 mA or more are available with slew-rate control. First Set of Output Transistors Output Pad From Internal Node Switch Second Set of Output Transistors Figure 6. Slew Rate Control Output Buffer AUTOMATIC TEST VECTOR GENERATION OKI's 0.8m ASIC technologies support Automatic Test Vector Generation (ATVG) using full scan-path design techniques, including the following: * * * * * * * * * Increases fault coverage 95% Uses Synopsys Test Compiler Automatically inserts scan structures Connects scan chains Traces and reports scan chains Checks for rule violations Generates complete fault reports Allows multiple scan chains Supports vector compaction Combinational Logic A FD1AS Scan Data In D C SD SS B FD1AS Q QN D C SD SS Q QN Scan Select Figure 7. Full Scan Path Configuration 12 Oki Semiconductor Scan Data Out --------------------------------------------------------------------------- MSM38S/MSM98S DESIGN PROCESS Level 1 [4] VHDL/HDL Description Synopsys Timing Script (optional) Functional Test Vectors Synthesis CAE Front-End Floorplanning Gate-Level Simulation Level 2 Netlist Conversion (EDIF 200) Test Vector Conversion (Oki TPL [3]) Scan Insertion (Optional) TDC [2] CDC [1] Formal Verification Floorplanning Pre-Layout Simulation Level 2.5 [4] Layout / Timing Driven Layout (optional) [6] Static Timing Analysis Fault Simulation [5] Oki Interface Automatic Test Pattern Generation Verification (Design Rule Check/Formal Verification) Post-Layout Simulation Level 3 [4] Manufacturing Prototype Test Program Conversion [1] Oki's Circuit Data Check program (CDC) verifies logic design rules [2] Oki's Test Data Check program (TDC) verifies test vector rules [3] Oki's Test Pattern Language (TPL) [4] Alternate Customer-Oki design interfaces available in addition to standard level 2 [5] Standard design process includes fault simulation [6] Requires Synopsys timing script for Oki timing driven layout Figure 8. Oki's Design Process Oki Semiconductor 13 MSM38S/MSM98S ---------------------------------------------------------------------------- OKI ADVANCED DESIGN CENTER CAD TOOLS * Floorplanning for front-end simulation and back-end layout controls * Clock tree structures improve first-time silicon success by eliminating clock skew problems * Power calculation which predicts circuit power under simulation conditions to accurately model package requirements Design Kits Platform Operating System[1] Vendor Software/Revision [1] Description Cadence Sun(R)[2] Solaris Ambit Buildgates NC-VerilogTM Verilog XL VerifaultTM Design Synthesis Design Simulation Design Simulation Fault Simulation Synopsys Sun [2] Solaris Design Compiler Ultra + Tetramax/ATPG Primetime DFT Compiler/Test Compiler RTL Analyzer VCS Design synthesis ATPG Static Timing Analysis (STA) Test synthesis RTL check Design Simulation Model Technology Inc. (MTI) Sun [2] NT Solaris WinNT4.0 MTI-VHDL MTI-Verilog Design Simulation Design Simulation Exemplar Sun [2] NT Solaris WinNT4.0 Leonardo Spectrum Design Synthesis Oki Sun [2] Solaris Floorplanner Floor planning Verplex Sun [2] Solaris Tuxedo Formal verification Zycad Sun [2] Solaris XPLUS Fault Simulation Vendor [1] Contact Oki Application Engineering for current software versions. [2] Sun or Sun-compatible. 14 Oki Semiconductor --------------------------------------------------------------------------- MSM38S/MSM98S PACKAGE OPTIONS MSM38S/98S Package Menu Prod Name SOG I/O MSM98S MSM38S Pads [1] 44 60 64 80 QFP QFJ 100 128 160 208 240 304 44 68 TQFP 84 44 64 80 LQFP B01 80 B02 92 100 B03 104 B04 116 B05 128 136 140 0110 0210 B06 BGA 152 160 B08 164 B09 176 B10 188 B11 200 B12 212 216 B13 224 B14 236 B15 248 B16 260 B17 272 B07 0300 0570 PBGA 100 144 176 208 256 352 420 280 B18 284 B19 296 B20 308 B21 320 B22 332 B23 344 0980 344 B24 356 B25 368 B26 380 B27 392 B28 404 B29 416 1500 2250 Body Size (mm) Lead Pitch (mm) 420 9x10 15x19 14x14 14x20 14x20 28x28 28x28 28x28 32x32 40x40 17x17 24x24 29x29 10x10 10x10 12x12 14x14 20x20 24x24 28x28 27x27 35x35 35x35 1.27 1.27 1.27 Ball Count 0.8 1.0 0.8 0.8 0.65 0.8 0.65 0.5 0.5 0.5 1.27 1.27 1.27 0.8 0.5 0.5 0.5 0.5 0.5 0.5 256 352 420 Signal I/O 231 304 352 Power Balls 12 16 32 Ground Balls 13 32 36 [1] I/O Pads can be used for input, output, bi-directional, power, or ground. l = Available now; m = In development Oki Semiconductor 15 MSM38S/MSM98S ---------------------------------------------------------------------------- NOTES 16 Oki Semiconductor The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. Certain parts in this document may need governmental approval before they can be exported to certain countries. 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