MSM38S Sea of Gates and
MSM98S Customer Structured Arrays
0.8µm Mixed 3-V/5-V
July 2001
OKI ASIC PRODUCTS
D
ATA
S
HEET
0 Oki Semiconductor
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CONTENTS
Description ................................................................................................................................................................1
Features .....................................................................................................................................................................1
MSM38S/98S Family Listing ..................................................................................................................................2
Array Architecture ...................................................................................................................................................3
MSM98S000 CSA Layout Methodology .........................................................................................................3
Electrical Characteristics .........................................................................................................................................5
Macro Library .........................................................................................................................................................10
Macrocells for Driving Clock Trees .....................................................................................................................11
Output Driver Macrocells for Slew Rate Control ..............................................................................................12
Automatic Test Vector Generation ......................................................................................................................12
Design process ........................................................................................................................................................13
OKI Advanced Design Center CAD Tools .........................................................................................................14
Package Options .....................................................................................................................................................15
1Oki Semiconductor
MSM38S/MSM98S
0.8µm Mixed 3-V/5-V Sea of Gates and Customer Structured Arrays
DESCRIPTION
OKI’s 0.8µm ASIC products, specially designed for mixed 3-V/5-V applications, are now available in both
Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MSM38S
Series and the CSA-based MSM98S Series use a three-layer-metal process on 0.8µm drawn (0.6µm L-effec-
tive) CMOS technology. The semiconductor process is adapted from OKI’s production-proven 16-Mbit
DRAM manufacturing process.
Ideal for low-power portable applications, the MSM38S/98S are constructed with separate power busses
for internal core logic and configurable I/O functions. Altogether, the architecture provides maximum
flexibility, meeting the needs of all 3-V, 5-V, and mixed 3-V/5-V signal requirements.
The MSM38S SOG Series is available in seven sizes with up to 420 I/O pads and over 135,000 usable gates.
SOG array sizes are designed to fit the most popular quad flat pack (QFP) packages, such as 100-, 136-,
160-, and 208-pin QFPs. MSM38S SOG-based designs are therefore ideal for pad-limited circuits that
require rapid prototyping turnaround times.
The MSM98S CSA Series is an all-mask-level superset of the SOG series, available in 29 sizes. The CSA
offerings combine the SOG architecture’s logic flexibility with the higher integration yielded by opti-
mized diffusion for faster and more compact memory blocks. The MSM98S is ideal for core-limited appli-
cations or circuits with large and/or multiple memory functions. Customer modification to the structure
of any of the 29 predefined masterslices, rather than creation of a new masterslice every time, improves
the prototyping turnaround time over cell-based manufacturing techniques.
Both product families are supported by OKI’s proprietary MEMGEN tool which quickly and easily gen-
erates SOG memories (for the MSM38S) as well as optimized memories for the MSM98S Series. The fam-
ilies also feature floorplanning to control pre-layout timing, clock-skew management software that
guarantees worst-case clock skew of 1 ns or less, and scan-path design techniques that support ATVG for
fault coverage approaching 100%.
FEATURES
• 0.8µm drawn three-layer metal CMOS
• Mixed 3-V/5-V operation for low power and high
speed
• SOG and CSA architecture availability
• Clock tree cells with ≤ 1.0-ns clock skew, worst-case
(fan-out = 2000 at 70 MHz)
• Usable density from 6.5k to 135k gates
• I/Os may be VSS, 3 V, 5 V, VDD, CMOS, TTL, and 3-
state, with 2-mA to 48-mA drive
• I/O level shifter cells, allowing any buffer (input,
output, or bidirectional) to interface with 3 V or 5 V
• Slew-rate-controlled outputs for low radiated noise
• User-configurable single and multi-port memories
• Specialized 3-V and 5-V macrocells, including phase-
locked loop, and PCI cells
• Floorplanning for front-end simulation and back-end
layout controls
• JTAG boundary scan and scan-path ATVG
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MSM38S/98S FAMILY LISTING
CSA Part #
MSM... SOG Part #
MSM... I/O Pads Rows
[1]
[1]Row and column numbers are used to evaluate the number and size of mega macrocells that may be included into each array. For
example, a 7,600-gate mega macrocell with a size and aspect ratio of 36 rows by 245 columns can be used on the
MSM98S032x032 or any larger array base, but not on the MSM98S029x029.
Columns Raw Gates Usable Gates
[2]
[2] Usable gate count is design dependent and varies based upon the number of fan-outs per net, internal busses, floor plan,
RAM/ROM blocks, etc.
98S020x020 — 80 44 148 6,512 4,689
98S023x023 — 92 51 176 8,976 6,463
— 38S0110 100 56 194 10,752 7,741
98S026x026 — 104 59 200 11,800 8,496
98S029x029 — 116 66 228 15,048 10,835
98S032x032 — 128 74 252 18,648 13,427
— 38S0210 136 79 270 21,172 15,244
98S035x035 — 140 81 276 22,356 16,096
98S038x038 — 152 89 304 27,056 19,480
— 38S0300 160 94 322 30,080 21,658
98S041x041 — 164 96 328 31,488 22,671
98S044x044 — 176 104 356 37,024 25,917
98S047x047 — 188 111 380 42,180 29,526
98S050x050 — 200 119 408 48,552 33,986
98S053x053 — 212 126 432 54,432 38,102
— 38S0570 216 129 442 56,760 39,732
98S056x056 — 224 134 456 61,104 42,162
98S059x059 — 236 141 484 68,244 47,088
98S062x062 — 248 149 508 75,692 51,471
98S065x065 — 260 156 536 83,616 56,859
98S068x068 — 272 164 560 91,840 62,451
— 38S0980 280 169 580 97,344 66,194
98S071x071 — 284 171 588 100,548 67,367
98S074x074 — 296 179 612 109,548 72,302
98S077x077 — 308 186 636 118,296 75,709
98S080x080 — 320 194 664 128,816 82,442
98S083x083 — 332 201 688 138,288 88,504
98S086x086 38S1500 344 209 716 149,644 95,772
98S089x089 — 356 216 740 159,840 99,101
98S092x092 — 368 224 768 172,032 103,219
98S095x095 — 380 231 792 182,952 109,771
98S098x098 — 392 239 816 195,024 117,014
98S101x101 — 404 246 844 207,624 124,574
98S104x104 — 416 254 868 220,472 132,283
— 38S2250 420 256 880 224,256 134,554
3Oki Semiconductor
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MSM38S/MSM98S
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ARRAY ARCHITECTURE
The primary components of a 0.8µm MSM38S/98S circuit include:
• I/O base cells
• Configurable I/O pads for V
DD
, V
SS
, or I/O (I/O in both 3V and 5V)
•V
DD
and V
SS
pads dedicated to wafer probing
• Separate power bus for output buffers
• Separate power bus for internal core logic and input buffers
• Core base cells containing N-channel and P-channel pairs, arranged in column of gates
• Isolated gate structure for reduced input capacitance and increased routing flexibility
Each array has 16 dedicated corner pads for power and ground use during wafer probing, with four pads
per corner. The arrays also have separate power rings for the internal core functions (V
DDC
and V
SSC
) and
output drive transistors (V
DDO
for 3 V and V
SSO
).
Figure 1. MSM38S/98S Array Architecture
MSM98S000 CSA Layout Methodology
The procedure to design, place, and route a CSA follows.
1. Select suitable base array frame from the available predefined sizes. To select an array size:
- Identify the macrocell functions required and the minimum array size to hold the macrocell
functions.
Four-transistor
basic core cell
Separate power bus over
I/O cell for output buffers
(VDDO (3.3 V), VDDO (5 V), VSSO)
VDD, VSS pads in
each corner for
wafer probing only
Configurable I/O pads for
VDD (3.3 V), VDD (5 V), VSS,
I/O (3.3 V), or I/O (5 V)
Separate power bus
for internal core logic
I/O cells include
level shifter
VSSO
VDDO (3.3 V)
VDDO (5 V)
Column
of Gates
Core Area
VDD = 3.3 or 5 V
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- Add together all the area occupied by the required random logic and macrocells and select
the optimum array.
2. Make a floor plan for the design’s megacells.
- OKI Design Center engineers verify the master slice and review simulation.
- OKI Design Center engineers floorplan the array using OKI’s proprietary floorplanner and
customer performance specifications.
- Using OKI CAD software, Design Center engineers remove the SOG transistors and replace
them with diffused memory macrocells to the customer’s specifications.
Figure 2
shows an array base after placement of the optimized memory macrocells.
Figure 2. Optimized Memory Macrocell Floor Plan
3. Place and route logic into the array transistors.
- OKI Design Center engineers use layout software and customer performance specifications
to connect the random logic and optimized memory macrocells.
Figure 3
marks the area in which placement and routing is performed with light shading.
Figure 3. Random Logic Place and Route
Mega macrocell
Early mask high-density ROM
High-density RAM
Multi-port RAM
5Oki Semiconductor
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MSM38S/MSM98S
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Conditions
[1]
[1] Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as
detailed in the other sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Value Unit
Power supply voltage V
DD
T
j
= 25° C
V
SS
= 0 V -0.5 to +6.5 V
Input voltage V
I
-0.5 to V
DD
+0.5 V
Output voltage V
O
-0.5 to V
DD
+0.5 V
Output current per I/O base cell I
O
-24 to + 24 mA
Current per power PAD I
PAD
-90 to +90 mA
Storage temperature T
stg
– -65 to +150 ° C
Recommended Operating Conditions (V
SS
= 0 V)
Parameter Symbol
Rated Value
UnitMin Typ Max
Power supply voltage V
DD
2.7 3.3 3.6 V
4.5 5.0 5.5 V
Operating temperature T
a
-40 +25 +85 °C
Input rise/fall time (normal type)
[1][2]
[1] trA, tfA – TTL interface, normal input buffer.
[2] trB, tfB – CMOS interface, normal input buffer.
tr
A
, tf
A
– 2 500 ns
tr
B
, tf
B
– 2 500 ns
Input rise/fall time (Schmitt Trigger type)
[3][4]
[3] trC, tfC – TTL interface, Schmitt Trigger input buffer.
[4] trD, tfD – CMOS interface, Schmitt Trigger input buffer.
tr
C
, tf
C
– – 60 µs
tr
D
, tf
D
– – 200 µs
Operating Range (V
SS
= 0 V)
Parameter Symbol Rated Value Unit
Supply voltage V
DD
2.7 to 5.5 V
Ambient temperature T
a
-40 to +85 ° C
Oscillation frequency
[1]
[1] 50-MHz oscillator frequency for V
DD
is 4.5 ~ 5.5 V.
f
OSC
30 k to 50 M Hz
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DC Characteristics
(V
DD
= 4.5 ~ 5.5 V, V
SS
= 0 V, T
j
= -40° C ~ +85° C)
Parameter Symbol Conditions
Rated Value
UnitMin Typ
[1]
[1] Typical condition is VDD = 5.0 V and Tj = 25° C for a typical process.
Max
High-level input voltage V
IH
TTL input 2.2 – V
DD
+0.5 V
CMOS input 0.7xV
DD
–V
DD
+0.5 V
Low-level input voltage V
IL
TTL input -0.5 – 0.8 V
CMOS input -0.5 – 0.3xV
DD
V
TTL-level Schmitt Trigger input threshold
voltage V
t+
– – 1.7 2.2 V
V
t-
– 0.8 1.3 – V
∆
VT V
t+
- V
t-
0.2 0.4 – V
CMOS-level Schmitt Trigger input threshold
voltage V
t+
– – 3.1 0.76xV
DD
V
V
t-
– 0.24xV
DD
1.8 – V
∆
VT V
t+
- V
t-
0.6 1.3 – V
High-level output voltage V
OH
I
OH
= 2, 4, 8, 12, 16, 24 mA 3.7 – – V
Low-level output voltage V
OL
I
OL
= 2, 4, 8, 12, 16, 24 mA – – 0.4 V
I
OL
= 48 mA – – 0.5 V
High-level input current I
IH
V
IH
= V
DD
– 0.01 10 µA
V
IH
= V
DD
(50 k
Ω
pull down) 20 100 250 µA
Low-level input current I
IL
V
IL
= V
SS
-10 -0.01 – µA
V
IL
= V
SS
(50 k
Ω
pull up) -250 -100 -20 µA
V
IL
= V
SS
(3 k
Ω
pull up) -5 -1.6 -0.5 mA
3-state output leakage current IOZ
H
V
OH
= V
DD
– 0.01 10 µA
IOZ
L
V
OL
= V
SS
-10 -0.01 – µA
V
OL
= V
SS
(50 k
Ω
pull up) -250 -100 -20 µA
V
OL
= V
SS
(3 k
Ω
pull up) -5 -1.6 -0.5 mA
Stand-by current
[2]
[2] RAM/ROM should be in power-down mode.
I
DDS
Output open
V
IH
= V
DD
, V
IL
= V
SS
– 0.1 100 µA
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MSM38S/MSM98S
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DC Characteristics
(V
DD
= 2.7 ~ 3.6 V, V
SS
= 0 V, T
j
= -40° C ~ +85° C)
Parameter Symbol Conditions
Rated Value
UnitMin Typ
[1]
[1] Typical condition is VDD = 3.3 V and Tj = 25° C for a typical process.
Max
High-level input voltage VIH CMOS input 0.7xVDD –V
DD+0.5 V
Low-level input voltage VIL CMOS input -0.5 – 0.3xVDD V
CMOS-level Schmitt Trigger input threshold
voltage Vt+ – – 2 0.76xVDD V
Vt- – 0.24xVDD 1–V
∆VT Vt+ - Vt- 0.1xVDD 1–V
High-level output voltage VOH IOH = 1, 2, 4, 6, 8, 12 mA 2.2 – – V
Low-level output voltage VOL IOL = 1, 2, 4, 6, 8, 12, 24 mA – – 0.4 V
High-level input current IIH VIH = VDD – 0.01 1 µA
VIH = VDD
(100 kΩ pull down) 5 35 120 µA
Low-level input current IIL VIL = VSS -1 -0.01 – µA
VIL = VSS (100 kΩ pull up) -120 -35 -5 µA
VIL = VSS (6 kΩ pull up) -2 -.55 -.120 mA
3-state output leakage current IOZHVOH = VDD – 0.01 1 µA
IOZLVOL = VSS -1 -0.01 – µA
VOL = VSS (100 kΩ pull up) -120 -35 -5 µA
VOL = VSS (6 kΩ pull up) -2 -.55 -.12 mA
Stand-by current[2]
[2] RAM/ROM should be in power-down mode.
IDDS Output open
VIH = VDD, VIL = VSS – 0.1 10 µA
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AC Characteristics
(Core VDD = 5 V, VSS = 0 V, Tj = 25° C)
Parameter Driving Type Conditions Rated Value[1][2]
[1] For the purpose of this table, Rated Value is calculated as an average of the LH and HL delay times of each macro type.
[2] Characteristics are quoted for a typical process.
Unit
Internal gate delay
times Inverter
2-input NAND
2-input NOR
1x
1x
1x
Input tr/tf = VDD /1.0 ns
Output loading:
FO = 1, L = 0 mm
0.20
0.25
0.28 ns
Inverter 1x
2x
4x
Input tr/tf = VDD /1.0 ns
Output loading:
FO = 2, L = 2 mm
L = Metal length
0.47
0.35
0.22 ns
2-input NAND 1x
2x
4x
0.57
0.36
0.25 ns
2-input NOR 1x
2x
4x
0.69
0.53
0.51 ns
Flip-flop (FD1A) Delay time:
Set-up time:
Hold time:
CLK↑ to Q
D to CLK↑
CLK↑ to D
1.63
1.5
0.1[3]
[3] thL (C,D) ≥ 0.1 ns. For I/O information, please refer to the AC Characteristics listed in the I/O table.
ns
Toggle frequency of flip-flop FO = 1, L = 0 mm 500 MHz
AC Characteristics
(Core VDD = 3.3 V, VSS = 0 V, Tj = 25° C)
Parameter Driving Type Conditions Rated Value[1][2]
[1] For the purpose of this table, Rated Value is calculated as an average of the LH and HL delay times of each macro type
[2] Characteristics are quoted for a typical process.
Unit
Internal gate delay
times Inverter
2-input NAND
2-input NOR
1x
1x
1x
Input tr/tf = VDD /1.0 ns
Output loading:
FO = 1, L = 0 mm
0.31
0.38
0.43 ns
Inverter 1x
2x
4x
Input tr/tf = VDD /1.0 ns
Output loading:
FO = 2, L = 2 mm
L = Metal length
0.72
0.54
0.34 ns
2-input NAND 1x
2x
4x
0.87
0.55
0.38 ns
2-input NOR 1x
2x
4x
1.06
0.81
0.78 ns
Flip-flop (FD1A) Delay time:
Set-up time:
Hold time:
CLK↑ to Q
D to CLK↑
CLK↑ to D
2.66
2.29
0.15[3]
[3] thL (C,D) ≥ 0.15 ns. For I/O information, please refer to the AC Characteristics listed in the I/O table.
ns
Toggle frequency of flip-flop FO = 1, L = 0 mm 327 MHz
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AC Characteristics
(I/O VDD = 3.3 V or 5 V, VSS = 0 V, Tj = 25° C)
Parameter Type Conditions
Rated Values For VDD Conditon[1][2]
[1] Rated values are calculated as an average of the L-H and the H-L delay times for each macro type.
[2] Characteristics are quoted for a typical process.
Unit
LL
3-V Ext
3-V Core
HL
3-V Ext
[3] 5-V
Core
[3] Parameters include level shifter cell where appropriate.
LH
5-V Ext
[3]
3-V Core
HH
5-V Ext
5-V Core
Input buffer
delay times TTL input Input
tr, tf = 0.2 ns/3.3 V
FO = 2,
L = 2 mm[4]
– – – 0.82 ns
CMOS input Input
tr, tf = 0.3 ns/5 V
(LH, HH)
tr, tf = 0.2 ns/3.3 V
(LL, HL)
FO = 2,
L = 2 mm [4]
[4] For L = 2 mm, metal capacitance value of 0.304 pF has been chosen.
0.95 1.78 0.96 0.71 ns
Output buffer
delay times
(tin = 0.3 ns/5 V
for LH & HL or
tin = 0.2 ns/3.3
V for LL & HL)
Push-pull for HH
& LH 4 mA
8 mA
16 mA
24 mA
CL = 20 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
–
–
–
–
–
–
–
–
2.90
3.86
3.87
3.69
1.39
1.86
2.03
2.51
ns
Push-pull for LL
& HL 2 mA
4 mA
8 mA
12 mA
CL = 20 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
2.30
3.11
3.34
3.76
1.53
1.99
2.18
2.58
–
–
–
–
–
–
–
–
ns
Output buffer
transition time
(20-80%)
Push-pull CL = 150 pF for 24 mA
buffer [5]
[5] Output rising and falling times are specified.
–
––
–3.38 (r)
3.59 (f) 2.66 (r)
3.04 (f) ns
Push-pull with slew rate control –
––
–9.20 (r)
7.86 (f) 3.60 (r)
3.62 (f) ns
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MACRO LIBRARY
Figure 4. OKI Macro Library
Macro Library
Macrocells
Basic macrocells
Basic macrocells
w/ Scan test
Clock tree driver
macrocells
Output macrocells
MSI macrocells
Mega macrocells
Input macro-
functions
Bi-directional
macro-functions
MSI macro-
functions
Oscillator macro-
functions
Macro-functions
Examples
NANDs
NORs
EXORs
Flip-flops
3-State outputs
Push-pull outputs
Counters
Shift registers
RTC
SCSI
Inputs
Inputs w/pull-ups
74199
74163
Gated oscillators
Latches
Flip-flops
Combinational logic
Open drain outputs
Slew rate control outputs
PCI Outputs
Inputs w/pull-downs
I/O
I/O w/pull-ups I/O w/pull-downs
PCI I/O
74151
SOG RAMs
(single- and
multi-port)
SOG ROMs
UART, 82Cxx
PCI, PCMCIA
Memory
macrocells
Optimized diffused RAMs
(Single- and multi-port)
Optimized diffused ROMs
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MACROCELLS FOR DRIVING CLOCK TREES
OKI offers clock-tree drivers that guarantee a skew time of less than 1.0 ns. The advanced layout software
uses dynamic driver placement and sub-trunk allocation to optimize the clock-tree implementation for a
particular circuit. Features of the clock-tree driver-macrocells include:
• Clock skew ≤ 1.0 ns
• Automatic fan-out balancing
• Dynamic sub-trunk allocation
• Single clock tree driver logic symbol
• Single-level clock drivers
• Automatic branch length minimization
• Dynamic driver placement
• Up to four clock trunks
The clock-skew management scheme is described in detail in the 0.8µm Technology Clock Skew Management
Application Note.
Figure 5. Clock Tree Structure
Clock Tree
Driver Macrocell
Clock Drivers
Sub Trunk
Clocked Cell
Input BufferPad
Branch
Main Trunk
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OUTPUT DRIVER MACROCELLS FOR SLEW RATE CONTROL
The slew-rate-control output driver macrocells reduce both simultaneous-switching noise and output-
ringing noise. The output transistors are split into two sets; first, one set of output transistors drive the
output pads, then, after the output passes the threshold, the second set of output transistors drive the I/O
pads.
Figure 6 below shows output drivers configured for slew-rate control. All outputs with a drive of 8 mA or
more are available with slew-rate control.
Figure 6. Slew Rate Control Output Buffer
AUTOMATIC TEST VECTOR GENERATION
OKI’s 0.8µm ASIC technologies support Automatic Test Vector Generation (ATVG) using full scan-path
design techniques, including the following:
• Increases fault coverage ≥ 95%
• Uses Synopsys Test Compiler
• Automatically inserts scan structures
• Connects scan chains
• Traces and reports scan chains
• Checks for rule violations
• Generates complete fault reports
• Allows multiple scan chains
• Supports vector compaction
Figure 7. Full Scan Path Configuration
Switch
Output Pad
Second Set of
Output Transistors
First Set of
Output Transistors
From Internal Node
Scan Data In
Scan Select
D
C
SD
SS
Q
QN
D
C
SD
SS
A B
Combinational Logic
FD1AS FD1AS
Scan Data OutQ
QN
13Oki Semiconductor
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DESIGN PROCESS
Floorplanning
Scan Insertion (Optional)
CDC [1]
Functional Test Vectors
VHDL/HDL Description
Test Vector Conversion
(Oki TPL [3])
Netlist Conversion
(EDIF 200)
TDC [2]
Pre-Layout Simulation
Layout / Timing Driven
Layout (optional) [6] Automatic Test
Pattern Generation
Static Timing Analysis
Post-Layout Simulation
Manufacturing
Prototype Test Program
Conversion
Level 1 [4]
Level 2
Level 2.5 [4]
Level 3 [4]
CAE Front-End
Oki Interface
[1] Oki’s Circuit Data Check program (CDC) verifies logic design rules
[2] Oki’s Test Data Check program (TDC) verifies test vector rules
[3] Oki’s Test Pattern Language (TPL)
[4] Alternate Customer-Oki design interfaces available in addition to standard level 2
[5] Standard design process includes fault simulation
[6] Requires Synopsys timing script for Oki timing driven layout
Gate-Level Simulation
Floorplanning
Synthesis
Fault Simulation [5]
Figure 8. Oki’s Design Process
Synopsys Timing Script
(optional)
Formal Verification
Verification (Design Rule
Check/Formal Verification)
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■ MSM38S/MSM98S ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
OKI ADVANCED DESIGN CENTER CAD TOOLS
• Floorplanning for front-end simulation and back-end layout controls
• Clock tree structures improve first-time silicon success by eliminating clock skew problems
• Power calculation which predicts circuit power under simulation conditions to accurately model
package requirements
Design Kits
Vendor Platform Operating System[1]
[1] Contact Oki Application Engineering for current software versions.
Vendor Software/Revision [1] Description
Cadence Sun®[2]
[2] Sun or Sun-compatible.
Solaris Ambit Buildgates
NC-Verilog™
Verilog XL
Verifault™
Design Synthesis
Design Simulation
Design Simulation
Fault Simulation
Synopsys Sun [2] Solaris Design Compiler Ultra +
Tetramax/ATPG
Primetime
DFT Compiler/Test Compiler
RTL Analyzer
VCS
Design synthesis
ATPG
Static Timing Analysis (STA)
Test synthesis
RTL check
Design Simulation
Model Technology
Inc. (MTI) Sun [2]
NT Solaris
WinNT4.0 MTI-VHDL
MTI-Verilog Design Simulation
Design Simulation
Exemplar Sun [2]
NT Solaris
WinNT4.0 Leonardo Spectrum Design Synthesis
Oki Sun [2] Solaris Floorplanner Floor planning
Verplex Sun [2] Solaris Tuxedo Formal verification
Zycad Sun [2] Solaris XPLUS Fault Simulation
15Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MSM38S/MSM98S ■
PACKAGE OPTIONS
MSM38S/98S Package Menu
Prod Name SOG I/O
Pads [1]
[1] I/O Pads can be used for input, output, bi-directional, power, or ground.
l = Available now; m = In development
QFP QFJ TQFP LQFP BGA PBGA
MSM98S MSM38S
44 60 64 80 100 128 160 208 240 304 44 68 84 44 64 80 100 144 176 208 256 352 420
B01 80 ❍❍●❍ ❍● ●●●
B02 92 ❍❍●❍ ❍❍ ●●●
0110 100 ●●●●● ●●●●●●●
B03 104 ❍❍●❍❍ ❍❍❍●●●●
B04 116 ❍❍● ❍ ❍❍❍●●●●
B05 128 ❍❍●❍❍ ●❍●●●●●
0210 136 ●●●●●● ●❍●●●●●●
B06 140 ❍❍●❍❍❍ ●❍❍●●●●❍
B07 152 ❍❍●❍❍● ❍❍❍ ●●●●
0300 160 ●❍● ●●● ●❍ ●●●●
B08 164 ❍ ● ❍●❍ ❍❍ ●●●●
B09 176 ●❍❍❍❍ ❍ ● ● ●❍
B10 188 ●❍❍●● ❍ ●●●❍
B11 200 ●❍❍●● ❍❍ ●●●❍❍
B12 212 ●❍❍●●● ❍❍❍ ●●●❍● ●
0570 216 ● ●●●● ❍❍● ●●●●● ●
B13 224 ●❍❍●❍● ❍❍❍ ●●●●● ●
B14 236 ●❍❍●❍● ❍❍ ●●●● ●
B15 248 ●❍❍●❍●❍ ❍❍ ●●●● ● ●
B16 260 ●❍❍●●●❍ ●❍ ●●●● ● ●
B17 272 ●❍ ●●●● ❍❍ ●●●● ● ●
0980 280 ●●●● ❍❍ ●●●● ● ●
B18 284 ●●●● ❍❍ ●●● ● ●●
B19 296 ●●●● ●● ●●● ● ●●
B20 308 ●●●● ❍ ●●● ● ●●
B21 320 ❍●●● ● ●●● ● ●●
B22 332 ●●●● ● ●●● ● ●●
B23 344 ●●❍● ●●● ●●
1500 344 ●●● ●●● ●●
B24 356 ●●● ●●● ●●
B25 368 ●❍ ●●●
B26 380 ❍● ●● ●
B27 392 ❍●● ●● ●
B28 404 ●❍❍❍ ●● ●
B29 416 ❍❍●● ●● ●
2250 420 ●●●● ●● ●
Body Size (mm)
9x10 15x19 14x14 14x20 14x20 28x28 28x28 28x28 32x32 40x40 17x17 24x24 29x29 10x10 10x10 12x12 14x14 20x20 24x24 28x28 27x27 35x35 35x35
Lead Pitch (mm) 0.8 1.0 0.8 0.8 0.65 0.8 0.65 0.5 0.5 0.5 1.27 1.27 1.27 0.8 0.5 0.5 0.5 0.5 0.5 0.5 1.27 1.27 1.27
Ball Count 256 352 420
Signal I/O 231 304 352
Power Balls 12 16 32
Ground Balls 13 32 36
16 Oki Semiconductor
■ MSM38S/MSM98S ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
NOTES
Oki Semiconductor
The information contained herein can change without notice owing to product and/or technical improvements.
Please make sure before using the product that the information you are referring to is up-to-date.
The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action
and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in
the actual circuit and assembly designs.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect,
improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited
to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range.
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When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges,
including but not limited to operating voltage, power dissipation, and operating temperature.
The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office
automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for
use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application
where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such
applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including
life support and maintenance.
Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser
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own expense, for export to another country.
Copyright 2001 Oki Semiconductor
Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by
Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki
Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is
granted under any patents or patent rights of Oki.
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