ONET1151M
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11.35-Gbps Differential Modulator Driver with Output Waveform Shaping
Check for Samples: ONET1151M
1FEATURES • –40°C to 100°C Operation
• Surface Mount 3-mm x 3-mm 16-Pin RoHS
2• 1.5-VPP Single-Ended Output Voltage into a 50- Compliant QFN Package
ΩLoad
• Programmable Input Equalizer APPLICATIONS
• Output Pre-emphasis • SONET OC-192/SDH STM-64 Optical
• Adjustable Rise and Fall Times Transmitters
• Cross-Point Control • 10-Gigabit Ethernet Optical Transmitters
• Output Polarity Select • SFP+ and XFP Transceiver Modules
• 2-Wire Digital Interface
• Single 3.3-V Supply
DESCRIPTION
The ONET1151M is a high-speed, 3.3-V modulator driver designed to modulate a differentially driven Mach
Zehnder Modulator at data rates from 1 Gbps up to 11.35 Gbps.
The output amplitude can be controlled with an externally applied voltage. A 2-wire serial interface allows digital
control of the equalizer, output pre-emphasis, eye crossing point, rise and fall times, and the amplitude,
eliminating the need for external components. Output waveform control, in the form of pre-emphasis, cross-point
adjustment and rise and fall time adjustment are available to improve the optical eye mask margin.
An optional input equalizer with 10 dB of boost at 5 GHz can be used for equalization of up to 300-mm (12 in.) of
microstrip or stripline transmission line on FR4 printed circuit boards.
The modulator driver is characterized for operation from –40°C to 100°C case temperature and is available in a
small footprint 3-mm × 3-mm 16-pin RoHS compliant QFN package.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2I2C is a trademark of Philips Semiconductor Inc.
PRODUCTION DATA information is current as of publication date. Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Limiter
8 Bit Register
Crosspoint
Pre-emphasis
Equalizer
Settings
Crosspoint Adjust
Crosspoint Adjust
Power-On
Reset
Band-Gap, Analog References,
Power Supply Monitor and
Temperature Sensor
2-Wire Interface and Control Logic
SDA
SCK
DIS
DIN+
DIN-
RZTC
RZTC
AMP
8 Bit Register
8 Bit Register
8 Bit Register
8 Bit Register
8 Bit Register
Crosspoint Settings
ADC Settings
10 Bit Register
8 Bit Register
ADC Analog to
Digital
Conversion
DC Offset Cancellation
Adjustable
Boost
8 Bit Register
PSM
TS
SDA
SCK
DIS
VCC
10 kΩ10 kΩ
10 kΩ
Limiter Current
8 Bit Register
OUT+
OUT-
Mod.
Current
Generator
Equalizer Amplifier
100Ω
ABT Settings
VCC
Active Back
Termination
VCCD To Digital Circuitry
BGV
BGV
AMP
ONET1151M
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
BLOCK DIAGRAM
Figure 1 shows a simplified block diagram of the ONET1151M. The modulator driver consists of an equalizer, a
limiter, an output driver, power-on reset circuitry, a 2-wire serial interface including a control logic block, a
modulation current generator, and an analog reference block.
Figure 1. Simplified Block Diagram of the ONET1151M
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OUT+
OUT-
DIS
VCCD
SCK
SDA
AMP
GND
BGV
RZTC
VCC
VCC
DIN+
GND
DIN-
GND
2
1
3
4
11
12
10
9
65 7 8
1516 14 13
ONET
1151M
16 Pin QFN
ONET1151M
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SLLSED8 –OCTOBER 2012
PACKAGE
The ONET1151M is packaged in a small footprint 3-mm × 3-mm 16-pin RoHS compliant QFN package with a
lead pitch of 0.5 mm.
Figure 2. 16-Pin QFN Package, 3-mm x 3-mm (Top View)
Table 1. PIN DESCRIPTIONS
PIN TYPE DESCRIPTION
NAME NO.
Disables bias, modulation, and peaking currents when set to high state. Includes a 10-kΩor
DIS 1 Digital–in 40-kΩpullup resistor to VCC.
VCCD 2 Supply 3.3 V ± 10% supply voltage for the digital logic. Connect to VCC.
SCK 3 Digital–in 2-wire interface serial clock. Includes a 10-kΩor 40-kΩpullup resistor to VCC.
SDA 4 Digital–in/out 2-wire interface serial data input. Includes a 10-kΩor 40-kΩpullup resistor to VCC.
GND 5, 8, 12 Supply Circuit ground
DIN+ 6 Analog–in Non-inverted data input. On-chip differentially 100-Ωterminated to DIN–. Must be AC coupled.
DIN– 7 Analog–in Inverted data input. On-chip differentially 100-Ωterminated to DIN+. Must be AC coupled.
Connect external zero TC 28.7-kΩresistor to ground (GND). Used to generate a defined zero
RZTC 9 Analog TC reference current for internal DACs.
Buffered bandgap voltage with 1.16-V output. This is a replica of the bandgap voltage at
BGV 10 Analog–out RZTC.
Output amplitude control. Output amplitude can be adjusted by applying a voltage of 0 to 2.5
AMP 11 Analog–in V to this pin.
VCC 13, 16 Supply 3.3 V ± 10% supply voltage. Connect to VCCD.
CML–out
OUT- 14 Inverted data output
(current)
CML–out
OUT+ 15 Non-inverted data output
(current)
EP EP Thermal Exposed die pad (EP) must be grounded.
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) VALUE
PARAMETER UNIT
MIN MAX
VCC Supply voltage(2) –0.3 4 V
VDIS, VRZTC, VSCK, VSDA,
VBGV, VAMP, VDIN+, VDIN-, Voltage at DIS, RZTC, SCK, SDA, BGV, AMP, DIN+, DIN-, OUT+, OUT- (2) –0.3 4 V
VOUT+, VOUT-
IDIN-, IDIN+ Max. current at input pins 25 mA
IMOD+, IMOD– Max. current at output pins 35 mA
ESD rating at all pins except OUT+ and OUT- 2 kV (HBM)
ESD ESD rating at OUT+ and OUT- 1.5 kV (HBM)
TJ, max Maximum junction temperature 125 °C
TSTG Storage temperature range –65 150 °C
TCCase temperature -40 110 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) VALUE
PARAMETER CONDITION UNIT
MIN TYP MAX
VCC Supply voltage 2.97 3.3 3.63 V
VIH Digital input high voltage DIS, SCK, SDA 2 V
VIL Digital input low voltage DIS, SCK, SDA 0.8 V
1.16-V bandgap bias across resistor, E96, 1%
RRZTC Zero TC resistor value(1) 28.4 28.7 29 kΩ
accuracy
VIN Differential input voltage swing 150 1200 mVp-p
Amplitude control input voltage
VAMP 0 2.5 V
range
tR-IN Input rise time 20%–80% 30 55 ps
tF-IN Input fall time 20%–80% 30 55 ps
TCTemperature at thermal pad –40 100 °C
(1) Changing the value alters the DAC ranges and the current consumption.
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ONET1151M
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DC ELECTRICAL CHARACTERISTICS
over recommended operating conditions with 50-Ωoutput load, VOUT+ = 1.5 VPP and RRZTC = 28.7 kΩ, unless otherwise noted.
Typical operating condition is at 3.3 V and TA= 25°C VALUE
PARAMETER CONDITION UNIT
MIN TYP MAX
VCC Supply voltage 2.97 3.3 3.63 V
VCC = 3.47 V, PKENA = 1 100
IVCC Supply current mA
VCC = 3.63 V, PKENA = 1 105
VCC = 3.47 V, PKENA = 1 347
P Power Dissipation mW
VCC = 3.63 V, PKENA = 1 381
RIN Data input resistance Differential between DIN+ / DIN- 80 100 120 Ω
High level digital input
IIH SCK, SDA, DIS set to VCC (1) –10 10 µA
current
Low level digital input
IIL SCK, SDA, DIS set to GND (1) –500 500 µA
current
VCC-RST VCC reset threshold voltage VCC voltage level which triggers power-on reset 2.3 2.5 2.8 V
VCC reset threshold voltage
VCC-RSTHYS 100 mV
hysteresis
(1) Assured by simulation over process, supply and temperature variation
AC ELECTRICAL CHARACTERISTICS
over recommended operating conditions with 50-Ωoutput load, VOUT+ = 1.5 VPP and RRZTC = 28.7 kΩunless otherwise noted.
Typical operating condition is at VCC =3.3 V and TA= 25°C. VALUE
PARAMETER CONDITION UNIT
MIN TYP MAX
Data rate 11.35 Gbps
0.01 GHz < f < 5 GHz –15
Differential input return
SDD11 dB
gain 5 GHz < f < 11.1 GHz –8
Differential to common
SCD11 0.01 GHz < f < 11.1 GHz –15 dB
mode conversion gain
Minimum output
VO-MIN 50-Ωload, single-ended 300 mVPP
amplitude
Maximum output
VO-MAX 50-Ωload, single-ended, OASH0 = OASH1 = 0 1.4 VPP
amplitude
Output amplitude stability 50-Ωload, single-ended 200 mV
20% – 80%, tR-IN < 40 ps, 50-Ωload, single-ended,
tR-OUT Output rise time 26 36 ps
cross point = 50%. (1)
20% – 80%, tF-IN < 40 ps, 50-Ωload, single-ended,
tF-OUT Output fall time 26 36 ps
cross point = 50%. (1)
EQENA = 0, K28.5 pattern at 11.35 Gbps,
150-mVPP, 600-mVPP, 1200-mVPP differential input voltage, 5 10
single-ended output.
750 mVPP ≤VOUT ≤1.5 VPP
Intersymbol interference
ISI psp-p
EQENA = 1, K28.5 pattern at 11.35 Gbps 6
(2) with 12-inch transmission line at the input,
150-mVPP, 600-mVPP, 1200-mVPP input to transmission line,
single-ended output.
750 mVPP ≤VOUT ≤1.5 VPP.
RJ Random output jitter EQENA = 0 0.3 0.6 psRMS
High cross point control 50-Ωload, single-ended 75 %
range
Low cross point control 50-Ωload, single-ended 25 %
range
(1) 1010 pattern with PKENA = 1 and PEADJ (Register 2) set to 0x0F.
(2) Jitter at the eye crossing point.
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AC ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions with 50-Ωoutput load, VOUT+ = 1.5 VPP and RRZTC = 28.7 kΩunless otherwise noted.
Typical operating condition is at VCC =3.3 V and TA= 25°C. VALUE
PARAMETER CONDITION UNIT
MIN TYP MAX
50-Ωload, single-ended,
Cross point stability VIN = 180 mVPP, 600 mVPP and 1200 mVPP, ±5 pp
VOUT = 1.2 VPP
50-Ωload, single-ended,
Cross point stability vs. VIN = 180 mVPP, 600 mVPP and 1200 mVPP, –6 6 pp
input amplitude VOUT = 1.2 VPP
BWAMP Bandwidth of AMP input 2.5 kHz
TOFF Transmitter disable time Rising edge of DIS to VOUT+ ≤0.15 VPP (3) 0.05 5 µs
TON Disable negate time Falling edge of DIS to VOUT+ ≥1.2 VPP (3) 1 ms
TINIT1 Power-on to initialize Power-on to registers ready to be loaded(3) 1 10 ms
Register load STOP command to part ready to transmit valid
TINIT2 Initialize to transmit 2 ms
data(3)
(3) Assured by simulation over process, supply, and temperature variation.
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DETAILED DESCRIPTION
EQUALIZER
The data signal is applied to an input equalizer by means of the input signal pins DIN+ / DIN–, which provide on-
chip differential 100-Ωline-termination. The equalizer is enabled by setting EQENA to 1 (bit 1 of register 0).
Equalization of up to 300-mm (12 in.) of microstrip or stripline transmission line on FR4 printed circuit boards can
be achieved. The amount of equalization is digitally controlled by the 2-wire interface and control logic block and
is dependant on the register settings EQADJ[0..7] (register 3). The equalizer can be turned off and bypassed by
setting EQENA to 0. For details about the equalizer settings, see Table 16.
LIMITER
By limiting the output signal of the equalizer to a fixed value, the limiter removes any overshoot after the input
equalization and provides the input signal for the output driver. Adjustments to the limiter bias current and emitter
follower current can be made to trade off the rise and fall times and supply current. The limiter bias current is
adjusted through LIMCSGN (bit 7 of register 6) and LIMC[0..2] (bits 4, 5 and 6 of register 6). The emitter follower
current is adjusted through EFCSGN (bit 3 of register 6) and EFC[0..2] (bits 0, 1 and 2 of register 6). In addition,
the slope of the emitter follower current can be modified with the EFCRNG bit (bit 3 of register 5). Setting
EFCRNG to 1 results in a steeper slope.
HIGH-SPEED OUTPUT DRIVER
The modulation current is sunk from the common emitter node of the limiting output driver differential pair by
means of a modulation current generator, which is digitally controlled by the 2-wire serial interface. The collector
nodes of the output stages are connected to the output pins OUT+ and OUT–. The collectors have internal active
back termination. The outputs are optimized to drive a 50-Ωsingle-ended load and to obtain the maximum
single-ended output voltage of 1.5 VPP, AC coupling and inductive pullups to VCC are required. The active back
termination emitter follower current is adjusted through ABTSGN (bit 3 of register 7) and ABTEF[0..2] (bits 0, 1
and 2 of register 7). ABTUP (bit 7 of register 7) and ABTDWN (bit 6 of register 7) can control the active back
termination auxiliary buffer amplitude. Setting ABTUP to 1 increases the amplitude and setting ABTDWN to 1
decreases the amplitude. For most instances, these settings may be left in the default mode.
For waveform shaping, output pre-emphasis can be enabled by setting PKENA to 1 (bit 5 of register 0) and
adjusting the peaking height through PEADJ[0..3] (register 2).
In addition, the polarity of the output pins can be inverted by setting the output polarity switch bit, POL (bit 2 of
register 0) to 1.
MODULATION CURRENT GENERATOR
The modulation current generator provides the current for the current modulator described above. The
modulation current generator is controlled by applying an analog voltage in the range of 0 to 2.5 V to the AMP
pin, or it can be digitally controlled by the 2-wire interface block. The default method of control is through the
AMP pin. To digitally control the output amplitude set AMPCTRL (bit 0 of register 0) to 1.
An 8-bit wide control bus, AMP[0..7] (register 1), can be used to set the desired modulation current, and
therefore, the output voltage.
To decrease the output amplitude by approximately 18% set OARNG to 1 (bit 7 of register 5), to increase it by
approximately 30 mVPP set OASH0 (bit 5 of register 5) to 1, or to increase it by approximately 60 mVPP set
OASH1 (bit 6 of register 5) to 1.
The modulation current, and therefore the output signal, can be disabled by setting the DIS input pin to a high
level or by setting ENA to 0 (bit 7 of register 0).
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(ADCx 264)
Temperature (°C) 6
-
=
ONET1151M
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DC OFFSET CANCELATION AND CROSS POINT CONTROL
The ONET1151M has DC offset cancellation to compensate for internal offset voltages. The offset cancellation
can be disabled and the eye crossing point adjustment enabled by setting CPENA to 1 (bit 3 of register 0). The
crossing point can be moved toward the one level by setting CPSGN to 0 (bit 7 of register 4) and it can be
moved toward the zero level by setting CPSGN to 1. The percentage of shift depends upon the register settings
CPADJ[0..6] (register 4) and the high cross point adjustment range bits HICP[0..1] (bits 0 and 1 of register 5).
Setting HICP0 and HICP1 to 1 results in the maximum adjustment range but increases the supply current.
ANALOG REFERENCE AND TEMPERATURE SENSOR
The ONET1151M modulator driver is supplied by a single 3.3-V ± 10% supply voltage connected to the VCC and
VCCD pins. This voltage is referred to ground (GND) and can be monitored as a 10-bit unsigned digital word
through the 2-wire interface.
On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from which
all other internally required voltages and bias currents are derived.
An external zero temperature coefficient resistor must be connected from the RZTC pin of the device to ground.
This resistor is used to generate a precise, zero-TC current which is required as a reference current for the on-
chip DACs.
In order to minimize the module component count, the ONET1151M provides an on-chip temperature sensor.
The temperature can be monitored as a 10-bit unsigned digital word through the 2-wire interface.
POWER-ON RESET
The ONE1151M has power on reset circuitry which ensures that all registers are reset to zero during startup.
After the power-on to initialize time (tINIT1), the internal registers are ready to be loaded. The part is ready to
transmit data after the initialize to transmit time (tINIT2), assuming that the chip enable bit ENA is set to 1 and the
disable pin DIS is low. The DIS pin has an internal 10-kΩpullup resistor so the pin must be pulled low to enable
the outputs.
The ONET1151M can be disabled using either the ENA control register bit or the disable pin DIS. In both cases
the internal registers are not reset. After the disable pin DIS is set low and/or the enable bit ENA is set back to 1,
the part returns to its prior output settings.
ANALOG TO DIGITAL CONVERTER
The ONET1151M has an internal 10-bit analog to digital converter (ADC) that converts the analog monitors for
temperature and power supply voltage into a 10-bit unsigned digital word. The first eight most significant bits
(MSBs) are available in register 14 and the two least significant bits (LSBs) are available in register 15.
Depending on the accuracy required, eight bits or 10 bits can be read. However, due to the architecture of the 2-
wire interface, in order to read the two registers, two separate read commands have to be sent.
The ADC is enabled by default. To monitor a particular parameter, select the parameter with ADCSEL (bit 0 of
register 13). Table 2 lists the ADCSEL bits and the monitored parameters.
Table 2. ADC Selection Bits and
the Monitored Parameter
ADCSEL Monitored Parameter
0 Temperature
1 Supply voltage
If it is not desired to use the ADC to monitor the two parameters then the ADC can be disabled by setting
ADCDIS to 1 (bit 7 of register 13) and OSCDIS to 1 (bit 6 of register 13).
The digital word read from the ADC can be converted to its analog equivalent through the following formulas:
Temperature without a mid point calibration:
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2.25 (ADCx 1380)
Power supply voltage (V) 1409
´ +
=
( )
(T_cal (°C) 273) (ADCx 1362)
Temperature (°C) ADC _ cal 1362 273
+ ´ +
=+ -
ONET1151M
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Temperature with a mid point calibration:
Power supply voltage:
2-WIRE INTERFACE AND CONTROL LOGIC
The ONET1151M uses a 2-wire serial interface for digital control. For example, the two circuit inputs, SDA and
SCK, are respectively driven by the serial data and serial clock from a microprocessor. The SDA and SCK pins
have internal 10-kΩpullups to VCC. If a common interface is used to control multiple parts, the internal pullups
can be set to 40 kΩby setting HITERM to 1 (bit 6 of register 0). The internal pullup for the DIS pin is also set to
40 kΩwhen HITERM is set to 1.
The 2-wire interface allows write access to the internal memory map to modify control registers and read access
to read out the control signals. The ONET1151M is a slave device only which means that it cannot initiate a
transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The
master device provides the clock signal as well as the START and STOP commands. The protocol for a data
transmission is as follows:
1. START command
2. 7-bit slave address (0001000) followed by an eighth bit which is the data direction bit (R/W). A zero indicates
a WRITE and a 1 indicates a READ.
3. 8-bit register address
4. 8-bit register data word
5. STOP command
Regarding timing, the ONET1151M is I2C™ compatible. The typical timing is shown in Figure 3 and complete
data write and read transfers are shown in Figure 4. Parameters for Figure 3 are defined in Table 3.
Bus Idle: Both SDA and SCK lines remain HIGH.
Start Data Transfer: A START condition (S) is defined by a change in the state of the SDA line from HIGH to
LOW while the SCK line is HIGH. Each data transfer is initiated with a START condition.
Stop Data Transfer: A STOP condition (P) is defined by a change in the state of the SDA line from LOW to
HIGH while the SCK line is HIGH. Each data transfer is terminated with a STOP condition. However, if the
master still wishes to communicate on the bus, it can generate a repeated START condition and address another
slave without first generating a STOP condition.
Data Transfer: Only one data byte can be transferred between a START and a STOP condition. The receiver
acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obligated to generate an acknowledge bit. The
transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the
acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the
acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver does not
acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a
STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time
later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by
the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the
master generates the STOP condition.
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tBUF
tHDSTA
tR
tLOW
tHDDAT
tHIGH tF
tSUDAT tSUSTA
tHDSTA
tSUSTO
P S S P
SDA
SCK
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Figure 3. I2C Timing Diagram
Table 3. Timing Diagram Definitions
Parameter Symbol Min Max Unit
SCK clock frequency fSCK 400 kHz
Bus free time between STOP and START conditions tBUF 1.3 μs
Hold time after repeated START condition. After this period, the first clock pulse is tHDSTA 0.6 μs
generated
Low period of the SCK clock tLOW 1.3 μs
High period of the SCK clock tHIGH 0.6 μs
Setup time for a repeated START condition tSUSTA 0.6 μs
Data HOLD time tHDDAT 0μs
Data setup time tSUDAT 100 ns
Rise time of both SDA and SCK signals tR300 ns
Fall time of both SDA and SCK signals tF300 ns
Setup time for STOP condition tSUSTO 0.6 μs
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S Slave Address Wr A Register Address A Data Byte A P
1711 8 1 8 11
S Slave Address Wr A Register Address A Data Byte N P
1711 8 1 8 11
Write Sequence
Read Sequence
S
1
Slave Address Rd A
711
Legend
S Start Condition
Wr Write Bit (bit value = 0)
Rd Read Bit (bit value = 1)
A Acknowledge
N Not Acknowledge
P Stop Condition
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Figure 4. Programming Sequence
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REGISTER MAPPING
The register mapping for register addresses 0 (0x00) through 15 (0x0F) are listed in Table 4 through Table 15.
Table 16 describes the circuit functionality based on the register settings.
Table 4. Register 0 (0x00) Mapping – Control Settings
Register Address 0 (0x00)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ENA HITERM PKENA PKRNG CPENA POL EQENA AMPCTRL
Table 5. Register 1 (0x01) Mapping – Modulation Amplitude
Register Address 1 (0x01)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AMP7 AMP6 AMP5 AMP4 AMP3 AMP2 AMP1 AMP0
Table 6. Register 2 (0x02) Mapping – Pre-Emphasis Adjust
Register Address 2 (0x02)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - PEADJ3 PEADJ2 PEADJ1 PEADJ0
Table 7. Register 3 (0x03) Mapping – Equalizer Adjust
Register Address 3 (0x03)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EQADJ7 EQADJ6 EQADJ5 EQADJ4 EQADJ3 EQADJ2 EQADJ1 EQADJ0
Table 8. Register 4 (0x04) Mapping – Cross Point Adjust
Register Address 4 (0x04)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPSGN CPADJ6 CPADJ5 CPADJ4 CPADJ3 CPADJ2 CPADJ1 CPADJ0
Table 9. Register 5 (0x05) Mapping – CPA Settings
Register Address 5 (0x05)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OARNG OASH1 OASH0 - EFCRNG - HICP1 HICP0
Table 10. Register 6 (0x06) Mapping – Limiter Bias Current Adjust
Register Address 6 (0x06)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LIMCSGN LIMC2 LIMC1 LIMC0 EFCSGN EFC2 EFC1 EFC0
Table 11. Register 7 (0x07) Mapping – ABT – Emitter Follower Control
Register Address 7 (0x07)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ABTUP ABTDWN - - ABTSGN ABTEF2 ABTEF1 ABTEF0
Table 12. Register 8 (0x08) – Register 12 (0x0C) Mapping – Not Used
Register Address 8 (0x08)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
--------
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Table 13. Register 13 (0x0D) Mapping – ADC Settings
Register Address 13 (0x0D)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADCDIS OSCDIS - - - - - ADCSEL
Table 14. Register 14 (0x0E) Mapping – ADC Output (Read Only)
Register Address 14 (0x0E)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2
Table 15. Register 15 (0x0F) Mapping – ADC Output (Read Only)
Register Address 15 (0x0F)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - - - ADC1 ADC0
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ONET1151M
SLLSED8 –OCTOBER 2012
www.ti.com
Table 16. Register Functionality
Register Bit Symbol Function
Enable chip bit:
7 ENA 1 = Chip enabled
0 = Chip disabled
SCK, SDA and DIS pin input termination select bit:
6 HITERM 1 = 40 kΩselected
0 = 10 kΩselected
Output pre-emphasis enable bit:
5 PKENA 1 = Pre-emphasis enabled (height controlled by register 2)
0 = Pre-emphasis disabled
Output pre-emphasis range bit:
4 PKRNG 1 = High range enabled
0 = Default range
0Cross point adjust enable bit:
3 CPENA 1 = Cross point adjustment is enabled
0 = DC offset cancellation is enabled
Output polarity switch bit:
2 POL 1: Pin 15 = OUT- and pin 14 = OUT+
0: Pin 15 = OUT+ and pin 14 = OUT-
Input equalizer enable bit:
1 EQENA 1 = Equalizer enabled (boost controlled by register 3)
0 = Equalizer disabled
Amplitude control selection bit:
0 AMPCTRL 1 = Amplitude control through the serial interface
0 = Amplitude control by an analog voltage input at AMP pin
7 AMP7 Output amplitude setting
6 AMP6
5 AMP5 Output voltage: 300 mVPP to 1.5 VPP in 256 steps
4 AMP4
13 AMP3
2 AMP2
1 AMP1
0 AMP0
7 -
6 -
5 -
4 -
23 PEADJ3 Pre-emphasis adjustment
2 PEADJ2 0 = no pre-emphasis
1 PEADJ1 > 0 = pre-emphasis added to output signal
0 PEADJ0
7 EQADJ7 Equalizer adjustment setting
6 EQADJ6
5 EQADJ5
4 EQADJ4 Maximum equalization for 00000000
33 EQADJ3 Minimum equalization for 11111111
2 EQADJ2
1 EQADJ1
0 EQADJ0
14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ONET1151M
ONET1151M
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SLLSED8 –OCTOBER 2012
Table 16. Register Functionality (continued)
Register Bit Symbol Function
7 CPSGN Eye cross-point adjustment setting
6 CPADJ6 CPSGN = 0 (positive shift)
5 CPADJ5 Maximum shift for 1111111
4 CPADJ4 Minimum shift for 0000000
43 CPADJ3 CPSGN = 1 (negative shift)
2 CPADJ2 Maximum shift for 1111111
1 CPADJ1 Minimum shift for 0000000
0 CPADJ0 Output amplitude range bit:
7 OARNG 1 = Decrease output amplitude by approximately 18%
0 = Default range
Upper output amplitude shift bit:
6 OASH1 1 = Output amplitude shifted upwards by approximately 60 mVPP
0 = Default
Lower output amplitude shift bit:
5 OASH0 1 = Output amplitude shifted upwards by approximately 30 mVPP
0 = Default
54 - Emitter follower current slope selection:
3 EFCRNG 1 = Step slope
0 = Shallow slope
2 - High cross point adjustment range bits:
1 HICP1 00 = Default adjustment range
0 HICP0 11 = Maximum increase in the adjustment range
Limiter bias current sign bit:
7 LIMCSGN 1 = Decrease limiter bias current
0 = Increase limiter bias current
6 LIMC2 Limiter bias current selection bits:
5 LIMC1 000 = No change
4 LIMC0 111 = Maximum current change
6Emitter follower current sign bit:
3 EFCSGN 1 = Increase emitter follower current
0 = Decrease emitter follower current
2 EFC2 Emitter follower current selection bits:
1 EFC1 000 = No change
0 EFC0 111 = Maximum current change
Active back termination auxiliary buffer amplitude control bit:
7 ABTUP 1 = Increase amplitude
0 = Default setting
Active back termination auxiliary buffer amplitude control bit:
6 ABTDWN 1 = Decrease amplitude
0 = Default setting
5 -
74 - Active back termination emitter follower current sign bit:
3 ABTSGN 1 = Increase emitter follower current
0 = Decrease emitter follower current
2 ABTEF2 Active back termination emitter follower current selection bits:
1 ABTEF1 000 = No change
0 ABTEF0 111 = Maximum current change
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: ONET1151M
ONET1151M
SLLSED8 –OCTOBER 2012
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Table 16. Register Functionality (continued)
Register Bit Symbol Function
ADC disable bit:
7 ADCDIS 1 = ADC disabled
0 = ADC enabled
ADC oscillator bit:
6 OSCDIS 1 = Oscillator disabled
0 = Oscillator enabled
5 -
13 4 -
3 -
2 -
1 - ADC input selection bits:
0 ADCSEL 1 = Supply monitor
0 = Temperature sensor
7 ADC9 (MSB) Digital representation of the ADC input source (read only)
6 ADC8
5 ADC7
4 ADC6
14 3 ADC5
2 ADC4
1 ADC3
0 ADC2
7 -
6 -
5 -
4 -
15 3 -
2 -
1 ADC1 Digital representation of the ADC input source (read only)
0 ADC0 (LSB)
16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ONET1151M
VCC
DIN+
DIN- MZ MOD-
MZ MOD+
RZTC
DIN+
DIN- OUT±
OUT+
DIS
SCK
SDA
VCC
VCC
GND
GND
VCCD
GND
AMP
BGV
ONET
1151M
16 Pin QFN
C1
0.1F
C2
0.1F
C3
0.1 F
C4
0.1 F
C5
0.1 F
DIS
SDA
SDK
28.7 k
RZTC
AMP
ONET1151M
www.ti.com
SLLSED8 –OCTOBER 2012
APPLICATION INFORMATION
Figure 5 shows a typical application circuit using the ONET1151M. The modulator must be AC coupled to the
driver for proper operation. The output amplitude is controlled through the AMP pin and the rest of the functions
are controlled through the 2-wire interface (SDA or SCK) by a microcontroller.
Pullup inductors from MOD+ and MOD- to VCC are required.
Figure 5. Differential AC Coupled Drive
Layout Guidelines
For optimum performance, use 50-Ωtransmission lines (100-Ωdifferential) for connecting the signal source to
the DIN+ and DIN- pins and 50-Ωtransmission lines (100-Ωdifferential) for connecting the OUT+ and OUT-
modulation current outputs to the modulator. The length of the transmission lines should be kept as short as
possible to reduce loss and pattern-dependent jitter.
In addition, VCCD can be connected to VCC and filtered from a common supply.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: ONET1151M
Transition Time (ps)
Amplitude Register Setting (ƒC)
C005
Rise Time
Fall Time
Transition time (ps)
TA - Free-Air Temperature (ƒC)
C006
Fall Time
Rise Time
Random Jitter (psrms)
Amplitude Register Setting (Decimal)
C003
Random Jitter (psrms)
TA - Free-Air Temperature (ƒC)
C004
ISI (pspp)
Amplitude Register Setting (Decimal)
C001
ISI (pspp)
TA - Free-Air Temperature (ƒC)
C002
ONET1151M
SLLSED8 –OCTOBER 2012
www.ti.com
TYPICAL CHARACTERISTICS
Typical operating condition is at VCC = 3.3 V, TA= 25°C, VOUT = 1.5 VPP single ended, EQENA = 0, PKENA = 1 with PEADJ =
0x0F and VIN = 600 mVPP (unless otherwise noted).
DETERMINISTIC JITTER DETERMINISTIC JITTER
vs vs
MODULATION CURRENT TEMPERATURE
Figure 6. Figure 7.
RANDOM JITTER RANDOM JITTER
vs vs
MODULATION CURRENT TEMPERATURE
Figure 8. Figure 9.
RISE-TIME AND FALL-TIME RISE-TIME AND FALL-TIME
vs vs
MODULATION CURRENT TEMPERATURE
Figure 10. Figure 11.
18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ONET1151M
500 mV/Div 15 ps/Div
500 mV/Div 15 ps/Div
Supply Current (mA)
TA - Free Air Temperature ( ƒC )
C009
500 mV/Div 15 ps/Div
SE Output Voltage (V)
AMP Pin Voltage (V)
C007
SE Output Voltage (V)
Amplitude Register Setting (Decimal)
C008
ONET1151M
www.ti.com
SLLSED8 –OCTOBER 2012
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V, TA= 25°C, VOUT = 1.5 VPP single ended, EQENA = 0, PKENA = 1 with PEADJ =
0x0F and VIN = 600 mVPP (unless otherwise noted).
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
AMP VOLTAGE AMP REGISTER SETTING
Figure 12. Figure 13.
SUPPLY CURRENT
vs EYE-DIAGRAM AT 10.3GBPS
TEMPERATURE VOUT=1.5VPP
Figure 14. Figure 15.
EYE-DIAGRAM AT 11.3GBPS EYE-DIAGRAM AT 11.3GBPS
VOUT=1.5VPP, 50% CROSS POINT VOUT=1.5VPP, 30% CROSS POINT
Figure 16. Figure 17.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: ONET1151M
500 mV/Div 15 ps/Div
500 mV/Div 15 ps/Div
ONET1151M
SLLSED8 –OCTOBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V, TA= 25°C, VOUT = 1.5 VPP single ended, EQENA = 0, PKENA = 1 with PEADJ =
0x0F and VIN = 600 mVPP (unless otherwise noted). EYE-DIAGRAM AT 11.3GBPS
EYE-DIAGRAM AT 11.3GBPS VOUT=1.5VPP, EQ SET TO 00,
VOUT=1.5VPP, 70% CROSS POINT 12’’ OF FR4 AT INPUTS
Figure 18. Figure 19.
20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: ONET1151M
PACKAGE OPTION ADDENDUM
www.ti.com 11-Aug-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ONET1151MRGTR ACTIVE VQFN RGT 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 100 1151M
ONET1151MRGTT ACTIVE VQFN RGT 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 100 1151M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Aug-2017
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ONET1151MRGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
ONET1151MRGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ONET1151MRGTR VQFN RGT 16 3000 367.0 367.0 35.0
ONET1151MRGTT VQFN RGT 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Aug-2017
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
16X 0.30
0.18
1.68 0.07
16X 0.5
0.3
1 MAX
(0.2) TYP
0.05
0.00
12X 0.5
4X
1.5
A3.1
2.9 B
3.1
2.9
VQFN - 1 mm max heightRGT0016C
PLASTIC QUAD FLATPACK - NO LEAD
4222419/B 11/2016
PIN 1 INDEX AREA
0.08
SEATING PLANE
1
49
12
58
16 13
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05
EXPOSED
THERMAL PAD
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.600
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
16X (0.24)
16X (0.6)
( 0.2) TYP
VIA
12X (0.5)
(2.8)
(2.8)
(0.58)
TYP
( 1.68)
(R0.05)
ALL PAD CORNERS (0.58) TYP
VQFN - 1 mm max heightRGT0016C
PLASTIC QUAD FLATPACK - NO LEAD
4222419/B 11/2016
SYMM
1
4
58
9
12
13
16
SYMM
LAND PATTERN EXAMPLE
SCALE:20X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
16X (0.6)
16X (0.24)
12X (0.5)
(2.8)
(2.8)
( 1.55)
(R0.05) TYP
VQFN - 1 mm max heightRGT0016C
PLASTIC QUAD FLATPACK - NO LEAD
4222419/B 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
ALL AROUND
METAL
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
SYMM
1
4
58
9
12
13
16
17
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ONET1151MRGTR ONET1151MRGTT