ATR2406DEVKIT2 - ATMEL - Datasheet.Live

Features

•Fully Integrated Low IF Receiver

•Fully Integrated GFSK Modulator for 72, 144, 288, 576 and 1152 Kbits/s

•High Sensitivity of Typically –93 dBm Due to Integrated LNA

•High Output Power of Typically +4 dBm

•Multi-channel Operation

– 95 Channels

– Support Frequency Hopping (ETSI) and Digital Modulation (FCC)

•Supply-voltage Range 2.9V to 3.6V (Unregulated)

•Auxiliary Voltage Regulator on Chip (3.2V to 4.6V)

•Low Current Consumption

•Few Low-cost External Components

•Integrated Ramp-signal Generator and Power Control for an Additional Power Amplifier

•Low Profile Lead-free Plastic Package QFN32 (5 mm × 5 mm × 0.9 mm)

•RoHs Compliant

Applications

•High-tech Multi-user Toys

•Wireless Game Controllers

•Telemetry

•Wireless Audio/Video

•Electronic Point of Sales

•Wireless Head Set

•FCC CFR47, Part 15, ETSI EN 300 328, EN 300 440 and ARIB STD-T-66 Compliant Radio

Links

1. Description

The ATR2406 is a single chip RF transceiver intended for applications in the 2.4-GHz

ISM band. The QFN32-packaged IC is a complete transceiver including image rejec-

tion mixer, low IF filter, FM demodulator, RSSI, TX preamplifier, power-ramping

generator for external power amplifier, integrated synthesizer, and a fully integrated

VCO and TX filter. No mechanical adjustment is necessary in production.

The RF transceiver offers a clock recovery function on-chip.

Low-IF 2.4-GHz

ISM Transceiver

ATR2406

4779N–ISM–12/08

ATR2406

Figure 1-1. Block Diagram

2. Pin Configuration

Figure 2-1. Pinning QFN32 - 5 × 5

LNA IR-Mixer

VCO

REG

REG_DEC

RAMP_OUT

TX_OUT

RX_IN

VREG_VCO

REG_CTRL VS_REG

VS_SYN

VREG IREF

CP REF_CLK TX_DATA VTUNE

AUX

REG

AUX

REG

TEST2

PU_REG

PU_TRX

RX_ON

TX_ON

nOLE

CLOCK

DATA

ENABLE

LIMITER

RSSI

DEMOD

RAMP

GEN PLL

GAUSSIAN

FILTER

CTRL

LOGIC

BUS

VCO

VS_IFD

RX_DATA

RSSI

VS_IFA

VS_RX/TX

TEST1

Divider

by 2

RX_ON

RAMP_OUT

TX_OUT

RX_IN1

RX_IN2

VS_TRX

RX_ON

RAMP_OUT

TX_OUT

RX_IN1

RX_IN2

VS_TRX

PU_REG

PENABLE

DATA

CLOCK

TX_DATA

RX_DATA

PU_TRX

nOLE

TX_ON

REG_CTRL

VREG

VS_REG

REG_DEC

VREG_VCO

VTUNE

VS_SYN

RSSI

VS_IFD

VS_IFA

RX-CLOCK

IREF

REF_CLK

31 30 29 28 27 26 25

9 10111213141516

ATR2406

4779N–ISM–12/08

ATR2406

Table 2-1. Pin Description

Pin Symbol Function

1 PU_REG Power-up input for auxiliary regulator

2 REF_CLK Reference frequency input

3 RSSI Received signal strength indicator output

4 VS_IFD Digital supply voltage

5 VS_IFA Analog supply voltage for IF circuits

6 RX-CLOCK RX-CLOCK, if RX mode with clock recovery is active

7 IC Internally connected. Connect to VS if internal AUX regulator is not used

8 IREF External resistor for band-gap reference

9 REG_CTRL Auxiliary voltage regulator control output

10 VREG Auxiliary voltage regulator output

11 VS_REG Auxiliary voltage regulator supply voltage

12 REG_DEC Decoupling pin for VCO_REG

13 VREG_VCO VCO voltage regulator

14 VTUNE VCO tuning voltage input

15 CP Charge-pump output

16 VS_SYN Synchronous supply voltage

17 VS_TRX Transmitter receiver supply voltage

18 RX_IN2 Differential receiver input 2

19 RX_IN1 Differential receiver input 1

20 TX_OUT TX driver amplifier output

21 RAMP_OUT Ramp generator output for PA power ramping

22 IC Internally connected, do not connect on PCB

23 IC Internally connected, do not connect on PCB

24 RX_ON RX control input

25 TX_ON TX control input

26 nOLE Open loop enable input

27 PU_TRX RX/TX/PLL/VCO power-up input

28 RX_DATA RX data output

29 TX_DATA TX data input

30 CLOCK 3-wire-bus: Clock input

31 DATA 3-wire-bus: Data input

32 ENABLE 3-wire-bus: Enable input

Paddle GND Ground

4779N–ISM–12/08

ATR2406

3. Functional Description

3.1 Receiver

The RF signal at RF_IN is differentially fed through the LNA to the image rejection mixer

IR_MIXER, driving the integrated low-IF band-pass filter. The IF frequency is 864 kHz. The limit-

ing IF_AMP with an integrated RSSI function feeds the signal to the digital demodulator

DEMOD. No tuning is required. Data slicing is handled internally.

3.2 Clock Recovery

For a 1152-kBit/s data rate, the receiver has a clock recovery function on-chip.

The receiver includes a clock recovery circuit which regenerates the clock out of the received

data. The advantage is that this recovered clock is synchronous to the clock of the transmitting

device (and thus to the transmitted data), which significantly reduces the load of the processing

microcontroller.

The falling edge of the clock is the optimal sampling position for the RX_Data signal, so at this

event the data must be sampled by the microcontroller. The recovered clock is available at pin 6.

3.3 Transmitter

The transmit data at TX_DATA is filtered by an integrated Gaussian filter (GF) and fed to the

fully integrated VCO operating at twice the output frequency. After modulation, the signal is fre-

quency divided by 2 and fed to the internal preamplifier PA. This preamplifier supplies typically

+4 dBm output power at TX_OUT.

A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external

power amplifier, is integrated. The slope of the ramp signal is controlled internally so that spuri-

ous requirements are fulfilled.

3.4 Synthesizer

The IR_MIXER, the PA, and the programmable counter (PC) are driven by the fully integrated

VCO, using on-chip inductors and varactors. The output signal is frequency divided to supply the

desired frequency to the TX_DRIVER, the 0/90 degree phase shifter for the IR_MIXER, and to

be used by the PC for the phase detector (PD) (fPD = 1.728 MHz). Open loop modulation is

supported.

3.5 Power Supply

An integrated band-gap–stabilized voltage regulator for use with an external low-cost PNP tran-

sistor is implemented. Multiple power-down and current saving modes are provided.

4779N–ISM–12/08

ATR2406

Electrostatic sensitive device.

Observe precautions for handling.

4. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters Symbol Min. Max. Unit

Supply voltage auxiliary regulator VS–0.3 +4.7 V

Supply voltage VS–0.3 +3.6 V

Control voltages Vcontr –0.3 VSV

Storage temperature Tstg –40 +125 °C

Input RF level PRF +10 dBm

ESD protection VESD_ana TBD V

VESD_dig TBD V

5. Operating Range

Parameters Symbol Min. Max. Unit

Supply voltage VS2.9 3.6 V

Auxiliary regulator supply voltage VS_BATT 3.2 4.6 V

Temperature ambient Tamb –10 +60 °C

Input frequency range fRX 2400 2483 MHz

4779N–ISM–12/08

ATR2406

6. Electrical Characteristics

VS = 3.6V with AUX regulator, Tamb = 25°C, unless otherwise specified

No. Parameters Test Conditions Symbol Min. Typ. Max. Unit

1 Supply

1.1 Supply voltage With AUX regulator VS3.2 3.6 4.6 V

1.2 Supply voltage Without AUX regulator VS2.9 3.0 3.6 V

1.3 RX supply current CW mode (peak current) IS57 mA

Burst mode at 10 Kbits/s(4) IS625 µA

1.4 TX supply current CW mode (peak current) IS42 mA

Burst mode at 10 Kbits/s(4) IS500 µA

1.5

Battery lifetime of a remote

control application using an

AVR®

See Section 10. “Appendix: Current

Calculations for a Remote Control”

on page 20

1.6 Supply current in power-down

mode

With AUX regulator

PU_TRX = 0; PU_REG = 0 IS< 1 µA

1.7 Supply current in power-down

mode

Without AUX regulator

PU_TRX = 0; PU_REG = 0 IS< 1 µA

2 Voltage Regulator

2.1 AUX regulator VREG 3.0 V

2.2 VCO regulator VREG_VCO 2.7 V

3 Transmitter Part

3.1 TX data rate 72/144/288/576/1152 kBits/s

3.2 Output power PTX 4 dBm

3.3 TX data filter clock 9 taps in filter fTXFCLK 10.368/13.824 MHz

3.4 Frequency deviation To be tuned by GFCS bits GFFM_nom ±400 kHz

3.5 Frequency deviation scaling(3) GFFM = GFFM_nom × GFCS

(Refer to bus protocol D9 to D11) GFCS 60 130 %

3.6 Frequency drift

With standard loop filter and slot

length of 1400 µs (Refer to the

application note “ATR2406 Loop

Filter and Data Rates”)

Δfo (drift) ±40 kHz

3.7 Harmonics BW = 100 kHz(1) –41.2 dBm

3.8

Spurious emissions

30 – 1000 MHz

1 – 12.75 GHz

1.8 – 1.9 GHz

5.15 – 5.3 GHz

BW = 100 kHz(1) –57

–57

dBm

4 Ramp Generator, Pin 21

4.1 Minimum output voltage TX_ON = low Vmin 0.7 V

4.2 Maximum output voltage Refer to bus protocol D12 to D13 Vmax 1.1 1.9 V

4.3 Rise time tr5µs

4.4 Fall time tf5µs

Notes: 1. Measured and guaranteed only on the Atmel® evaluation board, including microstrip filter, balun, and Smart Radio Fre-

quency (Smart RF) firmware. Conducted measured.

2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter.

For further information refer to the application notes.

3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation

in production to the nominal value of 400 kHz.

4. Burst mode with 0.9% duty cycle

4779N–ISM–12/08

ATR2406

5 Receiver Part

5.1 RX input impedance Differential Zin 170 + j0 Ω

5.2 Sensitivity At input for BER ≤10-3

at 1152 kBits/s(1) –93 dBm

5.3 Third order input intercept point IIP3 –15 dBm

5.4 Intermodulation rejection

BER < 10-3, wanted at -83 dBm,

level of interferers in channels

N + 2 and N + 4(1) IM332 dBc

5.5 Co-channel rejection BER < 10-3, wanted at –76 dBm(1) RCO –11 dBc

5.6 Adjacent channel rejection

±1.728 MHz

BER < 10-3, wanted at –76 dBm,

adjacent level referred to wanted

channel level(1) Ri (N – 1) 14 dBc

5.7 Bi-adjacent channel rejection

±3.456 MHz

BER < 10-3, wanted at –76 dBm,

bi-adjacent level referred to wanted

channel level(1) Ri (N – 2) 30 dBc

5.8

Rejection with ≥ 3 channels

separation

≥±5.128 MHz

BER < 10-3, wanted at –76 dBm,

n≥3 adjacent level referred to

wanted channel level(1) Ri (n ≥ 3) 40 dBc

5.9 Out of band rejection > 6 MHz BER < 10-3, wanted at –83 dBm at

2.45 GHz(1) Bldf>6MHz 38 dBc

5.10

Out of band rejection

2300 MHz to 2394 MHz

2506 MHz to 2600 GHz

BER < 10-3, wanted at –83 dBm at

2.45 GHz(1) Blnear 47 dBc

5.11

Out of band rejection

30 MHz to 2300 MHz

2600 MHz to 6 GHz

BER < 10-3, wanted at –83 dBm at

2.45 GHz(1) Blfar 57 dBc

6 RSSI Part

6.1 Maximum RSSI output voltage Under high RX input signal level VRSSImax 2.1 V

6.2 RSSI output voltage, monotonic

over range –96 dBm to –36 dBm

With –33 dBm at RF input

With –96 dBm at RF input VRSSI 1.9

0.1

7VCO

7.1 Oscillator frequency defined at

TX output Over full temperature range(1) 2400 2483 MHz

7.2 Frequency control voltage range VVTUNE 0.5 VCC – 0.5 V

7.3 VCO tuning input gain defined at

TX output GVCO 240 MHz/V

6. Electrical Characteristics (Continued)

VS = 3.6V with AUX regulator, Tamb = 25°C, unless otherwise specified

No. Parameters Test Conditions Symbol Min. Typ. Max. Unit

Notes: 1. Measured and guaranteed only on the Atmel® evaluation board, including microstrip filter, balun, and Smart Radio Fre-

quency (Smart RF) firmware. Conducted measured.

2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter.

For further information refer to the application notes.

3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation

in production to the nominal value of 400 kHz.

4. Burst mode with 0.9% duty cycle

4779N–ISM–12/08

ATR2406

8 Synthesizer

8.1 External reference input

frequency

D7 = 0

D7 = 1 REF_CLK 10.368

13.824

MHz

8.2 Sinusoidal input signal level

(peak-to-peak value) AC-coupled sine wave REF_CLK 500 1000 mVPP

8.3 Scaling factor prescaler SPSC 32/33 -

8.4 Scaling factor main counter SMC 86/87/88/89 -

8.5 Scaling factor swallow counter SSC 031-

9 Phase Detector

9.1 Phase detector comparison

frequency fPD 1728 kHz

10 Charge-pump Output

10.1 Charge-pump output current VCP = 1/2 VCC ICP ±2 mA

10.2 Leakage current VCP = 1/2 VCC IL±100 1000 pA

11 Timing Conditions(1)(2)

11.1 Transmit to receive time Reference clock stable TX →RX time 200 µs

11.2 Receive to transmit time Reference clock stable RX →TX time 200 µs

11.3 Channel switch time Reference clock stable CS time 200 µs

11.4 Power down to transmit Reference clock stable PD →TR time 250 µs

11.5 Power down to receive Reference clock stable PD →RX time 200 µs

11.6 Programming register Reference clock stable PRR time 3 µs

11.7 PLL settling time Reference clock stable PLL set time 200 µs

12 Interface Logic Input and Output Signal Levels, Pin DATA, CLOCK, ENABLE

12.1 HIGH-level input voltage Logic 1 VIH 1.4 3.1 V

12.2 LOW-level input voltage Logic 0 VIL –0.3 +0.4 V

12.3 HIGH-level output voltage Logic 1 VOH 3.1 V

12.4 LOW-level output voltage Logic 0 VOL 0V

12.5 Input bias current Logic 1 or logic 0 Ibias –5 +5 µA

12.6 3-wire bus clock frequency fCLKmax 10 MHz

6. Electrical Characteristics (Continued)

VS = 3.6V with AUX regulator, Tamb = 25°C, unless otherwise specified

No. Parameters Test Conditions Symbol Min. Typ. Max. Unit

Notes: 1. Measured and guaranteed only on the Atmel® evaluation board, including microstrip filter, balun, and Smart Radio Fre-

quency (Smart RF) firmware. Conducted measured.

2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter.

For further information refer to the application notes.

3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation

in production to the nominal value of 400 kHz.

4. Burst mode with 0.9% duty cycle

4779N–ISM–12/08

ATR2406

7. PLL Principle

Figure 7-1. PLL Principle

"- Main counter MC

"- Swallow counter SC

fCVO = 1728kHz x (SMC x 32 + SSC)

Programmable counter PC

VCO

TXDAT

Baseband controller

Reference counter (RC)

REF_CLK D7

13.824MHz 1

10.368MHz 0

Mixer

PA driver

Gaussian

filter (GF)

Divide

by 2

Charge

pump

External

loop filter

PLL reference frequency

REF_CLK

Phase frequency

detector (PD)

fPD = 1728kHz

4779N–ISM–12/08

ATR2406

Table 7-1 shows the LO frequencies for RX and TX in the 2.4-GHz ISM band. There are 95

channels available. Since the ATR2406 supports wideband modulation with 400-kHz deviation,

every second channel can be used without overlap in the spectrum.

7.1 TX Register Setting

The following 16-bit word has to be programmed for TX.

Note: D12 and D13 are only relevant if ramping generator in conjunction with external PA is used, otherwise it can be programmed 0

or 1.

The VRAMP voltage is used to control the output power of an external power amplifier. The volt-

age ramp is started with the TX_ON signal.

These bits are only relevant in TX mode.

Table 7-1. LO Frequencies

Mode fIF /kHz Channel f

ANT /MHz f

VCO / MHz divided by 2 SMC SSC N

C0 2401.056 2401.056 86 27 2779

C1 2401.920 2401.920 86 28 2780

... ... ... ... ... ...

C93 2481.408 2481.408 89 24 2872

C94 2482.272 2482.272 89 25 2873

RX 864

C0 2401.056 2401.920 86 28 2780

C1 2401.920 2402.784 86 29 2781

... ... ... ... ... ...

C93 2481.408 2482.272 89 25 2873

C94 2482.272 2483.136 89 26 2874

MSB LSB

Data bits

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

01 PA GFCS 1RC MC SC

Table 7-2. Output Power Settings with Bits D12 - D13

PA (Output Power Settings)

D13 D12 RAMP_OUT (Pin 21)

0 0 1.3V

0 1 1.35V

1 0 1.4V

1 1 1.75V

4779N–ISM–12/08

ATR2406

7.2 RX Register Setting

There are two RX settings possible. For a data rate of 1152 kBits/s, an internal clock recovery

function is implemented.

7.3 Register Setting Without Clock Recovery

Must be used for data rates below 1.152 Mbits/s.

Note: X values are not relevant and can be set to 0 or 1.

7.4 RX Register Setting with Internal Clock Recovery

Recommended for 1.152-Mbit/s data rate.

The output pin of the recovered clock is pin 6. The falling edge of the recovered clock signal

samples the data signal.

Note: X values are not relevant and can be set to 0 or 1.

7.5 PLL Settings

RC, MC and SC bits control the synthesizer frequency as shown in Table 7-3, Table 7-4 on page

12 and Table 7-5 on page 12.

Formula for calculating the frequency:

TX frequency: fANT = 864 kHz × (32 × SMC + SSC)

RX frequency: fANT = 864 kHz × (32 × SMC + SSC – 1)

MSB LSB

Data bits

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

01XXXXX0RC MC SC

MSB

Data bits

D24 D23 D22 D21 D20 D19 D18 D17 D16

10100 0000

LSB

Data bits

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

00XXX XX0RC MC SC

Table 7-3. PLL Settings of the Reference Counter Bit D7

RC (Reference Counter)

D7 CLK Reference

0 10.368 MHz

1 13.824 MHz

4779N–ISM–12/08

ATR2406

7.6 GFCS Adjustment

The Gaussian filter control setting (GFCS) is used to compensate for production tolerances by

tuning the modulation deviation in production to the nominal value of 400 kHz. These bits are

only relevant in TX mode.

Table 7-4. PLL Settings of the Main Counter Bits D5 to D6

MC (Main Counter)

D6 D5 SMC

0086

0187

1088

1189

Table 7-5. PLL Settings of the Swallow Counter Bits D0 to D4

SC (Swallow Counter)

D4 D3 D2 D1 D0 SSC

000000

000011

000102

... ... ... ... ... ...

1110129

1111030

1111131

Table 7-6. GFCS Adjustment of Bits D9 - D11

GFCS

D11 D10 D9 GFCS

00 060%

00 170%

01 080%

01 190%

1 0 0 100%

1 0 1 110%

1 1 0 120%

1 1 1 130%

4779N–ISM–12/08

ATR2406

7.7 Control Signals

The various transceiver functions are activated by the following control signals. A timing pro-

posal is shown in Figure 7-3 on page 14

7.8 Serial Programming Bus

The transceiver is programmed by the SPI (CLOCK, DATA and ENABLE).

After setting the enable signal to low, the data is transferred bit by bit into the shift register on the

rising edge of the clock signal, starting with the MSBit. When the enable signal has returned to

high, the programmed information is active. Additional leading bits are ignored and there is no

check made of how many clock pulses arrived during enable low.

The programming of the transceiver is done by a 16-bit or 25-bit data word (for the RX clock

recovery mode).

7.9 3-wire Bus Timing

Figure 7-2. 3-wire Bus Protocol Timing Diagram

Table 7-7. Control Signals and Functions

Signal Functions

PU_REG Activates AUX voltage regulator and the VCO voltage regulator supplying the

complete transceiver

PU_TRX Activates RX/TX blocks

RX_ON Activates RX circuits: DEMOD, IF AMP, IR MIXER

TX_ON Activates TX circuits: PA, RAMP GEN, Starts RAMP SIGNAL at RAMP_OUT

nOLE Disables open loop mode of the PLL

TTTEC

ENABLE

CLOCK

DATA

TL TCTPER

Table 7-8. 3-wire Bus Protocol Table

Description Symbol Minimum Value Unit

Clock period TPER 100 ns

Set time data to clock TS 20 ns

Hold time data to clock TH 20 ns

Clock pulse width TC 60 ns

Set time enable to clock TL 100 ns

Hold time enable to data TEC 0 ns

Time between two protocols TT 250 ns

4779N–ISM–12/08

ATR2406

Figure 7-3. Example TX and RX Timing Diagram

Power up Programming Programming Active TX slotActive RX slot Power down

optional

Power up

optional

Power down

> 40μs

> 200μs

> 40μs

> 50μs

Data

Pin name

MODE

PU_REG

Pin 1

PU_TRX

Pin 27

TX_DATA

Pin 29

3W_CLK

Pin 30

3W_DATA

Pin 31

3W_ENA

Pin 32

nOLE

Pin 26

REF_CLK

Pin 2

RX_ON

TRX (Output)

Signals fromSignals to TRX (Input)

Pin 24

TX_ON

Pin 25

RX_DATA

Pin 28

RSSI

Pin 3

RAMP_OUT

Pin 21

connected to

RAMP_IN of

optional PA Note: 1. Keep input signals at low level during power-down state of TRX

C3 C4 C1

C1 C2 C5

16/25 bits

> 200μs

Preamble

(1-0-1-0)

16 bits

REF_CLK

Valid signal

4779N–ISM–12/08

ATR2406

7.10 Received Signal Strength Indication (RSSI)

The RSSI is given as an analog voltage at the RSSI pin. A typical plot of the RSSI value is

shown in Figure 7-4.

Figure 7-4. Typical RSSI Value versus Input Power

Table 7-9. Description of the Conditions/States

Condition Description

C1 Power down

ATR2406 is switched off and the supply current is lower than 1 µA.

Power up

ATR2406 is powered up by toggling PU_REG and PU_TRX to high.

PU_REG enables the external AUX regulator transistor including VCO regulator.

PU_TRX enables internal blocks like the PLL and the VCO.

Depending on the value of the external capacitors (for example, at the AUX

regulator, if one is used), it is necessary to wait at least 40 µs until the different

supply voltages have settled.

Programming

The internal register of the ATR2406 is programmed via the three-wire interface.

At TX, this is just the PLL (transmit channel) and the deviation (Gaussian filter).

At RX, this is just the PLL (receive channel) and, if the clock recovery is used, also

the bits to enable this option. At the start of the three-wire programming, the

enable signal is toggled from high to low to enable clocking the data into the

internal register. When the enable signal rises again to high, the programmed

data is latched. This is the time point at which the settling of the PLL starts. It is

necessary to wait the settling time of 200 µs so that the VCO frequency is stable.

The reference clock needs to be applied to ATR2406 for at least the time when the

PLL is in operation, which is the programming state (C3) and the active slot (C4,

C5). Out of the reference clock, several internal signals are also derived, for

example, the Gaussian filter circuitry and TX_DATA sampling.

C4 This is the receive slot where the transmit burst is received and data as well as

recovered clock are available.

This is the active transmit slot. As soon as TX_DATA is applied to ATR2406, the

signal nOLE toggles to low which enables modulation in open-loop mode.

The preamble (1-0-1-0 pattern) should start being sent at the start of TX_ON.

-130 -110 -90 -70 -50 -30 -10 10

RF Level (dBm)

2.5

2.0

1.5

1.0

0.5

RSSI Level (V)

4779N–ISM–12/08

ATR2406

8. Application Circuit

The ATR2406 requires only a few low-cost external components for operation. A typical applica-

tion is shown in Figure 8-3 on page 17.

8.1 Typical Application Circuit

Figure 8-1. Microcontroller Interfacing with General Purpose MCU, Pin Connections between

Microcontroller and ATR2406

Figure 8-2. Example with AVR MCU

Note: 1. XTAL: for example, XRFBCC-NANL; 13.824 MHz, 10 ppm

Order at: Taitien Electronic, Taitien Specific No.: A009-x-B26-3, SMD

Microcontroller ATR2406

Configuration

and control

RF-DATA

Interface

TX_DATA

RX_DATA

RX-CLOCK

DATA

CLOCK

ENABLE

Ctrl_Lines

XTAL_OUT REF_CLK

XTAL(1)

ATR2406

RF_CTRL

RF_DATA

AVR_MCU

USART

GPIO

13.824MHz XTAL REF_CLK

nOLE

ENABLE

CLOCK

DATA

TX_ON

RX_ON

PU_TRX

PU_REG

GPIO1

GPIO2

TXD

RXD

XCK

GPIO3

GPIO4

GPIO5

TX_DATA

RX_DATA

RX-CLOCK

RSSI

4779N–ISM–12/08

ATR2406

Figure 8-3. Application Circuit for ATR2406-DEV-BOARD

2.2pF

5.6pF

25 G

TP2TP1

RX_DATA

RSSI

RX_CLOCK

REF_CLK

PU_REG

ENABLE

DATA

CLOCK

nOLE

PU_TRX

RAMP_OUT

RX_ON

VBATT

TX_DATA

CLOCK

TX_DATA

ENABLE

VS_IFA

VS_IFD

RSSI

REF_CLK

IREF

RX_CLOCK

PU_REG

TX_OUT

RAMP_OUT

VS_TRX

RX_IN2

RX_IN1

RX_ON

DATA

RX_DATA

PU_TRX

TX_ON

nOLE

REG_DEC

VREG_VCO

REG_CTRL

VS_REG

VREG

VTUNE

GND

VS_SYN

TX_ON

1.5pF

1.8pF

C24

C13

4.7μF

C12

100nF

C15

100nF

C16

4.7pF

4.7μF

C17

390pF

C29

4.7nF

C11

BC808

18pF

1.8pF

C10

R2 NC

J24

RSSI

RX_ON

CLOCK

PU_TRX

TX_DATA

TX_ON

VBATT

J10

REF_CLK

J4 J11

J12

J13

J14

J20

J19

J18

J17

J16

J15

VBATT

ENABLE

DATA

nOLE

RX_DATA

RX_CLOCK

PU_REG

SMASI

GND

ANT2

ANT

F antenna

Select integrated F antenna or

SMA connector by setting the

0 resistor

ANT GND

Microstrip

balun

Microstrip

ATR2416

Microstrip

Low-passfilter

C14

GND5

GND4

GND9

GND8

GND7

GND2

GND3

GND1

GND6

IC2

RFOUT (Ant)

1kΩ

1.5kΩ

62kΩ

C21

J26

C20, C21, COG

dielectric

C18 2.2nF

68pF

C19

470nF

C20

IC2P

GND

Slug

22nF

RAMP

J21

4779N–ISM–12/08

ATR2406

9. PCB Layout Design

Figure 9-1. PCB Layout ATR2406-DEV-BOARD

4779N–ISM–12/08

ATR2406

Table 9-1. Bill of Materials

Part Value Part Number Vendor Package Comment

C1 5.6 pF 0402

C3, C10 1.8 pF 0402

C4 390 pF 0402

C5 4.7 pF 0402 NC

C6, C7 2.2 pF 0402

C9 1.5 pF 0402

C11 18 pF 0402

C12, C15 100 nF 0402

C13, C16 4.7 µF B45196H2475M109 Epcos®3216 Optional(2)

C14 1 nF 0402 NC

C17 3.3 nF 0402 NC

C18 68 pF 0402

C19 470 nF 0402/0603

C20 22 nF, COG GRM21B5C1H223JA01 Murata 0805 COG, important for good

RF performance

C21 2.2 nF,

COG GRM1885C1H222JA01 Murata 0603 COG, important for good

RF performance

C23 4.7 nF 0402

C24 4.7 pF 0402

R3 62 kΩ62k, ≤5% 0402

R4 1.0 kΩ1k0, ≤5% 0402

R5 1.5 kΩ1k5, ≤5% 0402 Ref_Clk level, optional(1)

R6 1.5 kΩ1k5, ≤5% 0402 Ref_Clk level, optional(1)

IC2 ATR2406 ATR2406 Atmel MLF32

T1 BC808-40 BC808-40, any standard type can be used, but it is

important that be “–40”!

Vishay®, Philips®,

etc. SOT-23 Optional(2)

MSUB FR4 FR4, e_r = 4.4 at 2.45 GHz, H = 500 µm, T = 35 µm, tand = 0.02, surface, that is, chem. tin or chem. gold

Notes: 1. Not necessary if supplied RefClk level is within specification range

2. If no AUX regulator is used, then T1 and C16 can be removed and a jumper is needed from the collector to the emitter pad.

Additionally, pin 7 of the ATR2406 has to be connected to pin 4 or pin 5 to use the integrated F antenna, set jumper R2 (0R

resistor 0603)

Table 9-2. Parts Count Bill of Materials

Parts Count Required (Minimal BOM) Optional (Depending on Application)

Capacitors 0402 14 14

Capacitors >0402 2 4

Resistors 0402 2 2

Inductors 0402 – –

Semiconductors 1 2

4779N–ISM–12/08

ATR2406

10. Appendix: Current Calculations for a Remote Control

Assumptions:

Basic Numbers:

Amount of Current Needed to Transmit One Packet:

Protocol

A data packet consists of 24 bytes.

24 bytes = 240 bits (USART connection)

Tpacket_length = 210 µs at 1.152 Mbits/s

Channel The system will use five predefined channels for frequency hopping spread

spectrum (FHSS) which gives improved immunity against interferers

Loop filter Loop filter settling time will be 110 µs

Handheld device

If not in use, the handheld device will be in power-down mode with the AVR’s

watchdog timer disabled. The AVR power-down current is typically 1.25 µA. If

an external voltage regulator is used, additional power-down current has to be

taken into account

Base station device

The base station will periodically scan all the channels of the used subset. The

base station will stay on one channel for 2 seconds. If the base station receives

a correct packet, an acknowledge will be returned to the handheld device. The

power consumption of the base station device is not power-sensitive, as this

part of the application is normally mains powered

Peak current ATR2406 in TX at 1.152 Kbits/s 42 mA

Peak current ATR2406 in RX at 1.152 Kbits/s 57 mA

Peak current ATR2406 with synthesizer running 26 mA

Current ATmega88 active 5 mA

Current ATmega88 power down (no WDT) 1.25 µA

Current ATmega88 power down (+ WDT) 5 µA

Loop settling time of ATR2406 110 µs

Configuration of ATR2406 30 µs

Time needed for exchanging a packet at 1.152 Kbits/s 210 µs

Q1 = (0.005A + 0.026A) ×5030 µs = 155 µAs (charge up time ATR2406 + AVR internal calculations)

Q2 = (0.005A + 0.026A) ×30 µs = 0.93 µAs (charge for configuring the ATR2406)

Q3 = (0.005A + 0.026A) ×110 µs = 3.41 µAs (charge for settling the loop filter)

Q4 = (0.005A + 0.042A) ×210 µs = 9.87 µAs (charge for transmitting the packet)

Q5 = (0.005A) ×250 µs = 1.25 µAs (charge for turn around (TX to RX, RX to TX, etc.))

Q6 = (0.005A + 0.026A) ×30 µs = 0.93 µAs (charge for configuring the ATR2406)

Q7 = (0.005A + 0.026A) ×60 µs = 1.86 µAs (charge for settling the loop filter)

Q8 = (0.005A + 0.057A) ×50 µs = 3.10 µAs (charge until valid data can be received)

Q9 = (0.005A + 0.057A) ×210 µs = 13.02 µAs (charge for receiving the packet)

Q10 = (0.005A + 0.057A) ×50 µs = 3.1 µAs (charge for latency before receiving)

4779N–ISM–12/08

ATR2406

A successful packet exchange needs the following charge

Q = Q1 + Q2 + Q3 + Q4 + Q5 + Q6 + Q7 + Q8 + Q9 + Q10 = 192.47 µAs

As the described system is a FHSS system with 5 different channels, the system has to do this

up to five times before the packet is acknowledged by the base station. The average will be 2.5

times. In the case of an interfered environment, some more retries may be required; therefore, it

is assumed the factor will be 3. The power-up time is included only once, as the cycle will be

completed without powering up and down the handheld in order to be as power efficient as

possible.

Average current needed for a packet exchange:

155 µAs + (37.5 µAs ×3) = 267.5 µAs

If the device will be used 1000 times a day →3.1 µA

Average current in active mode:

→ System Power Down current:

Current ATmega88: 1.25 µA

Current ATR2406: 1.0 µA

Current VREG (+ ShutDown): 2.75 µA

Assumed average power-down current is 5 µA.

→Overall power consumption is 8.1 µA

It is assumed the system uses a small battery with a capacity of 100 mAh. This is 100.000 µAh.

→Battery lifetime will be around: 12345 hours = 514 days = 1.4 years.

The most important factor is to get the power-down current as low as possible!

Example:

Assume a system where the handheld is used just 10 times per day.

→Iactive = 0.031 µA

and assuming the power-down current of this device is just 4 µA.

→I = 0.031 µA + 4 µA = 4.03 µA

→Battery lifetime will be around 24807 hours = 1033 days = 2.83 years.

→Power-down current is the main factor influencing the battery lifetime.

4779N–ISM–12/08

ATR2406

12. Package Information

11. Ordering Information

Extended Type Number Package Remarks MOQ

ATR2406-PNQG QFN32 - 5x5 Taped and reeled, Pb-free 4000

ATR2406-DEV-BOARD – RF module 1

ATR2406-DEV-KIT2 –

Complete evaluation kit

and reference design

ATR2406 + ATmega88

916

3225

3.7

3.5

0.5 nom.

0.23

0.4

0.9±0.1

0.05-0.05

specifications

according to DIN

technical drawings

Issue: 1; 22.01.03

Drawing-No.: 6.543-5096.01-4

Package: QFN 32 - 5 x 5

Exposed pad 3.7 x 3.7

Dimensions in mm

Not indicated tolerances ± 0.05

4779N–ISM–12/08

ATR2406

13. Recommended Footprint/Landing Pattern

Figure 13-1. Recommenced Footprint/Landing Pattern

Table 13-1. Recommended Footprint/Landing Pattern Signs

Sign Size

A 3.2 mm

B 1.2 mm

C 0.3 mm

a 1.1 mm

b 0.3 mm

c 0.2 mm

d0.55 mm

e 0.5 mm

4779N–ISM–12/08

ATR2406

14. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision

mentioned, not to this document.

Revision No. History

4779N-ISM-12/08 • Put datasheet in a new template

• Section 12 “Package Information” on page 22 changed

4779M-ISM-02/07 • Put datasheet in a new template

• Table 9-1 “Bill of Materials” on page 19 changed

4779L-ISM-08/06

• Table “Electrical Characteristics” on pages 6 to 8 changed

• Section 10 “Appendix: Current Calculations for a Remote Control” on

pages 20 to 21 changed

• Table “Ordering Information” on page 22 changed

• Minor corrections to grammar and style throughout document

4779K-ISM-06/06

• Put datasheet in a new template

• Table “Electrical Characteristics” on pages 6 to 8 changed

• Section 10 “Appendix: Current Calculations for a Remote Control” on

pages 20 to 21 added

• Ordering Information on page 22 changed

4779N–ISM–12/08

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