pA a a Dae KS16112/4 INTRODUCTION The KS16112 and. KS16114 are synchronous, half-dupiex modems capable of speed up to 9600 bps (KS16112) or up to. 14400 bps (KS16114). These modem devices can operate over the public switched telephone network (PSTN) with the addition of the appropriate Data Access Arrangement (DAA). These modems satiafy the requirements specified in CCITT ro- commendations V.17 (KS16114), V.29, V.27 ter, V.21 Channel 2 and T.4, and meet the binary signaling requirements of T.30. These products are intended to .be used in Group 3 facsimile machines and can operate at 14400(KS161 14), 12000(KS 16114), 9600, 7200, 4800, 2400 or 300 bps depending on the selected configuration. These devices also feature V.17 short train (KS816114) and V.27 ter short train and three programmable tone detectors as well.as.a pro- grammable DTMF receiver. Additionally, HDLC framing (according to T.30) at 14400 (KS 16114), 9600/14400 bps FAX MODEM 68-PLCC-SQ i AN KS16112/4 12000 (KS 16114), 9600, 7200, 4800, 2400 or 300 bps ORDERING INFORMATION is also featured. - Device Package {| Operating Temperature + KS16112L | 68-PLCC-SQ O~+ 70 + KS16114L | 68-PLCC-SQ + : New Product FEATURES * Group 3 facsimile transmission/ reception according to: - CCITT V.17 short and long train (K818114) - CCITT V.28, V.27 ter short and long train, V.21 Ch.2, T.30 and T.4 Haif-duplex operation Receiver dynamic range : 0 dBm to -43 dBm Programmable transmit teva! : 0 dBm to -16.dBm Programmabie dual tone generation Programmable tone detection Programmable interface memory interrupt Programmable tum on and turn off thresholds Automatic T/2 adaptive equalizer HOLC capability at.all speeds CCITT V.24 compatible Interface TTL and CMOS cmpatible Diagnostic capability allowing telephone line quality monitoring Low power consumption (400 mW typical, KS16112 ; 400mW typical, KS16114 : 650mW typical) Rage ELECTRONICS 378KS16112/4 9600/14400 bps FAX MODEM BLOCK DIAGRAM FXAO 238 azo e elal la S85 alla READ Digital WRI Signal ENSS Processor IRE SEPWCLK SEPCLK RXAI SEPXO SEPYO SAMSUNG 379 ELECTRONICSKS16112/4 | 9600/14400 bps FAX MODEM PIN CONFIGURATION OCLK! SYNCIN2 ors KS16112/4 TXDI DCLK SEPWCLK SEPCLK SEPXO ADIN DAQUT SEPYO GNDA2 (% AMSUN 380 ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM PIN DESCRIPTION Pin No, Symbol Type Description Regiater select bus 67 RS4 These lines are used to address interface memory registers within 1 RSa the modem. When CS is active, the modem decodes RSO through 2 RS2 RS4 to address one of its 32 internal interface memory registers. 3 RS1 RS4 is the most significant bit. In a typical design, RSO - RS4 are Rso connected to Ad - Ad address lines of the host microprocessor. 55 D7 + Data bus 56 06 These bidirectional data bus lines provide parailei data transfer 57 DS between the modem and the host microprocessor. 58 D4 vO D7 is the most significant bit. 59 03 The direction of the D0 - 07 data bus is controfled by the 60 D2 READ - 2 and WRITE - RAW signats. 61 D1 When not being written into or read from, DO - D7 agsume the 62 Do high impedance state. * Chip select The modem is selected and decodes RSO - RS4 when CS 65 cs 1 becomes active at which time data transfer between the modem and the host can take place over the parallel data bus. Typically, CS is driven by address decode logic. * Read enable ( 8086 bus mode ) or phase2 ( 6500 bus. mode ) If 8085 bus is selected (ENSS is connected to ground ), this 66 READ -@ 2 { signal acts as the READ input. 1 6500 bus mode is selected (ENS is pulled up to +5V/), this signal acts as the Phase 2 clock input. + Write enable ( 3086 bus mode) or RUW ( 6500 bus mode) If 8085 bus mode is selected ( ENSS Is connected to ground ), this 64 WRITE-RW I signal acta as the WRITE input. tf 6500 bus mode is selected ( ENSS Is pulled up to +5V), this signal acts as the RAW strobe. SUES 381 ELECTRONICSKS16112/4 PIN DESCRIPTION ( Continued ) 9600/14400 bps FAX MODEM Pin No. Symbo! Type Description Interrupt request The modem can use IRQ to interrupt the host microprossor program execution. TRG can be enable in the modem interface memory to be asserted in response to a specified change of conditions in the madem status. IRQ is an open drain output and must be connected to an external pull up resistor of suitable value { typically, a 5.6 kQ, 1/4 watt, 5% resistor is adequate). 19 TXDI Transmit data input TXDI is the modem's transmit data serial input. When configured for serial data mode ( PDME bit is reset ), the modem accepts data bits for transmission via this input. When transmitting data, the modem reads the TXDI pin on the rising edge of OCLK. When the modem is configured for parallel data mode ( PDME bit set ), the TXDI pin is ignored and transmit data is accepted by the modem via the DBFR register. 27 RXDO. Receive data output RXDO is the modem receive data output. Received data is. output to the DTE via the RXDO pin in both serial and parallet data modes ( PDME bit set or reset). When receiving data, the modem outputs a data bit on the falling edge of DCLK. The center of RXDO bits coincides with the rising edge of DCLK, thus, the DTE equipment should read RXDO on the rising edge of OCLK. RTS Request to send When the RTS input is forced low, the transmitter starts transmitting the modem training sequence according to the selected configuration. Onice the training sequence has been transmitted ( signalled by the CTs pin and CTSB bit becoming active ), data present at either the TX input pin in serial mode ( PDME bit is reset } or written into the DBFR ragister in paralle| mode ( PDME bit is set ) is modulated and fransmitted. The RTS input pin is logically. ORed with the RTSB bit in the interface memory. 382KS16112/4 9600/14400 bps FAX MODEM PIN DESCRIPTION ( Continued ) Pin No. Symbol! Type Description Clearto send CTS is used to indicate of that the transmission training sequence 18 cTs has been completed and the modem is ready to transmit any data present at either the TXDI input pin in serial mode (PDME bit is reset) or in DBFR in paraliel mode ( PDME bit is set). Recelved line signal detector RLSD becomes active at the end of the reception of the training 28 RLSD 5 sequence indicating the beginning of data reception. if no training is detected but the received enargy level is abave the RLSD off to on threshold, RLSD will become active. Data clock DCLK.acts as received data clock or transmit data clock depending on the state of the modem ( transmit or receive mode). 20 DCLK o The frequency of the clock corresponds to the data rate of the selected modem configuration and is accurate to + 0.01% with a duty cycle of 50% + 1%. In receive mode the RXDO pin is. clocked out by the modem on the rising edge of DCLK. in transmit mode, TXDI is clocked in by the modem on the falling edge of OCLK. * Oscillator in / Out An external 24.00014MHz ( KS16112 ) of 38.00053MHz ( KS16114 ) crystal and two capacitors are connected to the XTALI and XTALO. Attemately, an external crystal oscillator of the appropriate frequency can be connected to the XTALI input leaving XTALO unconnected. 11 XTALI I In order to minimize electromagnetic emissions and ensure proper 12 XTALO oscillator start up and operation, the crystal and the capacitors should be placed as close as possible to the XTAL! and XTALO pins. Further, the circuit board traces connecting the crystal and capacitors to XTALL and XTALO should be as short as possible. The use of circuit board vias should be avoided in the crystal oscillator circuitry and circuit board traces should be routed using curved turns.KS16112/4 9600/14400 bps FAX MODEM PIN DESCRIPTION ( Continued ) Pin No. Symboi Type Description * Power On reset In/Out "PORT and PORO must be connected together forming a bidirectional 40 Por i modem reset signal ( POR ). __ 54 PORO oO When. power is first applied to the modem. POR is held low for approximately 350 ms. The modem is then ready for normal operation 15 ms after the low to high transition of POR. + 5V Digital voltage supply : 15 Voo Power This pin must be connected to +5V + 5% supply. The + 8V Digital power supply voltage ripple should not exceed 100mVp.p. + 5V Analog voltage supply 39 Vee Power This pin must be connected to +5V + 5% supply. The +8V Analog power supply voltage ripple should not exceed 100mVp.p. - 5V Analog voltage supply 34 Vee Power This pin must be connected to -5V + 5% supply. The -5V Analag power supply voltage ripple should not exceed 100mVp.p. 68 GND D1 a Digital ground 54 GND D2 These pin must be connected to digital ground. 2 GND At GND * Analog ground 30 GND A2 These pin must be connected to analog ground. * Enable 8086 bus mode When EN85 is connected to ground, 8085 bus mode is selected and the modem can interface directly to an 8085 compatible 9 ENSS | microprocessor bus using READ and WRITE. When ENSS is pulled up to + SV, 6500 bus mode is selected and the modem can interface directly to a 6500 compatible micro- processor using 2 and RAV. PSAMSUN cpp 884 " ELECTRONICSKS16112/4 . 9600/14400 bps FAX MODEM PIN DESCRIPTION ( Continued ) Pin No. Symbol Type Description Cable 1/2 equalizer select These two inputs are used to. select equalization for the follwing cable lengths : CABLE TYPE LENGTH Gain (dB) 40 CABL 1 i CABL2 | CABL1 | LENGTH | 700Hz | 1500Hz | 2000Hz | 3000Hz a CABL 2 low fow 0.0Km 0.00 0.00 0.00 0.00 jow high 1.8Km -0.99 -0,20 0.15 1.43 high low 3.6Km -2.39 -0.65 0.87 3.06 high high 7.2Km -3.93 1.22 4.90 4.58 XCLK output 13 XCLKO oO This output pin is a 12MHz (KS16112) or 1S9MHz (KS16114 ) square wave ouipul derived from XTALI. * YCLK output 14 YCLKO 5 This output pin is a GMHz ( KS16112) or 9.5MHz (KS16114 ) square wave output derived from XTALI. Serial eye pattern bit clock 23 SEPXO These two outputs provide two serial bit streams containing eye 26 SEPYO pattern display data for the oscilloscope X and Y axis. The data words are 9 bits long with the sign bit shifted out first and the bits clocked by the rising edge of SEPCLK. Serial eye pattern bit clock SEPCLK is a 230.4KHz clock used to shift the aya pattern data 22 SEPCLK QO into the serial to parallel converters. SEPXO and SEPYO are shifted out by the modem on the rising edge of SEPCLK. Serial eye pattern word clock SEPWCLK ( 9600Hz) provides SEPXO and SEPYO = 9) - bit word 21 SEPWCLK timing and its rising edge is used for copying the output of the serial to parallel converters into the X and Y digital to analog converters. 3 SAMS UN a ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM PIN DESCRIPTION ( Continued ) Pin No. Symbol Type Description Transmitter analog output The TXAO can supply a maximum of 3.03 Vox into a load 34 TXAO tesistance of 10.k2. (minimum ). An external analog smoothing filter with transfer function 28735.63 / (S$ + 11547.34 ) is required. * Recelver analog Input The input impedance of RXAI is greater them 1 NO. An extemal analog anti.- aliasing fitter with transfer function 45 RXAI | 21551.72 / (S + 11547.43 ) is required between the line interface and the modem RXAI input. The maximum input signal level into the anti-aliasing filter should not exceed OdBm. * Auxillary analog input The transmitter output ( TXAO ) can be accessed by user equipment through AUXAI. 32 AUXAI { Since this is a sampled input any signals with frequency components higher than 4800Hz ( half of the sampling rate ) will cause aliasing errors. The input impedence of AUXAI is 1 MQ and the gain to TXAO is OdB + 148. 44 AOQUT 5 * Smoothing fitter output ABSOLUTE MAXIMUM RATINGS (Ta =25 tv) Characteristic Symbol Vatue Unit Positive Digital Supply Voltage Vop 5V + 5% Vv Positive Analog Supply Voltage Vee 5V + 5% v Negative Analog Supply Voltage Vea -5V + 5% v Power Dissipation Pp 400 (KS16112), 550 (KS16114) mW Operating Temperature Torr O~70 c Storage Temperature Ts1 ~ 55 ~ 150 Cc en *eKS16112/4 9600/14400 bps FAX MODEM ELECTRICAL CHARACTERISTICS {Ta = 25 T, Vcc = 5V, Vag = -5V, Uniess otherwise specified ) Characteristic Pin Type | Symbot Test Condition Min | Typ | Max | unit TTL 20 | | Vee | Vv Vin - . Input Voltage POR! O8Vcc}- | Veco | V Vi _ 03} | o8 | v ; TTL Vea Voc # 5.25V, Vin = 5.25V ~ | | 40 | wa input Current TTLandPORT| = Vy Veo # 5.25V | {-a0o] ~ Input Leakage Current | TTLandPORI| | Vee = 5.25V 25| oA in ie Cu a . e 3 Vana) Vin = 0 to 5V Output Leakage Current TTL 3-S loaxs Vin = 0.4V to Voc - 1 - Par] yA V.24 Signals, hoap = -100 uA 35 | v TTL 3-S Vou loan = -40 yA 24 ~ ~ Vv and PORI Output Voltage V.24 Signals, ILoap = 1.6 A _ ~ 0.4 Vv IRQ, DO-D7 Vor, ltoap * 0.8 uA ~ 0.4 v and PORO tloap = 0.4 pA | 04 Vv i | |-o4][ ma Clock Output Current OnICER) _ lon cu _ _ 100 uA TTL and POR! _ 5 _ Capacitive Load an CG _ pF TTL wip-up ~ 20 TTL 3-S and _ _ Capacitive Drive open Drain Cp a 100 pF CLOCK | s | 387KS16112/4 9600/14400 bps FAX MODEM MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS (Ta = 25 tv) Characteristic Symbol Min Tye Max Unit CS Set up time tes 0 ~ _ nSec RSI Set-up time tas 25 _ ~_ nSec Data access time toa ~ _ 75 nSec Data hold time four 10 _ nSec Coritrol hold time fac 10 - nSec Write data set up time twos 20 - nSec Write data hold time touw 16 _ _ nSec Phase 2 Clock high tech 100 - o nSec REL 388 ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM cs READ WRITE f ks =| os a tes. etc | l | 1 RSO - RS4 N\ f WATE A / TT y ox | / _}~tor wos t Ml ta to rd DO- D7 , a. 8085 Bus Compatible ( EN85 = L. ) cs READ f \ WRITE / S00 Heat baton RSO -RS4 XXXXXY OKXXXXXXXXKKN AXXXXK RIW toon y N { 62 oe wor = tory DO~-D7 b. 6500 Bus Compatible ( EN85 = H" } Fig1. MICROPROCESSOR BUS INTERFACE TIMING DIAGRAM OURS ES 389 ELECTRONICSKS16112/4 TECHNICAL SPECIFICATIONS 1. Configurations, Signaling Rates and Data Rates 9600/14400 bps FAX MODEM The various modem configurations with the corresponding modulation specifications are shown in Table 1. Table 1. Modulation Specifications Modulation Carrier Fre- Data Rate Data Rate No of Bits No. of Signal Configuration Scheme quency (Hz) (bps) (Symbots/Sec.)| per Symbol Points VAT 14400 TCM 1800 14400 2400 6 128 (KS16114) V.17 1200 TCM 1800 42000 2400 5 64 (KS16114) V.17 9600 TCM 1800 9600 2400 4 32 (KS16114) V.17.7200 TCM 1800 7200 2400 3 16 (KS16114) V.29 9800 QAM 1700 9600 2400 4 16 V.28 7200 QAM 1700 7200 2400 3 8 V.29 4800 QAM 1700 4800 2400 2 4 V.27 ter 4806 DPSK 1800 4800 1600 3 8 V.27 ter 2406 DPSK 1800 2400 1200 2 4 V.21 Ch2 300 FSK 1650, 1850 300 300 1 _ 2. Transmitted Data Spectrum The Transmitted data spectrum is shaped with the following characteristics : At 2400 baud a square root of 20% raised cosine filter is used. At 1600 baud a square root of 50% raised cosine filter is used. At 1200 baud a square root of 90% rained cosine filter is used. 390 ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM 3. Turn On Sequence The transmitter turn-on sequence times are shown is Table 2. Table 2. Turn-On Sequence Durations Configuration EPTE OFF : EPTE ON V.17 long train (all speeds) (KS 16114) 1383 ms 1600 ms V.47 Short train (all speeds) (KS 16114) 442 ms 350 ms V.29 (all speeds) 253 ms 441 ms V.27 ter 4800 bps tong train 708 ms 915 ms V.27 ter 4800 bps shart train 50 ms 257 ms V.27 ter 2400 bps long train 943 ms 41150 ms V.27 ter 2400 bps short train 67. ms 274.ms V.21 Ch2 300 bps < 400 us < 400 us 4. Turn-off Sequence The turn-off sequence consists of : - for V.17.( KS16114 ) approximately 14 ms of remaining data and scrambled ones followed by 34 ms. of silence. - for V.29 approximately as of remaining data and scrambled ones followed by 20 ms of silence - for V.27 ter approximately 10 ms of remaining data and scrambled ones ( 1200 baud ) and 7 ms of data and scrambled ones ( 1600 baud ) and 20 ms of silence. - for V.21 ch 2 the tranemitter turns-of within 7 ms after RTS goes inactive. . Data Encoding The data encoding is in accordance with CCITT recommendations V.17 (KS16114), V.29, V.27 ter, V.24 Channel 2, and T.3. 6, Equalization Required line equiization is implemented in V.17 (KS16114 ), V.29 and V.27 ter modes with an adaptive 48 - tap T/2 transversal equalizer. 7. Tone Generation The modem is capable of generating single or dual tones in the frequency range of 400 to 3200 Hz with a resolution of 0.15 Hz and accuracy of 0.01%. This feature allows the modem to function as a DTMF dialer. &. Transmit Level The transmitter output level is programmable from 0 dBm to -15.0 dBm and is accurate to + 1.0 dB. SAMSUNG 391 ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM 9. Scrambler / Descrambier The scrambler and descrambler are in accordance with CCITT recommedations V.17 ( KS16114 ), V.29 and V.27 ter. 10. Receiver Dynamic Range The receiver can operate with line signal levels. from 0.dBm to -43.dBm at the receiver analog input (RXAD. The RLSD threshold levels are programmable as follows : Turn-on : - 10 dBm to - 47 dBm ( default = - 43 dBm ) Turn-off : - 10 dBm to - 52 dBm ( defautt = - 48 dBm) 11. Receiver Timing The receiver can track a timing error in the remote transmitter of up to. + 0.35% : 12. Carrier Recovery The reciver can track a frequency offset up to + 10 Hz. 13. Received Data The serial received data output ( RXDO ) is clamped to a constant mark whenever RLSD is off. 14. Tone Detection The modem features three tone detectors two of which operate in all non high speed modes. The third tone detector operates in all receive modes. The three tone detectors can be cascaded to form a single 12th order filter. The filter coefficients of each tone detector are programmabie by the host. 15. Power Requirements The power requirements are as follows : + 5V + 5% @60 mA (typical : KS16112), @9S5 mA (Typical : KS16114) ~ 5V + 5% @14 mA (typical ) 16. Environmental Requirements The environmental redquirements are as follows: Temperature operating range from 0 - 70 degree centigrade. 392 SAMSUNGKS16112/4 9600/14400 bps FAX MODEM 17. Differences Between the Samsung KS16112/4 and Rockwell R9GDFX/R144EFX The KS161 12/4 is pin to pin-and software compatible modem devices that can be used to replace the Rockwell R96 DFX / R144 EFX modem. Functionally, the Samsung and Rockwell modems .are nearly identical. However, there are a few differences between the two that the user should be aware of. The KS16112/4 features an improved equalizer with 48 taps thus allowing better performance without a compromise equalizer. The KS16112/4 works over 7 Japanese links as weil as over all:-ElA lines. The equalizer is always T/2 fractionally spaced and there is no provision for a T-spaced equalizer. Also when reading the equalizer taps from the DSP it should be noted that the direction of the time axis is different from Rockwell's (i.e. the smallest address corresponds to the oldest data ). The tap coefficients between the Samsung KS16112/4 and Rockwell R96 OFX / R144 EFX are not interchangeable ( i.e. taps stored from the R9G DFX / R144 EFX cannot be loaded into the KS16112/4). instantaneous energy detector (IED ) does not include state 2. During DTMF detection the DEDT bit is the same as the DTDT bit. The following DTMF parameters are not available : Minimum cycie time Minimum dropout time (is always setto 5 ms) Frequency deviation, low group Frequency deviation, high group Maximum energy hit time Programmabie interrupt does not include dual port interface memory locations 0 and 10 th. * The 'O1 and iO2 functions in the RAM access are not avaliable in the interface memory. Therefore the sampling rate cannot be changed. The signal level should be derived from the AGC gain word since the average energy is not implemented. * The carrier detect turn - on and carrier detect turn - off thresholds function differently from the R96DFX./ R144EFX. The carrier thresholds should be changed by changing MAXG (MAXG is RO96DFX / R144EFX compatible ). Samsung modem does not support squelch extend. The host should complete high speed configuration change prior ta 30mS before receiving signal. + The host should not write data into DBFR duting RTS - to- CTS in HDLC mode. * Maximum speech energy works differently from Rockwell. Maximum speech energy sets the ratio between the total energy the DTMF tone energy before valid DTMF digits are detected. The default is 4000 hex which is 3B. 393KS16112/4 9600/14400 bps FAX MODEM SOFTWARE INTERFACE Communication between the modem and the hoet microprocessor is accomplished means of a dual port interface memory. The dual port memory consists of 32 8-bit registers that both the host microprocessor and the modem have access to. The hast can contro! modem operation by writing contro! bits or parameter values to the dual port interflaca memory. The host can algo monitor modem operation by reading status bite or data value ( such as the eye quality monitor value or EQM ) from the interface memory. The dual port read and write procedures are described in section 3. 1. Dual - Port Memory Map The memory map for the 32 - byte interface memory registers is shown in Table 3. These ragisters can be accessed during any host read or write cycle. In order to operate on a single bit or a group of bits, the host microprocessor must first read the desired register, set or reset the desired bits and then write the modified and-unmodified bits back inte the interface memory register. 2. Modem Interface Memory Bit Definitions This section describes in detail the function of ail bits, fields and registers in the interface memory. All dit, field or register names are listed in alphanumeric order. For each bit, field or register the convention R : B ( D ) is used to indicate the loc- ation of the term and its power up default value. R is the register number ( hexadecimal ), B is the bit or group of bits within that register and D is the associated power up default value. A default value of -' indicates that the bit state depands on modem operating conditions, thus, these bits do not truly have a power up default value. ABORT Abortfidle 09: 3(-) in the transmit mode when. ABORT is.set the modem will finish sending the current DBFR byte after which it will send continuaqus ones ( if ZCLMP is reset ) or continuous zeros ( if ZCLMP is set ). When ABORTis reset the modem will no! send continuous ones or zeros. in the receive mode when ABORT is set the modem has received a minimum of seven consecutive ones. ABORT must then be reset by the host. ADR 1 Address 1 04:0-7( 17h) ADR 1 is used to specify the modem's internal RAM address.to be read or written { data RAM if CRAM1=0 or coefficient RAM if CRAM1=1) during a RAM access cycle. The 16-bit real and imaginary data to be written into RAM or read out of RAM is ptaced in XOM1, XDL1 and YDM1, YDL.1. The address value in ADR also determines the data to be output by the modem via the eye pattern interface ( SEPXO and SEPYO ). At power-up, ADR1 defautts to 17h which corresponds to the rotated equalizer output ( normal eye patiern output ). nes 394 ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM ADR 2 Address 2 14:0-7(-) ADR2 is used to specify the modem's internal RAM address to be read or written ( data RAM if CRAM2 = 0 or coefficient RAM if CRAM2 = 1) during a RAM access cycle. The 16 - bit real and imaginary data to be written into RAM or read out of RAM is placed in XOM2, XDL2 and YOM2Z, YOL2. Table 3. Oual Port interface Memory Map Register Function nan Value ( Bin } Bit { Hex) 7 6 5 4 3 2 1 0 Interrupt Handling 1F ~ XX0-XX0 | PINTA _ ad PINTE | PIRQ ~ _ CSET iE -- 0X -0X- INTAZ | INTA1 | INTA2 ~ BDA2 | INTE1 ~ BDA1 Not Used 1D XXXXXKAX - _ _ ~ _ _ _ _ DTMF Status 1G | --es-e-- DEDT | OTDT | DOTS | DSDET OTMFW 1B XOOOOOKKK ~ _ _ _ ~ _ ~ _ 1A KOXOQOKK ~ _ _ _ - - _ - Not Used 19 OQOOKKK _ _ _ ~ ~ _ ~ 18 POQOQOOKX ~ - _ ~ > _ ~ 17 | XXMOOOCKK a _ ~ - ~ 16 JOOOKXKK _ - _ _ ~ _ _ _ 15 ocooon00 RA2 jAHEOF) _ BRT2 | WT2 | CRAM2 RAM Access 2 14 [ween ene RAM ADDRESS?2 ( ADR2 ) Control Status 1B | ween eee X RAM DATA2 MSB ( XDM2 ) and Parallel Data 12 fo wwe neeee X RAM DATA2 LSB ( XDL2 ) Buffer Wf eee --e- Y RAM DATA2 MSB ( YDM2 ) Wf +--+ ---- Y RAM DATA2 LSB ( YDL2 ) / DATA BUFFER ( DBFR ) wnt | 395 ELECTRONICSSee gma ienetgucticens KS16112/4 9600/14400 bps FAX MODEM Tabie 3. Dual Port Interface Memory Map ( Continued ) Register Function od Value (ain ) Bit ( Hex ) 7 | 6 5 4 3 2 1 0 Modem Status OF + = XXXX - - IED - - _ CTSB |} DCDB Not Used OE XXOOOOOKK ~ ~ _ _ _ _ _ oD --x0OOK | REC | PNDT |] ~ ~ ~ _ - High Speed Status oc XK sas e ee _ ~- DATM;}SCRiS| PNS P28 P1S | SILDL Pragrammabie 0B go00coo00 INTMSK Interrupt Control oA 90000000 ITRG INTML. INTADR High Speed Contra! and HOLC Control o9 ~ 000 ---- ORUR | SAVEQ |FRZEQ] ZCLMP} ABORT | EOHF | CRCE| FLG and Status Tone Detect and High Speed Control O08 wo XXX TD3 ToH2 TDi | CASC | PNSX 7 - 7 & status 07 00001000 RTSB | TRND | TOME |SHTRN} EPTE ~ HDLCE Modcle Control - 06 00010100 CONFIG 05 | to000101 | RAI | ~ | ~ | - | - | BRT1 | WT" | CRAM RAM Access 1 04 00010111 RAM ADDRESS2 ( ADR? ) Control & Status OS | -eeenne- X RAM DATA MSB ( XOM1 ) and Programmable O2 | -----+-- X RAM DATA LSB ( XDL1 } Intarrupt Contro! O1 fo cwnanneee Y RAM DATA1 MSB ( YDM1 ) OO | ----+-- Y RAM DATA1 LSB ( YDL1) a... 396KS16112/4 9600/14400 bps FAX MODEM AHEOF Automatic HDLC End of Frame 16 :6(0) When AHEOF is set wtille in HDLC transmit mode, the modem automatically generates and tranamite the FCS (frame check sequence ) and at least one closing flag upon detecting an underrun condition in thetranamission of data, AHEOF is vatid only when the modem is configured for HDLC mode ( HDLCE is set ). BDA1 Buffer Data Available No.1 1E:0(-) When BDA has been get by the modem, the. modem has either written or read buffer data to/from the YDL41 register. The satting of the BDA( bit can set-up to cause an iRQ interrupt ( see INTE1 and INTA( bit descriptions ). When the host microprocessor reads or writes the YDL1 register, the modemautomatically resets the BDA bit. BDA2 Buffer Data Available No.2 1E:3(-} When BDA2 has been set by the modem and the modem is in paraiie! data mode ( PDME is set), with or without HDLC enable, transmit data has been read fram DBFR by the modem { transmit mode ) or received data has been written by the modem into DBFR ( receive mode ). When the modem is in serial mode ( PDME is resot ), the modem sets BDA2 whenever data has been read from or writen into YDL2. The satting of the BDA2 bit can be set-up to cause an [RQ interrupt ( see INTE2 and INTA2 bit descriptions ). When the host microprocessor reads or writes the YDOL2/DBFR register, the modem automatically resets the BDA2 bit. BRT1 Baud Rate 1 06:2(1) When BRT1 is set, RAM access for ADR1 takes place at the baud rate ( the baud rate depends on the selected configuration ). Otherwise it occurs at the sample rate ( 9,600HZz). This bit must be zero in FSK, Tone or DTMF receive modes. BRT2 Saud Rate 2 16:2(0) When 8RT2 is set RAM access for ADR2 takes place at the baud rate ( the baud rate depends on the selected configuration ). Otherwise it occurs at the sample rate ( 9,600Hz ). This bit must be zero in FSK, Tone or OTMF receive modes. CcASC Select 12th Order Filter Cascade 08:4(0) When CASC is set, the tone detectors are cascaded to form one 12th order filter ( TD3 is the output status bit for the 12th order fitter cascade ). When CASC is reset, the three tone detectors operate as three paraifel independent 4th order fitters. The 12th order mode is only valid in the FSK and DTMF receiver mode when RTS is off and RTSB is resut. 397 ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM CONFIG Configuration 06 :0-7(14) The Contents of CONFIG. determine the modem operating configuration. The following table lists all valid 8 - bit configuration codes and the correaponding selected contiguration : ( Hewndec i ') Selected Modem Configuration 31 V.17 14,400 bps TCM ( KS16114 ) 32 V.17 12,000 bps TCM ( KS16114 ) 34 V.17 9,600 bps TCM (KS16114) 38 V.17 7,200 bps TCM ( KS16114) 14 V.29 9,600 bps 12 V.29 7,200 bps 44 V.29 4,800 bps oA V.27 ter 4,800 bps oo V.27 ter 2,400 bps 96 Transmit : V.21 Ch 2 300 bps (PSK) Receive : V.21 Ch 2 300 bps (FSK) and tone detector Transmit : V.21 Ch 2 300 bps (FSK) 21 Receive : V.21 Ch 2 300 bps (FSK), tone detector and DTMF receiver 86 Transmit : Dual tone Receive : Tone detector At power up, the modem defaults te V.29 9600 bps. After changing the contents of CONFIG, the host = * must set the CSET bit to instruct the modem to carry out the configuration change. When the configu- ration change has been completed, the modem resets the CSET bit. CRAM1 Coefficient RAM 1 Select 06:0(1) When CRAM1 is set, ADR1 addresses coefficient RAM and when CRAM( is reset, ADR1 addresses data RAM. This bil must be set according to the desired RAM address. CRAM2 Coefficient RAM 2 Select 18:0(4)KS16112/4 9600/14400 bps FAX MODEM When CRAN2 is set, ADR2 addresses coefficient RAM and when CRAM2 is reset, ADR2 addresses data RAM. This bit must be set according to the desired RAM address. CRCE Cyclic Redundancy Check Error 08 :4{-) When CRCE and EOHF are both set the received frame is erroneaus. if CRCE is reset and EOHF is set the received frame is correct. CRCE becomes valid immediately before EOHF is set. CSET Configuration Set-up 1F:0(0) The host informs the modem to implement a configuration change by setting the CSET bit. The host sets the CSET bit after vsriting a configuration code into the CONFIG bits ( register 6:0-7) or after changing a bit in register 7 : 0 - 5. The CSET bit is reset by the modem after the configuration change has been completed. cTrss Clear to Send Bit OF :1(-) When CTSSB is set the modem has completed the training sequence transmission and any data present at TXDI ( if POME is reset ) or DBFR ( if PDME is set ) will be transmitted. CTSB parallels the operation ofthe CTS output pin. DATM Data Mode 0C :5(-) Status bit DATM is set. by the modem to indicate that the transmitter or receiver is in data mode. Data mode implies that the modem is in a state where user data may be transmitted or received. DBFR Transmit/Receive Data Buffer 10:0-7(-} When the modem is configured parallel data made ( PDME is set ), the host microproceasor reads parallel received data from DBFR or writes parallet transmit data into DBFR, DBFR data is tranemitted bit 0 first. Transmission and reception of data is synchronized by poiling the BDAZ status bit or it may be conducted under IRG inter- rupts (see INTE2 and INTA2 hit descriptions ). ee EEA 998KS16112/4_ 9600/14400 bps FAX MODEM ocpe Data Carrler Detect Bit OF :0(-) Status bit OCDB is set by the modem when the receiver has completed the reception of a training sequence or has detected energy above the RLSD turn-on threshold and is receiving data. OCDB parallels the oper- ation of the RLSO output pin. DEDT OTMF Early Detection 1G: 7(-} Status bit DEDT is set by the modem when ihe received signal may be a DTMF signal but the full determi- nation has not yet been made. This bit is reset by the modem after DSDET is set or if the signal fails to meet any of the DTMF signal requirements. DOTS DTMF On Time Satisfied 10:8 (-) Siatus bil DOTS is set by the modem when the on time requirements for a DTMF signal is satisfied. The modem resets this bit after OSDET is set or if the received signal fails ta meet any of the DTMF signal requirements. DSDET DTMF Signal Detected 10:4(-} Status. bit DSDET is set by the modem when the DTMF signal that satisfies all the detection requirements has sbeen detected. After detection, this bit must be reset by the host. DIDT Dual Tone Detected 10:6(-) When a signal that meets ail OTMF requirements except on time, off time any cycle time is detected, the modem sets status bit DTDT. The encoded. DTMF value is available at this time in OTMFW. This bit is reset by the modem after DSDET is set or if the signal fails to meet any of the OTMF dection require- ments. DTMFW OTMF Output Word 16: 0-3(-} The encoded DTMF output is written into this field when a DTMF tone is being received ( status bit OSDET is sat by modem ). The DTMF output codes are : a _ 400 SAMSUNGKS16112/4 9600/14400 bps FAX MODEM DTMF Encoded OTMF Encoded Symbol Output Symbol Output 4 0 3 8 4 1 6 9 7 2 9 A - 3 # B 2 4 A Cc 5 5 B D 8 6 Cc E 0 7 DB F EOHF End of HDLC Frame 09:2(-) in the transmit mode when AHEOF is reset, the EQHF bit is used (o instruct the modem to send the 16 - bit FCS and ending flag of a HOLC frame. The host must sat the EOHF hit after the modem has read the last byte of the frame from DBFR. The modem will then reset EQHF after generating and sending the end of frame sequence. if AHEOF is set, the madem will set EOHF and outputthe 16-bit FCS and at least one ending flag when an undarrun condition occurs. EOHF is reset when the frame closing flag is sent. In the receive mode, the modem set EOHF when it has received a frame ending flag and updates CRCE. The host must raset EOHF before the ending flag of the following frame. EPTE Each Protector Tone Enable 07:3(1) When this bit is set, the modem transmits unmodutated carrier for 187.5 ms followed by 20 ms of silance prior to sending the training sequence. With EPTE reset the modem will immediately send the traning sequence except in the V,29 configuration. in the V.29 configuration the modem precedes the training sequence with 20 ms of silence. FLG FLAG Mode 03 :.0(0) When FLG is set while in the HOLC tranamitter mode, the modem transmits a flag sequence. in the HDLC receive mode, the modem sets the FLG bit when it receives a flag sequence. SAMSUNG 401 ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM FRZEQ Freeze Equailzer 09:6(0) When control bit FRZEQ is set, equalizer tap updating is disabled freezing the equalizer tap coefficients at their current value. HDLCE HDLC Enable 07:0(0) When contro! bit HOLCE is set, the modem performs HDLC framing. To activate or deactivate HDLC. mode the host must set or rest HDLCE and POME and then set the CSET bit to instruct the modem to carry out the configuration change. jED instantaneous Energy Detector OF :.6-7 (0) IED is a fast responding energy detection status indicator. The received signal level is indicated by the following codes : 1ED Energy Level 0 No Energy Present 1 Invalid 2 invalid 3 Energy Above Turn-On Threshold INTA1 Interrupt Active 1 1E:6(-) if BDA. 1 is set by the modem when INTE 1 is set, the modem asserts IRQ and sets status bit INTA 1 to indicate that BDA 1 caused the interrupt. The host resets INTA 1 by reading or writing register 0. INTAZ Interrupt Active 2 4E:7(-) lf BDA 2 is set by the modem when INTE 2 is set, the modem asserts IRQ and sets status bit INTA 2 to indicate that BDA 2 caused the interrupt. The host resets INTA 2 by reading or writing register 10h. INTAOR Interrupt Address GA:0-4{(0) The contents of INTADR. specify the register number on which the programmable interrupt will take effect on. The host register address and the corresponding INTADR 5 - bit codes are provided in the table. AMSUNG 402 ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM Host Register INTADR Host Register INTADR { Hex } (Hex) {Hex} ( Hex } 01 10 1 18 02 01 12 09 03 1 13 19 04 02 14 OA 05 12 15 1A os 03 16 OB 07 43 17 1B 08 04 18 oc og 14 19 1c 05 1A oD OB 45 1B 1D oc 06 ic OE oD 16 4D. 1E oE 07 1 OF oF 7 WF iF INTE 1 interrupt Enable 4 1E:2(0) The modem will assert IRQ and sat INTA 1 when BDA 1 is set by the modem if control bit INTE 1 is set (interrup! enabie ). If INTE 1 is reset ( interrupt disable ) IRQ and INTA 1 are unaffected by BDA 1. INTE 2 interrupt Enable 2 1E:5(0) The modem will assert IRQ and set INTA 2 when BDA 2 is set by the modam if control bit INTE 2 is set (interrupt enabled ). If INTE 2 is reset ( interrupt disabled ) IRG and INTA 2 are unaffected by BDA 2. INTML interrupt Mask Logic (AND/OR Logic) 0A: 5( 0) When control bit INTML is set when programmable interrupts are enabled ( PINTE is set), the modem will logically AND the contents of the interface memory register specified by INTADR with the contents of INTMSK, thus the IRG condition will be met if all the bits in the specified register masked by INTMSK are set. When control bit INTML is reset when prograrnmable interrupts are enabled ( PINTE is set ), the modem will logically OR the contents of the interface memory register specified by INTAOR with the contents of INTMSK, thus the IRQ condition will be met if any the bits in the specified register masked by INTMSK are set. Note that [TRIG places additional interrupt triggering requirements on the programmabie interrupt which must also be met in order for IRG to be asserted by the modem. AMSUNG ELECTRONICS 403KS16112/4 9600/14400 bps FAX MODEM INTMSK interrupt Bit Mask 0B :0-7(0) Abit mask function is performed by this byte on the register specified by INTADR for the prgrammable interrupt. The INTML bit determines whether a logical AND or a logical OR masking operation is performed with the contents of the ragister specified by INTADR and the contents of INTMSK. Note that ITRIG places additional triggering requirements which must also be met in order for IRQ to be asserted by the modem. Additionally, programmable interrupts must be enable ( PINTE set) and PIRQ must have been reset by the host prior to the occurrence of the interrupt condition in erder for to be asserted by the modem. ITRIG Interrupt Triggering OA:6-7(0) ITRIG places triggerin larity requirements on the programmable interrupt which must be met in order for the modem to assert IRQ. The four possible [TRIG settings and the corresponding functions are described below. ITRIG (Bin) Description oo Continous interrupt when interrupt conditon ture 61 Interrupt when interrupt condition from false to true 10 Interrupt when interrupt condition from true to false 4 Interrupt when any change in interrupt condition ORUR Overrun / Underrun 08: 7(-} During HDLC paraliel mode data transmission ( HDLCE and PDME are set ) the host microprocessor must load DBFR with consecutive transmit data bytes within eight bit times of each other. if more than eight bit times elapse between transmit data bytes being written into OBFR, an underrun condition is detected by the modem and is indicated by the ORUR and ABORT bits being set. When an underrun condition occurs, the modem clamps the transmit data to ones. Tha clamping of transmit data will continue until the host microprocessor resets the ABORT bit. When the host microprocessor resets the ABORT bit, the modem will complete the transmission of the current group of eight binary ones and will then proceed to start the transmission of the next frame if BA2 has reset ( the host reading or writing DBFR cause BA2 to reset }, otherwise, the modem will transmit continuous HDLC flags. In the receive mode, the modem indicates an overrun condition by setting ORUR. An overrun condition occurs when the host microprocessor fails to read the received data in DBFR before it is overwritten by the next received byte. The host must reset the ORUR bit before the next received data overrun condition can be indicated by the modem setting ORUR. 404 SAMSUNGKS16112/4 9600/14400 bps FAX MODEM The ORUR function is disabled if the AHEOF control bit is set. The ORUR bit is valid only while the modem is configured for HDLC mode ( HDLCE is set ). PIS P1 Sequence oc: 1(-)} In the high speed tranamit mode ( all data configuration except FSK ), the modem sets P1S to indicate that the P1 sequence is being transmitted. The P1 sequence is also referred to as the echo protector tone and consists of 187.5 ms of unmodulated carrier followed by 20 ms of silence. In the recelve mode the P15 bit has no significance. P2S P2 Sequence OC: 2{-} in the high speed transmit mode ( all data configurations except FSK ), the modem set P2S to indicate that the PZ sequence is being transmitted. In the receive mode, the modem sets P2S to indicate that the modem has detected an incoming P2 sequence and is in the process of searching fot the P2 to PN transition. PDME Parallel Data Mode Enabie 07:5(0) When the POME control bit is set, the modem is configured for parallel data mode. During parallel data mode transmission, the modem accepts transmit data from DBFR ( 10: 0 - 7) rather than the TXD! serial input. During the receive mode the modem simultaneously outputs the received data to DBFR (10 :9-7) and the RXDO serial oufput. HOLC framing is performed only in parallel data mode. When POME is reset, the modem is in seria! data mode and the modem accepts transmit data via the TXDI serial input and issues received data via the RXDO serial output. When the host microprocessor sets or resets the PDME bit, it must also set the CSET bit to instruct the modem to carry aut the configuration change. PINTA Programmable Interrupt Active 1F:7{-) When programmable interrupts are enabled ( PINTE is set ). PINTA is set by the modem when the interrupt condition specified by INTMSK, INTADR, ITRIG.and INTML is true. The modem asserts IRQ if PIRQ has been previously reset by the host. PINTA is automatically reset when the host resets PIRQ. PINTE Programmable Interrupt Enabie 1F:4(0) When PINTE is set and the interrupt condition as specified by INTMSK, INTADR, ITRIG and INTML is true, the modem asserts IRQ if contro! bit PIRQ has been previously reset by the host. Bits INTMSK, INTADR, ITRIG, INTME, and PIRQ have no effect on IRQ and PINTA when programmable interrupts are disabled ( PINTE is reset ). PIRQ Programmable Interrupt Request 1F:3(-) When PINTE is set and the interrupt condition is true as specified by INTMSK, INTADR, ITRIG and INTML, the modem asserts IRQ if control bit PIRQ has been previously reset by the host, PIRQ is set by the modem when the programmable interrupt condition is true. The host must reset PIRQ after servicing the interrupt. The modem will not assert IRQ when an interrupt condition is met unless PIRQ is reset. IV 405 ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM PNDT PN Detected 0D: 6{-) The modem receiver sets the PNDT status bit to indicate that it has detected the begining of the PN segment of the training sequence. PNDT remains set during the reception of the PN segment and is reset at the end of the PN segment. PNS FIN Sequence 0C:3(-) in the high epeed transmit mode, the moder sets the PNS bit to. indicate that the PN segment of tha training sequence is being transmitted. in the high speed receive mode, the PNS bit is set by the modem while it is receiving the PN segment of the training sequence. PNSX PN Success 08: 3{-) The modem sets the PNSX status bit when it has successfully trained at the end of the PN segment of the high speed training sequence. if training fails, PNSX is reset. PNSX is valid after the OCDB bit is set. RA 1 RAM Acceas 14 05:7(1) When the host sets the RA 1 control bit, the modem accesses the RAM addressed by ADR 1 and the CRAM! bit and performs a read or write as determined by the WT1 control bit. RA2 RAM Access 2 16:7{(1) When the host sets the RA 2 control bit, the modem. accesses the RAM addressed by ADR 2 and the CRAN2 bit and performs a read or write as determined by the WT2 control bit. REC Recelve State 0D:7(-) The madem sets the REC status bit to indicate that the modem is in the raceive state. When the REC bit is reset, the modem is in the transmit state. RTSB Request to Send Bit 07:7(0) The modem begins a transmit sequence when the RTSB bil is set or the RTS input pin is driven low, The modem will continue to {ransmit as long as RTSB is set or RTS is low. SAVEQ Save Equalizer 09:6(0) When the SAVEG bit is set by the host, the taps of the adaptive equalizer are not cleared when entering the training state, thus saving the equalizer tap coefficients obtained during the previous training. 406 URES SE? ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM SCR1S Scrambled Ones Sequence OC: 4(-) in the high speed transmit made, the modem sets the SCR1S status bit to indicate that the modem is sending the scrambled ones sequence. in the high speed receive mode, the modem sete the SCR1S status bit to indicate that the modem is receiving the scrambled-ones sequence. in the receive mode, SCR1S Is reset to indicate thatthe modem is not receiving the scrambled ones sequence. SHTRN Short Train 07: 449) The KS16114 supports V.17 and V.27ter short train while the KS16112 supports V.27ter shor train. To utilize these short train modes, the receiver must first be trained using a long training sequence at the same speed as the subsequent short training sequence. After the long training sequence has been success- fully received, the host may configure the modem for short train mode by setting SHRTN. At this time the host must also set the SAVEQ bit to preserve the equalizer tap coefficients obtained during the long train. The CSET bit must be set after setting the SHTRN and SAVEQ bits to instruct the modem to carry out the new configuration. SILIDL Silence / idle 0C :0(-} When in the high speed transmit mode, the modem sets the SILIDL status bit to indicate that the modem is transmitting silence. in the high speed receive mode, the modem sets the SILIDL status bit to indicate that the modern is in the idle state waiting for energy to be received. To1 Tone Detector No.1 08:6(-) The TO1 bit is set when the modem detects energy above the turn-on threshold of tone detector number one. As the default, tone detector number one is programmed to detect energy in the 2100 Hz + 25 Hz frequency range. All three tone detectors (TD1, TD2, and TD3 ) have host programmable filter coefficients. Tone detector number one is operational in FSK, FSK and OTMF receiver and Tone configurations and whenever the modem is not transmitting. TD2 Tone Detector No.2 08: 6{-) The TD2 bit is set when the modem detects energy above the turn on threshold of tone detector number ona. As the default, tone detector number two is programmed to detect energy in the 1100 Hz + 30 Hz frequency range. All three tone detectors (TD1, TD2, and TD3.) have host programmable filter coefficients. Tone detector number two is operational in FSK, FSK and DTMF receiver and Tone configurations and whenever the modem is not transmitting. 407 WAMSUNG ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM TD3 Tone Detector No.3 08:7{-) The TD3 bit is eet when the modem detects energy above the turn-on threshold of tone detector number one. As the default, tone detector number three is programmed to detect energy in the 462.Hz + 14 Hz frequency range. All three tone detectors (TD1, TD2, and TD3 ) have host programmabie filter coefficients. Tone detector number two is operational in FSK, FSK and OTMF receiver and Tone configurations and whenever the modem is not transmitting. TO3 serves as the output status indicator when the CASC bit is set forming a 12th order filter using TD1, TO2 and TDS ( see CASC bit description ). TRND Training Disable 07:6(0) When the host sets the TRND bit while in the receive modo, the modem will not recognize the training sequence and will not enter the training state. in the transmit. mode, the modem will nol transmit the training sequence when the RTS input is activated or the RTSB bit is sot. wT RAM Write 1 06:1(0) When the WT1 contro! bit is set, the modem reads 16bits data from the Y RAM Data 1 registers ( YOM 1, YDL 1 ) and writes it into its internal RAM as addressed by ADR1 and CRAM1 immediately following the host setting the RA1 control bit. if the MSB of ADR1 is a zero, the data is copied into X RAM, if the MSB of ADR1 is a one, the data is copied into Y RAM. When WT1 is reset the modam reads real and imaginary 16 - bit data from its internal RAM locations as addressed by ADR1 and CRAM1 and writes it into the X RAM Data 1 registers (XDM1, XDL1) and Y RAM Data 1 registers ( YDM1, YDL1 } immediately after the host sat the RA1 control bit. WT2 RAM Write 2 16:1(0)} When the WT2 control bit is.set, tha modem feads 16bits data from the Y RAM Data 2 registers ( YDM.1, YDL 1) and writes it info its internal RAM as addressed by ADR2 and CRAM2 immediately following the host setting the RA2 control bit. if the MSB of ADR2 is a zero, the data is copied into X RAM. If the MSB of ADR2 is a one, the data is copied into Y RAM. When WT2 is reset the modem reads real and imaginary 146 - bit data from its internal RAM locations as addressed by ADR2 and CRAM2 and writes it into the X RAM Data 1 registers (XDM1, XDL1 ) and Y RAM Data 1 registers ( YOM1, YDL1 ) immediately after the host set the RA2 control bit. XDL1 X RAM Data 1 LSB 02: 0-7(-) XDL1 contains the least significant byte of the 16-bits X RAM1 Data word used while reading XRAM tocations. XDL2 X RAM Data 2 LSB 120-7 {-) 408 Etec erKS16112/4 9600/14400 bps FAX MODEM XDL2 contains the feast significant byte of the 16bits X RAM2 Data word used while reading XRAM locations. XDM1 X RAM Data 1 MSB 03.:0-7(-) XDM1 contains the most significant byte of the 16bits X RAM1 Data word used while reading XRAM locations. XDM2 X RAM Data 2 MSB 13:0-7(-) XDM2 contains the most significant byte of the 16bits X RAM2 Data word used while reading XRAM locations. YDLt Y RAM Data 1 LSB 00:0-7(-) YDAL1 contains the least significant byte of the 16bits Y RAM1 Data word used while reading YRAM locations. YDL2 Y RAM Data 2 LSB 10:0-7(-) YDAL2 contains the least significant byte of the 16bits Y RAM2 Data word used while reading YRAM locations. YDM1 Y RAM Data 1 MSB 01:0-7(-) YDM1 contains the most significant byte of the 16bits Y RAM1 Data word used while reading YRAM locations. YDM2 Y RAM Data 2 MSB 11:0-7(-) YDM2 contains the most significant byte of the 16bits Y RAM2 Data word used while reading YRAM locations. ZCLMP Zero Clamp 09:4(0) When both ABORT and ZCLMP are set the modem will transmit continuous zeros. When ZCLMP is reset and ABORT is set the modem will send continuous ones. With ABORT reset ZCLMP is disabted. 3. Digital Signal Processor ( DSP ) RAM Access The interna! OSP random access memory (RAM) is organized into two parts : real (XRAM ) and imaginary (YRAM ). The hast processor has access to both the XRAM and the YRAM. SAMSUNG 408KS16112/4 9600/14400 bps FAX MODEM 3.1 Interface Memory Access to DSP RAM The dual port interface memory is used during host to OSP RAM or DSP RAM-to-host data transfers. The DSP RAM address accessed is determined by the address stored in the DSP interlace memory ( ADRx, where X= 1 or 2). The words ( 16 bits each ) are transferred once each baud or once each sampling period ( determined by BRT, bit, where X = 1 of 2). The sampling rate is 9,800 Hz for all configurations, but the baud tate or symbol rate te determined by the selected configuration ( see Table 1}. Two RAM access bits in the modem interface memory instruct the DSP to access the XRAM and/or the YRAM. The host first sets the RA 1 and/or RA2 bits which are tested by the OSP each baud or sample period, as determined by the corresponding BRT; bit setting. The OSP RAM access functions, codes and registers are listed in Table 4. Table 4. Modem DSP RAM Access Codes Item No. Function BRT, CRAM, ADR, X,Y 1 Received Signal Samples 0 Qo 18 x 2 AGC Gain Word 0 1 15 x 3 Carrier Detect Tum on Threshold 0 1 37 x 4 Carrier Detect Turn off Threshoid 0 1 87 x 5 Receiver Sensitivity, MAXG 5 1 24 X 6 Tone 1 Frequency 0 1 21 x Tone 1 Transmit Output Level 0 6 22 x B Tone 2 Frequency 0 1 22 x 9 Tone 2 Transmit Output Level 0 0 23 x 10 Transmit Output Level 0 0 24 x 1 Equalizer Tap Coefficients 4 4 3A ~ 69 xX, 12 Rotated Equalizer Output, Eye Pattern 4 4 V7 X,Y 13 Decision Points, Ideal Points 1 0 7 X,Y 14 Error Vector 1 1 1D x, YKS16112/4 9600/14400 bps FAX MODEM Tabie 4. Modem DSP RAM Access Codes ( Continued ) Item No. Function BRT, CRAM, ADR, KY 15 Rotation Angle 4 1 oc Y 16 Frequency Correction 1 4 18 xX 17 Eye Quality Monitor, EQM 1 4 op x 18 Minimum DTMF On Time QO 1 1F x 19 Minimum DTMF Off Time 9 0 1F xX 20 Negative Twist Control ( DTMF ) 0 o 4 x 21 Positive Twist Control ( DTMF ) 0 0 SE Y 22 Number of Additional Flags ( HOLC ) o 1 85 Y 5 ~ 2A 23 TD1 Tone Detector Coefficients 0 4 25-2 x AS -AA Y 2B -30 24 102 Tone Detector Coefficients Q 1 x AB - BO Y 25 TD3 Tone Detector Coefficients 0 1 34-36 x Bt - BG Y 26 Maximum Speech Energy 0 4 iE x 3,2 Host OSP Read and Write Procedures The modem DSP RAM consists of four memory banks : data RAM real, data RAM imaginary, cofficient RAM real and coefficient RAM imaginary. When accessing the main RAM the desired RAM access code needs to be written into ADR, (X = 1,2), with 1 and 2 referring to RAM access 1 and 2 respactively. The RAM location is specified by bits 0-6 and bit 7, when zero, specifies a real ( XRAM ) RAM location, and, when one, an imaginary (YRAM ) RAM location. The BRTx ( X = 1,2 ) bit controls whether the data access takes place at the baud rate or the sampling rate. Tha CRAM, controls whether the data RAM ( CRAM, is reset ) or the coefficient RAM ( CRAM, is set } is accessed. in parallel data. mode ( POME is set 1) only RAM access associated with RAM Address1 is available since register 10h is used as the transmit/receive data buffer ( DBFR ). ; Ant AMSUNKS16112/4 | 9600/14400 bps FAX MODEM 3.3 DSP RAM Read Procedure The RAM read procedure is 4.32 bits transfer from DSP RAM to the interface memory. Both the X and Y RAM data is transferred simultaneously. The sequence of events is as follows : Before accessing the DSP interface memory first reset RA1 and/or RA2, then reset BOA1 and/or BDA2 by reading YOL1 and/or YDL2. Reset WT1 and/or WT2 to instruct the modem that a RAM read operation will take place when RA1 and/ar RA2 is set. e Load the RAM address into ADR1 and/or ADR2 and then set CRAMy and BRT to desired values, where x = 1 of 2. * Set RA1 and/or RA2 to instruct the modem to perform the RAM read operation. e BDA and/or BDA2 will be set when the modem has completed the transfer from the DSP RAM to the interface memory RAM data registers. * When the modem sets BDA1 and/or BDA2 IRQ is also asserted if INTE1 and/or INTE2 is set. INTA1 and/or INTA2 is set to inform the host that BDA1 and/or BDA2 was the source of the interrupt. In the order listed, read XDM1, XOL1, YDM1, and YDL1 ; and/or XDM2, XDL2, YOM2 and YDL2. Reading YDL1 resets INTA1 and BDA1 and/or reading YDL2 resets INTA2 and BDA2 causing IRQ to go inactive if no other interrupts are pending. 3.4 DSP RAM Write Procedure Tha DSP RAM write procedure is a 16 bits transfer from the interface memory to the OSP RAM, Thus X RAM data or Y RAM data can be transferred each baud or sample time. The sequence of events is as follows : Before writing to the DSP interface memory first reset RA1 and/or RA2 and then reset BDA1 and/or BDAZ by reading YDL1 and/or YDL2, respectively. Write the RAM address into ADR1 and/or ADR2 and then set CRAM1 and WRT1 and/or CRAM2 and BRT2 to the desired values. STs Ate ELECTRONICSKS16112/4 9600/14400 bps FAX MODEM Set WT1 and/or WT2 to instruct the modem that an RAM write operation will take place when RA1 and/or RAZ is set. * Write the desired data into the interface memory RAM data registers YDI1 and YOM1 and/or YDL2 and YDM2. Set RA1 and/or RAZ to instruct the modem ta perform the RAM write operation. * BDA1 and/or BDA2. will-be set when the transfer form the interface memory RAM data registers into RAM has been completed. * When BDA1 and/or BDAZ is set, IRQ is also asserted if INTE1 and/or INTE2 is set. * Reset INTA1 and BDA and/or INTA2 and BDA2 by reading or writting to YDL1 and/or YDL2. Reading or writting YOL1 and/or YDL2 also causes IRQ to return to the inactive state if no other interrupts are pending. 4. Parallel Data Transfers Parallel data transfers use register 10h in the interface memory ( DBFR ). The modem and the host can synchronize data transfers by observing the BDA2 bit in the interface memory. Parallel data transfers may also be performed under IRQ interrupts (see INTE2 and INTA2 bit descriptions ). 4.1 Receiving Paraltel Data During parallel data mode ( PDME is set}, the modem writes received data ta DBFR once every eight bit times. When received data is available the modem sets the BDAZ bit. The BDA2 bit is automatically reset when the host reads DBFR. When BDA2 is set the host must take action within eight bit times or the data will be lost since the modem will overwrite DBFR ( OBFR overrun condition ). The ieast significant bit of register OBFR represents the oldest data and the most significant bit represents the newest data received. 4.2 Transmitting Paraliel Data During parallel data mode ( POME Is set ), the modem reads OBFR once every eight bit times. The BDAZ bit is set by the modem when DBFR has been read, thus requesting the next transmit data byte. The BDAZ bit is reset automatically when the host writes to DBFR. When BDAZ is set the modem must respond within eight bit times or the modem will retransmit the data in register DBFR ( DBFR underrun conition ). 413KS16112/4 9600/14400 bps FAX MODEM The LSB ( bit 0) in DBFR is transmitted firet in time and MSB ( bit 7 ) is tranamitted last. &. Programmable interrupt Feature This feature makes it possible for the host to select an interrupt to occur on any combination of bits within an interface memory register. 5.1 Programmable interrupt Bits The programmable interrupt routine is executed at the sampling rate. ( 9,600Hz ) in all configurations. When the host sets the PINTE bit and the modem sets the PINTA bit, IRQ goes active ( low ) when the interrupt condition is met. The PIRQ bit must be reset by the host after the interrupt service since this bit will not be reset by the modem and no further interrupts will occur until PIRQ has been reset. An interrupt may occur due to a single interface memory register based on any combination of bits. The register is selected by specifying the interrupt Address in the INTADR field. The interrupt bit mask register ( INTMSK ) selects the bits to be tested in the interface memory register specified by INTADR. .2 Programmable Interrupt Operation Modes There are two operating logic modes ( AND/OR ) with each having four trigger options. The triggering option is selected by the ITRIG field and the logic ( AND/OR ) is selected by INTML. 6. DSP RAM Parameter Definitions and Scaling In the following the DSP RAM parameters are described as they appear in Table 4. Received Signal Sample / Received Signal Sample ( FSK ) Format : 18 bits, signed two's complement Equation : Vine (V) # [CAD Sample Word ) hj * (3.03/12 ) Vext = Vinr + LOG 10" (( AGC Gain (dB) ) {20} AGC Gain Word Format : 16 bits, unsigned Equation : AGC Gain (dB ) = 50[ 1 - (AGC Gain Word ) h/ 2] FEE TE 414KS16112/4 9600/14400 bps FAX MODEM Carrier Detect Turn-On Threshold Carrier Detect Turn-Off Threshold Receiver Sensitivity, MAXG Format: 16 bite, two's complement, positive value Equation : Carrier Detect Turn-on Threshold = 2185 [ 10 (TON*M9) Carrier Detact Turn-off Threshold = 2185 [ 10 (TOF +45) Receiver Sensitivity, MAXG = 685.36 [ 50 - Gain Limit (dB) ] Where : TON is the turn-on threshold in dB/10 TOFF is tha turn-off threshold in dB/10 MG = 50 [1 - (MAXG )h/2') 10 MAXG is programmable, default = OFCOh (4032) Tone 1 Frequency Tone 2 Frequency Format : 16 bits, unsigned Equation : N = 2"* / 9600 * ( Frequency in Hz ) Tone 1 Output Level * Tone 1 Output Level Format : 16 bits, two's complement, positive value . Total power is the resuit of both tone 1 power and tone 2 power added together. These can be independently calculated using the equation for transmit output level ( Tranemit output level ). SUE T aS 415KS16112/4 9600/14400 bps FAX MODEM Transmit Output Level Format: 16 bits, two's complement, positive Equation : Transmit Output Level = 18426 [ 10 (P/29)) Where : Po = Output Power ( dBm ) into 600 Q Equailzer Tap Coefficients Format : 16 bits, signed two's complement, compiex These numbers are complex.and thus require two write operations per tap. One for the real part and one for the imaginary part. Rotated Equalizer Output, Eye Pattern * Decision Points, ideal Points Format : 16 bits, two's complement, complex Error Vector Format : 16 bits, two's complement, compiex This is the difference between the received point and the nearest ideai point * Rotation Angle Format : 16 bits, two's complement Equation : Rotation Angle { degree ) = [ ( Rotation Angle Word ) h/ 2" } * 180 degree Frequency Correction Format : 16 bits, two's complement Equation : Frequency Corr. (Hz) = { (Frequency Corr. Word ) h/2"* | * baud in Hz 416KS16112/4 * Eye Quality Monitor ( EQM ) Format Minimum OTMF On Time Format Range Minimum OTMF Off Time Format Range Negative Twist Control! Format Range Positive Twist Control Format Range 9600/1440 bps FAX MODEM 16 bits, two's complement, positive This is the filtered squared magnitude of the error vector. 16 bits, two's complement, positive Oto 7FFFh 16 bits, two's complement, positive Oto 7FFFh 16 bits, two's compiement, positive Oto 7FFFh 16 bits, two's complement, positive Oto 7FFFh These parameters control the acceptable twist ( negative or positive } for the DTMF signals. Ta increase the acceptable twist ( negative or positive ) level decrease this parameters from its default vaiue. Number of Additional Flags ( HDLC } Format Equation : 16 bits, two's complement, positive desired number of flags - 4 This parameter specifies the number of flags between frames or at the end of the final frame in the HDLC mode. 417irae eae ee ae KS16112/4 9600/14400 bps FAX MODEM * TD1 Tone Detector Coefficient TO2 Tone Detector Coefficient * TO3 Tone Detector Coefficient Forrnat : 16 bits, two's compiement These parameters control the frequency responses of the three tone detec- tors. See Section Tone Detection for a detailed description of the structure of the tone detectors. Maximum Speech Energy Format : 16 bits, two's complement This parameter sets the ratio between the total energy ( speech energy plus DTMF energy ) and the DTMF tone energy before vaild OTMF digits are detected. The default is 4000hex which is 3dB. ; 418 ate!KS16112/4 | . 9600/14400 bps FAX MODEM HDLC OPERATION The modem is capable of performing HDLC framing ( High Level Data Link Control }. The modem uses the SDLC ( Synchronous Data Link Control ) in an aight bit octet format which is a subset of HDLC. 41. HDLC Frames Information on an HDLC link is transmitted by means of frames. The information is organized into a format specified by an international that enables the synchronization between the tranemitter and the receiver. An HOLC frame has the following parts : Flags Address Field Control Field Information Field Farne Check Sequence oe ee The frame check comuptation uses the cyclic redundancy check (CRC) method and implement a polynomial specified in CCITT T.30 and X.25 as foliows : x x2 4 Kh 4 4 The HDLC is functional under the following transmitter and receiver modes V.17 (KS16114) * V.29 * V.27ter V.21Ch.2 * V.21 Ch.2 with DTMF Receiver aa: 419 AERP eeeKS16112/4 9600/14400 bps FAX MODEM TONE GENERATION AND DETECTION 1. OTMF Dialing The modem includes two programmable tone generators that can be used to perform dual tone multi fre- quency (DTMF ) dialing. The amplitude and frequency of each tone generator are programmable by the host. 1.1 DTMF Requirements The DTMF tones consist of two sinusoidal signals, one from a high group of frequencies. and the other from a low group of frequencies. The two groupe of frequencies and the corresponding push button telephone characters are shown in Table 5. Signal power is defined for the combined as well as for the individual tones. The high frequency tone should be transmitted at approximately 2dB higher power than the low fre- quency tone, The maximum combined power should not exceed +1 dBm and the minimum steady state power should not be less than -8 dBm. The required minimum OTMF pulse duration is SOms, but approxi- mately 95ms is recommended for better retiabitity. The required interval between DTMF puises is 4S5ms but 70 ms is prefrred. Table . OTMF Frequencies High Frequency Group Low Frequency Group! 1209Hz | 1336Hz | 1477 Hz | 1622 Hz 697 Hz 1 2 3 A 770 Hz 4 5 6 B 852 Hz 7 8 9 c 941 Hz * 0 # D 1.2 Setting DTMF Parameters The amplitude and frequency of the two tones are set by the host in the DSP RAM. To generate a DTMF tone the modem needs to be in the TONE configuration ( CONFIG = 80h ). The host must then program the frequencies and levels of each tone. This procedure consists of writing a 16 bite binary number Into RAM using RAM accees code 27h with BRT; = 0 and CRAM; = 1 for tone 1 and RAM access code 22h with BRTx = 0 and CRAM, = 1 for tone 2. The power levels are programmed by writting a 16 bits binary number into RAM using RAM access code 22h with BRTx = O and CRAM, = 0 for tone 1 and RAM access code 23h with BRTx = 0 and CRAM, = 0 for tone 2. The hex numbers in these RAM location are acaled as follows : Frequency Number = 6.8267 F = ( where F is the desired frequency in Hz ) Power Number = 18426 " ( where Po is the desired power level in d&m) The hexadecimal numbers for OTMF generation are listed in Table 6. Power levels are selected to give each tone the desired output power while compensating for modem filter characteristics. a oeKS16112/4 9600/14400 bps FAX MODEM Table 6. OTMF Default Value Digit ADR, CRAM, BRT, Value Digit ADRy CRAM, BRT, Value (Hex) (Hex) 21 1 0 1918 21 1 0 1668 0 22 1 6 23A0 : 22 1 0 23A0 22 0 0 G5AB 22 0 0 65AB 23 0 0 7FFF 23 o Qo TFFF 21 1 0 1296 21 1 0 4658 1 22 1 0 203D 9 22 1 0 2763 22 0 Q 65A8 22 o ) 65AB 23 0 7FFF 23 0 0 TFFF 21 1 Q 1298 21 1 0 1918 2 22 1 0 24A0 . 22 1 0 203D 22 0 0 65AB 22 0 0 65AB 23 0 0 7FFF 23 0 0 TPFF 21 1 0 1296 21 1 0 1918 3 22 1 0 2763 # 22 1 Q 2763 22 0 Qo 65AB 22 0 0 65AB 23 9 0 TEFF 23 0 Q TFFF 21 1 0 1488 21 1 0 1296 22 1 0 203D 22 1 Q 288C 4 22 0 0 65AB A 22 0 0 65AB 23 0 0 7FFF 23 0 0 TFFF 21 1 0 1488 21 1 Q 1488 5 22 1 0 2300 8 22 1 0 2B8C 22 0 0 65AB 22 o 0 65AB 23 0 0 TFFF 23 0 9 FFF 21 1 0 1488 21 1 6 16B8 6 22 1 0 2763 22 4 6 288 22 0 6 68AB 22 0 0 65AB 23 0 0 TFFF 23 0 0 7FFF 241 1 0 1688 21 1 0 1918 ; 22 1 0 203D b 22 1 0 2B6C 22 Q 0 65AB 22 0 0 65AB 23 0 G TEFF 23 0 0 7FFF 421 SESE ELEKS16112/4 9600/14400 bps FAX MODEM 2. Tone Detection 2.1 Programmabie Tone Detection The modem includes three programmable independent tone detectors ( called TD1, TO2 and TD3). All three tone detectors are operational when the modern is in a non high speed mode. in the high speed mode only tone. detector TD3 is operational. The default center frequencies for the tone detectors are 2100 Hz ( TD1 ), 1100Hz (TO2 ) and 462Hz (TD2). The three tone detectors can be cascaded to from a single 12th order fitter by setting the CASC bit In the dual port interface memory. Each tone detector consists of two secound order fiters with two zeros. and two poles each, a first order energy averaging fiter and a threshold comparator. A block diagram of a tone detector is shown in Fig 2. Fitter { has a transter function ; 2 (a+ atz' + a2z) H1 (z) = 1+ 2biz! + 2b2z7 Filter 2 has transfer function : 2 (a0 + az" + a'2z7) H2 (z) = 1+ 2b'42! + 2b'2z? The energy averaging filter has a transfer function : a" H3 (2) = 1-b'z" THRESHOLD [output ABS COMPARATOR [7 Fig 2. Tone Detector Block Diagram 422KS16112/4 9600/14400 bps FAX MODEM _ The output of the threshold comparator controls the interface memory bits TD 1, TD 2 and TD 3. The bits are set if the output of the energy averaging filter is equal to or greater than 1/8 of full scale. Otherwise the bits are reset. Table 7 contains the default fitter coefficient values that are loaded into RAM upon power up. These default values corrspond to defautt frequencies 2100 Hz (TD1), 1100Hz (TD2) and 462Hz (TO3). Table 8 contains the RAM access codes for all fitter ' coefificients. Table 7. Default Tone Detector Fitter Coefficients Fr Freq. Offset Coeff. Value Coeff. Value Detected (he) Bandwidth (Hz) wz) Coeff.Name Wex) (Decimal) a0 = a0 0198 0.01245 b1 1AdA 0.20538 2100 2s 18 b't 4754 0.18243 b2=b2 coca 0.49402 a0 = a0 0148 0.00854 bt 60BE 0.75580 4100 30 19 bt 5E9C 0.72914 b2 = b2 coc4 0.49402 a0 =a 0048 6.00220 b1 79F3 0.95273 462 14 10 b4 7974 0.94885 b2 = b2 co83 -0.49600 Table 6. Filter RAM Access Codes RAM Access Code ( Hex ) Coefficient Name Tone 1 Tone 2 Tone 3 XY ad 25 2B 31 x ai 27 2c 32 x a2 a7 2D 33 x ao 28 2E 34 x at 23 2F 35 x a2 2A 30 36 x b' a6 AC B2 Y b2 A7 AD 83 Y bil Ag AF BS Y b'2 DA BO BG Y a Aa AE B4 Y b* AQ AB B1 YRE KS16112/4 Table 9. KS16112 Crystal Specifications Parameter Value Nominal Frequency (25 C. ) 24.00014 MHz Frequency Tolerance (25 TC ) + 0.0015% Operating Temperature OT 60T Storage Temperature -55 C to 85 Temperature Stability (0 C to 60 C ) + 0.003% Calibration Mode Parallel Resonant Shunt Capacitance 7pF ( max) Load Capacitance 18 + O.2pF Drive Level ( at 20 nW ) 2.5mW (max) Aging per Year 0.0005% Oscillation Mode Fundamental Series Resistance 25 2 (max) Maximum Frequency Variation + 0.035% ( 16.5pF or 19.5pF load capacitance ) 9600/14400 bps FAX MODEM Wi OIESES 424KS16112/4 9600/14400 bps FAX MODEM Table 10. KS16114 Fundamental Crystal Specifications Parameter Value Nominal Frequency (25C ) 38.000530 MHz Frequency Tolerance (25'U ) + 0,0015% Operating Temperature 0 te60.T Storage Ternperature -55 T to 85 T Temperature Stability (0 T to 60 T ) + 0.003% Calibration Mode Paraltel Resonant Shunt Capacitance 7pF ( max ) Series Capacitance : at 12.7 MHz 0.024 pF ( typ. ) at 38.00053 MHz 0.0022 pF ( typ.) Series Inducatance : at 12.7 MHz 6.58 mH (typ. } at 38.00053 MHz 7.97 mH (typ. ) Series Resistance: at 12.7 MHz 180 Q (max. ) at 38.00053 MHz 7O 2 (max.) Load Capacitance 18 + 0.2 pF Drive Level 1.0mW (max. ) Aging Per Year 0.005% ( max. ) Oscillation Mode Fundamental Maximum Frequency Variation + 0.0085% (16.5pF or 19.5pF load capacitance ) Wie UR eee 425KS16112/4 Table 11. KS16114 Third Overtone Crystal Specifications Parameter Value Normal Frequency (25 CT ) 38.000530 MHz Frequency Tolerance (25 'C } + 0.0015% Operating Temperature 0 to 0 T Storage Temperature -55 T to 85 T Temperature Stability (0 TC to 60 T ) + 0.003% Calibration Mods Parallel Resonant Shunt Capacitance 7 pF ( max.) Series Capacitance : at 12.7 MHz 0.024 pF (typ. ) at 38.00053 MHz 0.0022 pF ( typ. ) Series inductance - at 12.7 MHz 6.58 mH { typ. ) at 38.00053 MHz 7.97 mH ( typ.) Series Resistance: at 12.7 MHz 150 2 ( max.) at 38.00053 MHz 70 & (max) Load Capacitance 18 + 0.2 pF Drive Lavei 1.0mW ( max.) Aging Per Year 0.0005% ({ max. ) Oscillation Mode Third Overtone Maximum Frequency Variation + 9,0036% ( 16.5pF or 19.5pF load. capacitance ) 9600/14400 bps FAX MODEM SEES ELECTRONICS 426KS16112/4 | / 9600/14400 bps FAX MODEM MODEM CIRCUIT INTERFACE Tha modem is packaged in a 68 pin PLCC to be designed into OEM circuit boards. An example of a hard- ware realization in shown in Fig3. This figure also includes the circuitry needed to display the eye pattern. 22 SEPCLK ECLAN Ef sepwcik [2 SYNCIN! 49} SePxO 12 servo fa RS 4 (67, rs3 ht Rs 2{2 Rs 1(3_ RS o [4 b7 (& : pe [86 ) a ps fas pa a7 os 24 60 ba reietizg = OT TAN oF aout oo ERE pe) { Fran = WATER) AYOLKO tS 66 255 1% ta ~12V SN Vee READ-b2 10 *ayror as 2 Slew oS HE) a 1NAE260 [a|" TO! 8 | inreRFACE RM peuk #2 Poet Rxpo [27 Pie 4 we +5VA 30 * ly xray jt r we 2m | ihe RC XTALO eT pew High Freq. skt0 | % otf o4 19148 Alm Bect Mow 033 tos is No +ta ~ wae 6 Note) 1. Pin 5, 6, 8, 16, 37 : No Connection 2. All Resistors + 5%, > 1/8W unless noted 3. All Capacitors uF, + 20%, 50V unless noted Fig 3. Complete Modem Circult and Eye Pattern Generator ss 427 att ELECTRONICS9600/14400 bps FAX MODEM KS16112/4 , 23:37 so80 | on a} O1Max . ~ 127 0.46 A 1 7 1 See a a | | | g| y 428