2Gb NAND FLASH (x16) / 1Gb LPDDR (x32) MS29C2G24MAKLA1-XX FEATURES GENERAL DESCRIPTION Package: Microsemi package-on-package (PoP) MCP products combine NAND Flash and Mobile LPDRAM devices in a single MCP. These products target mobile applications with low-power, highperformance, and minimal package-footprint design requirements. * 152 Plastic Ball Grid Array (PBGA), 14 x 14 mm * 0.65 mm pitch Micron(R) NAND Flash and LPDDR components The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces (no shared address, control, data, or power balls). This bus architecture supports an optimized interface to processors with separate NAND Flash and Mobile LPDRAM buses. The NAND Flash and Mobile LPDRAM devices have separate core power connections and share a common ground (that is, VSS is tied together on the two devices). RoHS-compliant, "green" package Separate NAND Flash and LPDDR interfaces Space-saving multichip package/package-on-package combination Low-voltage operation (1.8V) Commercial and industrial temperature ranges The bus architecture of this device also supports separate NAND Flash and Mobile LPDRAM functionality without concern for device interaction. Same footprint as Micron MT29C2G24MAKLA-XIT NAND Flash-Specific Features Microsemi NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection and monitor device status (R/B#). Organization Page size * x16: 1056 words (1024 + 32 words) Block size: 64 pages (128K + 4K bytes) Mobile LPDDR-Specific Features This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign. No external voltage reference required No minimum clock rate requirement 1.8V LVCMOS-compatible inputs Programmable burst lengths Selectable output drive strength A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable signal. * This product is under development, is not qualified or characterized and is subject to change without notice. This device has an internal 4-bit ECC that can be enabled using the GET/SET features. See Internal ECC and Spare Area Mapping for ECC for more information. Partial-array self refresh (PASR) Deep power-down (DPD) mode Status read register (SRR) The 1Gb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824. It is internally configured as a quad-bank DRAM. Each of the x32's 268M-bit banks is organized as 8,192 rows by 1024 columns by 32 bits. In the reduced page-size (LG) option, each of the x32's 268M-bit banks is organized as 16,384 rows by 512 columns by 32 bits. Micron(R) is a registered trademark of Micron Technology, Inc. NOTES: 1. 2. 3. Throughout this data sheet, various figures and text refer to DQs as "DQ." DQ should be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte. For the lower byte (DQ[7:0]), DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ[15:8]), DM refers to UDM and DQS refers to UDQS. The x32 is divided into 4 bytes. For DQ[7:0], DM refers to DM0 and DQS refers to DQS0. For DQ[15:8], DM refers to DM1 and DQS refers to DQS1. For DQ[23:16], DM refers to DM2 and DQS refers to DQS2. For DQ[31:24], DM refers to DM3 and DQS refers to DQS3. Complete functionality is described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. Any specific requirement takes precedence over a general statement. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com For a more detailed data sheet on operations and specifications; contact factory. 1 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX FIGURE 1 - PIN CONFIGURATION TOP VIEW 1 2 3 4 5 6 7 8 9 A NC NC VDDQ DM1 DQ13 DQ15 VSSQ DQ10 DQ12 DQ16 DQ19 CK VSS DM2 VDDQ DQ21 DQ20 DM3 DQS3 NC NC A B NC NC DQ6 DQ7 VDDQ DQ9 DQ14 DQS1 DQ11 DQ8 DQ17 DQ18 CK# VSSQ DQS2 VDD DQ23 DQ22 DQ28 NC NC B C VSSQ DQS0 DQ24 DQ26 C D DQ3 DQ5 DQ25 DQ29 D E DQ0 DQ1 DQ27 DQ31 E F VSSQ VDDQ VSSQ VDDQ F G DQ4 DQ2 A0 DQ30 G H DM0 VSS VSS VDD H J VDD I/O14 A2 A3 J K FWE# I/O15 A1 A9 K L NC RE# VDDQ VSSQ L M I/O13 VSS A7 A6 M N I/O10 VCC A8 A11 N P I/O12 I/O11 VSS VDD P R I/O8 VSS A5 A12 R T I/O9 VCC DNU CS0# T U I/O1 I/O0 CAS# A4 U V I/O3 I/O2 BA1 RAS# V W DNU LOCK VSSQ VDDQ W Y NC NC I/O6 I/O7 WP# VSS VCC NC NC R/B# VSS RFU DNU VDD CKE0 A10 VSS DWE# VSSQ NC NC Y AA NC NC I/O4 I/O5 NC VCC VSS CE0# ALE CLE VDD TQ VSS VDDQ DNU VSSQ VDD BA0 VDDQ NC NC AA 1 2 3 4 5 6 7 8 9 Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 10 11 12 13 14 15 16 17 18 19 20 21 10 11 12 13 14 15 16 17 18 19 20 21 2 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX FIGURE 2 - 152-BALL (SINGLE LPDDR) FUNCTIONAL BLOCK DIAGRAM CE0# VCC CLE ALE RE# 2G NAND Flash (x16) I/O 0-15 FWE# WP# R/B# LOCK VSS CS0# VDD CK VDDQ 4 CK# CKE0 RAS# DM 1G LPDDR (x32) DQ 0-31 CAS# 4 DWE# DQS TQ Address 0-12, VSSQ BA0, BA1 VSS ELECTRICAL SPECIFICATIONS TABLE 1 - ABSOLUTE MAXIMUM RATINGS Parameters/Conditions VCC, VDD, VDDQ supply voltage relative to VSS Symbol Min VCC, VDD, VDDQ Voltage on any pin relative to VSS Storage temperature range Max Unit -1.0 2.4 V VIN -0.5 2.4 or (supply voltage1 + 0.3V), whichever is less V - -40 +125 C Note: 1. Supply voltage references VCC, VDD, or VDDQ. sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational TABLE 2 - RECOMMENDED OPERATING CONDITIONS Parameters Symbol Min Typ Max Unit Supply voltage VCC, VDD 1.70 1.80 1.95 V VDDQ 1.70 1.80 1.95 V -- -40 -- +85 C I/O supply voltage Operating temperature range Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 3 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX TABLE 3 - x16 NAND BALL DESCRIPTIONS Symbol Type ALE Input Address latch enable: When ALE is HIGH, addresses can be transferred to the on-chip address register. CE0# Input Chip enable: Gates transfers between the host system and the NAND device. CLE Input Command latch enable: When CLE is HIGH, commands can be transferred to the on-chip command register. Input When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCK LOCK, connect LOCK to VSS during power-up, or leave it unconnected (internal pull-down). LOCK Description RE# Input Read enable: Gates information from the NAND device to the host system. FWE# Input Write enable: Gates information from the host system to the NAND device. WP# Input Write protect: Driving WP# LOW blocks ERASE and PROGRAM operations. I/O[15:0] Input/output R/B# Output Ready/busy: Open-drain, active-LOW output that indicates when an internal operation is in progress. VCC Supply VCC: NAND power supply. Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information. Data is output only during READ operations; at other times the I/Os are inputs. TABLE 4 - x32 LPDDR BALL DESCRIPTIONS Symbol Type Description A[12:0] Input Address inputs: Specifies the row or column address. Also used to load the mode registers. The maximum LPDDR address is determined by density and configuration. BA0, BA1 Input Bank address inputs: Specifies one of the 4 banks. CAS# Input Column select: Specifies which command to execute. Input CK is the system clock. CK and CK# are differential clock inputs. All address and control signals are sampled and referenced on the crossing of the rising edge of CK with the falling edge of CK#. CK, CK# CKE0 Input Clock enable: CKE0 is used for a single LPDDR product. CS0# Input Chip select: CS0# is used for a single LPDDR product. DM[3:0] Input Data mask: Determines which bytes are written during WRITE operations. RAS# Input Row select: Specifies the command to execute. DWE# Input Write enable: Specifies the command to execute. DQ[31:0] Input/output Data bus: Data inputs/outputs. DQS[3:0] Input/output Data strobe: Coordinates READ/WRITE transfers of data; one DQS per DQ byte. TQ Output Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85C. VDD Supply VDD: LPDDR power supply. VDDQ Supply VDDQ: LPDDR I/O power supply. VSSQ Supply VSSQ: LPDDR I/O ground. TABLE 3 - NON-DEVICE-SPECIFIC DESCRIPTIONS Symbol Type Description VSS Supply DNU -- VSS: Shared ground. Do not use NC -- No connect: Not internally connected. RFU1 -- Reserved for future use. Note: 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 4 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX 2Gb: x16 NAND FLASH MEMORY - 1.8V FEATURES Open NAND Flash Interface (ONFI) 1.0-compliant1 * Pass/fail condition * Write-protect status Internal data move operations supported within the device from which data is read Single-level cell (SLC) technology Organization * Page size x16: 1056 words (1024 + 32 words) * Block size: 64 pages (128K + 4K bytes) * Device size: 2Gb: 2048 blocks Asynchronous I/O performance Ready/Busy# (R/B#) signal provides a hardware method of detecting operation completion WP# signal: Write protect entire device First blocks (block address 00h) is valid when shipped from factory with ECC; for minimum required ECC, see Error Management * tRC/tWC: 35ns Array performance * Read page: 25s * Program page: 300s (TYP) * Erase block: 500s (TYP) Command set: ONFI NAND Flash Protocol RESET (FFh) required as first command after power-on Quality and reliability * Data retention: 10 years Endurance: 100,000 program/erase cycles Advanced command set Operating voltage range * Program cache * Read cache sequential * Read cache random * One-time programmable (OTP) mode * Programmable drive strength * Interleaved die (LUN) operations * Read unique ID * Block lock * Internal data move Operation status byte provides software method for detecting * VCC: 1.7-1.95V Operating temperature * Commercial: 0C to +70C * Industrial (IT): -40C to +85C NOTES: 1. The ONFI 1.0 specification is available at www.onfi.org. * Operation completion Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 5 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX NAND FLASH ELECTRICAL SPECIFICATIONS Stresses greater than those listed can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods can affect reliability. TABLE 6 - ABSOLUTE MAXIMUM RATINGS Voltage on any pin relative to VSS Parameter/Condition Symbol Min Max Unit Voltage Input VIN -0.6 +2.4 V VCC supply voltage VCC -0.6 +2.4 V Storage temperature TSTG -65 +150 C - - 5 mA Short circuit output current, I/Os TABLE 7 - RECOMMENDED OPERATING CONDITIONS Parameter/Condition Operating temperature Symbol Commercial Min TA Industrial Typ Max Unit 0 - +70 C -40 - +85 C VCC supply voltage VCC 1.65 1.8 1.95 V Ground supply voltage VSS 0 0 0 V TABLE 8 - VALID BLOCKS Parameter Valid block number Symbol Device Min Max Unit Notes NVB 2G 2008 2048 blocks 1, 2 NOTES: 1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad blocks upon shipment. Additional bad blocks may develop over time; however, the total number of available blocks will not drop below NVB during the endurance life of the device. Do not erase or program blocks marked invalid by the factory. 2. Block 00h (the first block) is guaranteed to be valid with ECC when shipped from the factory. TABLE 9 - CAPACITANCE Description Symbol Max Unit Notes Input capacitance CIN 10 pF 1, 2 Input/output capacitance (I/O) CIO 10 pF 1, 2 NOTES: 1. These parameters are verified in device characterization and are not tested. 2. Test conditions: TC = 25C; f = 1 MHz; Vin = 0V. TABLE 10 - TEST CONDITIONS Parameter Input pulse levels Device Value 2G 0.0V to VCC Input rise and fall times Notes 5ns Input and output timing levels VCC/2 Output load 1 TTL GATE and CL = 30pF 1 NOTE: 1. Verified in device characterization, not tested. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 6 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX NAND FLASH ELECTRICAL SPECIFICATIONS - AC CHARACTERISTICS AND OPERATING CONDITIONS TABLE 11 - AC CHARACTERISTICS: COMMAND, DATA, AND ADDRESS INPUT Parameter Symbol Min Max Unit Notes ALE to data start tADL 100 - ns 1 ALE hold time tALH 4 - ns ALE setup time tALS 15 - ns CE# hold time tCH 4 - ns CLE hold time tCLH 5 - ns CLE setup time tCLS 15 - ns CE# setup time tCS 24 - ns Data hold time tDH 4 - ns Data setup time tDS 15 - ns WRITE cycle time tWC 35 - ns WE# pulse width HIGH tWH 15 - ns WE# pulse width tWP 17 - ns WP# setup time tWW 100 - ns NOTE: 1. Timing for tADL begins in the address cycle on the final rising edge of WE# and ends with the first rising edge of WE# for data input. TABLE 12 - AC CHARACTERISTICS: NORMAL OPERATION Note 1 applies to all Parameter Symbol Min Max Unit ALE to RE# delay tAR 10 - ns CE# access time tCEA - 30 ns CE# HIGH to output High-Z tCHZ - 45 ns CLE to RE# delay tCLR 10 - ns CE# HIGH to output hold tCOH 15 - ns Output High-Z to RE# LOW tIR 0 - ns READ cycle time tRC 35 - ns Notes 2 RE# access time tREA - 24 ns RE# HIGH hold time tREH 15 - ns RE# HIGH to output hold tRHOH 15 - ns RE# HIGH to WE# LOW tRHW 100 - ns RE# HIGH to output High-Z tRHZ - 100 ns RE# LOW to output hold tRLOH 0 - ns RE# pulse width tRP 17 - ns Ready to RE# LOW tRR 20 - ns Reset time (READ/PROGRAM/ERASE) tRST - 5/10/500 s 3 WE# HIGH to busy tWB - 100 ns 4 WE# HIGH to RE# LOW tWHR 80 - ns 2 NOTES: 1. AC characteristics may need to be relaxed if I/O drive strength is not set to full. 2. Transition is measured 200mV from steady-state voltage with load. This parameter is not tested. 3. The first time the RESET (FFh) command is issued while the device is idle, the device will be busy for a maximum of 1ms. Thereafter, the device will be busy for maximum 5s. 4. Do not issue a new command during tWB, even if R/B# is ready. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 7 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX NAND FLASH ELECTRICAL SPECIFICATIONS - DC CHARACTERISTICS AND OPERATING CONDITIONS (cont'd) TABLE 12 - DC CHARACTERISTICS AND OPERATING CONDITIONS Parameter Conditions Symbol Min Typ Max Unit tRC = tRC (MIN); CE# = VIL; IOUT = 0mA ICC1 - 10 20 mA PROGRAM current - ICC2 - 10 20 mA ERASE current - ICC3 - 10 20 mA Sequential READ current Standby current (TTL) Standby current (CMOS) CE# = VIH; LOCK = WP# = 0V/VCC ISB1 - - 1 mA CE# = VCC - 0.2V; LOCK = WP# = 0V/VCC ISB2 - 10 50 A Rise time = 1ms Line capacitance = 0.1F IST - - 10 per die mA VIN = 0V to VCC ILI - - 10 A Staggered power-up current Input leakage current Output leakage current Input high voltage VOUT = 0V to VCC ILO - - 10 A I/O[15:0], CE#, CLE, ALE, WE#, RE#,WP#, R/B# VIH 0.8 x VCC - VCC + 0.3 V Input low voltage, all inputs Notes 1 - VIL -0.3 - 0.2 x VCC V Output high voltage IOH = -100A VOH VCC - 0.1 - - V Output low voltage IOL = -100A VOL - - 0.1 V 2 Output low current VOL = 0.4V IOL (R/B#) 3 4 - mA 3 2 NOTES: 1. Measurement is taken with 1ms averaging intervals and begins after VCC reaches VCC (MIN). 2. VOH and VOL may need to be relaxed if I/O drive strength is not set to full. 3. IOL (RB#) may need to be relaxed if R/B pull-down strength is not set to full. TABLE 13 - PROGRAM/ERASE CHARACTERISTICS Symbol Typ Max Unit Notes Number of partial page programs Parameter NOP - 4 Cycles 1 BLOCK ERASE operation time tBERS 0.5 3 ms Busy time for PROGRAM CACHE operation (1.8V) tCBSY 3 600 s Busy time for SET FEATURES and GET FEATURES operations (1.8V) tFEAT - 3 s Busy time for PROGRAM/ERASE on locked block tLBSY - 3 s LAST PAGE PROGRAM operation time tLPROG - - - Busy time for OTP DATA PROGRAM operation if OTP is protected tOBSY - 30 s PAGE PROGRAM operation time (1.8V) tPROG 300 600 s tR - 25 s tRCBSY 3 25 s Data transfer from Flash array to data register Busy time for READ CACHE operation 2 3 NOTES: 1. Four total partial-page programs to the same page. 2. tCBSY MAX time depends on timing between internal program completion and data-in. 3. tLPROG = tPROG (last page) + tPROG (last - 1 page) - command load time (last page) - address load time (last page) - data load time (last page). Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 8 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX FIGURE 3 - ARRAY ORGANIZATION 1056 words I/O0 Cache Register 1024 32 Data Register 1024 32 64 pages = 1 block (64K + 2K) words 1 block 2048 blocks per device I/O15 1 page = (1K + 32 words) 1 block = (1K + 32) words x 64 pages = (64K + 2K) words 1 device = (1K + 32) words x 64 pages x 2048 blocks = 2112Mb TABLE 14 - ARRAY ADDRESSING Cycle I/O[15:8] I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 First LOW CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 Second LOW LOW LOW LOW LOW LOW CA101 CA9 CA8 Third LOW BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0 Fourth LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 Fifth LOW LOW LOW LOW LOW LOW LOW LOW BA16 NOTES: 1. If CA10 is 1, then CA[9:5] must be 0. 2. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. 3. I/O[15:8] are not used during the addressing sequence and should be driven LOW. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 9 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX 1Gb: x32 MOBILE LPDDR SDRAM Features VDD/VDDQ = 1.8V Programmable burst lengths (BL): 2, 4, 8, or 16 Bidirectional data strobe per byte of data (DQS) Concurrent auto precharge option is supported Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Auto refresh and self refresh modes Differential clock inputs (CK and CK#) Partial-array self refresh (PASR) Commands entered on each positive CK edge Deep power-down (DPD) DQS edge-aligned with data for READs; center-aligned with data for WRITEs Status read register (SRR) 1.8V LVCMOS-compatible inputs Selectable output drive strength (DS) 4 internal banks for concurrent operation Clock stop capability Data masks (DM) for masking write data--one mask per byte 64ms refresh TABLE 15 - CONFIGURATION ADDRESING - 1Gb Architecture 32 Meg x 32 Configuration 8 Meg x 32 x 4 banks Refresh count 8K Row addressing 8K A[13:0] Column addressing 1K A[9:0] Status Read Register The status read register (SRR) is used to read the manufacturer ID, revision ID, refresh multiplier, width type, and density of the device, as shown in Figure 4. The SRR is read via the LOAD MODE REGISTER command with BA0 = 1 and BA1 = 0. The sequence to perform an SRR command is as follows: 1. The device must be properly initialized and in the idle or all banks precharged state. 2. Issue a LOAD MODE REGISTER command with BA[1:0] = 01 and all address pins set to 0. 3. Wait tSRR; only NOP or DESELECT commands are supported during the tSRR time. 4. Issue a READ command. 5. Subsequent commands to the device must be issued tSRC after the SRR READ command is issued; only NOP or DESELECT commands are supported during tSRC. SRR output is read with a burst length of 2. SRR data is driven to the outputs on the first bit of the burst, with the output being "Don't Care" on the second bit of the burst. FIGURE 4 - STATUS READ REGISTER TIMING T0 T1 T2 PRE1 NOP LMR T3 T4 T5 T6 T8 CK# CK tSRR Command tSRC NOP2 READ NOP NOP NOP Valid tRP Address BA0, BA1 0 BA0 = 1 BA1 = 0 CL = 33 DQS Note 5 SRR out 4 DQ Don't Care Transitioning Data Notes on next page. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 10 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX NOTES for figure 4: 1. All banks must be idle prior to status register read. 2. NOP or DESELECT commands are required between the LMR and READ commands (tSRR), and between the READ and the next VALID command (tSRC). 3. CAS latency is predetermined by the programming of the mode register. CL = 3 is shown as an example only. 4. Burst length is fixed to 2 for SRR regardless of the value programmed by the mode register. 5. The second bit of the data-out burst is a "Don't Care." Figure 5 - Status Register Definition DQ15...DQ0 DQ18 DQ19 DQ17 S31..S16 31..16 Reserved1 0 S12 0 S10 1 1 1 1 1 0 1 0 1 1 1 S8 S7 7 S6 S5 6 5 Revision ID S4 4 S3 1 S11 1 1 0 0 1 0 1 S9 9 8 12 11 10 Type Width Refresh Rate 1Gb LPDDR S8 0 1 0 13 DQ23 DQ22 DQ28 DQ26 DQ24 DQ27 DQ25 DQ29 DQ30 DQ31 Density Device Type S9 0 0 1 0 0 0 S15 S14 S13 S12 S11 S10 15 14 Density S15 S14 S13 DQ16 DQ21 DQ20 Device Width 32 bits S7 0 S6 0 S5 0 S4 0 ... ... ... ... X X X X S3 S2 S1 3 2 1 Manufacturer ID S2 1 S1 1 S0 1 I/O bus (CLK L->H edge) S0 0 Status register Manufacturer ID Micron Revision ID The manufacturer's revision number starts at `0000' and increments by `0001' each time a change in the specification (AC timings or feature set), IBIS (pullup or pull-down characteristics), or process occurs. Refresh Multiplier2 Reserved Reserved Reserved 2X 1X Reserved 0.25X Reserved Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com NOTES: 1. Reserved bits should be set to 0 for future compatibility. 2. Refresh multiplier is based on the memory device on-board temperature sensor. Required average periodic refresh interval = tREFI x multiplier. 11 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX LPDDR ELECTRICAL SPECIFICATIONS Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TABLE 16 - ABSOLUTE MAXIMUM RATINGS Note 1 applies to all parameters in this table Parameter VDD/VDDQ supply voltage relative to VSS Symbol Min Max Unit VDD/VDDQ -1.0 2.4 V V C Voltage on any pin relative to VSS VIN -0.5 2.4 or (VDDQ + 0.3V), whichever is less Storage temperature (plastic) TSTG -55 150 NOTE: 1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed VDD. TABLE 17 - AC/DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS Notes 1-5 apply to all parameters/conditions in this table; VCC/VCCQ = 1.70-1.95V Parameter/Condition Symbol Min Max Unit Notes Supply voltage VDD 1.70 1.95 V 6, 7 I/O supply voltage VDDQ 1.70 1.95 V 6, 7 Input voltage high VIH 0.8 x VDDQ VDDQ + 0.3 V 8, 9 Input voltage low VIL -0.3 0.2 x VDDQ V 8, 9 VIN -0.3 VDDQ + 0.3 V 10 DC input differential voltage VID(DC) 0.4 x VDDQ VDDQ + 0.6 V 10, 11 AC input differential voltage VID(AC) 0.6 x VDDQ VDDQ + 0.6 V 10, 11 VIX 0.4 x VDDQ 0.6 x VDDQ V 10, 12 Address and command inputs Clock inputs (CK, CK#) DC input voltage AC differential crossing voltage Data inputs DC input high voltage VIH(DC) 0.7 x VDDQ VDDQ + 0.3 V 8, 9, 13 DC input low voltage VIL(DC) -0.3 0.3 x VDDQ V 8, 9, 13 AC input high voltage VIH(AC) 0.8 x VDDQ VDDQ + 0.3 V 8, 9, 13 AC input low voltage VIL(AC) -0.3 0.2 x VDDQ V 8, 9, 13 DC output high voltage: Logic 1 (IOH = -0.1mA) VOH 0.9 x VDDQ - V DC output low voltage: Logic 0 (IOL = 0.1mA) VOL - 0.1 x VDDQ V II -1 1 A IOZ -5 5 A Data outputs Leakage current Input leakage current Any input 0V VIN VDD (All other pins not under test = 0V) Output leakage current (DQ are disabled; 0V VOUT VDDQ) Operating temperature Commercial TA 0 70 C Industrial TA -40 85 C Notes on next page Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 12 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX LPDDR ELECTRICAL SPECIFICATIONS (cont'd) NOTES: 1. All voltages referenced to VSS. 2. All parameters assume proper device initialization. 3. Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 4. Outputs measured with equivalent load; transmission line delay is assumed to be very small: 50 9. 50 I/O I/O 10pF 20pF Full drive strength 5. 6. 7. 8. 10. 11. 12. Half drive strength Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The output timing reference voltage level is VDDQ/2. Any positive glitch must be less than one-third of the clock cycle and not more than +200mV or 2.0V, whichever is less. Any negative glitch must be less than one-third of the clock cycle and not exceed either -150mV or +1.6V, whichever is more positive. 13. VDD and VDDQ must track each other and VDDQ must be less than or equal to VDD. To maintain a valid level, the transitioning edge of the input must: 8a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). 8b. Reach at least the target AC level. 8c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). VIH overshoot: VIHmax = VDDQ + 1.0V for a pulse width 3ns and the pulse width cannot be greater than one-third of the cycle rate. VIL undershoot: VILmin = -1.0V for a pulse width 3ns and the pulse width cannot be greater than one-third of the cycle rate. CK and CK# input slew rate must be 1 V/ns (2 V/ns if measured differentially). VID is the magnitude of the difference between the input level on CK and the input level on CK#. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. DQ and DM input slew rates must not deviate from DQS by more than 10%. 50ps must be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. TABLE 18 - CAPACITANCE (X32) Note 1 applies to all the parameters in this table Parameter Symbol Min Max Unit Input capacitance: CK, CK# CCK 1.5 3.0 pF Delta input capacitance: CK, CK# CDCK - 0.25 pF CI 1.5 3.0 pF Input capacitance: command and address Delta input capacitance: command and address CDI - 0.5 pF Input/output capacitance: DQ, DQS, DM CIO 1.5 4.5 pF Delta input/output capacitance: DQ, DQS, DM CDIO - 0.5 pF Notes 2 2 3 NOTES: 1. This parameter is guaranteed by design, not tested. 2. The input capacitance per pin group will not differ by more than this maximum amount for any given device. 3. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 13 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX LPDDR ELECTRICAL SPECIFICATIONS - IDD PARAMETERS TABLE 19 - IDD SPECIFICATIONS AND CONDITIONS Notes 1-5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70-1.95V Max Parameter/Condition Symbol -5 -54 -6 -75 Unit Notes Operating 1 bank active precharge current: tRC = tRC (MIN); tCK = tCK (MIN); CKE is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable IDD0 110 105 100 70 mA 6 Precharge power-down standby current: All banks idle; CKE is LOW; CS is HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD2P 600 600 600 600 A 7, 8 Precharge power-down standby current: Clock stopped; All banks idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD2PS 600 600 600 600 A 7 Precharge nonpower-down standby current: All banks idle; CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD2N 18 17 15 12 mA 9 Precharge nonpower-down standby current: Clock stopped; All banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD2NS 14 13 8 8 mA 9 Active power-down standby current: 1 bank active; CKE = LOW; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD3P 3.6 3.6 3.6 3.6 mA 8 Active power-down standby current: Clock stopped; 1 bank active; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD3PS 3.6 3.6 3.6 3.6 mA Active nonpower-down standby: 1 bank active; CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD3N 20 19 18 16 mA 6 Active nonpower-down standby: Clock stopped; 1 bank active; CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD3NS 16 15 14 12 mA 6 Operating burst read: 1 bank active; BL = 4; CL = 3; tCK = tCK (MIN); Continuous READ bursts; Iout = 0mA; Address inputs are switching every 2 clock cycles; 50% data changing each burst IDD4R 150 145 140 120 mA 6 Operating burst write: One bank active; BL = 4; tCK = tCK (MIN); Continuous WRITE bursts; Address inputs are switching; 50% data changing each burst IDD4W 150 145 140 120 mA 6 tRFC = 138ns IDD5 140 140 140 140 mA 10 tRFC = tREFI IDD5A 15 15 15 14 mA 10, 11 IDD8 10 10 10 10 A 7, 13 Auto refresh: Burst refresh; CKE = HIGH; Address and control inputs are switching; Data bus inputs are stable Typical deep power-down current at 25C: Address and control pins are stable; Data bus inputs are stable Notes on next page Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 14 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX LPDDR ELECTRICAL SPECIFICATIONS - IDD PARAMETERS (cont'd) TABLE 20 - IDD6 SPECIFICATIONS AND CONDITIONS Notes 1-5, 7, and 12 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70-1.95V Parameter/Condition Self refresh: CKE = LOW; tCK = tCK (MIN); Address and control inputs are stable; Data bus inputs are stable Full array, 85C Symbol Low Power Standard IDD6 Units 1000 1200 A Full array, 45C 500 750 A 1/2 array, 85C 750 900 A 1/2 array, 45C 440 730 A 1/4 array, 85C 600 750 A 1/4 array, 45C 380 680 A 1/8 array, 85C 550 750 A 1/8 array, 45C 350 620 A 1/16 array, 85C 500 700 A 1/16 array, 45C 330 540 A NOTES: 1. All voltages referenced to VSS. 2. Tests for IDD characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The output timing reference voltage level is VDDQ/2. 4. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time with the outputs open. 5. IDD specifications are tested after the device is properly initialized and values are averaged at the defined cycle rate. 6. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRASmax for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 7. 8. 9. 10. 11. 12. 13. 15 Measurement is taken 500ms after entering into this operating mode to provide settling time for the tester. VDD must not vary more than 4% if CKE is not active while any bank is active. IDD2N specifies DQ, DQS, and DM to be driven to a valid high or low logic level. CKE must be active (HIGH) during the entire time a REFRESH command is executed. From the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge until tRFC later. This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH command period (tRFC (MIN)) else CKE is LOW (for example, during standby). Values for IDD6 85C are guaranteed for the entire temperature range. All other IDD6 values are estimated. Typical values at 25C, not a maximum value. 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX LPDDR ELECTRICAL SPECIFICATIONS - AC OPERATING CONDITIONS TABLE 21 - ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS Notes 1-9 apply to all the parameters in this table; VDD/VDDQ = 1.70-1.95V -5 Parameter Access window of DQ from CK/CK# Clock cycle time Symbol CL = 3 CL = 2 CL = 3 CL = 2 tAC tCK -54 -6 -75 Min Max Min Max Min Max Min Max 2.0 5.0 2.0 5.0 2.0 5.5 2.0 6.0 2.0 6.5 2.0 6.5 2.0 6.5 2.0 6.5 5.0 - 5.4 - 6 - 7.5 - 12 - 12 - 12 - 12 - Unit Notes ns ns 10 CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK CKE minimum pulse width (high and low) tCKE 1 - 1 - 1 - 1 - tCK 11 Auto precharge write recovery + precharge time tDAL - - - - - - - - - 12 DQ and DM input hold time relative to DQS (fast slew rate) tDHf 0.6 - 0.6 - 0.6 - 0.8 - ns 13, 14, 15 DQ and DM input hold time relative to DQS (slow slew rate) tDHs 0.7 - 0.7 - 0.7 - 0.9 - ns DQ and DM input setup time relative to DQS (fast slew rate) tDSf 0.6 - 0.6 - 0.6 - 0.8 - ns DQ and DM input setup time relative to DQS (slow slew rate) tDSs 0.7 - 0.7 - 0.7 - 0.9 - ns DQ and DM input pulse width (for each input) tDIPW 1.8 - 1.9 - 2.1 - 1.8 - ns 2.0 5.0 2.0 5.0 2.0 5.5 2.0 6.0 ns 2.0 6.5 2.0 6.5 2.0 6.5 2.0 6.5 ns Access window of DQS from CK/CK# CL = 3 CL = 2 tDQSCK DQS input high pulse width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS input low pulse width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ - 0.4 - 0.45 - 0.45 - 0.6 ns WRITE command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS falling edge from CK rising - hold time tDSH 0.2 - 0.2 - 0.2 - 0.2 - tCK DQS falling edge to CK rising - setup time tDSS 0.2 - 0.2 - 0.2 - 0.2 - tCK Data valid output window (DVW) n/a Half-clock period tHP ns 17 tCH, tCL - tCH, tCL - tCH, tCL - ns 18 - 5.0 - 5.0 - 5.5 - 6.0 ns - 6.5 - 6.5 - 6.5 - 6.5 ns tLZ 1.0 - 1.0 - 1.0 - 1.0 - ns 19 Address and control input hold time (fast slew rate) tIHF 0.9 - 1.0 - 1.1 - 1.3 - ns 15, 21 Address and control input hold time (slow slew rate) tIHS 1.1 - 1.2 - 1.2 - 1.5 - ns Address and control input setup time (fast slew rate) tISF 0.9 - 1.0 - 1.1 - 1.3 - ns Address and control input setup time (slow slew rate) tISS 1.1 - 1.2 - 1.2 - 1.5 - ns Address and control input pulse width tIPW 2.3 - 2.5 - 2.6 - tIS + tIH - ns LOAD MODE REGISTER command cycle time tMRD 2 - 2 - 2 - 2 - tCK DQ-DQS hold, DQS to first DQ to go nonvalid, per access tQH tHP tQHS - tHP tQHS - tHP tQHS - tHP tQHS - ns Data hold skew factor tQHS - 0.5 - 0.5 - 0.65 - 0.75 ns ACTIVE-to-PRECHARGE command tRAS 40 70,000 42 70,000 42 70,000 45 70,000 ns ACTIVE to ACTIVE/ACTIVE to AUTO REFRESH command period tRC 55 - 58.2 - 60 - 67.5 - ns Active to read or write delay tRCD 15 - 16.2 - 18 - 22.5 - ns Refresh period tREF - 64 - 64 - 64 - 64 ms CL = 2 Data-out Low-Z window from CK/CK# tHZ tQH - tDQSQ tQH - tDQSQ 13, 17 - CL = 3 tQH - tDQSQ 16 tCH, tCL Data-out High-Z window from CK/ CK# tQH - tDQSQ 13, 14, 15 19, 20 15, 21 16 13, 17 22 28 Notes on next page Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 16 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX LPDDR ELECTRICAL SPECIFICATIONS - AC OPERATING CONDITIONS (cont'd) TABLE 22 - ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (cont'd) Notes 1-9 apply to all the parameters in this table; VDD/VDDQ = 1.70-1.95V -5 Parameter -54 -6 -75 Symbol Min Max Min Max Min Max Min Max Unit Notes Average periodic refresh interval tREFI - 7.8 - 7.8 - 7.8 - 7.8 s 23 AUTO REFRESH command period tRFC 110 - 110 - 110 - 110 - ns PRECHARGE command period tRP 15 - 16.2 - 18 - 22.5 - ns CL = 3 tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK CL = 2 tRPRE 0.5 1.1 0.5 1.1 0.5 1.1 0.5 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK Active bank a to active bank b command tRRD 10 - 10.8 - 12 - 15 - ns Read of SRR to next valid command tSRC CL + 1 - CL + 1 - CL + 1 - CL + 1 - tCK DQS read preamble SRR to read tSRR 2 - 2 - 2 - 2 - tCK DQS write preamble tWPRE 0.25 - 0.25 - 0.25 - 0.25 - tCK DQS write preamble setup time tWPRES 0 - 0 - 0 - 0 - ns 24, 25 DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 26 Write recovery time tWR 15 - 15 - 15 - 15 - ns 27 Internal WRITE-to-READ command delay tWTR 2 - 2 - 1 - 1 - tCK Exit power-down mode to first valid command tXP 2 - 2 - 1 - 1 - tCK Exit self refresh to first valid command tXSR 112.5 - 112.5 - 112.5 - 112.5 - ns NOTES: 1. All voltages referenced to VSS. 2. All parameters assume proper device initialization. 3. Tests for AC timing and electrical AC and DC characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage ranges specified. 4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to system environment. Specifications are correlated to production test conditions (generally a coaxial transmission line terminated at the tester electronics). For the half-strength driver with a nominal 10pF load, parameters tAC and tQH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by design/characterization. Use of IBIS or other simulation tools for system design validation is suggested. 50 13. Referenced to each output group: For x32, DQS0 with DQ[7:0]; DQS1 with DQ[15:8]; DQS2 with DQ[23:16]; and DQS3 with DQ[31:24]. 14. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/ DQS slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If the slew rate exceeds 4 V/ns, functionality is uncertain. 15. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and addresses) are measured between VIL(DC) to VIH(AC) for rising input signals and VIH(DC) to VIL(AC) for falling input signals. 16. These parameters guarantee device timing but are not tested on each device. 17. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tHP tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is provided a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. 18. tHP (MIN) is the lesser of tCL (MIN) and tCH (MIN) actually applied to the device CK and CK# inputs, collectively. 19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (tHZ) or begins driving (tLZ). 20. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. 21. Fast command/address input slew rate 1 V/ns. Slow command/address input slew rate 0.5 V/ ns. If the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from the 0.5 V/ns. tIH has 0ps added, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. 22. READs and WRITEs with auto precharge must not be issued until tRAS (MIN) can be satisfied prior to the internal PRECHARGE command being issued. 23. The refresh period equals 64ms. This equates to an average refresh rate of 7.8125s 24. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 25. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic low) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 26. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 27. At least 1 clock cycle is required during tWR time when in auto precharge mode. 28. Clock must be toggled a minimum of two times during the tXSR period. 50 I/O I/O 10pF 20pF Full drive strength Half drive strength 5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference voltage level for signals other than CK/ CK# is VDDQ/2. 6. A CK and CK# input slew rate 1 V/ns (2 V/ns if measured differentially) is assumed for all parameters. 7. All AC timings assume an input slew rate of 1 V/ns. 8. CAS latency definition: with CL = 2, the first data element is valid at (tCK + tAC) after the clock at which the READ command was registered; for CL = 3, the first data element is valid at (2 x tCK + tAC) after the first clock at which the READ command was registered. 9. Timing tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VDDQ/2 or to the crossing point for CK/CK#. The output timing reference voltage level is VDDQ/2. 10. Clock frequency change is only permitted during clock stop, power-down, or self refresh mode. 11. In cases where the device is in self refresh mode for tCKE, tCKE starts at the rising edge of the clock and ends when CKE transitions HIGH. 12. tDAL = (tWR/tCK) + (tRP/tCK): for each term, if not already an integer, round up to the next highest integer. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 28 17 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX FIGURE 6 - 152-BALL BGA PACKAGE BOTTOM VIEW 152x O0.46 (0.018) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 13 (0.512) BSC 14 0.1 (0.5510.004) Ball A1 ID 0.65 (0.026) TYP 0.65 (0.026) TYP 13 (0.512) BSC A B C D E F G H J K L M N P R T U V W Y AA 0.34 (0.014) MIN 1.28 MAX 14 0.1 (0.5510.004) NOTE: (1) Dimension applies to solder ball post reflow on O0.35 ball pad. All linear dimensions are millimeters and parenthetically in inches Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 18 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX ORDERING INFORMATION MS 29C 2G 24M A K L A 1 - X X MERCURY SYSTEMS MS PRODUCT FAMILY 29C-2Gb/1Gb NAND FLASH DENSITY 2G = 2Gb NAND FLASH LPDRAM DENSITY 24M = 1G LPDDR OPERATING VOLTAGE RANGE A = 1.8V NAND FLASH CONFIGURATION K = x16 LPDRAM CONFIGURATION L = x32 CHIP COUNT A = 2; 1 NAND FLASH / 1 LPDDR SDRAM PACKAGE CODES 1 = 152 Ball BGA LPDRAM ACCESS TIME X = CLOCK CYCLE TIME Speed Grade Clock Rate CAS Latency -5 200 MHz CL3 -54 185 MHz CL3 -6 166 MHz CL3 -75 133 MHz CL3 OPERATING TEMPERATURE I = INDUSTRIAL TEMPERATURE (-40C to +85C) C = COMMERCIAL TEMPERATURE (0C to +70C) Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 19 4400.04E-0816-ss-MS29C2G24MAKLA1-XX MS29C2G24MAKLA1-XX Document Title 2GB NAND / 1GB LPDDR Revision History Rev # History Release Date Status Rev 0 Changes (Pg. 1-19) April 2011 Advanced July 2011 Advanced October 2011 Preliminary September 2012 Final August 2016 Final 0.1 Create new data sheet Rev 1 Changes (Pg. 2-4) 1.1 Figure 1 - pin AA15 from A13 to DNU 1.2 Figure 2 - changed Address 0-14 to 0-12 1.3 Table 4 - changed A[14:0] to A[12:0] Rev 2 Changes (Pg. 1) 2.1 Change status to Preliminary and add bullet to Features section "Same footprint as Micron MT29C2G24MAKLA-XIT" Rev 3 Changes (Pg. 1, 3, 13, 14) 3.1 Add status read register (SRR) 3.2 Change storage temperature to -40C to 125C 3.3 Change data sheet status to final Rev 4 Changes (Pg. All) (ECN 10156) 4.1 Change document layout from Microsemi to Mercury Systems Mercury Systems reserves the right to change products or specifications without notice. (c) 2016 Mercury Systems. All rights reserved. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 20 4400.04E-0816-ss-MS29C2G24MAKLA1-XX