HARRIS SEMICONDUCTOR HS-82C54RH Radiation Hardened CMOS Programmable Interval Timer aD August 1995 Features Pinouts 24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24 Radiation Hardened - Total Dose > 10 RAD (Si) - Transient Upset > 10 RAD (Si)/sec TOP VIEW - Latch Up Free EPI-CMOS oo V Fal vop - Functional After Total Dose 1 x 10 RAD (Si) D lH = wa Low Power Consumption - IDDSB = 20uA - IDDOP=12mA + Pin Compatible with NMOS 8254 and the Harris 82054 ps [5 os fe os pe [6 p2] RD pi] cS pa] At hg] Ao * High Speed, No Wait State Operation with 5MHz HS-80C86RH - E a ne + Three Independent 16-Bit Counters Le ii ; ; ciko [3 fi6] GATE 2 + Six Programmable Counter Modes ; ; ouTo fio} 5] CLK 1 + Binary or BCD Counting GATES fa ia] GATES + Status Read Back Command enpD [iz] 13] OUT 1 Hardened Field, Self-Aligned, Junction Isolated CMOS Process + Single 5V Supply * Military Temperature Range -55C to +125C 24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24 Description TOP VIEW The Harris HS-82C54RH is a high performance, radiation hardened da 24 =e Vb CMOS version of the industry standard 8254 and is manufactured i 23 = Wa using a hardened field, self-aligned silicon gate CMOS process. It has bE ==; 3 22 = SAD three independently programmable and functional 16-bit counters, D4 = 4 a acs each capable of handling clock input frequencies of up to SMHz. Six oe c ; io = 2 programmable timer modes allow the HS-82G54RH to be used as an Ot - on 1a Sik 2 event counter, elapsed time indicator, a programmable one-shot, or DO ~_ 8 17 __ 0uT 2 for any other timing application. The high performance, radiation cKO 9 16 SGATE2 hardness, and industry standard configuration of the HS-82C54RH ouTor= = 10 15 = cK 1 make it compatible with the HS-80C86RH radiation hardened micro- GATEQE: 11 14 = GATE processor. GND eq 12 13 =9g OUT Static CMOS circuit design insures low operating power. The Harris hardened field CMOS process results in performance equal to or greater than existing radiation resistant products at a fraction of the power. Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE HS1-82C54RH-Q 55C to +125C H31-82C54RH-8 24 Lead SBDIP 24 Lead SBDIP -55C to +125C HS1-82C54RH-Sample 425C H83-82C54RH-Q H89-82C54RH-8 24 Lead SBDIP -55C to +125C. 24 Lead Ceramic Flatpack -55C to +125C. 24 Lead Ceramic Flatpack HS9-82C54RH/Sample 425C H89-82C54RH/P roto 24 Lead Ceramic Flatpack -55C to +125C 24 Lead Ceramic Flatpack CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper |.C. Handling Procedures. Copyright Harris Corporation 1995 { 518059 3043.1 Spec Number File NumberHS-82C54RH Pin Description PIN SYMBOL | NUMBER TYPE DESCRIPTION D7-Do 1-8 VO DATA: Bi-directional three state data bus lines, connected to system data bus. CLK O 9 | CLOCK 0: Clock input of Counter 0. OUT 0 10 o OUT 0: Output of Counter 0. GATE 0 11 | GATE 0: Gate input of Counter 0. GND 12 GROUND: Power supply connection. OUT 1 13 o OUT 1: Output of Counter 1. GATE 1 14 | GATE 1: Gate input of Counter 1. CLK 1 15 | GLOCK 1: Clock input of Counter 1. GATE 2 16 | GATE 2: Gate input of Counter 2. OUT 2 17 o OUT 2: Output of Counter 2. CLK 2 18 | CLOCK 2: Clock input of Counter 2. Ao, Al 19-20 | ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write operations. Normally connected to the system address bus. Al AO Selects 0 0 Counter 0 0 1 Counter 1 1 0 Counter 2 1 1 Control Word Register cs 21 CHIP SELECT: Alow on this input enables the HS-82C54RH to respond to RD and WR signals. RD and WR are ignored otherwise. RD 22 | READ: This input is low during GPU read operations. WR 23 | WRITE: This inputis low during CPU write operations. VBD 24 VDD: The +5V power supply pin. A 0.1uF capacitor between pins 12 and 24 is recommended for decoupling. Functional Diagram INTERNAL BUS DATA BUS BUFFER CLK O GATES OUT a COUNTER 0 CONTROL WORD REGISTER STATUS LATCH D7 STATUS RD g REGISTER AD z CLK 1 WA a COUNTER Cet AO 3 1 2 OUT 1 At E CONTROL Logic CLK 2 GATE 2 OUT 2 CONTROL WORD REGISTER COUNTER 2 N CLK N OUT N Spec Number 518059Specifications HS-82C54RH Absolute Maximum Ratings Reliability Information Supply Voltage... 0... eee +7.0V. Thermal Resistance BA Bie Input or Output Voltage SBDIP Package.................... 40C WCW Applied for all Grades.... 2.0... .0.00000. VS3S8-0.3V to VDD+0.3V Ceramic Flatpack Package ........... 60C aCcw Storage Temperature Range ................. -65C to +150C =Maximum Package Power Dissipation at +125C Ambient Junction Temperature... 6... eee +175C SBDIP Package......... 0.0.0... 1.25W Lead Temperature (Soldering 10s).................... +300C Ceramic Flatpack Package ....................0.05. 0.83W Typical Derating Factor........... 2.4mA/MHz Increase in IDDOP If device power exceeds package dissipation capability, provide heat ESD Classification ...... 0.0.0.0... ee Class 1 sinking or derate linearly at the following rate: SBDIP Package............. 00.0.0. e eee eee 25.0mWiC Ceramic Flatpack Package 16.7mW/C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage ito the device. This is a stress only rating and operation of the device al these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions +4.5V to +5.5V -55C to +125C Operating Voltage Range Operating Temperature Range................ Input Low Voltage (VIL)... 6... eee OV to +0.8V Input High Voltage (VIH) VDD -1.5V to VBD TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A LIMITS PARAMETER SYMBOL CONDITIONS SUBGROUPS | TEMPERATURE | MIN | MAX | UNITS TTL Output High Current IOH1 VDD = 4.5V, VO = 3.0V, 1,2,3 -55C, +25C, -2.5 mA VIN = OV of 4.5V +125C CMOST Output High IOH2 VDD = 4.5V, VO = 4.1V, 1,2,3 -55C, +25C, -100 pA Current VIN = 0Vor4.5V +125C Output Low Current IOL VDD = 4.5V, VO = 0.4V, 1,23 -55C, +25C, 25 mA VIN = OV or 4.5V 4+125C Input Leakage Current ILorlIH | VDD =5.5V, VIN =0Vor5.5V 1,23 -55C, +25C, -1.0 1.0 A Pins: 9,11, 14-16, 18-23 4125C Output Leakage Current lOZ7L or | VDD =5.5V, VIN = OV of 5.5V 1,2,3 -55C, +25C, -10 10 pA 1OZH Pins: 1-8 +125C Standby Power Supply IDDSB VDD =5.5V, VIN=GNDor VDD 1,2,3 -5BC, +25C, 20.0 pA Current IO = OmA, Counters +125C Programmed Operating Power Supply IDDOP VDD =5.5V, VIN=GNDor VDD 1,2,3 -5BC, +25C, 12.0 mA Current IO = OmA, CLKO = CLK1 = +125C CLK2 = 5MHz Functional Tests FT VDD = 4.5V and 5.5V, 7, 8A, 8B -55C, +25C, VIN = GND or VDD, f = 1MHz +125C Noise Immunity FN VDD = 5.5V, VIN = GND or 7, 8A, 8B -55C, 425C, Functional Test VDD - 1.5 and VDD = 4.5V, 4125C VIN = 0.8V or VDD TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS AC's Tested at Worst Case VDD (s), Guaranteed Over Full Operating Range. LIMITS GROUP A PARAMETER SYMBOL CONDITIONS SUBGROUPS TEMPERATURE MIN | MAX | UNITS Address Stable Before RD TAVRL | VDD=4.5V 9, 10, 11 -55C, +25C, +125C 75 ns CS Stable Before RD TSLRL | VDD =4.5V 9, 10, 11 -55C, +25C, +125C 0 ns Address Hold Time After RD TRHAX | VDD=4.5V 9,10, 11 -55C, +25C, +125C 0 ns RD Pulse Width TRLRH | VDD=4.5V 9,10, 11 -55C, +25C, 4125C | 240 ns Data Delay from RD TRLDV | VDD=4.5V g,10,11 -55C, +25C, +125C 200 ns Spec Number 518059Specifications HS-82C54RH TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) ACs Tested at Worst Case VDD (s), Guaranteed Over Full Operating Range. GROUP A Mis PARAMETER SYMBOL CONDITIONS | SUBGROUPS TEMPERATURE MIN | MAX | UNITS Command Recovery Time TRHRL | VDD=4.5V 9,10, 11 -55C, +25C, +125C 320 ns WRITE CYCLE Address Stable Before WR TAVWL [| VDD=4.5V 9,10, 11 -559C, 425C, 41259C 0 ns CS Stable Before WR TSLWL | VDD=4.5V 9, 10, 11 55C, +25C, +125C 0 ns Address Hold Time After WR TWHAX | VDD =4.5V 9,10, 11 -55C, +25C, +125C 0 ns WR Pulse Width TWLWH [| VDD =4.5V 9,10, 11 -55C, +25C, +125C 240 ns Data Setup Time Before WR TDVWH | VDD =4.5V 9,10, 11 559C, +25C, 41259C 225 ns Data Hold Time After WR TWHDX [| VDD=4.5V 9,10, 11 -55C, +25C, +125C 35 ns Command Recovery Time TWHWL | VDD = 4.5V 9,10, 11 -55C, +25C, +125C 320 ns CLOCK AND GATE Clock Period TCLCL | VDD=45V 9,10, 11 -55C, +25C, +125C 200 ns High Pulse Width TCHCL | VDD=4.5V 9,10, 11 -55C, +25C, +125C 100 ns Low Pulse Width TCLCH [| VDD=4.5V 9,10, 11 -55C, +25C, +125C 100 ns Gate Width High TGHGL | VDD =4.5V 9,10, 11 -55C, +25C, +125C 80 ns Gate Width Low TGLGH | VDD =4.5V 9,10, 11 -55C, +25C, +125C 80 ns Gate Setup Time to CLK TGVCH [VDD=4.5V 9,10, 11 -55C, +25C, +125C 80 ns Gate Hold Time After CLK TCHGX | VDD=4.5V 9,10, 11 -55C, +25C, +125C 80 ns Output Delay from CLK TCLOV | VDD=4.5V 9,10, 11 -B5C, 425C, 41259C 240 ns Output Delay from Gate TGLOV | VDD=4.5V 9,10, 11 -55C, +25C, +125C 200 ns Data Delay from Address Read TAVAV [| VDD=4.5V 9,10, 11 -55C, +25C, +125C 275 ns Output Delay from WR High TWHOVY | VDD =4.5V 9,10, 11 -559C, 425C, 41259C 260 ns TABLE 3. ELECGTRIGAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS TEMPERATURE MIN | MAX | UNITS Input Capacitance CIN VDD = Open, f = 1MHz, Ta = +25C 15 pF All measurements referenced to device ground. Output Capacitance COUT VDD = Open, f = 1MHz, Ta = +25C 15 pF All measurements referenced to device ground. /O Capacitance COUT VDD = Open, f = 1MHz, Ta = +25C 20 pF All measurements referenced to device ground. TIMING REQUIREMENTS RD/ to Data Fleat TRHDZ | VDD =4.5V and 5.5V -55C < Ta < +125C 8 145 ns TIMING RESPONSES Clock Rise Time TCHICH?2 | VDD = 4.5V and 5.5V, 1.0V to 3.5V -55C < Ta < +125C 25 ns Clock Fall Time TCLICL2 | VDD = 4.5V and 5.5V, 3.5V to 1.0V -55C < Ta < +125C 25 ns NOTE: The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are character- ized upon initial design release and upon design changes which would affect these characteristics. Spec Number 518059Specifications HS-82C54RH TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: See +25C limits in Table 1 and Table 2 for Post RAD limits (Sub Groups 1, 7 and 9). TABLE 5. BURN-IN DELTA PARAMETERS (+25C) PARAMETER SYMBOL DELTA LIMITS Standby Power Supply Current IDDSB +2A Output Leakage Current IGZL, IOZH +2 A Input Leakage Current HH, HL +200nA Output Low Current IOL +500uA or 10% of BBI Reading* TTL Output High Current IGH TTL +500nA or 10% of BBI Reading CMOS Cutput High Current IOH CMOS +204 or 10% of BBI Reading* * Which ever is greater. TABLE 6. APPLICABLE SUBGROUPS GROUP A SUBGROUPS CONFORMANCE MIL-STD-883 RECORDED RECORDED GROUP METHOD TESTED FOR -Q FOR -Q@ TESTED FOR -8 FOR -8 Initial Test 100% 5004 1,7,9 1 (Note 2) 1,7,9 Interim Test 100% 5004 17,9,A 1, A(Note 2) 1,7,9 PDA 100% 5004 1,7, 1,7 Final Test 100% 5004 2, 3, BA, 8B, 10, 11 2,3, 8A, 8B, 10, 11 Group A (Note 1) Sample 5005 1, 2,3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, BA, 8B, 9, 10,11 Subgroup BS Sample 5005 1,2, 3, 7, 8A, 8B, 9,10,11,A | 1,2,3, A (Note 2) N/A Subgroup B6 Sample 5005 1,7,9 N/A Group C Sample 5005 NYA NA 1,2, 3, 7, 8A, 8B, 9, 10,11 Group D Sample 5005 1,7,9 1,7,9 Group E, Subgroup 2 Sample 5005 1,7,9 1,7,9 NOTES: 1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised. 2. Table 5 parameters only Spec Number 518059HS-82C54RH Harris Space Level Product Flow -Q Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% Die Attach 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Methed 2010, Condition A CSI and/or GS| PreCap (Note 6} 100% Temperature Cycle, Method 1019, Gondition , 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (TO) 100% Static Burn-In 1, Condition A or B, 72 Hours Min, +125G Min, Method 1015 NOTES: 100% Interim Electrical Test 1 (71) 100% Delta Calculation (T0-T1) 100% PDA 1, Method 5004 (Note 1) 100% Dynamic Burn-In, Condition D, 240 Hours, +125C or Equivalent, Method 1015 100% Interim Electrical Test 2(T2) 100% Delta Calculation (T0-T2) 100% PDA 2, Method 5004 (Note 1) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic (X-Ray), Method 2012 (Note 2} 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 3) Sample - Group B, Method 5005 (Note 4) Sample - Group D, Method 5005 (Notes 4 and 5) 100% Data Package Generation (Note 7) CSI and/or GSI Final (Note 6) 1. Failures from subgroup 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 2. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 3. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 4. Group B and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B Test, Group B Samples, Group D Test and Group D Samples. 5. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.. should include a separate line item for Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases. 6. CSI and/or GSI inspections are optional and will not be performed unless required by theP.O. When required, the P.. should include separate line items for CS! PreCap inspection, CSI final inspection, GSI PreCap inspection, and/or GSI final inspection. 7. Data Package Contents: X-Ray report and film. Includes penetrometer measurements. by an authorized Quality Representative. Cover Sheet (Harris Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Harris Part Number, Lot Number, Quantity). Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photoes with percent of step coverage. GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Harris. Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). Lot Serial Number Sheet (Good units serial number and lot number). Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. Group B and D attributes and/or Generic data is included when required by the P.O. The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformanceis signed Spec Number 518059HS-82C54RH Harris Space Level Product Flow -8 GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% Die Attach Periodic- Wire Bond Pull Monitor, Method 2011 Periodic- Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition B CSI an/or GSI PreGap (Note 5) 100% Temperature Cycle, Method 1019, Gondition , 10 Cycles 100% Constant Acceleration, Method 2001, Condition per 100% Dynamic Burn-In, Condition D, 160 Hours, +125C or Equivalent, Method 1015 100% Interim Electrical Test 100% PDA, Method 5004 (Note 1} 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 2) Sample - Group B, Method 5005 (Note 3) Method 5004 100% External Visual 100% Initial Electrical Test ( Sample - Group , Method 5005 (Notes 3 and 4) Sample - Group D, Method 5005 (Notes 3 and 4) 100% Data Package Generation (Note 6) CSI and/or GS! Final (Note 5) NOTES: 1. Failures from subgroup 1, 7 are used for calculating PDA. The maximum allowable PDA = 5%. 2. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 3. Group B, C and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B Test, Group Test, Group G Samples, Group D Test and Group D Samples. 4. Group C and/or Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.. should include a separate line item for Group C Generic Data and/or Group D Generic Data. Generic data is not guar- anteed to be available and is therefore not available in all cases. 5. CSI and/or GSI inspections are optional and will not be performed unless required by theP.O. When required, the P.@. should include separate line items for CSI PreCap inspection, CSI final inspection, GSI PreCap inspection, and/or GSI final inspection. 6. Data Package Contents: + Cover Sheet (Harris Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Harris Part Number, Lot Number, Quantity). * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Harris. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). + Group B, C and D attributes and/or Generic data is included when required by the P.O. + The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformanceis signed by an authorized Quality Representative. Spec Number 518059HS-82C54RH AC Test Circuits AC Testing input, Output Waveform v1 R41 INPUT INPUT OUTPUT FROM TEST VIH 40.4V VOH DEVICE UNDER TEST POINT 1.5V S S 15V R2 Tt VIL 0.4V VOL * Includes stray and jig capacitance NOTE: AC Testing: All input signals must switch between VIL -0.4V and VIH +0.4V. Input rise and fall times are driven at ins/V. TEST CONDITION DEFINITION TABLE TEST CONDITION v1 Ri R2 C1 1 1.7 510 OPEN | 150pF Waveforms AQ-1 DATA BUS Ao-1 * TAVRL > ~=- TRHAX cs \ TSLRL> [= oN RLRH gees RD 2e| - TRHDZ TRLDV s) oe _ WR DAA s = = = = mm = = VALID = BUS FIGURE 1. WRITE FIGURE 2. READ TCLCH TCLicL2 TCHCL TCLCL_ hr cLK TCH1CH2 : 4 le-TevcH _JGHGL TCHGX TRHAL GATEG Sf \ _TWHWL TGLGH s! be _TCLOV RD, WR OUTPUT a haa 2=| TGLOV TCHGX ee FIGURE 3. RECOVERY FIGURE 4. CLOCK AND GATE Spec Number 518059HS-82C54RH Burn-in Circuits VDD VDD F3 F4 Fs F6 Fr Fa Fa Fo Fid _ F 7 ag Fo Fi STATIC CONFIGURATION FOR BOTH DYNAMIC CONFIGURATION FOR BOTH FLATPACK & SBDIP PACKAGE FLATPACK & SBDIP PACKAGE NOTES: NOTES: 1. VDD = 6.5V 45% 1. VDD = 6.5V + 5%(Burn-In) 2. Ta = +125C Minimum 2. VDD = 6.0V + 5%(Life Test) 3. Resistors = 10kQ 3. Ta = +125C Minimum 4. IDD < 100pA 4. IDD < 20mA 5. AC: FO is compliment of FO 5. Resistors = 10K, except for loads = 2.7kQ FQ is a 50% duty cycle pulse burst 6. -O.3V <VIL<0.8V FQ is left high after pulse burst 7. VDD -1.0V < VIH = VDD +0.5V 8. AC: FO is compliment of FO FQ = 100kHz +10%, 50% Duty Cycle Fi = FO/2, F2=Fi/2...Fi0=F9/2 irradiation Circuits HS-82C54RH 5.5V NOTES: 1. VOD=5.5V+ 10%, Ta = +25C 2. Group E Testing is performed in Sidebrazed DIP 3. Group E Sample Size is 2 diefwafer Spec Number 518059HS-82C54RH Functional Description General The HS-82C54BRH is a programmable interval timer/counter designed for use with microcomputer systems. It is a general purpose, multi-timing element that can be treated as an array of I/O ports in the system software. The HS-82C54RH solves one of the most common prob- lems in any microcomputer system, the generation of accu- rate time delays under software control. Instead of setting up timing loops in software, the programmer configures the HS-82G54RH to match his requirements and programs one of the counters for the desired delay. After the desired delay, the HS-82C54RH will interrupt the CPU. Software overhead is minimal and variable length delays can easily be accommodated. Some of the other timer functions common to micro-comput- ers which can be implemented with the HS-82C54RH are: * Real time clock Event counter Digital one-shot Programmable rate generator Square wave generator Binary rate multiplier Gomplex waveform generator Complex motor controller Data Bus Buffer This three-state, bi-directional, 8-bit buffer is used to interface the HS-82C54RH to the system bus (see Figure 5). cLKO GATEQ OUTS COUNTER D7. a CLK 1 GATE 1 COUNTER 1 OuT 1 INTERNAL BUS CLK 2 GATE 2 OUT 2 CONTROL WORD EGISTER COUNTER 2 FIGURE 5. DATA BUS BUFFER AND READ/WRITE LOGIC FUNCTION Read/Write Logic The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the HS-82C54RH. Al and AO select one of the three counters or the Control Word Register to be read from/ written into. A low on the RD input tells the HS-82C54RH that the CPU is reading one of the counters. A low on the WR input tells the HS-82C54RH that the CPU is writing either a Control Word or an initial count. Both RD and WA are qualified by CS; AD and WR are ignored unless the HS-82C54RH has been selected by holding CS low. Control Word Register The Control Word Register (Figure 6) is selected by the Read/Write Logic when A1, AO = 11. If the CPU then does a write operation to the HS-82C54RH, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the Gounter operation. The Gontrol Word Register can only be written to; status information is available with the Read-Back Command. Counter 0, Counter 1, Counter 2 These three functional clocks are identical in operation, so only a single Counter will be described. The internal block diagram of a single counter is shown in Figure 7. The counters are fully independent. Each Counter may operate in a different Mode. The Control Word Register is shown in the figure; it is not part of the Counter itself, but its contents determine how the Counter operates. DATA BUS BUFFER D?-DO INTERNAL BUS CLK 2 GATE 2 OUT 2 | COUNTER | ur FIGURE 6. CONTROL WORD REGISTER AND COUNTER FUNCTIONS 10 Spec Number 518059HS-82C54RH INTERNAL BUS STATUS LATCH STATUS EGI CLKN OUTN FIGURE 7. COUNTER INTERNAL BLOCK DIAGRAM The Status Register, shown in the figure, when latched, contains the current contents of the Control Word Register and status of the output and null count flag. (See detailed explanation of the Read-Back Gommand.} The actual counter is labeled CE for Counting Element. It is a 16-bit presettable synchronous down counter. LM and OLL are two 8-bit latches. OL stands for Output Latch, subscripts M and L for Most significant byte and Least significant byte, respectively. Both are normally referred to as one unit and called just OL. These latches normally follow the CE, but if a suitable Counter Latch Gommand is sent to the HS-82C54RH, the OL latches the present count until read by the CPU and then returns to following the CE. One latch at a time is enabled by the counters Control Logic to drive the internal bus. This is how the 16-bit Counter communicates over the 8-bit internal bus. Note that the CE itself cannot be read; whenever you read the count, it is the OL that is being read. Similarly, there are two 8-bit registers called CRM and CRL (for Count Register}. Both are normally referred to as one unit and called just CR. When a new count is written to the Gounter, the count is stored in the GR and later transferred to the CE. The Control Logic allows one register at a time to be loaded from the internal bus. Both bytes are transferred to the CE simultaneously. CRM and CRL are cleared when the Counter is programmed for one byte counts (either most significant byte only or least significant byte only) the other byte will be zero. Note that the CE cannot be written into; whenever a count is written, it is written into the CR. The Control Logic is also shown in the diagram. CLKn, GATEn, and OUTn are all connected to the outside world through the Control Logic. HS-82C54RH System Interface The HS-82C54RH is treated by the system software as an array of peripheral I/O ports; three are Counters and the fourth is a Control Word Register for MODE programming. Basically, the select inputs AO, Ai connect to the AO, Al address bus signals of the CPU. The CS can be derived directly from the address bus using a linear select method or it can be connected to the output of a decoder, such as a Harris HD-6440 for larger systems. ADDRESS BUS (16) | At | AQ | CONTROL BUS | | |vOR vow 4S DATA BUS (8) Al AQ CS Do-D7 HS-82C54RH COUNTER COUNTER COUNTER a 1 2 OUT GATE CLK OUT GATE CLK OUT GATE CLK TTT TTT TTT FIGURE 8. HS-82C54RH SYSTEM INTERFACE Operational Description General After power-up, the state of the HS-82C54RH is undefined. The Mode, count value, and cutput of all Counters are undefined. How each Counter operates is determined when it is programmed. Each Gounter must be programmed before it can be used. Unused Counters need not be programmed. Programming The HS-82C54RH Counters are programmed by writing a Gontrol Word and then an initial count. All Control Words are written into the Control Word Register, which is selected when A1, AO = 11. The Control Word specifies which Counter is being programmed. By contrast, initial counts are written into the Counters, not the Gontrol Word Register. The A1, AO inputs are used to select the Counter to be written into. The format of the initial count is determined by the Control Word used. Write Operations The programming procedure for the HS-82C54RH is very flexible. Only two conventions need to be remembered: 1. For each Counter, the Control Word must be written before the initial count is written. . The initial count must follow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). Since the Control Word Register and the three Counter shave separate addresses (selected by the A1, AO inputs}, and each Control Word specifies the Counter it applies to (SCO, SC1 bits), no special instruction sequence is required. Any programming sequence that follows the conventions above is acceptable. 14 Spec Number 518059HS-82C54RH Control Word Format Ai, AQ =11;CS=0; RD=1:WR=0 D7 D6 DS D4 D3 D2 D1 DO 8c 8c2 RW1 RwWo M2 M1 Mo BCD SC - Select Counter: M - Mode: sci sco Select Counter 0 Select Counter 1 Select Counter 2 Read-Back Command (See Read Operations) RW - Read/Write RW1 RWo 0 0 Counter Latch Command (See Read Operations) BCD - Binary Coded Decimal: 0 1 ReadMrite least significant byte only. 0 Binary Counter 16-bits 1 0 Read/Write most significant byte only. 1 Binary Coded Decimal (BCD) Counter (4 Decades) 1 1 ReadMrite least significant byte first, then NOTE: Dont Care bits (X) should be 0 to insure compatibility with most significant byte. future products. FIGURE 9. CONTROL WORD FORMAT Control Word - Counter 0 Control Word - Counter 2 LSB of count - Counter 0 Control Word - Counter 1 MSB of count - Counter 0 Control Word - Counter 0 Control Word - Counter 1 LSB of count - Counter 2 LSB of count - Counter 1 MSB of count - Counter 2 MSB of count - Counter 1 LSB of count - Counter 1 Control Word - Counter 2 MSB of count - Counter 1 LSB of count - Counter 2 LSB of count - Counter 0 MSB of count - Counter 2 MSB of count - Counter 0 Control Word - Counter 0 Control Word - Counter 1 Control Word - Counter 1 Control Word - Counter 0 Control Word - Counter 2 LSB of count - Counter 1 LSB of count - Counter 2 Control Word - Counter 2 LSB of count - Counter 1 LSB of count - Counter 0 LSB of count - Counter 0 MSB of count - Counter 1 MSB of count - Counter 0 LSB of count - Counter 2 MSB of count - Counter 1 MSB of count - Counter 0 MSB of count - Counter 2 1 0 MSB of count - Counter 2 NOTE: In all fourexamples, all counters are programmed to Read/Write two-byte counts. These are only four of many possible programming sequences. FIGURE 10. A FEW POSSIBLE PROGRAMMING SEQUENCES Spec Number 518059 12HS-82C54RH A new initial count may be written to a Counter at any time without affecting the Counters programmed Mcede in anyway. Counting will be affected as described in the Mode definitions. The new count must follow the programmed count format. If a Counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter. Otherwise, the Counter will be loaded with an incorrect count. Read Operations It is often desirable to read the value of a Counter without disturbing the count in progress. This is easily done in the HS-82C54RH. There are three possible methods for reading the Gounters. The first is through the Read-Back Gommand, which is explained later. The second is a simple read operation of the Counter, which is selected with the A1, AO inputs. The only requirement is that the GLK input of the selected Counter must be inhibited by using either the GATE input or external logic. Otherwise, the count may be in process of changing when it is read, giving an undefined result. Counter Latch Command The other methed for reading the Counters involves a special software command called the Counter Latch Gommand. Like a Control Word, this command is written to the Control Word Register, which is selected when A1, AO = 11. Also, like a Control Word, the SCO, SC1 bits select one of the three Counters, but two other bits, D5 and D4, distinguish this command from a Control Word. Ai, AO =11;CS=0;RAD=1; WR=0 held in the latch until it is read by the CPU (or until the Counter is reprogrammed}. The count is then unlatched automatically and the OL returns to following the Counting Element (CE). This allows reading the contents of the Counters on the fly without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one Counter. Each latched Counters OL holds its count until read. Counter Latch Commands do not affect the programmed Mode of the Counter in any way. lf a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch Command is ignored. The count read will be the count at the time the first Counter Latch Command was issued. With either method, the count must be read according to the programmed format; specifically, if the Counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other; read or write or programming operations of other Counters may be inserted between them. Another feature of the HS-82C54RH is that reads and writes of the same Counter may be interleaved; for example, if the Counter is programmed for two byte counts, the following sequence is valid. 1. Read least significant byte. 2. Write new least significant byte. 3. Read most significant byte. 4. Write new most significant byte. If a Counter is programmed to read or write two-byte counts, the following precaution applies: A program MUST NOT transfer control between reading the first and second byte to another routine which also reads from that same Counter. Otherwise, an incorrect count will be read. Read-Back Command D7 D6 D5 D4 D3 D2 D1 Bo | SCI | Sco | 0 | 0 | X X | X | X The Read-Back Command allows the user to check the : count value, programmed Mode, and current state of the $C1, SCO - specify counter to be latched OUT pin and Null Count flag of the selected Counter(s). Sci Sci Counter The command is written into the Control Word Register and has the format shown in Figure 12. The command applies to 0 0 0 the Gounters selected by setting their corresponding bits D3, 0 0 1 D2,D1i=1. , , > AO, Al = 11;CS=0;AD=1;WR=0 1 1 Read-Back Command D7 06 DS D4 D3 D2 D1 Do D5, D4 = 00 designates Counter Latch Command 1 1 COUNT | STATUS J CNT 2} CNT TICNT OT 0 X = Don't Care D5: 0 = Latch count of selected Counters(s) NOTE: Dont Care bits (X) should be 0 to insure compatibility with D4: 0 = Latch status of selected Counters(s) fut duct D3: 1 = Select Counter 2 HIUFe Products. D2: 1 = Select Counter 1 FIGURE 11. COUNTER LATCH COMMAND FORMAT D1: 1 = Select Counter 0 DO: Reserved for future expansion; Must be 0 The selected Counters Qutput Latch (OL) latches the count when the Counter Latch Command is received. This count is FIGURE 12. READ-BACK COMMAND FORMAT Spec Number 518059 13HS-82C54RH The Read-Back Gommand may be used to latch multiple Counter Output Latches (OL) by setting the COUNT bit D5 = 0 and selecting the desired Counter(s). This single command is functionally equivalent to several Counter Latch Gommands, one for each Gounter latched. Each Counters latched count is held until it is read (or the Counter is repro- grammed). That Counter is automatically unlatched when read, but other Counters remain latched until they are read. If multiple count Read-Back Commands are issued to the same Counter without reading the count, all but the first are ignored; i.e., the count which will be read is the count at the time the first Read-Back Command was issued. The Read-Back Command may also be used to latch status information of selected Counter(s) by setting STATUS bit D4 = 0. Status must be latched to be read; status of a Counter is accessed by a read from that Counter. The Counter status format is shown in Figure 13. Bits DS through DO contain the Gounters programmed Mode exactly as written in the last Mode Control Word. CUTPUT bit D7 contains the current state of the OUT pin. This allows the user to monitor the Counters output via software, possibly eliminating some hardware from a system. D7 D6 D5 D4 D3 D2 Ot1 DBO OUT NULL RW1 | RWO | M2 | M1 MO | BCD PUT COUNT D7 1 = Out Pin is 1 0 = Out pinis 0 D6 71 =Null count 0 = Count available for reading D5-D0 = Counter programmed mode (See Figure 5) FIGURE 13. STATUS BYTE NULL COUNT bit D6 indicates when the last count written to the Counter Register (CR) has been loaded into the Counting Element (CE). The exact time this happens depends on the Mode of the Counter and is described in the Mode Definitions, but until the count is loaded into the Counting Element (CE), it cant be read from the Counter. If the count is latched or read before this time, the count value will not reflect the new count just written. The operation of Null Count is shown in Figure 14. THIS ACTION: CAUSES: A. Write to the Control Word Register: (Note 1) | Null Gount = 1 B. Write to the Count Register (CR): (Note 2) Null Count = 1 C. New count is loaded into CE (CR CE): Null Count = 0 NOTES: 1. Only the Counter specified by the Control Word will have its Null Count set to 1. Null Count bits of other Counters are unaffected. If the Counter is programmed for two-byte counts (least signifi- cant byte then most significant byte} Null Count goes to 1 when the second byte is written. FIGURE 14. NULL COUNT OPERATION If multiple status latch operations of the Counter(s) are performed without reading the status, all but the first are ignored; i.e., the status that will be read is the status of the Counter at the time the first status Read-Back Command was issued. Both count and status of the selected Counter(s) may be latched simultaneously by setting both COUNT and STATUS bits D5, D4 = 0. This is functionally the same as issuing two separate Read-Back Commands at once, and the above discussions apply here also. Specifically, if multiple count and/or status Read-Back Commands are issued to the same Counter(s) without any intervening reads, all but the first are ignored. This is illustrated in Figure 15. If both count and status of a Counter are latched, the first read operation of that Gounter will return latched status, regardless of which was latched first. The next one or two reads (depending on whether the Counter is programmed for one or two byte counts) return latched count. Subsequent reads return unlatched count. COMMAND D4 D7 | D6 | D5 D3 | D2 | D1 DO DESCRIPTION RESULT 1 1 0 0 0 0 1 0 Counter 0 Read back count and status of Count and status latched for Counter 0 Read-back status of Counter 1 Status latched for Counter 1 Read-back status of Counters 2, 1 Status latched for Counter 2, but not Counter 1 Read-back count of Counter 2 Count latched for Counter 2 Counter 1 Read-back count and status of Count latched for Counter 1, but not status Read-back status of Counter 1 Command ignored, status already latched for Counter 1 FIGURE 15. READ-BACK COMMAND EXAMPLE 14 Spec Number 518059HS-82C54RH Write into Counter 0 Write into Counter 1 Write into Gounter 2 Write Control Word Read from Counter 0 Read from Counter 1 Read from Counter 2 No-Gperation (Three-State) No-Gperation (Three-State) 1 1 x No-Gperation (Three-State) FIGURE 16. READ/WRITE OPERATIONS SUMMARY Mode Definitions The following are defined for use in describing the operation of the HS-82C54RH. CLK PULSE: A rising edge, then a falling edge, in that order, of a Counters CLK input. TRIGGER: A rising edge of a Counters Gate input. COUNTER LOADING: The transfer of a count from the CR to the CE (See Func- tional Description) Mode 0: Interrupt on Terminal Count Mode 0 is typically used for event counting. After the Control Word is written, OUT is initially low, and will remain low until the Counter reaches zero. OUT then goes high and remains high until a new count or a new Moce 0 Control Word is written to the Counter. GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect on OUT. After the Control Word and initial count are written to a Counter, the initial count will be loaded on the next CLK pulse. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not go high until N+ 1 CLK pulses after the initial count is written. If a new count is written to the Counter it will be loaded on the next GLK pulse and counting will continue from the new count. If a two-byte count is written, the following happens: 1. Writing the first byte disables counting. OUT is set low immediately (no clock pulse required). 2. Writing the secondbyte allows the new count to be loaded on next GLK pulse. This allows the counting sequence to be synchronized by software. Again OUT does not go high until N + 1 CLK pulses after the new count of N is written. If an initial count is written while GATE = Q, it will still beloaded on the next CLK pulse. When GATE goes high, OUT will go high N GLK pulses later; no GLK pulse is needed to load the Counter as this has already been cone. cw=10 LSB=4 0 0 FF FF FF FE | OUT \ i a0,90 g 0 0 0 | FF Ju|u[win | ]g oie |S lel cCW-=10 LSB=3 LSB =2 GATE OUT vases \ a0{/o j}o |o|0 | oO |FF siw[win [Sooo (209) ole . Counters are programmed for binary (not BCD) counting and for readingAwriting least significant byte (LSB) only. . The Counter is always selected (CS always low). 3. CW stands for Control Word; CW = 10 means a Control Word of 10, Hex is written to the Counter. 4. LSB stands for Least significant byte of count. . Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the most signifi- cant byte. Since the Counter is programmed to read/write LSB only, the most significant byte cannot be read. 6. N stands for an undefined count. . Vertical lines show transitions between count values. FIGURE 17. MODE 0 Mode 1: Hardware Retriggerable One-Shot OUT will be initially high. OUT will go low on the GLK pulse following a trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high and remain high until the GLK pulse after the next trigger. After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse N GLK cycles in duration. The one-shot is retrigger- able, hence OUT will remain low for N CLK pulses after any trigger. The one-shot pulse can be repeated without rewriting the same count into the Gounter. GATE has no effect on OUT. If a new count is written to the Counter during a one-shot pulse, the current one-shot is not affected unless the Counter is retriggered. In that case, the Counter is loaded 15 Spec Number 518059HS-82C54RH with the new count and the one-shot pulse continues until the new count expires. CW=12 LSB=3 ojo |o|o sini inin soe [9 [a | Peis |g | FF /3 | 2 CW=12 LSB=3 0/90 0 Li 0/90 0 simon nin sie isis le ls [el CW=12 LSB=2 LSB=4 we LST Vd eK UU LULL ALL LAL GATE UTNE, rman Promere FF Eig |g | FF |FE|4 | 3 NOTES: 1. Counters are programmed for binary (not BCD) counting and for reading/writing least significant byte (LSB) only. 2. The Counteris always selected (CS always low). 3. CW stands for Control Word; CW = 10 means a Control Word of 10, Hex is written to the Counter. 4. LSB stands for Least significant byte of count. . Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the most signifi- cant byte. Since the Gounter is programmed to read/write LSB only, the most significant byte cannot be read. 6. N stands for an undefined count. 7. Vertical lines show transitions between count values. FIGURE 18. MODE 1 Mode 2: Rate Generator This Mode functions like a divide-by-N counter. It is typically used to generate a Real Time Clock interrupt. OUT will initially be high. When the initial count has decremented to 1, OUT goes low for one CLK pulse. OUT then goes high again, the Counter reloads the initial count and the process is repeated. Mode 2 is periodic; the same sequence is repeated indefinitely. For an initial count of N, the sequence repeats every N CLK cycles. GATE = 1 enables counting; GATE = 0 disables counting. If GATE goes low during an output pulse, OUT is set high immediately. A trigger reloads the Counter with the initial count on the next GLK pulse; OUT goes low N CLK pulses after the trigger. Thus the GATE input can be used to synchronize the Gounter. After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. OUT goes low N CLK pulses after the initial count is written. This allows the Counter to be synchronized by software also. Writing a new count while counting does not affect the current counting sequence. If a trigger is received after writing a new count but before the end of the current pericd, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count. Otherwise, the new count will be loaded at the end of the current counting cycle. CW-=14 LSB=3 ao; 0 0 a o o 0 in iN Jn || gle ig Is |g 131s | CW-=12 LSB=3 WR GATE \ ; OUT j 1 } Qa /|]0a 0 0 0 0 g In inn fn | glee 1s Is 13 1s | CwW-=14 LSB=4 LSB =5 GATE OUT | Ly 0 0 0 0 0 0/9 Nin(n [uals] (9 )s a|s. NOTES: . Gounters are programmed for binary (not BCD) counting and for readingAwriting least significant byte (LSB) only. . The Counter is always selected (CS always low). 3. CW stands for Control Word; CW = 10 means a Control Word of 10, Hex is written to the Counter. 4. LSB stands for Least significant byte of count. . Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the most signifi- cant byte. Since the Counter is programmed to read/write LSB only, the most significant byte cannot be read. 6. N stands for an undefined count. . Vertical lines show transitions between count values. FIGURE 19. MODE 2 Mode 3: Square Wave Mode Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2 except for the duty cycle of OUT. OUT will initially be high. When half the initial count has expired, OUT goes low for the remainder of the count. Mode 3 is periodic; the sequence above is repeated indefinitely. An initial count of N results in a square wave with a period of N CLK cycles. 16 Spec Number 518059HS-82C54RH GATE = 1 enables counting; GATE = 0 disables counting. If GATE goes low while OUT is low, OUT is set high immedi- ately; no GLK pulse is required. A trigger reloads the Counter with the initial count on the next CLK pulse. Thus the GATE input can be used to synchronize the Counter.After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. This allows the Counter to be synchronized by software also. Writing a new count while counting does not affect the cur- rent counting sequence. If a trigger is received after writing a new count but before the end of the current half-cycle of the square wave, the Counter will be loaded with the new count on the next GLK pulse and counting will continue from the new count. Otherwise, the new count will be loaded at the end of the current half-cycle. Mode 3 is implemented as follows: EVEN COUNTS: OUT is initially high. The initial count is loaded on one GLK pulse and then is decremented by two on succeeding GLK pulses. When the count expires, OUT changes value and the Counter is reloaded with the initial count. The above process is repeated indefinitely. ODD COUNTS: OUT is initially high. The initial count is loaded on one GLK pulse, decremented by one on the next CLK pulse, and then decremented by two on succeeding CLK pulses. When the count expires, OUT goes low and the Counter is reloaded with the initial count. The count is decre- mented by three on the next GLK pulse, and then by two on succeeding GLK pulses.When the count expires, OUT goes high again and the Counter is reloaded with the initial count. The above process is repeated indefinitely. So for odd counts, OUT will be high for (N + 1}/2 counts and low for (N-1}/2 counts. Mode 4: Software Triggered Mode OUT will be initially high. When the initial count expires, OUT will go low for one GLK pulse then go high again. The count- ing sequence is Triggered by writing the initial count. GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect on OUT. After writing a Control Word and initial count, the Counter will be loaded on the next GLK pulse. This GLK pulse does not decrement the count, so for an initial count of N, OUT does not strobe low until N + 1 GLK pulses after the initial count is written. If a new count is written during counting, it will be loaded on the next GLK pulse and counting will continue from the new count. If a two-byte count is written, the following happens: 1. Writing the first byte has no effect on counting. 2. Writing the secondbyte allows the new count to be loaded on the next CLK pulse. This allows the sequence to be retriggered by software. OUT strobes low N + 1 CLK pulses after the new count of N is written. Mode 5: Hardware Triggered Strobe (Retriggerable) OUT will initially be high. Gounting is triggered by a rising edge of GATE. When the initial count has expired, OUT will go low for one GLK pulse and then go high again. After writing the Control Word and initial count, the Counter will not be loaded until the CLK pulse after a trigger. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not strobe low until N + 1 CLK pulses after trigger. A trigger results in the Counter being loaded with the initial count on the next CLK pulse. This allows the counting sequence to be regretted. OUT strobes low N + 1 CLK pulses after any new trigger. GATE has no effect on the state of OUT. If a new count is written during counting, the current count- ing sequence will not be affected. If a trigger occurs after the new count is written but before the current count expires, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there. CW=16 LSB=4 we LS cu PULP UP LLLP GATE out Ls S$ Infwfw im oles ola [salsa |e. 0;a/0 o|9a a0/9a 0/0 0 In[wimin ilo is ie i2 [sig isis is. CW=16 LSB=4 we VSL] GATE \ j ow - g0;0/90 o|90 0/9 0/0 0 In[mfn ini gels isle feiss is ie. NOTES: . Counters are programmed for binary (not BCD) counting and for readingwriting least significant byte (LSB) only. . The Counter is always selected (CS always low). 3. CW stands for Control Word; CW = 10 means a Control Word of 10, Hex is written to the Counter. . LSB stands for Least significant byte of count. 5. Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the most signifi- cant byte. Since the Counter is programmed to read/write LSB only, the most significant byte cannot be read. 6. N stands for an undefined count. 7. Vertical lines show transitions between count values. FIGURE 20. MODE 3 17 Spec Number 518059HS-82C54RH cCW=18 LSB=3 CW=1A LSB =3 0 )0 |0 | O |FE | FF/ FF 2 |1 =| 0 |FF | FE/FD CW =18 LSB =3 WR GATE out J a Isfuin|y]s]e 9 (oo) 6 lee. NOTES: 1. Counters are programmed for binary (not BCD) counting and for readingAwriting least significant byte (LSB) only. 2. The Counter is always selected (CS always low). . CW stands for Control Word: CW = 10 means a Control Word of 10, Hex is written to the Counter. 4. LSB stands for Least significant byte of count. . Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the most signifi- cant byte. Since the Counter is programmed to read/write LSB only, the most significant byte cannot be read. 6. N stands for an undefined count. 7. Vertical lines show transitions between count values. FIGURE 21. MODE 4 WR 4 );0o )}0 |0 |FF/FF;/ 9/9 3 |2 |1 |0 |FF\/FE| 5 /|4 NOTES: . Counters are programmed for binary (not BCD) counting and for readingAwriting least significant byte (LSB) only. 2. The Counter is always selected (CS always low). . CW stands for Control Word: CW = 10 means a Control Word of 10, Hex is written to the Counter. 4. LSB stands for Least significant byte of count. . Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the most signifi- cant byte. Since the Counter is programmed to read/write LSB only, the most significant byte cannot be read. 6. N stands for an undefined count. 7. Vertical lines show transitions between count values. FIGURE 22. MODE 5 18 Spec Number 518059HS-82C54RH Operation Common to All Modes Programming When a Control Word is written to a Counter, all Control Logic is immediately reset and OUT goes to a known initial state; no CLK pulses are required for this. Gate The GATE input is always sampled on the rising edge of CLK. In Modes 0, 2, 3 and 4 the GATE input is level sensitive, and logic level is sampled on the rising edge of CLK. In modes 1, 2, 3 and 5 the GATE input is rising-edge sensitive. In these Mcdes, a rising edge of Gate (trigger) sets an edge-sensitive flip-flop in the Counter. This flip-flop is then sampled on the next rising edge of CLK. The flip-flop is reset immediately after it is sampled. In this way, a trigger will be detected no matter when it occurs - a high logic level does not have to be maintained until the next rising edge of CLK. Note that in Modes 2 and 3, the GATE input is both edge-and level-sensitive. Counter New counts are loaded and Counters are decremented on the falling edge of CLK. The largest possible initial count is 0; this is equivalent to 2"5 for binary counting and 10* for BCD counting. The Gounter does not stop when it reaches zero. In Modes 0, 1, 4 and 5 the Counter wraps around to the highest count, either FFFF hex for binary counting or 9999 for BCD counting, and continues counting. Modes 2 and 3 are periodic; the Counter reloads itself with the initial count and continues counting from there. GATE PIN OPERATIONS SUMMARY SIGNAL STATUS LOW OR GOING MODES LOW RISING HIGH 0 Disables counting Enables counting 1 1) Initiates count- ing 2) Resets output after next clock 2 1) Disables counting [Initiates counting | Enables 2) Sets output imme- counting diately high 3 1) Disables counting [Initiates counting | Enables 2) Sets output imme- counting diately high 4 1) Disables counting Enables counting 5 Initiates counting MODE NOTE: 0 is equivalent to 2 counting. MINIMUM AND MAXIMUM INITIAL COUNTS MIN COUNT 0 1 2 3 4 5 1 1 2 2 1 1 for binary counting and 1 MAX COUNT 0 0 0 0 0 0 for BCD 19 Spec Number 518059HS-82C54RH Metallization Topology DIE DIMENSIONS: 4700 x 5510um x 485um + 25.4um METALLIZATION: Type: Al/Si . ; Thickness: 11kA +2kA GLASSIVATION: Type: SiO2 5 Thickness: 8kA + 1kA WORST CASE CURRENT DENSITY: 7.9 x 104 Afom? Metallization Mask Layout HS-82C54RH a a | a 2 g f Sie le & = a & a c* et He : (21) 6S D (4) (20) A1 D3 (5) (19) Ao D2 (6) D1 (7) (18) CLK 2 (17) OUT 2 DO (8) r] (16) GATE 2 CLK 1 (15) z = = pL < 6 GATE 0 (11) Spec Number 518059 20