MMBTA56WT1 Driver Transistor PNP Silicon Moisture Sensitivity Level: 1 ESD Rating: Human Body Model - 4 kV ESD Rating: Machine Model - 400 V http://onsemi.com COLLECTOR 3 MAXIMUM RATINGS Rating Symbol Value Unit Collector-Emitter Voltage VCEO -80 Vdc Collector-Base Voltage VCBO -80 Vdc Emitter-Base Voltage VEBO -4.0 Vdc IC -500 mAdc Symbol Max Unit PD 150 mW RJA 833 C/W TJ, Tstg -55 to +150 Collector Current - Continuous 1 BASE 2 EMITTER THERMAL CHARACTERISTICS Characteristic Total Device Dissipation FR-5 Board TA = 25C Thermal Resistance, Junction to Ambient Junction and Storage Temperature 3 1 2 SC-70 CASE 419 STYLE 3 C MARKING DIAGRAM FM D FM = Specific Device Code D = Date Code ORDERING INFORMATION Device MMBTA56WT1 Semiconductor Components Industries, LLC, 2002 April, 2002 - Rev. 0 1 Package Shipping SC-70 3000/Tape & Reel Publication Order Number: MMBTA56WT1/D MMBTA56WT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Max Unit Collector-Emitter Breakdown Voltage (Note 1) (IC = -1.0 mAdc, IB = 0) V(BR)CEO -80 - Vdc Emitter-Base Breakdown Voltage (IE = -100 Adc, IC = 0) V(BR)EBO -4.0 - Vdc Collector Cutoff Current (VCE = -60 Vdc, IB = 0) ICES - -0.1 Adc Collector Cutoff Current (VCB = -60 Vdc, IE = 0) (VCB = -80 Vdc, IE = 0) ICBO - - - -0.1 100 100 - - OFF CHARACTERISTICS Adc ON CHARACTERISTICS DC Current Gain (IC = -10 mAdc, VCE = -1.0 Vdc) (IC = -100 mAdc, VCE = -1.0 Vdc) hFE - Collector-Emitter Saturation Voltage (IC = -100 mAdc, IB = -10 mAdc) VCE(sat) - -0.25 Vdc Base-Emitter On Voltage (IC = -100 mAdc, VCE = -1.0 Vdc) VBE(on) - -1.2 Vdc fT 50 - MHz SMALL-SIGNAL CHARACTERISTICS Current-Gain - Bandwidth Product (Note 2) (IC = -100 mAdc, VCE = -1.0 Vdc, f = 100 MHz) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. 2. fT is defined as the frequency at which |hfe| extrapolates to unity. TURN-ON TIME -1.0 V 5.0 s 100 +10 V 0 Vin tr = 3.0 ns TURN-OFF TIME VCC +40 V RL 100 OUTPUT RB Vin * CS 6.0 pF 5.0 F VCC +VBB tr = 3.0 ns *Total Shunt Capacitance of Test Jig and Connectors For PNP Test Circuits, Reverse All Voltage Polarities Figure 1. Switching Time Test Circuits http://onsemi.com 2 OUTPUT * CS 6.0 pF 100 5.0 s RL RB 5.0 F 100 +40 V f T , CURRENT-GAIN - BANDWIDTH PRODUCT (MHz) MMBTA56WT1 200 100 VCE = -2.0 V TJ = 25C 50 C, CAPACITANCE (pF) 100 70 50 30 -5.0 -7.0 -10 -20 -30 -50 -70 -100 Cobo 10 5.0 -0.1 -0.2 -200 -10 -20 -1.0 k -700 -500 ts 100 s -300 VCC = -40 V IC/IB = 10 IB1 = IB2 TJ = 25C tr td @ VBE(off) = -0.5 V -20 -30 -50 -70 -100 -200 -300 TA = 25C CURRENT LIMIT THERMAL LIMIT SECOND BREAKDOWN LIMIT -30 -20 -10 -500 -1.0 IC, COLLECTOR CURRENT (mA) -1.0 VCE = -1.0 V -55C 80 -20 -50 -50 -70 -100 -100 -200 VBE(on) @ VCE = -1.0 V -0.4 0 -0.5 -500 VBE(sat) @ IC/IB = 10 -0.6 -0.2 60 -5.0 -10 -20 -30 TJ = 25C -0.8 V, VOLTAGE (VOLTS) 25C 40 -0.5 -1.0 -2.0 -5.0 -7.0 -10 Figure 5. Active-Region Safe Operating Area 400 200 -2.0 -3.0 VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 4. Switching Time TJ = 125C 1.0 s TC = 25C -100 -70 -50 tf -50 -100 1.0 ms -200 10 -5.0 -7.0 -10 h FE , DC CURRENT GAIN -5.0 Figure 3. Capacitance 200 100 -0.5 -1.0 -2.0 Figure 2. Current-Gain -- Bandwidth Product I C , COLLECTOR CURRENT (mA) t, TIME (ns) 20 VR, REVERSE VOLTAGE (VOLTS) 300 30 30 IC, COLLECTOR CURRENT (mA) 1.0 k 700 500 20 Cibo 7.0 20 -2.0 -3.0 100 70 50 TJ = 25C 70 VCE(sat) @ IC/IB = 10 -1.0 -2.0 -5.0 -10 -20 -50 -100 -200 IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA) Figure 6. DC Current Gain Figure 7. "ON" Voltages http://onsemi.com 3 -500 -1.0 R VB , TEMPERATURE COEFFICIENT (mV/ C) VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS) MMBTA56WT1 TJ = 25C -0.8 -0.6 IC = -100 mA IC = -50 mA IC = -250 mA IC = -500 mA -0.4 -0.2 IC = -10 mA 0 -0.05 -0.1 -0.2 -0.5 -1.0 -2.0 -5.0 -10 -20 -50 -0.8 -1.2 -1.6 -2.0 RVB for VBE -2.4 -2.8 -0.5 -1.0 -2.0 -5.0 -10 -20 -50 -100 -200 IB, BASE CURRENT (mA) IC, COLLECTOR CURRENT (mA) Figure 8. Collector Saturation Region Figure 9. Base-Emitter Temperature Coefficient http://onsemi.com 4 -500 MMBTA56WT1 INFORMATION FOR USING THE SC-70/SOT-323 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.025 0.65 0.025 0.65 0.075 1.9 0.035 0.9 0.028 0.7 inches mm SC-70/SOT-323 POWER DISSIPATION The power dissipation of the SC-70/SOT-323 is a function of the pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows. PD = into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 150 milliwatts. PD = 150C - 25C 833C/W = 150 milliwatts The 833C/W assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 150 milliwatts. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, a higher power dissipation can be achieved using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time should not The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 5 MMBTA56WT1 PACKAGE DIMENSIONS SC-70/SOT-323 CASE 419-04 ISSUE L A L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3 B S 1 2 D G C 0.05 (0.002) J N K H http://onsemi.com 6 DIM A B C D G H J K L N S INCHES MIN MAX 0.071 0.087 0.045 0.053 0.032 0.040 0.012 0.016 0.047 0.055 0.000 0.004 0.004 0.010 0.017 REF 0.026 BSC 0.028 REF 0.079 0.095 STYLE 3: PIN 1. BASE 2. EMITTER 3. COLLECTOR MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.00 0.30 0.40 1.20 1.40 0.00 0.10 0.10 0.25 0.425 REF 0.650 BSC 0.700 REF 2.00 2.40 MMBTA56WT1 Notes http://onsemi.com 7 MMBTA56WT1 Thermal Clad is a registered trademark of the Bergquist Company. ON Semiconductor is a trademark and is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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