MMBTA56WT1-D - ON Semiconductor

 Semiconductor Components Industries, LLC, 2002

April, 2002 – Rev. 0 1Publication Order Number:

MMBTA56WT1/D

MMBTA56WT1

Driver Transistor

PNP Silicon

Moisture Sensitivity Level: 1

ESD Rating: Human Body Model – 4 kV

ESD Rating: Machine Model – 400 V

MAXIMUM RATINGS

Rating Symbol Value Unit

Collector–Emitter Voltage VCEO –80 Vdc

Collector–Base Voltage VCBO –80 Vdc

Emitter–Base Voltage VEBO –4.0 Vdc

Collector Current – Continuous IC–500 mAdc

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Total Device Dissipation FR–5 Board

TA = 25°CPD150 mW

Thermal Resistance,

Junction to Ambient RJA 833 °C/W

Junction and Storage Temperature TJ, Tstg –55 to +150 °C

Device Package Shipping

ORDERING INFORMATION

MMBTA56WT1 SC–70

SC–70

CASE 419

STYLE 3

3000/Tape & Reel

MARKING DIAGRAM

FM D

FM = Specific Device Code

D = Date Code

COLLECTOR

BASE

EMITTER

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MMBTA56WT1

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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS

Collector–Emitter Breakdown V oltage (Note 1)

(IC = –1.0 mAdc, I B = 0) V(BR)CEO –80 – Vdc

Emitter–Base Breakdown Voltage

(IE = –100 Adc, IC = 0) V(BR)EBO –4.0 – Vdc

Collector Cutoff Current

(VCE = –60 Vdc, IB = 0) ICES – –0.1 Adc

Collector Cutoff Current

(VCB = –60 Vdc, IE = 0)

(VCB = –80 Vdc, IE = 0)

ICBO –

––

–0.1

Adc

ON CHARACTERISTICS

DC Current Gain

(IC = –10 mAdc, V CE = –1.0 Vdc)

(IC = –100 mAdc, VCE = –1.0 Vdc)

hFE 100

100 –

–

Collector–Emitter Saturation Voltage

(IC = –100 mAdc, IB = –10 mAdc) VCE(sat) – –0.25 Vdc

Base– E m itte r On Voltage

(IC = –100 mAdc, VCE = –1.0 Vdc) VBE(on) – –1.2 Vdc

SMALL–SIGNAL CHARACTERISTICS

Current–Gain – Bandwidth Product (Note 2)

(IC = –100 mAdc, VCE = –1.0 Vdc, f = 100 MHz) fT50 – MHz

1. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2.0%.

2. fT is defined as the frequency at which |hfe| extrapolates to unity.

Figure 1. Switching Time Test Circuits

OUTPUT

TURN-ON TIME

-1.0 V VCC

+40 V

* CS  6.0 pF

100

Vin

5.0 F

tr = 3.0 ns

+10 V

5.0 s

OUTPUT

TURN-OFF TIME

+VBB VCC

+40 V

* CS  6.0 pF

100

Vin

5.0 F

tr = 3.0 ns

5.0 s

*Total Shunt Capacitance of Test Jig and Connectors

For PNP Test Circuits, Reverse All Voltage Polarities

MMBTA56WT1

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Figure 2. Current–Gain — Bandwidth Product Figure 3. Capacitance

Figure 4. Switching T ime

IC, COLLECTOR CURRENT (mA)

-100 -200-10

200

100

VR, REVERSE VOLTAGE (VOLTS)

-1.0 -100-0.1

100

-2.0

VCE = -2.0 V

TJ = 25°C

fT, CURRENT-GAIN - BANDWIDTH PRODUCT (MHz

)

C, CAPACITANCE (pF)

-2.0 -3.0 -5.0 -7.0 -20 -30 -50 -70

7.0

5.0 -0.2 -0.5 -5.0 -10 -20 -50

TJ = 25°C

Cibo

Cobo

IC, COLLECTOR CURRENT (mA)

-10-5.0

500

200

100

-100

t, TIME (ns)

-50 -200 -500

1.0 k

300

700

-7.0 -300-70-20 -30

VCC = -40 V

IC/IB = 10

IB1 = IB2

TJ = 25°C

td @ VBE(off) = -0.5 V

Figure 5. Active–Region Safe Operating Area

VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)

-10 -50-1.0

-500

-200

-100

-50

-20

-10

-20-2.0 -5.0

-1.0 k

IC, COLLECTOR CURRENT (mA)

1.0 ms

1.0 s

TA = 25°C

CURRENT LIMIT

THERMAL LIMIT

SECOND BREAKDOWN LIMIT

100 s

TC = 25°C

-3.0 -7.0 -30 -100-70

-30

-70

-300

-700

Figure 6. DC Current Gain

-2.0 -500-0.5

IC, COLLECTOR CURRENT (mA)

400

200

100

-10

, DC CURRENT GAIN

TJ = 125°C

-1.0 -5.0

VCE = -1.0 V

-20 -100-50 -200

hFE

25°C

-55°C

Figure 7. “ON” Voltages

V, VOLTAGE (VOLTS)

-10 -500-1.0

IC, COLLECTOR CURRENT (mA)

-1.0

-0.8

-0.6

-0.4

-0.2

-100

TJ = 25°C

VBE(sat) @ IC/IB = 10

VCE(sat) @ IC/IB = 10

VBE(on) @ VCE = -1.0 V

-0.5 -2.0 -5.0 -200-20 -50

MMBTA56WT1

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Figure 8. Collector Saturation Region Figure 9. Base–Emitter Temperature

Coefficient

IC, COLLECTOR CURRENT (mA)

IB, BASE CURRENT (mA)

RVB , TEMPERATURE COEFFICIENT (mV/ C)

°

, COLLECTOR-EMITTER VOLTAGE (VOLTS

)

VCE

-100 -500-0.5

-0.8

-1.2

-1.6

-2.0

-2.4

-2.8

-10

RVB for VBE

-1.0 -2.0 -5.0 -20 -50 -200

-0.1 -10-0.05

-1.0

-0.8

-0.6

-0.4

-0.2

-1.0

TJ = 25°C

-50

IC =

-100 mA

IC =

-50 mA

IC =

-250 mA

IC =

-500 mA

IC =

-10 mA

-20-2.0 -5.0-0.2 -0.5

MMBTA56WT1

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PD = TJ(max) – TA

RθJA

PD = 150°C – 25°C

833°C/W = 150 milliwatts

•The soldering temperature and time should not

exceed 260°C for more than 10 seconds.

•When shifting from preheating to soldering, the

maximum temperature gradient should be 5°C or less.

•After soldering has been completed, the device

should be allowed to cool naturally for at least three

minutes. Gradual cooling should be used as the use of

forced cooling will increase the temperature gradient

and result in latent failure due to mechanical stress.

•Mechanical stress or shock should not be applied dur-

ing cooling

* Soldering a device without preheating can cause exces-

sive thermal shock and stress which can result in damage

to the device.

INFORMATION FOR USING THE SC–70/SOT–323 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the to-

tal design. The footprint for the semiconductor packages

must be the correct size to insure proper solder connection

SC–70/SOT–323 POWER DISSIPATION

The power dissipation of the SC–70/SOT–323 is a func-

tion of the pad size. This can vary from the minimum pad

size for soldering to the pad size given for maximum pow-

er dissipation. Power dissipation for a surface mount de-

vice is determined by TJ(max), the maximum rated junction

temperature of the die, RθJA, the thermal resistance from

the device junction to ambient; and the operating tempera-

ture, TA. Using the values provided on the data sheet, PD

can be calculated as follows.

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values

into the equation for an ambient temperature TA of 25°C,

one can calculate the power dissipation of the device

which in this case is 150 milliwatts.

The 833°C/W assumes the use of the recommended

footprint on a glass epoxy printed circuit board to achieve

a power dissipation of 150 milliwatts. Another alternative

would be to use a ceramic substrate or an aluminum core

board such as Thermal Clad. Using a board material

such as Thermal Clad, a higher power dissipation can be

achieved using the same footprint.

interface between the board and the package. With the

correct pad geometry, the packages will self align when

subjected to a solder reflow process.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated

temperature of the device. When the entire device is heated

to a high temperature, failure to complete soldering within

a short time could result in device failure. Therefore, the

following items should always be observed in order to mini-

mize the thermal stress to which the devices are subjected.

•Always preheat the device.

•The delta temperature between the preheat and

soldering should be 100°C or less.*

•When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering

method, the difference should be a maximum of 10°C.

inches

0.035

0.9

0.075

0.7

1.9

0.028

0.65

0.025

0.65

0.025

MMBTA56WT1

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PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.071 0.087 1.80 2.20

B0.045 0.053 1.15 1.35

C0.032 0.040 0.80 1.00

D0.012 0.016 0.30 0.40

G0.047 0.055 1.20 1.40

H0.000 0.004 0.00 0.10

J0.004 0.010 0.10 0.25

K0.017 REF 0.425 REF

L0.026 BSC 0.650 BSC

N0.028 REF 0.700 REF

S0.079 0.095 2.00 2.40

0.05 (0.002) STYLE 3:

PIN 1. BASE

2. EMITTER

3. COLLECTOR

SC–70/SOT–323

CASE 419–04

ISSUE L

MMBTA56WT1

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Notes

MMBTA56WT1

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MMBTA56WT1/D

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