Vishay Siliconix
SiP4282
Document Number: 65740
S10-0671-Rev. E, 29-Mar-10
www.vishay.com
1
1.2 A Slew Rate Controlled Load Switch in PPAK SC75-6,
and TDFN4 1.2 mm x 1.6 mm
FEATURES
• 1.8 V to 5.5 V input voltage range for SiP4282
• 1.5 V to 5.5 V input voltage range for
SiP4282A
• Very low RDS(ON), typically 105 mΩ at 5 V and
175 mΩ at 3 V
• Slew rate controlled turn-on time options: 100 µs, and
1 ms
• Fast shutdown load discharge
• Low quiescent current, 4 µA for SiP4282
• Low quiescent current, 1 µA for SiP4282A
• Low shutdown current < 1 µA
• UVLO of 1.4 V for SiP4282
• PowerPAK SC-75 1.6 mm x 1.6 mm and TDFN4 1.2 mm
x 1.6 mm packages
• Compliant to RoHS directive 2002/95/EC
APPLICATIONS
• Cellular telephones
• Digital still cameras
• Personal digital assistants (PDA)
• Hot swap supplies
• Notebook computers
• Personal communication devices
• Portable Instruments
DESCRIPTION
The SiP4282 series is a slew rate controlled high side switch.
The switch is of a low ON resistance P-Channel MOSFET
that supports continuous current up to 1.2 A.
The SiP4282 series operates with an input voltage from
1.8 V to 5.5 V. It offers under voltage lock out that turns the
switch off when an input under voltage condition exists. The
"A" option without UVLO extends the minimum operation
voltage from 1.8 V down to 1.5 V. The SiP4282 is available in
two different versions of slew rates, 100 µs and 1 ms. The
SiP4282 series integrates load discharge circuit to ensure
the discharge of capacitive load when the switch is disabled.
The SiP4282 features low input logic level to interface with
low control voltage from microprocessors. This device has a
very low operating current (typically 2.5 µA for SiP4282 and
50 pA for SiP4282A).
The SiP4282 is available in lead (Pb)-free package options
including 6 pin PPAK SC75-6, and 4 pin TDFN4 1.2 mm x
1.6 mm DFN4 packages. The operation temperature range
is specified from - 40 °C to + 85 °C.
The SiP4282 compact package options, operation voltage
range, and low operating current make it a good fit for battery
power applications.
TYPICAL APPLICATION CIRCUIT
Figure 1 - SiP4282 Typical Application Circuit
SiP4282
INVOUT
OUT
VIN
GND
GND
GND
ON/OFF
ON/OFF
C
1 µF
IN C
0.1 µF
OUT
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Document Number: 65740
S10-0671-Rev. E, 29-Mar-10
Vishay Siliconix
SiP4282
Notes:
xxx = Lot Code
Notes:
a. Device mounted with all leads and power pad soldered or welded to PC board.
b. Derate 11.1 mW/°C above TA = 70 °C.
c. Derate 5.9 mW/°C above TA = 70 °C, see PCB layout.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
ORDERING INFORMATION
Temperature Range Package Slew Rate (typ.) Under Voltage Lockout Marking Part Number
- 40 °C to 85 °C
PPAK SC75-6
1 ms No LDxxx SiP4282ADVP2-T1GE3
100 µs No LExxx SiP4282ADVP3-T1GE3
100 µs Yes LFxxx SiP4282DVP3-T1GE3
TDFN4 1.2 x 1.6
1 ms No AAx SiP4282ADNP2-T1GE4
100 µs No ABx SiP4282ADNP3-T1GE4
100 µs Yes ACx SiP4282DNP3-T1GE4
ABSOLUTE MAXIMUM RATINGS
Parameter Limit Unit
Supply Input Voltage (VIN) - 0.3 to 6
V
Enable Input Voltage (VON/OFF) - 0.3 to 6
Output Voltage (VOUT)- 0.3 to VIN + 0.3
Maximum Continuous Switch Current (IMAX)1.4
A
Maximum Pulsed Current (IDM) VIN
VIN ≥ 2.5 V 3
VIN < 2.5 V 1.6
ESD Rating (HBM) 4000 V
Junction Temperature (TJ)- 40 to 125 °C
Thermal Resistance (θJA)a6 pin PPAK SC75b90 °C/W
4 pin TDFN4 1.2 mm x 1.6 mmc170
Power Dissipation (PD)a6 pin PPAK SC75b610 mW
4 pin TDFN4 1.2 mm x 1.6 mmc324
RECOMMENDED OPERATING RANGE
Parameter Limit Unit
Input Voltage Range (VIN) for SiP4282 Version 1.8 to 5.5 V
Input Voltage Range (VIN) for SiP4282A Version 1.5 to 5.5 V
Operating Temperature Range - 40 to 85 °C
Document Number: 65740
S10-0671-Rev. E, 29-Mar-10
www.vishay.com
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Vishay Siliconix
SiP4282
Notes:
a) The algebriac convention whereby the most negative value is a minimum and the most positive a maximum.
b) Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing
c) Part requires minimum start-up of VIN ≥ 2.0 V to ensure operation down to 1.8 V.
d) For VIN outside this range consult typical ON/OFF threshold curve.
SPECIFICATIONS
Parameter Symbol
Test Conditions Unless Specified
VIN = 5.0, TA = - 40 °C to 85 °C
(Typical values are at TA = 25 °C)
Limits
- 40 °C to 85 °C
Unit
Min.a Typ.bMax.a
Operating Voltagec
VIN
For SiP4282xxx 1.8 - 5.5
V
Operating Voltage For SiP4282Axxx 1.5 - 5.5
Under Voltage Voltage VUVLO For SiP4282xxx, VIN falling 1.0 1.4 1.8
Under Voltage Lockout Hysteresis VUVLO(hyh) For SiP4282xxx - 250 - mV
Quiescent Current IQ
For SiP4282xxx, On/Off = active - 2.5 4 µA
For SiP4282Axxx, On/Off = active - 0.00005 1
On-Resistance RDS(on)
VIN = 5 V, IL = 500 mA, TA = 25 °C - 105 230
mΩ
VIN = 4.2 V, IL = 500 mA, TA = 25 °C - 110 250
VIN = 3 V, IL = 500 mA, TA = 25 °C - 135 290
VIN = 1.8 V, IL = 500 mA, TA = 25 °C - 230 480
For SiP4282Axxx, VIN = 1.5 V,
IL = 500 mA, TA = 25 °C - 350 520
On-Resistance Temp-Coefficient TCRDS - 2800 - ppm/°C
On/Off Input Low VoltagedVIL
For SiP4282Axxx,
VIN ≥ 1.5 V to < 1.8 V --0.3
V
VIN ≥ 1.8 V to < 2.7 V --0.4
VIN ≥ 2.7 V to ≤ 5.5 V --0.6
On/Off Input High VoltagedVIH
VIN ≥ 1.5 V to < 2.7 V 1.3 --
VIN ≥ 2.7 V to < 4.2 V 1.5 - -
VIN ≥ 4.2 V to ≤ 5.5 V 1.8 - -
On/Off Input Leakage ISINK VOn/Off = 5.5 V --1µA
Output Pull-Down Resistance RPD On/Off = Inactive, TA = 25 °C - 180 250 Ω
SiP4282Axxx2 Versions
Output Turn-On Delay Time td(on) VIN = 5 V, RLOAD = 10 Ω, TA = 25 °C -2040
µsOutput Turn-On Rise Time t(on) VIN = 5 V, RLOAD = 10 Ω, TA = 25 °C - 1100 1500
Output Turn-Off Delay Time td(off) VIN = 5 V, RLOAD = 10 Ω, TA = 25 °C -410
SiP4282xxx3 and SiP4282Axxx3 Versions
Output Turn-On Delay Time td(on) VIN = 5 V, RLOAD = 10 Ω, TA = 25 °C -2040
µsOutput Turn-On Rise Time t(on) VIN = 5 V, RLOAD = 10 Ω, TA = 25 °C - 140 180
Output Turn-Off Delay Time td(off) VIN = 5 V, RLOAD = 10 Ω, TA = 25 °C -410
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Document Number: 65740
S10-0671-Rev. E, 29-Mar-10
Vishay Siliconix
SiP4282
PIN CONFIGURATION
TYPICAL CHARACTERISTICS internally regulated, 25 °C, unless otherwise noted
Figure 2 - PPAK SC75-6 Package
IN
IN
GND
OUT
ON/OFF
OUT
4
5
61
2
3
Bottom ViewFigure 3 - TDFN4 1.2 mm x 1.6 mm Package
4
3
1
2
Bottom View
ON/OFF
IN
OUT
GND
GND
PIN DESCRIPTION
Pin Number
Name Function
PPAK TDFN4
1, 2 3 IN This pin is the p-channel MOSFET source connection. Bypass to ground through a 1 µF capacitor.
3 2 GND Ground connection
4 4 ON/OFF Enable input
5, 6 1 OUT This pin is the p-channel MOSFET drain connection. Bypass to ground through a 0.1 µF capacitor.
Figure 4 - Quiescent Current vs. Input Voltage
Figure 6 - Quiescent Current vs. Temperature
01.5 2.0 2.5 3.5 4.5 5.53.0 4.0 5.0
0.04
0.02
0.06
0.08
0.10
0.12
VIN (V)
IQ - Quiescent Current (nA)
SiP4282A
0.001
- 40 - 20 0 40 80 10020 60
0.1
0.01
1
10
Temperature (°C)
IQ - Quiescent Current (nA)
SiP4282A
VIN = 5 V
VIN = 3 V
Figure 5 - Quiescent Current vs. Input Voltage
Figure 7 - Quiescent Current vs. Temperature
01.0 1.5 2.0 3.0 4.0 5.52.5 3.5 4.5 5.0
1.0
0.5
1.5
2.0
2.5
3.0
VIN (V)
IQ - Quiescent Current (µA)
SiP4282
0
- 40 - 20 0 40 80 10020 60
1.5
0.5
2.5
2.0
1.0
3.0
3.5
Temperature (°C)
IQ - Quiescent Current (µA)
SiP4282
VIN = 5 V
VIN = 3 V
Document Number: 65740
S10-0671-Rev. E, 29-Mar-10
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Vishay Siliconix
SiP4282
TYPICAL CHARACTERISTICS internally regulated, 25 °C, unless otherwise noted
Figure 8 - Off Switch Current vs. Input Voltage
Figure 10 - RDS(ON) vs. Input Voltage
Figure 12 - Output Pull-Down Resistance vs.
0
1.5 2.0 2.5 3.5 5.0 6.03.0 4.0 5.54.5
150
50
250
200
100
300
350
VIN (V)
ISD(OFF) - Off Switch Current (nA)
50
1.5 2.0 2.5 3.5 5.53.0 4.0 4.5 5.0
250
100
450
350
150
550
200
400
300
500
V
IN
(V)
RDS - On-Resistance (mΩ)
IL = 1.2 A
IL = 100 mA
IL = 500 mA
- 40 - 20 0 40 10020 60 80
Temperature (°C)
RPD - Output Pull-Down (Ω)
150
160
170
180
190
200
210
220
Figure 9 - Off Switch Current vs. Temperature
Figure 11 - RDS(ON) vs. Temperature
Figure 13 - ON/OFF Threshold vs. Input Voltage
0
- 40 - 20 0 40 10020 60 80
150
50
250
200
100
300
Temperature (°C)
ISD(OFF) - Off Switch Current (nA)
VIN = 5 V
60
- 40 - 20 0 40 10020 60 80
140
80
100
180
120
160
Temperature (°C)
RDS - On-Resistance (mΩ)
VIN = 5 V
VIN = 3 V
ILOAD = 500 mA
0.4
1.5 2.0 2.5 3.5 6.03.0 4.0 5.04.5 5.5
1.2
0.6
0.8
1.6
1.0
1.4
VIN (V)
On/Off Threshold Voltage (V)
VIH
VIL
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Document Number: 65740
S10-0671-Rev. E, 29-Mar-10
Vishay Siliconix
SiP4282
TYPICAL WAVEFORMS
Figure 14 - SiP4282Axxx2 Switching (VIN = 3 V)
Figure 16 - SiP4282Axxx2 Switching (VIN = 5 V)
Figure 18 - SiP4282xxx3 and SiP4282Axxx3 Switching
(VIN = 3 V)
Figure 15 - SiP4282Axxx2 Turn-Off (VIN = 3 V)
Figure 17 - SiP4282Axxx2 Turn-Off (VIN = 5 V)
Figure 19 - SiP4282xxx3 and SiP4282Axxx3 Turn-Off
(VIN = 3 V)
SiP4282
Vishay Siliconix
Document Number: 65740
S10-0671-Rev. E, 29-Mar-10
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TYPICAL WAVEFORMS
BLOCK DIAGRAM
PCB LAYOUT
Figure 20 - SiP4282xxx3 and SiP4282Axxx3 Switching (VIN = 5 Figure 21 - SiP4282xxx3 and SiP4282Axxx3 Turn-Off (VIN = 5 V)
Figure 22 - SiP4282 Functional Block Diagram
Level
Shift
Under
Voltage
Lockout
SiP4282xxx3
only
Turn-On
Slew Rate
Control
GND
ON/OFF
OUT
IN
Top Bottom
Figure 23 - TDFN4 1.2 mm x 1.6 mm PCB Layout
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Document Number: 65740
S10-0671-Rev. E, 29-Mar-10
Vishay Siliconix
SiP4282
DETAILED DESCRIPTION
The SiP4282 is a P-Channel MOSFET power switches
designed for high-side slew rate controlled load-switching
applications. Once turned on, the slew-rate control circuitry
is activated and current is ramped in a linear fashion until it
reaches the level required for the output load condition. This
is accomplished by first elevating the gate voltage of the
MOSFET up to its threshold voltage and then by linearly
increasing the gate voltage until the MOSFET becomes fully
enhanced. At this point, the gate voltage is then quickly
increased to the full input voltage to reduce RDS(ON) of the
MOSFET switch and minimize any associated power losses.
The SiP4282A-2 version has a modest 1 ms turn on slew rate
feature, which significantly reduces in-rush current at turned
on time and permits the load switch to be implemented with
a small input capacitor, or no input capacitor at all, saving
cost and space. All versions features a shutdown output dis-
charge circuit which is activated at shutdown (when the part
is disabled through the On/Off pin) and discharges the output
pin through a small internal resistor hence, turning off the
load.
For SiP4282-3, in instances where the input voltage falls
below 1.4 V (typically) the under voltage lock-out circuitry
protects the MOSFET switch from entering the saturation
region or operation by shutting down the chip.
APPLICATION INFORMATION
Input Capacitor
While a bypass capacitor on the input is not required, a 1 µF
or larger capacitor for CIN is recommended in almost all
applications. The bypass capacitor should be placed as
physically close as possible to the SiP4282 to be effective in
minimizing transients on the input. Ceramic capacitors are
recommended over tantalum because of their ability to
withstand input current surges from low impedance sources
such as batteries in portable devices.
Output Capacitor
A 0.1 µF capacitor or larger across VOUT and GND is
recommended to insure proper slew operation. COUT may be
increased without limit to accommodate any load transient
condition with only minimal affect on the SiP4282 turn on
slew rate time. There are no ESR or capacitor type
requirement.
Enable
The On/Off pin is compatible with both TTL and CMOS logic
voltage levels.
Protection Against Reverse Voltage Condition
The P-channel MOSFET pass transistor has an intrinsic
diode that is reversed biased when the input voltage is
greater than the output voltage. Should VOUT exceed VIN,
this intrinsic diode will become forward biased and allow
excessive current to flow into the IC thru the VOUT pin and
potentially damage the IC device. Therefore extreme care
should be taken to prevent VOUT from exceeding VIN.
In conditions where VOUT exceeds VIN a Schottky diode in
parallel with the internal intrinsic diode is recommended to
protect the SiP4282.
Thermal Considerations
The SiP4282 is designed to maintain a constant output load
current. Due to physical limitations of the layout and
assembly of the device the maximum switch current is 1.2 A,
as stated in the Absolute Maximum Ratings table. However,
another limiting characteristic for the safe operating load
current is the thermal power dissipation of the package. To
obtain the highest power dissipation (and a thermal
resistance of 90 °C/W) the power pad of the device should
be connected to a heat sink on the printed circuit board.
The maximum power dissipation in any application is
dependant on the maximum junction temperature,
TJ(MAX) = 125 °C, the junction-to-ambient thermal resistance
for the SC-75 PPAK package, θJ-A = 90 °C/W, and the
ambient temperature, TA, which may be formulaically
expressed as:
It then follows that, assuming an ambient temperature of
70 °C, the maximum power dissipation will be limited to about
610 mW.
So long as the load current is below the 1.2 A limit, the
maximum continuous switch current becomes a function two
things: the package power dissipation and the RDS(ON) at the
ambient temperature.
As an example let us calculate the worst case maximum load
current at TA = 70 °C. The worst case RDS(ON) at 25 °C
occurs at an input voltage of 1.8 V and is equal to 480 mΩ.
The RDS(ON) at 70 °C can be extrapolated from this data
using the following formula
RDS(ON) (at 70 °C) = RDS(ON) (at 25 °C) x (1 + TC x ΔT)
Where TC is 3300 ppm/°C. Continuing with the calculation
we have
RDS(ON) (at 70 °C) = 480 mΩ x (1 + 0.0033 x (70 °C - 25 °C))
= 551 mΩ
The maximum current limit is then determined by
which in case is 1.05 A. Under the stated input voltage
condition, if the 1.05 A current limit is exceeded the internal
die temperature will rise and eventually, possibly damage the
device.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65740.
90
125
(max.)
(max.)
A
AJ
A
J T
TT
P
-
=
-
=
-
θ
) (
(max.)
(max.)
ON DS
LOAD
R
P
I <
Document Number: 91000 www.vishay.com
Revision: 18-Jul-08 1
Disclaimer
Legal Disclaimer Notice
Vishay
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting
from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding
products designed for such applications.
Product names and markings noted herein may be trademarks of their respective owners.
Package Information
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Revision: 07-Nov-11 1Document Number: 65734
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TDFN4 1.2 x 1.6 Case Outline
DIM.
MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.50 0.55 0.60 0.020 0.022 0.024
A1 0.00 - 0.05 0.00 - 0.002
A3 0.15 REF. 0.006
b 0.20 0.25 0.30 0.008 0.010 0.012
D 1.15 1.20 1.25 0.045 0.047 0.049
D2 0.81 0.86 0.91 0.032 0.034 0.036
e 0.50 BSC 0.020
E 1.55 1.60 1.65 0.061 0.063 0.065
E2 0.45 0.50 0.55 0.018 0.020 0.022
K 0.25 TYP. 0.010 TYP.
L 0.25 0.30 0.35 0.010 0.012 0.014
ECN: S11-2099-Rev. B, 07-Nov-11
DWG: 5995
Top View Bottom View
Side View
21
43
34
12
D
E
A
A1
b
e
L
A3
E2
D2
K
Index Area
(D/2 x E/2)
Pin #1 ID
(Optional)
Vishay Siliconix
Package Information
Document Number: 73850
22-May-06
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1
DIM
MILLIMETERS INCHES
Min Nom Max Min Nom Max
A 0.70 0.75 0.80 0.028 0.030 0.032
A1 0 - 0.05 0 - 0.002
b 0.20 0.25 0.30 0.008 0.010 0.012
C 0.15 0.20 0.25 0.006 0.008 0.010
D 1.55 1.60 1.65 0.0061 0.063 0.065
D1 0.95 1.00 1.05 0.037 0.039 0.041
E 1.55 1.60 1.65 0.061 0.063 0.065
E1 0.55 0.60 0.65 0.022 0.024 0.026
e 0.50 BSC 0.020 BSC
e1 1.00 BSC 0.039 BSC
K 0.15 - - 0.006 - -
K2 0.20 - - 0.008
L 0.20 0.25 0.30 0.008 0.010 0.012
ECN: S-60845-Rev. B, 22-May-06
DWG: 5953
PowerPAK SC75-6L (Power IC only)
®
Top View
Pin 1 Dot
By Marking
PPAKSC75
(1.6 x 1.6 mm)
K2 K2
Bottom View
e1
Side View
A
A1
C
D
E
e
b
D1
Exposed pad
E1
Exposed pad
K
K
Pin3 Pin 2 Pin1
L
Pin4 Pin 5 Pin6
Document Number: 66558 www.vishay.com
Revision: 05-Mar-10 1
PAD Pattern
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR TDFN4 1.2 x 1.6
Recommended Minimum Pads
Dimensions in mm
12
3
4
0.30
0.50
0.86
0.20 0.50
2.0
0.20
0.55 0.55
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Revision: 02-Oct-12 1Document Number: 91000
Disclaimer
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