IS31AP4912
Integrated Silicon Solution, Inc. – www.issi.com 1
Rev. C, 12/23/2015
STEREO HEADPHONE DRIVER
January 2016
GENERAL DESCRIPTION
The IS31AP4912 is stereo headphone drivers
designed to allow the removal of the output
DC-blocking capacitors for reduced component count
and cost. The IS31AP4912 is ideal for small portable
electronics where size and cost are critical design
parameters.
The IS31AP4912 integrates click-and-pop suppression
circuitry and thermal protect circuit. The gain of the
amplifier is adjusted via external resistors.
IS31AP4912 is available in UTQFN-12 (2mm × 2mm)
packages. It operates from 2.7V to 5.5V over the
temperature range of -40°C to +85°C.
FEATURES
No output DC-blocking capacitors
Supply voltage from 2.7V ~ 5.5V
Low output noise (7µV)
High SNR (103dB)
-95dB PSRR
Thermal protect circuit
Integrated click-and-pop suppression circuitry
UTQFN-12 (2mm × 2mm) package
APPLICATIONS
Cellular handsets and PDAs
Notebook PC
MP3
Portable gaming
TYPICAL APPLICATION CIRCUIT
Figure 1 Typical Application Circuit
Note: The SGND and PGND pins of the IS31AP4912 must be routed separately back to the decoupling capacitor in order to provide proper
device operation. If the SGND and PGND pins are connected directly to each other, the part functions without risk of failure, but the noise and
THD performance do not meet the specifications.
IS31AP4912
Integrated Silicon Solution, Inc. – www.issi.com 2
Rev. C, 12/23/2015
PIN CONFIGURATION
Package Pin Configuration (Top View)
UTQFN-12
1
2
3
9
8
7
CN
INR
INL
OUTR
VREF
VCC
PIN DESCRIPTION
No. Pin Description
1 CN Charge pump flying capacitor negative terminal.
2 INR Right channel audio input.
3 INL Left channel audio input.
4 OUTL Left channel audio output.
5 SDB Shutdown control terminal, active low.
6 SGND Signal Ground.
7 VCC Supply voltage.
8 VREF
Internal produced supply voltage for charge pump and
audio power amplifier.
9 OUTR Right channel audio output.
10 CP Charge pump flying capacitor positive terminal.
11 PGND Power ground.
12 VSS Output from charge pump.
IS31AP4912
Integrated Silicon Solution, Inc. – www.issi.com 3
Rev. C, 12/23/2015
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Order Part No. Package QTY/Reel
IS31AP4912-UTLS2-TR UTQFN-12, Lead-free 3000
Copyright©2015IntegratedSiliconSolution,Inc.Allrightsreserved.ISSIreservestherighttomakechangestothisspecificationanditsproductsatany
timewithoutnotice.ISSIassumesnoliabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.Customersare
advisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts.
IntegratedSiliconSolution,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionofthe
productcanreasonablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.Productsarenot
authorizedforuseinsuchapplicationsunlessIntegratedSiliconSolution,Inc.receiveswrittenassurancetoitssatisfaction,that:
a.)theriskofinjuryordamagehasbeenminimized;
b.)theuserassumeallsuchrisks;and
c.)potentialliabilityofIntegratedSiliconSolution,Incisadequatelyprotectedunderthecircumstances
IS31AP4912
Integrated Silicon Solution, Inc. – www.issi.com 4
Rev. C, 12/23/2015
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC -0.3V ~ +6.0V
Voltage at any input pin -0.3V ~ VCC+0.3V
Maximum junction temperature, TJMAX 150°C
Storage temperature range, TSTG -65°C ~ +150°C
Operating temperature range, TA -40°C ~ +85°C
Thermal resistance, JA 63.1°C/W
ESD (HBM)
ESD (CDM)
±8kV
±1kV
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VCC = 2.7V ~ 5.5V, TA = 25°C, unless otherwise noted. Typical value is TA = 25°C, VCC = 3.6V.
Symbol Parameter Condition Min. Typ. Max. Unit
VCC Supply voltage 2.7 5.5 V
ICC Quiescent current No load 3 5.5 mA
ISD Shutdown current VSDB = 0V 1 µA
fOSC Operating frequency 250 kHz
|VOS| Output offset voltage VIN = 0V 1 mV
VIH High-level input voltage 1.4 V
VIL Low-level input voltage 0.4 V
ELECTRICAL CHARACTERISTICS (NOTE 1)
TA = 25°C, VCC = 3.6V, unless otherwise noted.
Symbol Parameter Condition Min. Typ. Max. Unit
PO Output power THD+N = 1%, RL = 32, f = 1kHz 30 mW
THD+N Total harmonic distortion
plus noise PO = 20mW, RL = 32, f = 1kHz 0.024 %
tWU Wake-up time from
shutdown 39 ms
PSRR Power supply rejection ratio VP-P = 200mV, RL = 32, f = 217Hz -95 dB
VP-P = 200mV, RL = 32, f = 1kHz -93 dB
VNO Output voltage noise 7 µV
SNR Signal-to-noise ratio PO = 30mW, THD+N = 0.1% 103 dB
Note 1: Guaranteed by design.
IS31AP4912
Integrated Silicon Solution, Inc. – www.issi.com 5
Rev. C, 12/23/2015
TYPICAL PERFORMANCE CHARACT ERISTIC
THD+N(%)
Output Power(W)
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
1m 2m 5m 10m 20m 50m 100m
f = 20Hz
f = 1kHz
f = 10kHz
V
CC
= 3.0V
R
L
= 32
Figure 2 THD+N vs. Output Power
THD+N(%)
Output Power(W)
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
1m 2m 5m 10m 20m 50m 100m
V
CC
= 4.2V
R
L
= 32
f = 1kHz
f = 20Hz
f = 10kHz
Figure 4 THD+N vs. Output Power
Output Voltage(V)
20 20k50 100 200 500 1k 2k 5k 10k
Frequency(H z)
1u
20u
2u
3u
5u
7u
10u
V
CC
= 3.0V~4.2V
R
L
= 32
Figure 6 Noise
THD+N(%)
Output Power(W)
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
1m 2m 5m 10m 20m 50m 100m
f = 20Hz
f = 1kHz
f = 10kHz
V
CC
= 3.6V
R
L
= 32
Figure 3 THD+N vs. Output Power
THD+N(%)
20 20k50 100 2 00 500 1k 2k 5k 10k
Frequency(Hz)
0.001
1
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5 V
CC
= 3.0V~4.2V
R
L
= 32
P
O
= 20mW
Figure 5 THD+N vs. Frequency
PSRR(dB)
20 20k50 100 200 500 1k 2k 5k 10k
Frequency(Hz)
-120
+0
-100
-80
-60
-40
-20
V
CC
= 3.6V, 4.2V
R
L
= 32
Input Grounded
Figure 7 PSRR vs. Frequency
IS31AP4912
Integrated Silicon Solution, Inc. – www.issi.com 6
Rev. C, 12/23/2015
FUNCTIONAL BLOCK DIAGRAM
IS31AP4912
Integrated Silicon Solution, Inc. – www.issi.com 7
Rev. C, 12/23/2015
APPLICATION INFORMATION
CHARGE PUMP CONVERTER
IS31AP4912 integrate a charge pump converter to
change input supply voltage (VCC) into a negative
voltage providing a 0V reference voltage for output.
The charge pump converter only needs three external
components: supply decoupling capacitor, output
bypass capacitor and flying capacitor.
Choose low ESR capacitors to ensure the best
operating performance and place the capacitors as
close as possible to the IS31AP4912.
GAIN SETTING
The input resistors (RIN) and feedback resistors (RF)
set the gain of the amplifier according to Equation (1).
IN
F
R
R
ain G
V
V (1)
For example, in Figure 1:
RF = 20k, RIN = 20k,
so, 1G 20
20 ain
V
V
Resistor matching is very important in the amplifiers.
The balance of the output on the reference voltage
depends on matched ratios of the resistors. CMRR,
PSRR, and cancellation of the second harmonic
distortion diminish if resistor mismatch occurs.
Therefore, it is recommended to use 1% tolerance
resistors or better to keep the performance optimized.
Matching is more important than overall tolerance.
Resistor arrays with 1% matching can be used with a
tolerance greater than 1%.
Place the input resistors very close to the IS31AP4912
to limit noise injection on the high-impedance nodes.
INPUT CAPACITOR (CIN)
The input capacitors and input resistors form a high
pass filter with the corner frequency, fC, determined in
Equation (2).
ININ CR
c
f
2
1
(2)
For example, in Figure 1:
RIN = 20k, CIN = 0.47µF,
so, Hz
c
fFk 17
47.0202
1
The value of the input capacitor is important to
consider as it directly affects the bass (low frequency)
performance of the circuit. The capacitors should have
a tolerance of ±10% or better, because any mismatch
in capacitance causes an impedance mismatch at the
corner frequency and below.
DESIGN NOTE
COMPONENT SELECTION
The value and ESR of the output capacitor for charge
pump will affect output ripple and transient
performance. A X7R or X5R ceramic capacitor in 2.2F
should be recommended. The flying capacitor should
use a 2.2µF X7R or X5R ceramic capacitor.
All the capacitors should support at least 10V.
PCB LAYOUT
The decoupling capacitors should be placed close to
the VCC pin and the output capacitors should be
placed close to the VSS pin. The flying capacitor
should be placed close to the CN and CP pins. The
input capacitors and input resistors should be placed
close to the INR and INL pins and the traces must be
parallel to prevent noise. The traces of OUTR and
OUTL pins connected to the headphone should be as
possible as short and wide. The recommended width is
0.5mm.
Trace width should be at least 0.75mm for the power
supply and the ground plane. The SGND and PGND
pins of the IS31AP4912 must be routed separately
back to the decoupling capacitor in order to provide
proper device operation. If the SGND and PGND pins
are connected directly to each other, the part functions
without risk of failure, but the noise and THD
performance do not meet the specifications.
IS31AP4912
Integrated Silicon Solution, Inc. – www.issi.com 8
Rev. C, 12/23/2015
CLASSIFICATION REFLOW PROFILES
Profile Feature Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp) 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)* Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc) Max 30 seconds
Average ramp-down rate (Tp to Tsmax) 6°C/second max.
Time 25°C to peak temperature 8 minutes max.
Figure 8 Classification Profile
IS31AP4912
Integrated Silicon Solution, Inc. – www.issi.com 9
Rev. C, 12/23/2015
PACKAGING INFORMATION
UTQFN-12
IS31AP4912
Integrated Silicon Solution, Inc. – www.issi.com 10
Rev. C, 12/23/2015
RECOMMENDED LAND PATTERN
Note:
1. Land pattern complies to IPC-7351.
2. All dimensions in MM.
3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since
land pattern design depends on many factors unknown (eg. user’s board manufacturing specs), user must determine suitability for use.
IS31AP4912
Integrated Silicon Solution, Inc. – www.issi.com 11
Rev. C, 12/23/2015
REVISION HIST ORY
Revision Detail Information Date
A Initial release 2011.11.17
B Update POD 2013.06.06
C 1. Add ESD value and JA
2. Add land pattern and update POD 2015.12.23
