FEBRUARY 2012
AS7C38096A
1M X 8 BIT HIGH SPEED CMOS SRAM
1
FEATURES
Fast access time : 10ns
Very low power consumption:
Operating current:
80mA(TYP. 10ns)
Standby current (Normal version):
3mA(TYP.)
Single 3.3V power supply
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data retention voltage : 1.5V (MIN.)
Green package available
Package: 44-pin 400 mil TSOP-II
48-ball 6mmx8mm TFBGA
GENERAL DESCRIPTION
The AS7C38096A is a 8M-bit high speed CMOS static
random access memory organized as 1,024K words by 8
bits. It is fabricated using very high performance, high
reliability CMOS technology. Its standby current is stable
within the range of operating temperature.
The AS7C38096A operates from a single power
supply of 3.3V and all inputs and outputs are fully TTL
compatible
PRODUCT FAMILY
Product
Family
Operating
Temperature
Vcc Range
Speed
Standby(ISB1,TYP.)
Operating(Icc1,TYP.)
AS7C38096A
-40 ~ 85℃
2.7 ~ 3.6V
10ns
3mA
80/70mA
FEBRUARY 2012
AS7C38096A
1M X 8 BIT HIGH SPEED CMOS SRAM
2
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
1024Kx8
MEMORY ARRAY
COLUMN I/O
A0-A19
Vcc
Vss
DQ0-DQ7
CE#
WE#
OE#
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A19
Address Inputs
DQ0 – DQ7
Data Inputs/Outputs
CE#
Chip Enable Inputs
WE#
Write Enable Input
OE#
Output Enable Input
VCC
Power Supply
VSS
Ground
NC
No Connection
FEBRUARY 2012
AS7C38096A
1M X 8 BIT HIGH SPEED CMOS SRAM
3
PIN CONFIGURATION
44-pin TSOP(Type II)
48-ball 6mmx8mm TFBGA
TFBGA
NCNC
A3
A10A9 A11
A0
A14
A8 A19
WE#
DQ0
DQ3
NC
A18
Vss
NC
A13
NC
Vcc
Vcc
A15
Vss
CE#
NC
DQ7
DQ4
NC
A2OE# A1
A6A5
A4NC
1 2 3 4 5 6
H
G
C
D
E
F
A
B
A12
NC
A17 A7
A16
NC
DQ1
DQ2
NC NC
DQ6
DQ5
NC
FEBRUARY 2012
AS7C38096A
1M X 8 BIT HIGH SPEED CMOS SRAM
4
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Voltage on VCC relative to VSS
VT1
-0.5 to 4.6
V
Voltage on any other pin relative to VSS
VT2
-0.5 to VCC+0.5
V
Operating Temperature
TA
-40 to 85
℃
Storage Temperature
TSTG
-65 to 150
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for
extended period may affect device reliability.
TRUTH TABLE
MODE
CE#
OE#
WE#
I/O OPERATION
SUPPLY CURRENT
Standby
H
X
X
High-Z
ISB1
Output Disable
L
H
H
High-Z
ICC
Read
L
L
H
DOUT
ICC
Write
L
X
L
DIN
ICC
Note: H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP. *4
MAX.
UNIT
Supply Voltage
VCC
-10
2.7
3.3
3.6
V
Input High Voltage
VIH*1
2.2
-
VCC+0.3
V
Input Low Voltage
VIL*2
- 0.3
-
0.8
V
Input Leakage Current
ILI
VCC ≧ VIN ≧ VSS
- 1
-
1
µA
Output Leakage
Current
ILO
VCC ≧ VOUT ≧ VSS,
Output Disabled
- 1
-
1
µA
Output High Voltage
VOH
IOH = -8mA
2.4
-
-
V
Output Low Voltage
VOL
IOL =4mA
-
-
0.4
V
Average Operating
Power supply Current
Icc
CE# = VIL , II/O = 0mA
;f=max
-10
-
100
130
mA
Icc1
CE# ≧VCC - 0.2V, Other
pin is at 0.2V or Vcc-0.2V
II/O = 0mA;f=max
-10
80
110
mA
Standby Power
Supply Current
Isb
CE# ≧Vih
Other pin is at Vil or Vih
40
mA
Standby Power
Supply Current
ISB1
CE# ≧VCC - 0.2V;
Other pin is at 0.2V or Vcc-0.2V
3
25
mA
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
FEBRUARY 2012
AS7C38096A
1M X 8 BIT HIGH SPEED CMOS SRAM
5
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
UNIT
Input Capacitance
CIN
-
8
pF
Input/Output Capacitance
CI/O
-
10
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
speed
10ns
Input Pulse Levels
0.2V to Vcc-0.2V
Input Rise and Fall Times
3ns
Input and Output Timing Reference Levels
1.5V
Output Load
CL = 30pF + 1TTL,
IOH/IOL = -4mA/8mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
SYM.
AS7C38096A-10
UNIT
MIN.
MAX.
Read Cycle Time
tRC
10
-
ns
Address Access Time
tAA
-
10
ns
Chip Enable Access Time
tACE
-
10
ns
Output Enable Access Time
tOE
-
4.5
ns
Chip Enable to Output in Low-Z
tCLZ*
2
-
ns
Output Enable to Output in Low-Z
tOLZ*
0
-
ns
Chip Disable to Output in High-Z
tCHZ*
-
4
ns
Output Disable to Output in High-Z
tOHZ*
-
4
ns
Output Hold from Address Change
tOH
2
-
ns
(2) WRITE CYCLE
PARAMETER
SYM.
AS7C38096A-10
UNIT
MIN.
MAX.
Write Cycle Time
tWC
10
-
ns
Address Valid to End of Write
tAW
8
-
ns
Chip Enable to End of Write
tCW
8
-
ns
Address Set-up Time
tAS
0
-
ns
Write Pulse Width
tWP
8
-
ns
Write Recovery Time
tWR
0
-
ns
Data to Write Time Overlap
tDW
6
-
ns
Data Hold from End of Write Time
tDH
0
-
ns
Output Active from End of Write
tOW*
2
-
ns
Write to Output in High-Z
tWHZ*
-
4
ns
*These parameters are guaranteed by device characterization, but not production tested.
FEBRUARY 2012
AS7C38096A
1M X 8 BIT HIGH SPEED CMOS SRAM
6
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
Dout Data Valid
tOHtAA
Address
tRC
Previous Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
Dout Data Valid
tOH
OE#
tACE
CE#
tAA
Address
tRC
High-ZHigh-Z
tCLZ
tOLZ
tOE
tCHZ
tOHZ
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low.
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
FEBRUARY 2012
AS7C38096A
1M X 8 BIT HIGH SPEED CMOS SRAM
7
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
Dout
Din Data Valid
tDW tDH
(4) High-Z
tWHZ
WE#
tWP
tCW
CE#
tWRtAS
tAW
Address
tWC
(4)
TOW
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
Dout
Din Data Valid
tDW tDH
(4) High-Z
tWHZ
WE#
tWP
tCW
CE# tWRtAS
tAW
Address
tWC
Notes :
1.WE#, CE# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the
bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
FEBRUARY 2012
AS7C38096A
1M X 8 BIT HIGH SPEED CMOS SRAM
8
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
VCC for Data Retention
VDR
CE# ≧ VCC - 0.2V
1.5
-
3.6
V
Data Retention Current
IDR
VCC =1.5V
CE# ≧VCC - 0.2V;
Other pin is at 0.2V or Vcc-0.2V
-
-
3
25
mA
Chip Disable to Data
Retention Time
tCDR
See Data Retention
Waveforms (below)
0
-
-
ns
Recovery Time
tR
tRC*
-
-
ns
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Vcc
CE#
VDR ¡Ù 1.5V
CE# ¡Ù Vcc-0.2V
Vcc(min.)
VIH
tRtCDR
VIH
Vcc(min.)
FEBRUARY 2012
AS7C38096A
1M X 8 BIT HIGH SPEED CMOS SRAM
9
PACKAGE OUTLINE DIMENSION
44-pin 400mil TSOP-Ⅱ Package Outline Dimension
SYMBOLS
DIMENSIONS IN MILLMETERS
DIMENSIONS IN MILS
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
-
-
1.20
-
-
47.2
A1
0.05
0.10
0.15
2.0
3.9
5.9
A2
0.95
1.00
1.05
37.4
39.4
41.3
b
0.30
-
0.45
11.8
-
17.7
c
0.12
-
0.21
4.7
-
8.3
D
18.212
18.415
18.618
717
725
733
E
11.506
11.760
12.014
453
463
473
E1
9.957
10.160
10.363
392
400
408
e
-
0.800
-
-
31.5
-
L
0.40
0.50
0.60
15.7
19.7
23.6
ZD
-
0.805
-
-
31.7
-
y
-
-
0.076
-
-
3
Θ
0o
3o
6o
0o
3o
6o
FEBRUARY 2012
AS7C38096A
1M X 8 BIT HIGH SPEED CMOS SRAM
10
48-ball 6mm × 8mm TFBGA Package Outline Dimension
FEBRUARY 2012
AS7C38096A
1M X 8 BIT HIGH SPEED CMOS SRAM
11
ORDERING INFORMATION
BGA : 48-ball 6 mm x 8 mm TFBGA
Industrial -40°C ~ +85°C
AS7C38096A-10BIN
TSOP II : 44-pin 400 mil TSOP II
Industrial -40°C ~ +85°C
AS7C38096A-10TIN