GLT540L16 ADVANCED 4M (2-Bank x 131072-Word x 16-Bit) Synchronous DRAM FEATURES Single 3.3 V 0.3 V power supply Clock frequency 100 MHz / 125 MHz / 143 MHz/ 166 MHz Fully synchronous operation referenced to clock rising edge Dual bank operation controlled by BA (Bank Address) CAS latency- 1 / 2 / 3 (programmable) Burst length- 1 / 2 / 4 / 8 & Full Page (programmable) Burst type- sequential / interleave (programmable) Byte control by DQMU and DQML Column access - random Auto precharge / All bank precharge controlled by A[8] Auto refresh and Self refresh 1024 refresh cycles / 16 ms LVTTL Interface 400-mil, 50-Pin Thin Small Outline Package (TSOP II) with 0.8 mm lead pitch Single write option GENERAL DESCRIPTION The GLT540L16 is a 2-bank x 131072-word x 16-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The GLT540L16 achieves very high speed data rate up to 166 MHz. March 2000 (Rev. 0) 1 FUNCTIONAL BLOCK DIAGRAM A[8:0] BA Mode Register CLK CKE Clock Buffer CS RAS CAS WE DQML DQMU Control Signal Buffer Control Circuitry Address Buffer Memory Array Bank #0 I/O Buffer DQ[15:0] Memory Array Bank #1 Figure 1. 4M (2-Bank x 131072-Word x 16-Bit) Synchronous DRAM Signal Description Signal Type Description CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. CKE Input Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. CS Input Chip Select: When CS is high, any command means No Operation. RAS, CAS, WE Input Combination of RAS, CAS, WE defines basic commands. A[8:0] Input A[8:0] specify the Row / Column Address in conjunction with BA. The Row Address is specified by A[8:0]. The Column Address is specified by A[7:0]. A[8] is also used to indicate precharge option. When A[8] is high at a read / write command, an auto precharge is performed. When A[8] is high at a precharge command, both banks are precharged. BA Input Bank Address: BA is not simply A[9]. BA specifies the bank to which a command is applied. BA must be set with ACT, PRE, READ, WRITE commands. DQ[15:0] Input / Output Data In and Data out are referenced to the rising edge of CLK. DQML Input Lower Din[7:0] Mask / Lower Output[7:0] Disable: When DQML is high in burst write, lower Din[7:0] for the current cycle is masked. When DQML is high in burst read, lower Dout[7:0] is disabled at the next but one cycle. DQMU Input Upper Din[15:8] Mask / Upper Output[15:8] Disable: When DQMU is high in burst write, upper Din(8-15) for the current cycle is masked. When DQMU is high in burst read, upper Dout[15:8] is disabled at the next but one cycle. VDD, VSS Power Supply Power Supply for the memory array and peripheral circuitry. VDDQ, VSSQ Power Supply VDDQ and VSSQ are supplied to the Output Buffers only. 2 G-LINK Technology March 2000 (Rev. 0) FUNCTIONAL DESCRIPTION The GLT540L16 provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of RAS, CAS and WE at CLK rising edge. In addition to 3 signals, CS, CKE and A[8] are used as chip select, refresh option, and precharge option, respectively. Read (READ) [RAS = H, CAS = L, WE = H] To know the detailed definition of commands, please see the command truth table. Write (WRITE) [RAS = H, CAS =WE = L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A[8] = H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA). CLK CS READ command starts burst read from the active bank indicated by BA. First output data appears after CAS latency. When A[8] = H at this command, the bank is deactivated after the burst read (auto-precharge, READA). Chip Select: L=select, h=deselect RAS Command CAS Command WE Command CKE Refresh option @refresh command A[8] Precharge Option @ precharge or read/write command Define Basic Commands Activate (ACT) [RAS = L, CAS = WE = H] ACT command activates a row in an idle bank indicated by BA. Precharge (PRE) [RAS = L, CAS = H, WE = L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A[8] = H at this command, both banks are deactivated (precharge all, PREA). Auto-Refresh (REFA) [RAS = CAS = L, WE = CKE = H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. Any other command should not be asserted until tRC is met. Command Truth Table [1] Command CKE n-1 CKE n CS RAS CAS WE BA A8 A[7:0] Deselect DESEL Mnemonic H X H X X X X X X No Operation NOP H X L H H H X X X Row Address Entry & Bank Activate ACT H X L L H H V V V Single Bank Precharge PRE H X L L H L V L X Precharge All Banks PREA H X L L H L V H X Column Address Entry & Write WRITE H X L H L L V L V Column Address Entry & Write with Auto-Precharge WRITEA H X L H L L V H V Column Address Entry & Read READ H X L H L H V L V Column Address Entry & Read with Auto-Precharge READA H X L H L H V H V Auto-Refresh REFA H H L L L H X X X Self-Refresh Entry REFS H L L L L H X X X Self-Refresh Exit REFSX L H H X X X X X X L H L H H H X X X Burst Terminate TBST H X L H H L X X X Mode Register Set MRS H X L L L L L L V 1. H = High Level, L = Low Level, V = Valid, X = Don't Care, n = CLK cycle number G-LINK Technology March 2000 (Rev. 0) 3 Function Truth Table [1] [2] Current State IDLE ROW ACTIVE READ WRITE 4 CS RAS CAS Address [3] WE Action [4] Command H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST ILLEGAL [5] L H L X BA, CA, A[8] READ / WRITE ILLEGAL [5] L L H H BA, RA ACT Bank Active, Latch RA L L H L BA, A[8] PRE / PREA NOP [6] L L L H X REFA Auto-Refresh [7] L L L L Op-Code, Mode-Add MRS Mode Register Set [7] H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST NOP L H L H BA, CA, A[8] READ / READA Begin Read, Latch CA, Determine AutoPrecharge L H L L BA, CA, A[8] WRITE / WRITEA Begin Write, Latch CA, Determine AutoPrecharge L L H H BA, RA ACT Bank Active / ILLEGAL [5] L L H L BA, A[8] PRE / PREA Precharge / Precharge All L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST Terminate Burst L H L H BA, CA, A[8] READ / READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge [8] L H L L BA, CA, A[8] WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine Auto-Precharge [8] L L H H BA, RA ACT Bank Active / ILLEGAL [5] L L H L BA, A[8] PRE / PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST Terminate Burst L H L H BA, CA, A[8] READ / READA Terminate Burst, Latch CA, Begin Read, Determine Auto-Precharge [8] L H L L BA, CA, A[8] WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine Auto-Precharge [8] L L H H BA, RA ACT Bank Active / ILLEGAL [5] L L H L BA, A[8] PRE / PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL G-LINK Technology March 2000 (Rev. 0) Function Truth Table [1] [2] (Continued) Current State READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE PRE -CHARGING ROW ACTIVATING WRITE RECOVERING Address [3] Action [4] Command CS RAS CAS WE H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST ILLEGAL L H L H BA, CA, A[8] READ / READA ILLEGAL L H L L BA, CA, A[8] WRITE / WRITEA ILLEGAL L L H H BA, RA ACT Bank Active / ILLEGAL [5] L L H L BA, A[8] PRE / PREA ILLEGAL [5] L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST ILLEGAL L H L H BA, CA, A[8] READ / READA ILLEGAL L H L L BA, CA, A[8] WRITE / WRITEA ILLEGAL L L H H BA, RA ACT Bank Active / ILLEGAL [5] L L H L BA, A[8] PRE / PREA ILLEGAL [5] L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Idle after tRP) L H H H X NOP NOP (Idle after tRP) L H H L BA TBST ILLEGAL [5] L H L X BA, CA, A[8] READ / WRITE ILLEGAL [5] L L H H BA, RA ACT ILLEGAL [5] L L H L BA, A[8] PRE / PREA NOP [6] (Idle after tRP) L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Row Active after tRCD) L H H H X NOP NOP (Row Active after tRCD) L H H L BA TBST ILLEGAL [5] L H L X BA, CA, A[8] READ / WRITE ILLEGAL [5] L L H H BA, RA ACT ILLEGAL [5] L L H L BA, A[8] PRE / PREA ILLEGAL [5] L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST ILLEGAL [5] L H L X BA, CA, A[8] READ / WRITE ILLEGAL [5] L L H H BA, RA ACT ILLEGAL [5] L L H L BA, A[8] PRE / PREA ILLEGAL [5] L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL G-LINK Technology March 2000 (Rev. 0) 5 Function Truth Table [1] [2] (Continued) Current State REFRESHING MODE REGISTER SETTING 1. 2. 3. 4. 5. 6. 7. 8. 6 Address [3] Action [4] Command CS RAS CAS WE H X X X X DESEL NOP (Idle after tRC) L H H H X NOP NOP (Idle after tRC) L H H L BA TBST ILLEGAL L H L X BA, CA, A[8] READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A[8] PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Idle after tRSC) L H H H X NOP NOP (Idle after tRSC) L H H L BA TBST ILLEGAL L H L X BA, CA, A[8] READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A[8] PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H = High Level, L= Low Level, X = Don't Care. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No OPeration. ILLEGAL = Device operation and/or data-integrity are not guaranteed. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. NOP to bank precharging or in idle state. May precharge bank indicated by BA. ILLEGAL if any bank is not idle. Must satisfy bus contention, bus turn around, write recovery requirements. G-LINK Technology March 2000 (Rev. 0) Function Truth Table for CKE [1] Current State SELF-REFRESH [2] POWER DOWN ALL BANKS IDLE [3] ANY STATE other than listed above 1. 2. 3. 4. CKE n-1 CKE n CS RAS CAS WE Add H X L H L L L L L H L L Action X X X X X INVALID H X X X X Exit Self-Refresh (Idle after tRC) H L H H H X Exit Self-Refresh (Idle after tRC) H L H H L X ILLEGAL H L H L X X ILLEGAL H L L X X X ILLEGAL L X X X X X NOP (Maintain Self-Refresh) X X X X X X INVALID H X X X X X Exit Power Down to Idle L X X X X X NOP (Maintain Self-Refresh) H H X X X X X Refer to Function Truth Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State = Power Down H H X X X X X Refer to Function Truth Table H L X X X X X Begin CLK Suspend at Next Cycle [4] L H X X X X X Exit CLK Suspend at Next Cycle [4] L L X X X X X Maintain CLK Suspend H = High Level, L= Low Level, X = Don't Care. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. Must be legal command. G-LINK Technology March 2000 (Rev. 0) 7 Power On Sequence 3. Issue precharge commands for all banks. (PRE or PREA) Before starting normal operation, the following power on sequence is necessary to prevent damage or malfunction. 4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands. 1. Apply power and start clock. Attempt to maintain CKE high, DQMU / DQML high and NOP condition at the inputs. 5. Issue a mode register set command to initialize the mode register. After this sequence, the SDRAM is idle state and ready for normal operation. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200 ms. SELF REFRESH REFS REFSX MODE REGISTER SET MRS IDLE REFA AUTO REFRESH CKEL CKEH CLK SUSPEND POWER DOWN ACT CKEL CKEH ROW ACTIVE TBST TBST WRITE READ WRITE A WRITE SUSPEND CKEL CKEH READE A READ WRITE WRITE READ WRITE A CKEL CKEH READ SUSPEND CKEL CKEH READ A SUSPEND READE A WRITE A WRITE A SUSPEND CKEL CKEH READE A WRITE A READ A PRE PRE POWER APPLIED POWER ON PRE PRE PRECHARGE Automatic Sequence Command Sequence Figure 2. Simplified State Diagram 8 G-LINK Technology March 2000 (Rev. 0) Mode Register Burst Length, Burst Type and CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command. LATENCY MODE BA A8 A7 WBL 0 O 0 0 0 0 1 1 1 1 CL 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 A6 A5 A4 A3 LTMODE A2 A1 BT A0 CLK BL CAS LATENCY R 1 2 3 R R R R CS 0 0 0 0 1 1 1 1 BURST LENGTH BURST TYPE Write Burst Length (WBL) BA Length 0 = BL specified 1 Single bit (BL = 1) BL 0 0 1 1 0 0 1 1 BT = 0 0 1 1 2 0 4 1 8 0 R 1 R 0 R 1 Full Page 0 1 BT = 1 1 2 4 8 R R R R RAS CAS WE BA, A[8:0] SEQUENTIAL INTERLEAVED CLK CAS Latency Command Address Burst Length Burst Length READ WRITE Y Y DQ Q0 Q1 Q2 Q3 D0 D1 D2 D3 Burst Type Initial Address BL A2 A1 A0 0 0 0 0 0 0 Column Addressing Sequential 8 Interleaved 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 0 0 0 1 2 3 0 1 2 3 - 0 1 1 2 3 0 1 0 3 2 - 1 0 2 3 0 1 2 3 0 1 - 1 1 3 0 1 2 3 2 1 0 - - 0 0 1 0 1 - - 1 1 0 1 0 4 2 G-LINK Technology March 2000 (Rev. 0) 9 OPERATIONAL DESCRIPTION Bank Activate Precharge The SDRAM has two independent banks. Each bank is activated by the ACT command with the bank address (BA). A row is indicated by the row address A[8:0] The minimum activation interval between one bank and the other bank is tRRD. The PRE command deactivates the bank indicated by BA. When both banks are active, the precharge all command (PREA, PRE + A[8] = H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command can be issued. CLK Command ACT ACT READ tRRD A[7:0] Xa Xb Ya A[8] Xa Xb 0 BA 0 1 0 DQ PRE ACT tRAS tRP Xb 1 Xb 1 Qa0 Qa1 Qa2 Qa3 Precharge All Figure 3. Bank Activation and Precharge All (BL=4, CL=3) 10 G-LINK Technology March 2000 (Rev. 0) Read (tRP) can be hidden behind continuous output data (in case of BL = 4) by interleaving the dual banks. When A[8] is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge start timing depends on CAS Latency. The next ACT command can be issued after tRP from the internal precharge timing. After tRCD from the bank activation, a READ command can be issued. 1st output data is available after the CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length is BL. The start address is specified by A[7:0], and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time CLK Command ACT READ ACT READ PRE tRCD A[7:0] Xa Ya Xb Yb A[8] Xa 0 Xb 0 BA 0 0 1 DQ Qa0 0 1 0 Burst Length Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 CAS Latency Figure 4. Dual Bank Interleaving READ (BL=4, CL=3) CLK Command ACT READ A ACT tRCD tRP A[7:0] Xa Y Xa A[8] Xa 1 Xa BA 0 0 0 DQ Qa0 Qa1 Qa2 Qa3 Internal Precharge begins Figure 5. READ with Auto-Precharge (BL=4, CL=3) CLK Command ACT READ A CL=3 DQ CL=2 DQ Qa0 Qa0 Qa1 Qa2 Qa1 Qa2 Qa3 Qa3 Internal Precharge Start Timing Figure 6. READ Auto-Precharge Timing (BL=4) G-LINK Technology March 2000 (Rev. 0) 11 Write case of BL = 4) by interleaving the dual banks. From the last input data to the PRE command, the write recovery time (tRDL) is required. When A[8] is high at a WRITE command, the auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT command can be issued after tRP from the internal precharge timing. After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following (BL-1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A[7:0], and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data (in CLK Command ACT WRITE ACT tRCD WRITE PRE 0 tRCD A[7:0] Xa Y Xb A[8] Xa 0 Xb Y tRDL (1 CLK) 0 BA 0 0 1 1 0 Db0 Db1 DQ Da0 Burst Length Da1 Da2 Da3 Db2 Db3 Figure 7. Dual Bank Interleaving WRITE (BL=4) CLK Command ACT WRITE ACT tRCD tRP A[7:0] Xa Y Xa A[8] Xa 1 Xa BA 0 0 DQ Da0 0 Da1 Da2 tRDL Da3 Internal Precharge Begins Figure 8. WRITE with Auto-Precharge (BL=4) 12 G-LINK Technology March 2000 (Rev. 0) Burst Interruption [Read Interrupted by Read] The burst read operation can be interrupted by a new read of the same or the other bank. GLT540L16 allows random column access. READ to READ interval is 1 CLK minimum. CLK Command READ READ READ READ A[7:0] Yi Yj Yk Yl A[8] 0 0 0 0 BA 0 0 1 0 DQ Qi0 Qj0 Qj1 Qk0 Qk1 Qk2 Ql0 Ql1 Ql2 Ql3 Internal Precharge Start Timing Figure 9. READ Interrupted by READ (BL=4, CL=3) [Read Interrupted by Write] Burst read operation can be interrupted by write of the same or the other bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQMU / DQML to prevent the bus contention. The output is disabled automatically 2 cycles after WRITE assertion. CLK Command READ WRITE A[7:0] Yi Yj A[8] 0 0 BA 0 0 DQMU, DQML Q D Qi0 DQM U/ DQML control Dj0 Dj1 Dj2 Write control Dj3 Figure 10. READ Interrupted by WRITE (BL=4, CL=3) G-LINK Technology March 2000 (Rev. 0) 13 [Read Interrupted by Precharge] Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is minimum 1 CLK. A PRE command disables the data output, depending on the CAS Latency. The figure below shows examples, when the data-out is terminated. CLK Command READ PRE DQ CL=3 Command Q0 READ Q0 READ Command READ PRE Q0 READ DQ Q0 READ Q1 Q2 Q3 PRE DQ Command Q2 Q0 DQ CL=2 Q1 Q3 PRE DQ Command Q2 PRE DQ Command Q1 Q1 Q2 PRE Q0 Figure 11. READ Interrupted by Precharge (BL=4) 14 G-LINK Technology March 2000 (Rev. 0) [Read Interrupted by Burst Terminate] Similarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. READ to TBST interval is minimum 1 CLK. The figure below shows examples, when the data-out is terminated. CLK Command READ TBST DQ CL=3 Q0 Command READ Q0 READ Q2 Q0 Command READ TBST DQ Q0 Command READ Q0 Command READ Q1 Q2 Q3 TBST DQ DQ Q1 Q3 TBST DQ CL=2 Q2 TBST DQ Command Q1 Q1 Q2 TBST Q0 Figure 12. READ Interrupted by Burst Terminate (BL=4) G-LINK Technology March 2000 (Rev. 0) 15 [Write Interrupted by Write] Burst write operation can be interrupted by new write of the same or the other bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. CLK Command WRITE WRITE WRITE WRITE A[7:0] Yi Yj Yk Yl A[8] 0 0 0 0 BA 0 0 1 0 DQ Di0 Dj0 Dj1 Dk0 Dk1 Dk2 Dl0 Dl1 Dl2 Dl3 Figure 13. WRITE Interrupted by WRITE (BL=4) [Write Interrupted by Read] input data on DQ at the interrupting READ cycle is "don't care". Using the DQMU / DQML to prevent the bus contention is optional. Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The CLK Command WRITE READ WRITE READ A[7:0] Yi Yj Yk Yl A[8] 0 0 0 0 BA 0 0 0 1 DQMU, DQML DQ Di0 Qj0 Qj1 Dk0 Dk1 Figure 14. WRITE interrupted by READ (BL=4, CL=3) 16 G-LINK Technology March 2000 (Rev. 0) Ql0 [Write Interrupted by Precharge] Burst write operation can be interrupted by precharge of the same bank. Random column access is allowed. Because the write recovery time (tRDL) is required between the last input data and the next PRE, 3rd data should be masked with DQMU / DQML shown as below. CLK Command WRITE PRE ACT A[7:0] Ya Xb A[8] 0 0 Xb BA 0 0 0 DQMU, DQML DQ Di0 Di1 This data should be masked to satisfy tRDL requirement. Figure 15. WRITE Interrupted by Precharge (BL=4) [Write Interrupted by Burst Terminate] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. The figure below shows the case 3 words of data are written. Random col- umn access is allowed. WRITE to TBST interval is minimum 1 CLK. CLK Command WRITE A[7:0] Ya A[8] 0 BA 0 TBST DQMU, DQML DQ Da0 Da1 Da2 Figure 16. WRITE Interrupted by Burst Terminate (BL=4) G-LINK Technology March 2000 (Rev. 0) 17 Auto Refresh Single cycle of auto-refresh is initiated with a REFA (CS = RAS = CAS = L, WE = CKE = H) command. The refresh address is generated internally. 1024 REFA cycles within 16 ms refresh 4 Mbit memory cells. The auto- refresh is performed on each bank alternately (ping-pong refresh). Before performing an auto-refresh, both banks must be in the idle state. Additional commands must not be supplied to the device before tRC from the REFA command. CLK CS NOP or Deselect RAS CAS WE CKE Minimum tRC A[8:0] BA Auto Refresh on Bank 0 Auto Refresh on Bank 1 Figure 17. Auto Refresh Self Refresh Self-refresh mode is entered by issuing a REFS command (CS = RAS = CAS = L, WE = H, CKE = L). Once the selfrefresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input (but asynchronous), all other inputs including CLK are disabled and ignored, and power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX). After tRC from REFSX both banks are in the idle state and a new command can be issued after tRC, but DESEL or NOP commands must be asserted till then. CLK Stable CLK CS NOP RAS CAS WE CKE new command A[8:0] X minimum tRC for recovery BA 0 Self Refresh Entry Self Refresh Exit Figure 18. Self-Refresh 18 G-LINK Technology March 2000 (Rev. 0) CLK Suspend suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle, but a command at the following cycle is ignored. CKE controls the internal CLK at the following cycle. Figure 19 and Figure 20 show how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input ext. CLK CKE int. CLK CLK CKE Command Standby Power Down PRE NOP NOP CKE Command NOP NOP NOP NOP NOP NOP NOP Active Power Down ACT NOP NOP NOP NOP NOP Figure 19. Power Down by CKE CLK CKE Command DQ WRITE D0 READ D1 D2 D3 Q0 Q1 Q2 Q3 Figure 20. DQ Suspend by CKE G-LINK Technology March 2000 (Rev. 0) 19 DQMU / DQML Control data word by word. DQMU / DQML to write mask latency is 0. During reads, DQMU / DQML forces upper / lower output to Hi-Z word by word. DQMU / DQML to output HiZ latency is 2. DQMU / DQML is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQMU / DQML masks upper / lower input CLK Command WRITE READ DQML DQ[7:0] DQMU DQ[15:8] D0 D2 D3 Q0 Masked by DQML = High D0 Q1 D1 Masked by DQMU = High D3 Q0 Disabled by DQMU =High Figure 21. DQMU / DQML Function 20 G-LINK Technology March 2000 (Rev. 0) Q3 Disabled by DQML = High Q2 Q3 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings [1] Symbol Parameter Ratings Unit with respect to VSS -1.0 to 4.6 V Supply Voltage for Output with respect to VSSQ -1.0 to 4.6 V Input Voltage with respect to VSS -1.0 to 4.6 V VO Output Voltage with respect to VSSQ -1.0 to 4.6 V IO Output Current 50 mA PD Power Dissipation TOPR Operating Temperature TSTG Storage Temperature VDD Supply Voltage VDDQ VI Conditions TA = 25 C 1000 mW 0 to 70 C -65 to 150 C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions (TA = 0 to +70C, unless otherwise noted) Symbol Parameter Min Typ Max Unit VDD Supply Voltage 3.0 3.3 3.6 V VDDQ Supply Voltage for Output 3.0 3.3 3.6 V [1] High-Level Input Voltage all inputs 2.0 VDDQ + 0.3 V VIL [2] Low-Level Input Voltage all inputs -0.3 0.8 V VIH 1. VIH (max) = 5.6 V for pulse width less than 3 ns. 2. VIL (min) = -2.0 V for pulse width less than 3 ns. DC Characteristics (TA = 0 to +70C, VDD = VDDQ = 3.3 0.3V, VSS = VSSQ = 0 V, unless otherwise noted) Symbol Parameter Test Conditions Min Max Unit 0.4 V VOH High-Level Output Voltage IOH = -2 mA VOL Low-Level Output Voltage IOL = 2 mA 2.4 V IOZ Off-state Output Current Q floating VO = 0 to VDDQ -10 10 mA II Input Current VIH = 0 to VDDQ + 0.3 V -10 10 mA Capacitance (TA = 0 to +70C, VDD = VDDQ = 3.3 0.3 V, VSS = VSSQ = 0 V, unless otherwise noted) Symbol CI(A) Parameter Input Capacitance, address pin CI(C) Input Capacitance, control pin CI(K) Input Capacitance, CLK pin CI/O Input Capacitance, I/O pin Test Condition VI = VSS f = 1 MHz VI = 25 mVrms Min Max Unit 2.5 5 pF 2.5 5 pF 2.5 5 pF 4 7 pF G-LINK Technology March 2000 (Rev. 0) 21 Average Supply Current from VDD (TA = 0 to +70C, VDD = VDDQ = 3.3 0.3 V, VSS = VSSQ = 0 V, unless otherwise noted) Rating (Max) -6 -7 -8 -10 Unit ICC1S Symbol Operating Current, Single Bank Parameter tRC = min, tCLK = min, BL = 1, CL = 3 Test Conditions 120 110 100 90 mA ICC1D Operating Current, Dual Bank tRC = min, tCLK = min, BL = 1, CL = 3 170 150 140 120 mA ICC2H Standby Current, CKE = H both banks idle, tCLK = min, CKE = H 20 20 20 20 mA ICC2L Standby Current, CKE = L both banks idle, tCLK = min, CKE = L 2 2 2 2 mA ICC3H Active Standby Current, CKE = H both banks active, tCLK = min, CKE = H 35 35 35 35 mA ICC3L Active Standby Current, CKE = L both banks active, tCLK = min, CKE = L 2 2 2 2 mA ICC4 Burst Current tCLK = min, BL = 4, CL = 3, both banks active 150 140 130 120 mA ICC5 Auto-Refresh Current tRC = min, tCLK = min 110 100 90 80 mA ICC6 Self-Refresh Current CKE < 0.2 V 1 1 1 1 mA Low Power 300 300 300 300 mA AC Characteristics (TA = 0 to +70C, VDD = VDDQ = 3.3 0.3 V, VSS = VSSQ = 0 V, unless otherwise noted) [1] -6 Symbol Parameter Min tCLK CLK Cycle Time tCH CLK High Pulse Width tCL CLK Low Pulse Width 2.0 tT Transition Time of CLK 1 -7 Max CL=2 CL=3 Min -8 Max Min 9 10 6 7 2.0 2.5 2.5 10 1 -10 Max Max Unit 13 ns 8 10 ns 3 3.5 ns 3 10 Min 1 3.5 10 1 ns 10 ns tIS Input Setup Time (all inputs) 2 2.5 2.5 2.5 ns tIH Input Hold Time (all inputs) 1 1 1 1 ns tRC Row Cycle Time 60 63 72 90 ns tRCD Row to Column Delay 18 21 24 30 ns tRAS Row Active Time 42 tRP Row Precharge Time 18 tCCD Column Address to Column Address Delay tRRD Act to Act Delay Time tRSC Mode Register Set Cycle Time tRDL Last Data-In to Row Precharge Delay tREF Refresh Interval Time 100k 42 100k 48 100k ns 1 1 1 1 CLK 2 2 2 2 CLK 2 2 2 2 CLK 1 1 1 1 CLK 16.4 16.4 1.4V Any AC timing is referenced to the input signal crossing 22 G-LINK Technology March 2000 (Rev. 0) ns 30 16.4 Signal 100k 24 1. Input Pulse Levels: 0.8 V to 2.0 V. Input Timing Measurement Level: 1.4 V. CLK 60 21 1.4V 16.4 ms Switching Characteristics (TA = 0 to +70C, VDD = VDDQ = 3.3 0.3 V, VSS = VSSQ = 0 V unless otherwise noted) -6 Symbol Parameter Min -7 Max Min 5.5 -8 Max Min 6 -10 Max Min Unit 7 ns Access Time from CLK CL = 3 tOH Output Hold Time from CLK 2 2.5 3 3 ns tOLZ Delay Time, Output Low Impedance from CLK 1 1 1 1 ns tOHZ Delay Time, Output High Impedance from CLK 5.5 6 Max tAC 6 6 CLK 7 ns 1.4V VTT = 1.4V tAC 50 W VREF = 1.4V VOUT + tOH DQ tOHZ 1.4V 50 pF (1) CLK 1.4V Output Timing Measurement Reference Point 1. For GLT540L16-6, -7, the Output Load is 30 pF. DQ 1.4V Figure 22. Output Load Condition G-LINK Technology March 2000 (Rev. 0) 23 CLK tRCD tRDL tRAS tRP CS tRC RAS CAS WE HIGH CKE DQMU, DQML A[7:0] Xa A[8] Xa BA B0 DQ Yi Xb B0 D ACT Xb WRITE D D B0 B0 PRE ACT D Figure 23. WRITE Cycle (single bank) BL=4 24 G-LINK Technology March 2000 (Rev. 0) tRDL tRDL CLK tRCD tRCD tRAS tRP CS tRC tRRD tRAS RAS CAS WE HIGH CKE DQMU, DQML A[7:0] Xa A[8] Xa BA B0 DQ ACT Ya Xb Yb Xb B0 B1 Da0 Da1 WRITE ACT Da2 Da3 B1 B0 Db0 Db1 WRITE PRE B1 Db2 Db3 PRE Figure 24. WRITE Cycle (Dual Bank) BL=4 G-LINK Technology March 2000 (Rev. 0) 25 CLK tRCD tRCD tRAS tRP CS tRC RAS CAS WE CKE DQMU, DQML A[7:0] X A[8] X Y X X2 BA DQ Q ACT READ Q Q Q PRE Figure 25. READ Cycle (Single Bank) BL=4, CL=3 26 G-LINK Technology March 2000 (Rev. 0) tRCD tRCD CLK tRRD tRAS tRAS tRP CS tRC RAS CAS WE CKE DQMU, DQML A[7:0] Xa A[8] Xa Y Xb Y Xa Xb Xa BA DQ Qa ACT READ Qa Qa Qa READ Qb Qb Qb PRE ACT Qb Figure 26. READ Cycle (Dual Bank) BL=4, CL=3 G-LINK Technology March 2000 (Rev. 0) 27 CLK tRCD tRAS CS RAS CAS WE CKE DQMU, DQML A[7:0] X A[8] X Y Y BA DQ D ACT WRITE D D D Q READ Figure 27. WRITE to READ (Single Bank) BL=4, CL=3 28 G-LINK Technology March 2000 (Rev. 0) Q Q Q tRCD tRCD CLK tRRD tRAS tRAS tRP CS tWR tRC RAS CAS WE CKE DQMU, DQML A[7:0] Xa A[8] Xa Y Xb Y Xa Xb Xa BA DQ ACT Da Da WRITE ACT Da Da READ PRE Qb0 Qb1 PRE ACT Qb2 Qb3 Figure 28. WRITE to READ (Dual Bank) BL=4, CL=3 G-LINK Technology March 2000 (Rev. 0) 29 CLK tRCD tRAS CS RAS CAS WE CKE DQML DQMU A[7:0] X A[8] X Y Y BA DQ[7:0] D D D Q Q DQ[15:8] D D D Q Q ACT WRITE Q Q READ Figure 29. DQM Byte Control for WRITE 3030to READ (Single Bank) BL=4, CL=3 30 G-LINK Technology March 2000 (Rev. 0) CLK tRCD tWR tRAS CS RAS CAS WE CKE for output disable DQMU, DQML A[7:0] Xa A[8] Xa Y Y BA DQ Qa0 PRE READ Qa1 D D D D WRITE PRE Figure 30. READ to WRITE (Single Bank) BL=4, CL=3 G-LINK Technology March 2000 (Rev. 0) 31 tRCD tRCD CLK tRRD tRAS tRP tRAS CS tRC tWR RAS CAS WE CKE for output disable DQMU, DQML A[7:0] Xa A[8] Xa Y Xb Y Xa Xb Xa BA DQ Qa ACT READ ACT Qa PRE Db WRITE Db ACT Figure 31. READ to WRITE (Dual Bank) BL=4, CL=3 32 G-LINK Technology March 2000 (Rev. 0) Db Db PRE CLK tRCD tWR + tRP tRC33 CS RAS CAS WE CKE DQMU, DQML A[7:0] X A[8] X Y X X BA DQ D ACT WRITE A D D D Internal Precharge starts this timing depends on BL ACT Figure 32. Write with Auto-Precharge BL=4 G-LINK Technology March 2000 (Rev. 0) 33 CLK tRCD tRP tRC CS RAS CAS WE CKE DQMU, DQML A[7:0] X A[8] X Y X X BA DQ Q ACT READ Q Q Internal Precharge start s @ CL=3, BL=4 this timing depends on CL and BL Q ACT Figure 33. Read with Auto-Precharge BL=4, CL=3 34 G-LINK Technology March 2000 (Rev. 0) CLK tRP tRC CS RAS CAS WE CKE DQMU, DQML A[7:0] A[8] BA DQ PRE A If any bank is active, it must be precharged REF S REF S Figure 34. Auto-Refresh G-LINK Technology March 2000 (Rev. 0) 35 CLK tRP CS RAS CAS WE CKE DQMU, DQML A[7:0] A[8] BA DQ If any bank is active, it PRE A must be precharged REF S Figure 35. Self-Refresh Entry 36 G-LINK Technology March 2000 (Rev. 0) CLK tRC NOP or desel CS RAS CAS WE CKE tSRX DQMU, DQML A[7:0] X A[8] X BA DQ Internal CLK Re-start ACT Figure 36. Self-Refresh Exit G-LINK Technology March 2000 (Rev. 0) 37 CLK tRP tRPC tRCD CS RAS CAS WE CKE DQMU, DQML A[7:0] Mode A[8] X Y X BA DQ Q PRE A If any bank is active, it must be precharged MRS ACT READ Figure 37. Mode Register Set BL=4, CL=3 38 G-LINK Technology March 2000 (Rev. 0) Q Q PACKAGING INFORMATION VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQML WE CAS RAS CS BA A8/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Top View 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC DQMU CLK CKE NC NC NC A7 A6 A5 A4 VSS Figure 38. 50-Pin 400 mil TSOP II Pin Assignment G-LINK Technology March 2000 (Rev. 0) 39 21.35 max. 20.95 0.1 0.125 26 11.76 0.2 10.16 0.1 50 + 0.05 - 0.02 Detail A 1 25 1.0 0.10 0.125 0.075 0.8 0.3 +0.1/-0.05 0.1 Detail A 0~10 0.5 0.1 Figure 39. 50-Pin 400 mil Plastic TSOP II Package Dimensions 40 G-LINK Technology March 2000 (Rev. 0) ORDERING INFO GLT5160L16 Part Number Mode Cycle Time Max Frequency Interface Package GLT540L16-10TC Synchronous 10 100 MHz LVTTL 50-Pin 400 mil Plastic TSOP II GLT540L16-8TC Synchronous 8 125 MHz LVTTL 50-Pin 400 mil Plastic TSOP II GLT540L16-7TC Synchronous 7 143 MHz LVTTL 50-Pin 400 mil Plastic TSOP II GLT 540L16-6TC Synchronous 6 166MHz LVTTL 50-Pin 400 mil Plastic TSOP ll G-LINK Technology March 2000 (Rev. 0) 41 42 G-LINK Technology March 2000 (Rev. 0) G-LINK Technology March 2000 (Rev. 0) 43 www.glinktech.com G-LINK Technology 2701 Northwestern Parkway Santa Clara, CA 95051, USA TEL: 408-492-9068 * FAX: 408-492-9067 G-LINK Technology Corporation, Taiwan 6F, No. 24-2, Industry E. Rd. IV Science-Based Industrial Park Hsin Chu, Taiwan, R.O.C. TEL: 03-578-2833 * FAX: 03-578-5820 (c) 1999 G-LINK Technology All rights reserved. No part of this document may be copied or reproduced in any form or by any means or transferred to any third party without the prior written consent of G-LINK Technology. Circuit diagrams utilizing G-LINK products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for design purposes is not necessarily given. G-LINK Technology reserves the right to change products or specifications without notice. The information contained in this document does not convey any license under copyrights, patent rights or trademarks claimed and owned by G-LINK or its subsidiaries. G-LINK assumes no liability for G-LINK applications assistance, customer's product design, or infringement of patents arising from use of semiconductor devices in such systems' designs. Nor does G-LINK warrant or represent that any patent right, copyright, or other intellectual property right of G-LINK covering or relating to any combination, machine, or process in which such semiconductor devices might be or are used. G-LINK Technology's products are not authorized for use in life support devices or systems. Life support devices or systems are device or systems which are: a) intended for surgical implant into the human body and b) designed to support or sustain life; and when properly used according to label instructions, can reasonably be expected to cause significant injury to the user in the event of failure. The information contained in this document is believed to be entirely accurate. However, G-LINK Technology assumes no responsibility for inaccuracies. Printed in USA