MMA8452QR1 - NXP SEMICONDUCTORS

Document Number: MMA8452Q

Rev. 10, 04/2016

NXP Semiconductors

Data sheet: Technical data

MMA8452Q, 3-axis, 12-bit/8-bit

digital accelerometer

The MMA8452Q is a smart, low-power , three-axis, capacitive, micromachined

accelerometer with 12 bits of resolution. This accelerometer is packed with

embedded functions with flexible user programmable options, configurable to two

interrupt pins. Embedded interrupt functions allow for overall power savings

relieving the host processor from continuously polling data .

The MMA8452Q has user selectable full scales of ±2 g/±4 g/±8 g with high-pass

filtered data as well as non-filtered data available real-time. The device can be

configured to generate inertial wakeup interrupt signals from any combination of

the configurable embedded functions allowing the MMA8452Q to monitor events

and remain in a low-power mode during periods of inactivity. The MMA8452Q is

available in a 16-pin QFN, 3 mm x 3 mm x 1 mm packag e.

Features

• 1.95 V to 3.6 V supply voltage

• 1.6 V to 3.6 V inte rface vol ta g e

•±2 g/±4 g/±8 g dynamically selectable full-scale

• Output data rates (ODR) from 1. 56 Hz to 800 Hz

• 99 μg/√Hz noise

• 12-bit and 8-bit digital output

•I

2C digital output interface

• Two programmab l e i nterrupt pins for six interrupt sour ce s

• Three embedded channels of motion detection

— Freefall or motion detection: one channel

— Pulse detection: one channel

— Transient detection: one channel

• Orientation (portrait/landscape) detection with set hysteresis

• Automatic ODR change for auto-wake and return to sleep

• High-pass filter data available real-time

•Self-test

• Current consumption: 6 μA to 165 μA

Typical app lications

• E-compass applications

• S tatic orientation detection (portrait/landscape, up/down, left/right, back/front

position identi fication)

• Notebook, e-reader, and laptop tumble and freefall detection

• Real-time orientation detection (virtual reality and gaming 3D user position feedback)

• Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-re ckoning GPS backup)

• Motion detection for portable product po wer saving (auto-sleep and auto-wake for cell phone, PDA, GPS, gaming)

• Shock and vibration monitori ng (mechatronic compensation, shipping and warranty usage logging)

• User interface (menu scrolling by orientation change, pulse detection for button replacement)

Ordering information

Part number Temperature range Package description Shipping

MMA8452QT –40°C to +85°C QFN-16 Tray

MMA8452QR1 –40°C to +85°C QFN-16 Tape and Reel

MMA8452Q

16-pin QFN

3 mm x 3 mm x 1 mm

Top an d bottom view

Top view

Pin connecti ons

141516

876

VDD

VDDIO

BYP

DNC

SCL

GND

INT1

GND

INT2

SA0

SDA

MMA8452Q

Sensors

2NXP Semiconductors

Related documentation

The MMA8452Q device features and operations are described in a variety of reference manuals, user guides, and application

notes. To find the most-current versions of these documents:

1. Go to the NXP homepage at: http://www.nxp.com/

2. In the ALL search box at the top of the page, enter the device number MMA8452Q.

3. Click the Documents link.

Contents

1 Block Diagram and Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Mechanical and Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Zero-g offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3 Self-test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 System Modes (SYSMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1 Device calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2 8-bit or 12-bit data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.3 Low-power modes vs. high-resolution modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.4 Auto-wake/sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.5 Freefal l an d moti on detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.6 Transient detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.7 Pulse detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.8 Orientation detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.9 Interrupt register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.10 Serial I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.1 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 Portrait/landscape embedded function registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3 Motion and freefall embedded function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4 Transient (HPF) acceleration detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.5 Single, double and directional pulse-d etection registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.6 Auto-wake/sleep detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.7 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.8 User offset correction registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7 Printed Circuit Board Layout and Device Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.1 Printed circuit board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.2 Overview of soldering considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.3 Halogen content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.1 Tape and reel information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.2 Package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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MMA8452Q

1 Block Diagram and Pin Description

Figure 1. Block diagr am

Figure 2. Direction of the detectable accelerations

12-bit SDA

SCL

I2C

Embedded

DSP

Functions

C to V

Internal

OSC Clock

GEN

ADC

Converter

VDDIO

VSS

X-axis

Transducer

Y-axis

Transducer

Z-axis

Transducer

Freefall

and Motion

Detection

Transient

Detection

(i.e., fast-motion,

transient)

Orientation with

Set Hysteresis

and Z-lockout

Shake Detection

through

Motion

Threshold

Auto-wake/auto-sleep configurable with debounce counter and multiple motion interrupts for control

Auto-wake/sleep Active mode

sleep

VDD

INT1

INT2

Active mode

wake

Single, Double

and Directional

Tap Detection

MODE Options

Low Power

Low Noise + Low Power

High Resolution

Normal

MODE Options

Low Power

Low Noise + Low Power

High Resolution

Normal

DIRECTION OF THE

DETECTABLE ACCELERATIONS

(BOTTOM VIEW)

(TOP VIEW)

Earth Gravity

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4NXP Semiconductors

MMA8452Q

Figure 3 shows the device configura tio n in the six different orientation modes. These orientations are defined as the following:

PU = portrait up, LR = landscape right, PD = portrait down, LL = landsca p e le ft, back and front side views. Th e r e are several

registers to configure the orientation detection and are described in detail in the register setting section.

Figure 3. Landscape/portrait orientation

Figure 4. Application diagram

Top View

Earth Gravity

Pin 1

Xout @ 0 g

Yout @ –1 g

Zout @ 0 g

Xout @ 1 g

Yout @ 0 g

Zout @ 0 g

Xout @ 0 g

Yout @ 1 g

Zout @ 0 g

Xout @ –1 g

Yout @ 0 g

Zout @ 0 g

LR Side View

FRONT

Xout @ 0 g

Yout @ 0 g

Zout @ 1 g

BACK

Xout @ 0 g

Yout @ 0 g

Zout @ –1 g

0.1μF

1.6V-3.6V

VDDIO

4.7kΩ4.7kΩ

GND

VDDIO

SCL

INT2

INT1

GND

SDA

SA0

VDD

BYP

MMA8452Q

1415

678

4.7μF

INT1

INT2

SA0

0.1μF

1.95V - 3.6V

VDD

SCL

SDA

DNC

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MMA8452Q

The device power is supplied through VDD line. Power supply decoupling capacitors (100 nF ceramic plus 4.7 µF bulk, or a single

4.7 µF ceramic) should be placed as near as possible to the pins 1 and 14 of the device.

The control signals SCL, SDA, and SA0 are not tolerant of voltages more than VDDIO + 0.3 V. If VDDIO is removed, the control

signals SCL, SDA, and SA0 will clamp any logic signals with their internal ESD protection dio des.

The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) are user programmable through the I2C

interface. The SDA and SCL I2C connections are open drain and therefore require a pullup resistor as shown in the application

diagram in Figure 4.

Table 1. Pin descriptions

Pin # Pin name Description

1 VDDIO Internal power supply (1.62 V to 3.6 V)

2 BYP Bypass capacitor (0.1 μF)

3 DNC Do not connect to anything, leave pin isolated and floating.

4SCL

I2C serial clock, open drain

5 GND Connect to ground

6SDA

I2C serial data

7SA0

I2C least significant bit of the device I2C address, I2C 7-bit address = 0x1C (SA0 = 0), 0x1D (SA0 = 1).

8 NC Internally not connected

9 INT2 Inertial interrupt 2, output pin

10 GND Connect to ground

11 INT1 Inertial interrupt 1, output pin

12 GND Connect to ground

13 NC Internally not connected

14 VDD Power supply (1.95 V to 3.6 V)

15 NC Internally not connected

16 NC Internally not connected (can be GND or VDD)

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2 Mechanical and Electrical S pecifications

2.1 Mechanical characteristics

Table 2. Mechanical characteristics @ VDD = 2.5 V, VDDIO = 1.8 V, T = 25 °C unless otherwise noted.

Parameter Test conditions Symbol Min Typ Max Unit

Measurement range(1)

1. Dynamic range is limited to 4 g when the low-noise bit in register 0x2A, bit 2 is set.

FS[1:0] set to 00

2 g mode

—±2—

FS[1:0] set to 01

4 g mode —±4—

FS[1:0] set to 10

8 g mode —±8—

Sensitivity

FS[1:0] set to 00

2 g mode

— 1024 —

counts/g

FS[1:0] set to 01

4 g mode — 512 —

FS[1:0] set to 10

8 g mode — 256 —

Sensitivity accuracy(2)

2. Sensitivity remains in spec as stated, but changing oversampling mode to low power causes 3% sensitivity shift. This behavior is also seen

when changing from 800 Hz to any other data rate in the normal, low noise + low power or high resolution mode.

— Soa — ±2.64 — %

Sensitivity change vs. temperature

FS[1:0] set to 00

2 g mode

TCSo

—

±0.008

—

%/°C

FS[1:0] set to 01

4 g mode ——

FS[1:0] set to 10

8 g mode ——

Zero-g level offset accuracy(3)

3. Before board mount.

FS[1:0] 2 g, 4 g, 8 g TyOff — ±17 — mg

Zero-g level offset accuracy post-board mount(4)

4. Post-board mount offset specifications are based on an 8-layer PCB, relative to 25°C.

FS[1:0] 2 g, 4 g, 8 gTyOffPBM — ±20 — mg

Zero-g level change vs. temperature –40 °C to 85 °C TCOff — ±0.15 — mg/°C

Self-test output change(5)

5. Self-test is one direction only.

FS[1:0] set to 0

4 g mode Vst —

—

+44

+61

+392

—

LSB

ODR accuracy

2-MHz clock — — — ±2 — %

Output data bandwidth — BW ODR/3 — ODR/2 Hz

Output noise Normal mode ODR = 400 Hz Noise — 126 — µg/√Hz

Output noise low-noise mode(1) Normal mode ODR = 400 Hz Noise — 99 — µg/√Hz

Operating temperature range — Top –40 — +85 °C

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MMA8452Q

2.2 Electrical characteristics

Table 3. Electrical characteristics @ VDD = 2.5 V, VDDIO = 1.8 V, T = 25 °C unless otherwise noted.

Parameter Test conditions Symbol Min Typ Max Unit

Supply voltage — VDD(1)

1. There is no requirement for power supply sequencing. The VDDIO input voltage can be higher than the VDD input voltage.

1.95 2.5 3.6 V

Interface supply voltage — VDDIO(1) 1.62 1.8 3.6 V

Low-power mode

ODR = 1.56 Hz

IddLP

—6—

μA

ODR = 6.25 Hz — 6—

ODR = 12.5 Hz — 6—

ODR = 50 Hz — 14 —

ODR = 100 Hz — 24 —

ODR = 200 Hz — 44 —

ODR = 400 Hz — 85 —

ODR = 800 Hz — 165 —

Normal mode

ODR = 1.56 Hz

Idd

—24 —

μA

ODR = 6.25 Hz — 24 —

ODR = 12.5 Hz — 24 —

ODR = 50 Hz — 24 —

ODR = 100 Hz — 44 —

ODR = 200 Hz — 85 —

ODR = 400 Hz — 165 —

ODR = 800 Hz — 165 —

Current during boot sequence, 0.5 mSec max

duration using recommended bypass cap VDD = 2.5 V Idd Boot — — 1mA

Value of capacitor on BYP pin –40 °C 85 °C Cap 75 100 470 nF

Standby mode current @ 25 °C VDD = 2.5 V, VDDIO = 1.8 V,

standby mode IddStby — 1.8 5 μA

Digital high-level input voltage

SCL, SDA, SA0 —VIH 0.7*VDDIO — — V

Digital low-level input voltage

SCL, SDA, SA0 —VIL — — 0.3*VDDIO V

High-level output voltage

INT1, INT2 IO = 500 μA VOH 0.9*VDDIO — — V

Low-level output voltage

INT1, INT2 IO = 500 μA VOL — — 0.1*VDDIO V

Low-level output voltage

SDA IO = 500 μAVOLS—

—0.1*VDDIO V

Power on ramp time —0.001 — 1000 ms

Boot time Time from VDDIO on and

VDD > VDD min until I2C is ready

for operation, Cbyp = 100 nF Tbt — 350 500 µs

Turn-on time(2)

2. Note the first sample is typically not very precise. Depending on ODR/MODS setting, a minimum of three samples is recommended for full

precision.

Time to obtain valid data from

standby mode to active mode. Ton1 —2/ODR + 1 ms s

Turn-on time Time to obtain valid data from valid

voltage applied. Ton2 —2/ODR + 2 ms —

Operating temperature range —Top –40 —+85 °C

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2.3 I2C interface characteristics

Table 4. I2C slave timing values(1)

1.All values referred to VIH(min) (0.3 VDD) and VIL(max) (0.7 VDD) levels.

Parameter Symbol I2C fast-mode Unit

Min Max

SCL clock frequency fSCL 0 400 kHz

Bus-free time between stop and start condition tBUF 1.3 —μs

(Repeated) start hold time tHD;STA 0.6 —μs

Repeated start setup time tSU;STA 0.6 —μs

Stop condition setup time tSU;STO 0.6 —μs

SDA data hold time tHD;DAT 0.05 0.9(2)

2.This device does not stretch the low period (tLOW) of the SCL signal.

μs

SDA setup time tSU;DAT 100 —ns

SCL clock low time tLOW 1.3 —μs

SCL clock high time tHIGH 0.6 —μs

SDA and SCL rise time tr20 + 0.1 Cb(3)

3.Cb = total capacitance of one bus line in pF.

300 ns

SDA and SCL fall time tf20 + 0.1 Cb(3) 300 ns

SDA valid time (4)

4.tVD;DAT = time for data signal from SCL low to SDA output (high or low, depending on which one is worse).

tVD;DAT —0.9(2) μs

SDA valid acknowledge time (5)

5.tVD;ACK = time for acknowledgement signal from SCL low to SDA output (high or low, depending on which one is worse).

tVD;ACK —0.9(2) μs

Pulse width of spikes on SDA and SCL that must be suppressed by

internal input filter tSP 050ns

Capacitive load for each bus line Cb —400 pF

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Figure 5. I2C slave timing diagram

2.4 Absolute maximum ratings

Stresses above those listed as absolute maximum ratings may cause permanent damage to the device. Exposure to maximum

rating conditions for extended periods may affect device reliability.

Table 5. Maximum ratings

Rating Symbol Value Unit

Maximum acceleration (all axes, 100 μs) gmax 5,000 g

Supply voltage VDD –0.3 to + 3.6 V

Input voltage on any control pin (SA0, SCL, SDA) Vin –0.3 to VDDIO + 0.3 V

Drop test Ddrop 1.8 m

Operating temperature range TOP –40 to +85 °C

Storage temperature range TSTG –40 to +125 °C

Table 6. ESD and latchup protection characteristics

Rating Symbol Value Unit

Human body model HBM ±2000 V

Machine model MM ±200 V

Charge device model CDM ±500 V

Latchup current at T = 85°C —±100 mA

VIL = 0.3VDD

VIH = 0.7VDD

This device is sensitive to mechanical shock. Improper handling can cause permanent damage of the part or

cause the part to otherwise fail.

This device is sensitive to ESD, improper handling can cause permanent damage to the part.

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3 Terminology

3.1 Sensitivity

The sensitivity is represented in counts/g. In 2 g mode the sensitivity is 1024 counts/g. In 4 g mode the sensitivity is

512 counts/g and in 8 g mode the sensitivity is 256 counts/g.

3.2 Zero-g offset

Zero-g offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if the sensor is stationary. A

sensor stationary on a horizontal surface will measure 0 g in X-axis and 0 g in Y-axis whereas the Z-axis will measure 1 g. The

output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 0x00, data expressed as 2's

complement number). A deviation from ideal value in this case is called zero-g offset. Offset is to some extent a result of stress

on the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or

exposing it to extensive mechan ical stress.

3.3 Self-test

Self-test checks the transducer functionality without external mechanical stimulus. When self-test is activated, an electrostatic

actuation force is applied to the sensor, simulating a small acceleration. In this case, the sensor outputs will exhibit a change in

their DC levels which are related to the selected full scale through the device sensitivity. When self-test is activated, the device

output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic

test-force.

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MMA8452Q

4 System Modes (SYSMOD)

Figure 6. MMA8452Q mode transition diagram

All register contents are preserved when transitioning from active to standby mode. Some registers are reset when transitioning

from st an d by to acti ve . Th e se are all noted in the device memory map register table. The sleep and wake modes are active

modes. For more information on how to use the sleep and wake modes and how to transition between these modes, please refer

to the functionality section of this document.

Table 7. Mode of operation desc ription

Mode I2C bus state VDD Fu nction description

OFF Powered down <1.8V

VDDIO Can be > VDD

• The device is powered off.

• All analog and digital blocks are shutdown.

•I

2C bus inhibited.

Standby I2C communication is possible >1.8V

• Only digital blocks are enabled.

analog subsystem is disabled.

• Internal clocks disabled.

• Registers accessible for read/write.

• Device is configured in standby mode.

Active

(wake/sleep) I2C communication is possible >1.8V • All blocks are enabled (digital, analog).

OFF

WakeStandby

OFF

Active

SYSMOD = 00

SYSMOD = 10

SYSMOD = 01

Auto-sleep/wake

Condition

VDD > 1.8 V

VDD < 1.8 V

CTRL_REG1

Active bit = 1

CTRL_REG1

Active bit = 0

CTRL_REG1

Active bit = 0

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MMA8452Q

5 Functionality

The MMA8452Q is a low-power, digita l output 3-axis linear accelerometer wi th a I 2C interface and embedded logic used to detect

events and notify an external microprocessor over interrupt lines. The functionality includes the following:

• 8-bit or 12-bit data which includes high-pass filtered dat a

• Four different oversampling options for compromising between resolution and current consumption based on application

requirements

• Additional low-noise mode that functions independe ntly of the oversampling modes for higher resolution

• Low-power and auto-wake/sleep mo des for conservation of current consumption

• Single-/double-pulse with directional information one channel

• Motion detection with directional information or freefall one channel

• Transient detection based on a high-pass filter and settable threshold for detecting the change in acceleration above a

threshold with directional information one channel

• Portrait/landscape detection w ith trip points fixed at 30° and 60° for smooth transitions between orientations.

All functionality is availa ble in 2 g, 4 g or 8 g dynamic ranges. There are many configuration settings for enabling all the dif ferent

functions. Separate application notes have be en provided to help configure the device for each embedded functionality.

Table 8. Features of the MMA845xQ devices

Feature list MMA8451Q MMA8452Q MMA8453Q

Digital resolution (bits) 14 12 10

Digital sensitivity (counts/g) 4096 1024 256

Data-ready interrupt Yes Yes Yes

Single-pulse interrupt Yes Yes Yes

Double-pulse interrupt Yes Yes Yes

Directional-pulse interrupt Yes Yes Yes

Auto-wake Yes Yes Yes

Auto-sleep Yes Yes Yes

Freefall interrupt Yes Yes Yes

32-level FIFO Yes No No

High-pass filter Yes Yes Yes

Low-pass filter Yes Yes Yes

Orientation detection portrait/landscape = 30°, landscape to portrait = 60°,

and fixed 45° threshold Yes Yes Yes

Programmable orientation detection Yes No No

Motion interrupt with direction Yes Yes Yes

Transient detection with high-pass filter Yes Yes Yes

Low-power mode Yes Yes Yes

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MMA8452Q

5.1 Device calibration

The device interface is factory calibrated for sensitivity and zero-g of fset for each axis. The trim values are stored in non- volatile

memory (NVM). On power-up, the trim parameters are read from NVM and applied to the circuitry. In normal use, further

calibration in the end application is not necessary. However, the MMA8452Q allows the user to adjust the zero-g offset for each

axis af ter p ower-up, c hanging the def ault of f set values. The user offset adjustments are stored in six volatile regi sters. Fo r more

information on device calibration, refer to application note, AN4069.

5.2 8-bit or 12-bit data

The measured acceleration data is stored in the OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and

OUT_Z_LSB registers as 2’s complement 12-bit numbers. The most significant 8-bits of each axis are stored in OUT_X (Y,

Z)_MSB, so applications nee din g only 8-bit results can use these three registers and ig n ore OU T_X,Y, Z_LSB. To do this, the

F_READ bit in CTRL_REG1 must be set. When the F_READ bit is cleared, the fast-read mode is disabled.

When the full-scale is set to 2 g, the measurement range is –2 g to +1.999 g, and each count corresponds to 1 g/1024

(1 mg) at 12-b its resolution. When the full-scale is set to 8 g, the measurement range is –8 g to +7.996 g, and each count

corresponds to 1 g/256 (3.9 mg) at 12-bits reso lution. The resolu tion is reduced by a factor of 16 if on ly the 8-bit resul ts are used.

For more information on the data manipulation between data format s and modes, refer to NXP application note AN4076. There

is a device driver available that can be used with the Sensor Toolbox demo board (LFSTBEB8451, 2, 3Q).

5.3 Low-power modes vs. high-resolution modes

The MMA8452Q can be optimized for lower power modes or for higher resolution of the output data. High resolution is achieved

by setting the LNOISE bit in register 0x2A. This improves the resolution but be awar e that the dynamic range is limited to 4 g

when this bit is set. This will affect all internal functions and reduce noise. Another method for improving the resolution of the data

is by oversampling. One of the oversampling schemes of the data can activated when MODS = 10 in register 0x2B which will

improve the resolution of the output data only. The highest resolution is achieved at 1.56 Hz.

There is a trade-off between low power and high resolution. Low power can be achieved when the oversampling rate is reduced.

The lowest power is achieved when MODS = 11 or when the sample rate is set to 1.56 Hz. F or more info rmation on how to

configure the MMA8452Q in low-power mode or high-resolution mode and to realize the benefits, refer to NXP application note

AN4075.

5.4 Auto-wake/sleep mode

The MMA8452Q can be configured to transition between sample rates (with their respect ive current consumption ) based on four

of the interrupt functions of the device. The advantage of using the auto-wa ke /sleep is that the system can automatically transition

to a higher sample rate (higher current consumption) when needed but spends the majority of the time in the sleep mode (lower

current) when the device does not require higher sampling rates. Auto-w a k e refers to the device being triggered by one of the

interrupt f unctions to transition to a higher sampl e rate. T his may also interrupt the processor to transition from a sleep mode to a

higher power mode.

Sleep mode occurs after the accelerometer has not detected an interrupt for longer than the user definable time-out period. The

device will transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode to save on

current during this period of inactivity.

The interrupts that can wake the device from sleep are the following: pulse detection, orientation detection, motion/freefall, and

transient detection. Refer to AN4074, for more detailed information for configuring the auto-wake/sle ep.

5.5 Freefall and motion detection

MMA8452Q has flexible interrupt architecture for detecting either a freefall or a motion. Freefall can be enabled where the set

threshold must be less than the configured threshold, or motion can be enabled where the set threshold must be greater than

the threshold. The motion configuration has the option of enabling or disabling a high-pass filter to eliminate tilt data (static offset).

The freefall does not use the high-pass filter. For det ails on the freefall and motion detection with specific application examples

and recommended configuration settings, refer to NXP application note AN4070.

5.5.1 Freefall detection

The detection of freefall involves the monitoring of the X, Y, and Z axes for the condition where the acceleration magnitude is

below a user specified threshold for a user definable amount of time. Normally, the usable threshold ranges are between

±100 mg and ±500 mg.

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14 NXP Semiconductors

MMA8452Q

5.5.2 Motion detection

Motion is often used to simply alert the main processor that the device is currently in use. When the acceleration exceeds a set

threshold the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the

threshold and tim ing valu es co nf igu re d for the event. The moti o n det ectio n fun c ti o n can analyze static acceleration changes or

faster jolts. For example, to detect that an object is spinning, all three axes would be enabled with a threshold detection of > 2 g.

This condition would ne ed to occur for a minimum of 100 ms to ensure that the event wasn't just noise. The timing value is set

by a configurable debounce counter. The debounce counter acts like a filter to determine whether the condition exists for

configurable set of time (i.e., 100 ms or longer). There is also directional data available in the source register to detect the

direction of the motion. This is useful for applications such as directional shake or flick, which assists with the algorithm for various

gesture detections.

5.6 Transient detection

The MMA8452Q has a built-in high-pass filter. Acceleration data goes through the high-pass filter, eliminating the offset (DC) and

low frequenci es. The high-p ass fi lter cutoff frequency can be set b y th e user to four different fr eq ue ncies which are depe nd ent

on the outpu t data rate (ODR ). A higher cutof f frequency ensures the DC dat a or slower moving data will be filtered out, allowing

only the h igher frequencies to pass. The embedded t r a n s i e n t detection functio n uses the high -pass fi ltered dat a allowing t he user

to set the threshold and debounce counter. The tra nsient detection feature can be used in the same manner as the motion

detection by bypassing the high-pass filter. There is an option in the configuration register to do this. This adds more flexibility to

cover various customer use cases.

Many applicat ions use the ac celeromete r’s static acceleration read ings (i.e., tilt) whic h measur e the change in accele rati on due

to gravity onl y. These functions be nefit from accelera tion data being filtered with a low-pa ss filter where high-frequency data is

considered noise. However, there are many functions where the accelerometer must analyze dynamic acceleration. Functions

such as ta p, flick, shake and step counting are based on the analysis of the change in the acceleration. It is simpler to interpret

these functions dependent on dynamic acceleration data when the static component has been removed. The tr ans ie nt detection

function can be routed to either interrupt pin through bit 5 in CTRL_REG5 register (0x2E). registers 0x1D to 0x20 are the

dedicated t ra n si e nt detection configuration registers. The source register contains directional data to determine the direction of the

acceleration, either positive or negative. For details on the benefits of the embedded tran sie nt detection function along with specific

application examples and recommended configuration settings, please refer to NXP application note AN4071.

5.7 Pulse detection

The MMA8452Q has embedded single/dou ble and directional pulse detection. This function has various customizing timers for

setting the pulse time width and the latency time between pulses. There are programmabl e thresholds for all three axes. The

pulse detection can be configured to run through the high-pass filter and also through a low-pass filter, which provides more

customizing and tunable pulse -detection schemes. The status register provides updates on the axes where the event was

detected and the direction of the tap. For more information on ho w to configure th e device for pulse detection, please refer to

NXP application note AN4072.

5.8 Orientation detection

The MMA8452Q has an orientation detection algorithm with the ability to detect all six orient ations. The transition from portrait to

landscape is fixed with a 45° threshold angle and a ±14° hysteresis angle. This allows the for a smooth transition from portrait to

landscape at approximately 30° and then from landscape to portrait at approximately 60°.

The angle at which the device no longer detects the orientation change is referred to as the Z-lockout angle. The device operates

down to 29° from the flat position. All angles are accurate to ±2°.

For further information on the orientation detection function refer to NXP application note AN4068.

Figure 8 shows the definitions of the trip angles going from landscape to portrait (A) and then also from portrait to landscape (B).

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NXP Semiconductors 15

MMA8452Q

Figure 7. Landscape/portrait orientation

Figure 8. Illustration of landscape to portrait transition (A) and portrait to landscap e tr an sition (B)

Figure 9 illustrates the Z-angle lockout region. When lif ting the device upright from the flat position it will be active for orientation

detection as low as 29° from flat.

Figure 9. Illustration of Z-tilt angle lockout t rans ition

Top View

Earth Gravity

Pin 1

Xout @ 0 g

Yout @ –1 g

Zout @ 0 g

Xout @ 1 g

Yout @ 0 g

Zout @ 0 g

Xout @ 0 g

Yout @ 1 g

Zout @ 0 g

Xout @ –1 g

Yout @ 0 g

Zout @ 0 g

Side View

FRONT

Xout @ 0 g

Yout @ 0 g

Zout @ 1 g

BACK

Xout @ 0 g

Yout @ 0 g

Zout @ –1 g

Portrait

Landscape to portrait

90°

Trip angle = 60°

0° Landscape

Portrait

Portrait to landscape

90°

Trip angle = 30°

0° Landscape

(A) (B)

Upright

NORMAL

90°

Z-LOCK = 29°

0° Flat

DETECTION

REGION

LOCKOUT

REGION

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5.9 Interrupt register configurations

There are six configurable interrupts in the MMA8452Q: data-ready, motion/freefall, pulse, orientation, transient, and auto-sleep

events. These six inte rrupt sources can be routed to one of two interrupt pins. The int errupt source mu st be en abl e d and

configured. If the event flag is asserted because the event condition is detected, the corresponding interrupt pin, INT1 or INT2,

will assert .

Figure 10. System interrupt generation block diagram

5.10 Serial I2C interface

Acceleration data may be accessed through an I2C interface thus making the device particularly suitable for direct interfacing with

a microcontroller. The MMA8452Q features an interrupt signal which indicates when a new set of measured acceleration dat a is

available thus simplifying data synchronization in the digital system that uses the device. The MMA8452Q may also be configured

to generate other interrupt signals accordingly to the programmable embe dded functions of the device for motion, freefall,

transient, orientation, and pulse.

The registers embedded inside the MMA8452Q are accessed through the I2C serial interface (Table 9). To enable the I2C

interface, VDDIO line must be tied high (i.e., to the interface supply voltage). If VDD is not present and VDDIO is present, the

MMA8452Q is in off mode and communications on the I2C interface are ignored. The I2C interface may be used for

communicati on s be tween other I2C devices and the MMA8452Q does not affect the I2C bus.

There are two signals associated with the I2C bus; the serial clock line (SCL) and the serial data line ( SD A). The latt er is a

bidirectional line used for sending and receiving the data to/from the interface . External pullup resistors connected to VDDIO are

expected for SDA and SCL. When the bus is free both the lines are high. The I2C interface is compliant with fast mode (400 kHz),

and normal mode (100 kHz) I2C sta ndards (Table 5).

Table 9. Serial interface pin description

Pin name Pin description

SCL I2C serial clock

SDA I2C serial data

SA0 I2C least significant bit of the device address

INTERRUPT

CONTROLLER

Data Ready

Motion/Freefall

Pulse

Orientation

Transient

Auto-sleep

INT ENABLE INT CFG

INT1

INT2

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MMA8452Q

5.10.1 I2C operation

The transaction on the bus is st arted through a start condition (start) signal. S tart condition is defined as a high to low transition on

the data line while the SCL line is held high. After start has been transmitted by the master , the bus is considered busy. The next

byte of data transmitted after start cont ains the slave address in the first seven bit s, and the eighth bit tells whether the master is

receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the

first seven bits af ter a start condition with its address. If they match, the device considers it self addressed by the master . The 9th

clock pulse, following the slave address byte (and each subsequent byte) is the acknowledge (ACK). Th e transmitter must

release the SDA line during the ACK period. The receiver must then pull the dat a line low so that it remains stable low during the

high period of the acknowledge clock period.

A low to high transition on the SDA line while the SCL line is high is defined as a stop condition (stop). A data transfer is always

terminated by a stop. A master may also issue a repeated start during a data transfer. The MMA8452Q expect s repeated start s

to be used to randomly read from specific registers.

The MMA8452Q's standard slave address is a choice between the two sequential addresses 0011100 and 0011101. The selection

is made by the high- and low-logic level of the SA0 (pin 7) input respectively. The slave addresses are factory programmed and

alternate addresses are available at customer request. The format is shown in Table 10.

Single-byte read

The MMA845 2 Q has an internal ADC that can sample, convert and return sensor data on request. The transmission of an

8-bit command begins on the falling edge of SCL. After the eight clock cycles are used to send the command, note that the data

returned is sent with the MSB first once the data is received. Figure 11 shows the timing diagram for the ac celeromete r 8-bit I2C

read operation. The master (or MCU) transmits a st art condition (ST) to the MMA8452Q, slave address ($1D), with the R/W bit

set to ‘0’ for a write, and the MMA8452Q sends an acknowledgement. Then the master (or MCU) transmits the address of the

register to read and the MMA8452Q sends an acknowledgement. The master (or MCU) transmits a repeated start condition (SR)

and then addresses the MMA8452Q ($1D) with the R/W bit set to ‘1’ for a read from the previously selected register. The Slave

then acknowledges and transmits the dat a from the requested register. The master does not acknowledge (NAK) the transmitted

data, but transmits a stop condition to end the data transfer.

Multiple-byte read

When performing a multi-byte read or burst read , the MMA8452Q automatically increments the received register address

commands after a read command is received. Therefore, after following the step s of a single-byte read, multiple bytes of data

can be read from sequential registers after each MMA8452Q acknowledgment (AK) is received until a no acknowledge (NAK)

occurs from the master followed by a stop co ndition (SP) signaling an end of transmission.

Single-byte write

To start a write command, the master transmits a st art condition (ST) to the MMA8 452Q, slave address ($1D) with the R/W bit set

to ‘0’ for a write, the MMA8452Q sends an acknowledgement. Then the master (MCU) transmits the address of the register to

write to, and the MMA8452Q sends an acknowledgement. Then the master (or MCU) transmits the 8-bit dat a to write to the

designated regi st er and the MMA8452 Q se nds an ackn o w led g ement that it has receive d the data. Since this transmissi o n is

complete, the master transmits a stop condition (SP) to the data transfer. The data sent to the MMA8452Q is now stored in the

approp riate register.

Multiple -byte write

The MMA8452Q automatically increments the received register address commands after a write command is received.

Therefor e, after following the steps of a sing le-byte write, mult ipl e by tes of da ta can be writ ten to s equ entia l regi sters a fter each

MMA8452Q acknowledgment (ACK) is received.

Table 10. I2C device address sequence

Command [7:2]

Device address [1]

SA0 [7:1]

Device address R/W [7:0]

8-bit final value

Read 001110 0 0x1C 1 0x39

Write 001110 0 0x1C 0 0x38

Read 001110 1 0x1D 1 0x3B

Write 001110 1 0x1D 0 0x3A

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I2C data sequence diagrams

Figure 11. I2C data sequence diagrams

< Single-byte read >

Master ST Device Address[6:0] WRegister Address[7:0] SR Device Address[6:0] R NAK SP

Slave AK AK AK Data[7:0]

< Multiple-byte read >

Master ST Device Address[6:0] WRegi ster Address[7:0] SR Device Address[6:0] R AK

Slave AK AK AK Data[7:0]

Master AK AK NAK SP

Slave Data[7:0] Data[7:0] Data[7:0]

< Single-byte write >

Master ST Device Ad dress[6:0] WRe gis t e r Ad dress[7:0] Data[7:0] SP

Slave AK AK AK

< Multiple-byte write >

Master ST Device Address[6:0] WRegi ster Address[7:0] Data[7:0] Data[7:0] SP

Slave AK AK AK AK

Legend

ST: Start condition SP: Stop condition NAK: No acknowledge W: Write = 0

SR: Repeated start condition AK: Acknowledge R: Read = 1

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NXP Semiconductors 19

MMA8452Q

6 Register Descriptions

Table 11. Register address map

Name Type Register

address Auto-increment address Default Hex

value Comment

F_READ = 0 F_READ = 1

STATUS(1)(2) R 0x00 0x01 00000000 0x00 Real time status

OUT_X_MSB(1)(2) R 0x01 0x02 0x03 Output — [7:0] are 8 MSBs of 12-bit sample.

OUT_X_LSB(1)(2) R 0x02 0x03 0x00 Output — [7:4] are 4 LSBs of 12-bit sample.

OUT_Y_MSB(1)(2) R 0x03 0x04 0x05 Output — [7:0] are 8 MSBs of 12-bit sample.

OUT_Y_LSB(1)(2) R 0x04 0x05 0x00 Output — [7:4] are 4 LSBs of 12-bit sample.

OUT_Z_MSB(1)(2) R 0x05 0x06 0x00 Output — [7:0] are 8 MSBs of 12-bit sample.

OUT_Z_LSB(1)(2) R 0x06 0x00 Output — [7:4] are 4 LSBs of 12-bit sample.

Reserved R 0x07 — — — Reserved. Read return 0x00.

Reserved R 0x08 — — — Reserved. Read return 0x00.

SYSMOD R 0x0B 0x0C 00000000 0x00 Current System mode

INT_SOURCE(1)(2) R 0x0C 0x0D 00000000 0x00 Interrupt status

WHO_AM_I R 0x0D 0x0E 00101010 0x2A Device ID (0x2A)

XYZ_DATA_CFG(3)(4) R/W 0x0E 0x0F 00000000 0x00 HPF data out and dynamic range settings

HP_FILTER_CUTOFF(3)(4) R/W 0x0F 0x10 00000000 0x00 Cutoff frequency is set to 16 Hz @ 800 Hz

PL_STATUS(1)(2) R 0x10 0x11 00000000 0x00 Landscape/p ortrait orientation status

PL_CFG(3)(4) R/W 0x11 0x12 10000000 0x80 Landscape/portrait confi guration.

PL_COUNT(3)(4) R 0x12 0x13 00000000 0x00 Landscape/portrait debounce count er

PL_BF_ZCOMP(3)(4) R 0x13 0x14 01000100 0x44 Back/front, Z-lock trip threshold

P_L_THS_REG(3)(4) R 0x14 0x15 10000100 0x84 Portrait to landscape trip angle is 29°

FF_MT_CFG(3)(4) R/W 0x15 0x16 00000000 0x00 Freefall/motion functional block configuration

FF_MT_SRC(1)(2) R 0x16 0x17 00000000 0x00 Freefall/motion event source register

FF_MT_THS(3)(4) R/W 0x17 0x18 00000000 0x00 Freefall/motion t hreshold register

FF_MT_COUNT(3)(4) R/W 0x18 0x19 00000000 0x00 Freefall/motion debounce counter

Reserved R 0x19 -

0x1C ———

Reserved. Read return 0x00.

TRANSIENT_CFG R/W 0x1D 0x1E 00000000 0x00 Transient functional block configuration

TRANSIENT_SRC(1)(2) R 0x1E 0x1F 00000000 0x00 Transient event status register

TRANSIENT_THS(3)(4) R/W 0x1F 0x20 00000000 0x00 Transient event threshold

TRANSIENT_COUNT(3)(4) R/W 0x20 0x21 00000000 0x00 Transient debounce counter

PULSE_CFG(3)(4) R/W 0x21 0x22 00000000 0x00 ELE, Doubl e_XYZ or Single_XYZ

PULSE_SRC(1)(2) R 0x22 0x23 00000000 0x00 EA, Double_XYZ or Single_XYZ

PULSE_THSX(3)(4) R/W 0x23 0x24 00000000 0x00 X pulse threshold

PULSE_THSY(3)(4) R/W 0x24 0x25 00000000 0x00 Y pulse threshold

PULSE_THSZ(3)(4) R/W 0x25 0x26 00000000 0x00 Z pulse threshold

PULSE_TMLT(3)(4) R/W 0x26 0x27 00000000 0x00 Time limit for pulse

PULSE_LTCY(3)(4) R/W 0x27 0x28 00000000 0x00 Latency time for 2nd pulse

PULSE_WIND(3)(4) R/W 0x28 0x29 00000000 0x00 Window time for 2nd pulse

ASLP_COUNT(3)(4) R/W 0x29 0x2A 00000000 0x00 Counter setting for auto-sleep

CTRL_REG1(3)(4) R/W 0x2A 0x2B 00000000 0x00 Data rate, active mode

CTRL_REG2(3)(4) R/W 0x2B 0x2C 00000000 0x00 Sleep enable, OS modes, RST, ST

CTRL_REG3(3)(4) R/W 0x2C 0x2D 00000000 0x00 W ake from sleep, IPOL, PP_OD

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20 NXP Semiconductors

MMA8452Q

Note:Auto-increment addresses which are not a simple increment are highlighted in bold. The auto-increment addressing is only enabled when

device registers are read using I2C burst-read mode. Therefore the internal storage of the auto-increment address is cleared whenever a

stop condition is detected.

6.1 Data registers

The following are the data registers for the MMA8452Q. For more information on data manipulation of the MMA8452Q, refer to

application note , AN4076.

CTRL_REG4(3)(4) R/W 0x2D 0x2E 00000000 0x00 Interrupt enable register

CTRL_REG5(3)(4) R/W 0x2E 0x2F 00000000 0x00 Interrupt pin (INT1/IN T2) map

OFF_X(3)(4) R/W 0x2F 0x30 00000000 0x00 X-axis offset adjust

OFF_Y(3)(4) R/W 0x30 0x31 00000000 0x00 Y-axis offset adjust

OFF_Z(3)(4) R/W 0x31 0x0D 00000000 0x00 Z-axis offset adjust

Reserved (do not modify) 0x40 – 7F — — — Reserved. Read return 0x00.

1. Register contents are reset when transition from standby to active mode occurs.

2. This register data is only valid in active mode.

3. Register contents are preserved when transition from active to standby mode occurs.

4. Modification of this register’s contents can only occur when device is standby mode except CTRL_REG1 active bit and CTRL_REG2 RST bit.

0x00: STATUS data status register (read only)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR

Table 12. STATUS description

Field Description

ZYXOW X, Y, Z-axis data overwrite. Default value: 0

0: No data overwrite has occurred

1: Previous X, Y, or Z data was overwritten by new X, Y, or Z data before it was read

ZOW Z-axis data overwrite. Default value: 0

0: No data overwrite has occurred

1: Previous Z-axis data was overwritten by new Z-axis data before it was read

YOW Y-axis data overwrite. Default value: 0

0: No data overwrite has occurred

1: Previous Y-axis data w as overwritten by new Y-axis data before it was read

XOW X-axis data overwrite. Default value: 0

0: No data overwrite has occurred

1: Previous X-axis data w as overwritten by new X-axis data before it was read

ZYXDR X, Y, Z-axis new data ready. Default value: 0

0: No new set of data ready

1: A new set of data is ready

ZDR Z-axis new data available. Default value: 0

0: No new Z-axis data is ready

1: A new Z-axis data is ready

YDR Y-axis new data available. Default value: 0

0: No n ew Y-axis data ready

1: A new Y -axis data is ready

XDR X-axis new data available. Default value: 0

0: No n ew X-axis data ready

1: A new X -axis data is ready

Table 11. Register address map (continued)

Name Type Register

address Auto-increment address Default Hex

value Comment

F_READ = 0 F_READ = 1