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FA5502P/M
FUJI Power Supply Control IC
Power Factor Correction
FA5502P/M
Application Note
June `02
Fuji Electric Co., Ltd.
Matsumoto Factor
y
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FA5502P/M
1.This Data Book contains the product specifications, characteristics, data, materials, and
structures as of June 2002. The contents are subject to change without notice for specification
changes or other reasons. When using a product listed in this Data Book, be sure to obtain the
latest specifications.
2. All applications described in this Data Book exemplify the use of Fuji's products for your
reference only. No right or license, either express or implied, under any patent, copyright, trade
secret or other intellectual property right owned by Fuji Electric Co., Ltd. is (or shall be deemed)
granted. Fuji makes no representation or warranty, whether express or implied, relating to the
infringement or alleged infringement of other's intellectual property rights which may arise from
the use of the applications described herein.
3. Although Fuji Electric is enhancing product quality and reliability, a small percentage of
semiconductor products may become faulty. When using Fuji Electric semiconductor products in
your equipment, you are requested to take adequate safety measures to prevent the equipment
from causing a physical injury, fire, or other problem if any of the products become faulty. It is
recommended to make your design fail-safe, flame retardant, and free of malfunction.
4.The products introduced in this Data Book are intended for use in the following electronic and
electrical equipment which has normal reliability requirements.
• Computers • OA equipment • Communications equipment (terminal devices)
• Measurement equipment • Machine tools • Audiovisual equipment
• Electrical home appliances • Personal equipment • Industrial robots, etc.
5.If you need to use a product in this Data Book for equipment requiring higher reliability than
normal, such as for the equipment listed below, it is imperative to contact Fuji Electric to obtain
prior approval. When using these products for such equipment, take adequate measures such
as a backup system to prevent the equipment from malfunctioning even if a Fuji's product
incorporated in the equipment becomes faulty.
• Transportation equipment (mounted on cars and ships) • Trunk communications equipment
• Traffic-signal control equipment • Gas leakage detectors with an auto-shut-off feature
• Emergency equipment for responding to disasters and anti-burglary devices • Safety devices
6. Do not use products in this Data Book for the equipment requiring strict reliability such as
(without limitation)
• Space equipment • Aeronautic equipment • Atomic control equipment
• Submarine repeater equipment • Medical equipment
7. Copyright © 1995 by Fuji Electric Co., Ltd. All rights reserved. No part of this Data Book may be
reproduced in any form or by any means without the express permission of Fuji Electric.
8. If you have any question about any portion in this Data Book, ask Fuji Electric or its sales
agents before using the product. Neither Fuji nor its agents shall be liable for any injury caused
by any use of the products not in accordance with instructions set forth herein.
WARNING
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FA5502P/M
CONTENTS
page
1. Description • • • • • • • • • • • • • • • 4
2. Features • • • • • • • • • • • • • • • 4
3. Outline • • • • • • • • • • • • • • • 4
4. Block diagram • • • • • • • • • • • • • • • 5
5. Pin assignment • • • • • • • • • • • • • • • 5
6. Ratings and characteristics • • • • • • • • • • • • • • • 6
7. Characteristic curves • • • • • • • • • • • • • • • 9
8. Description of each circuit • • • • • • • • • • • • • • • 13
9. Design advice • • • • • • • • • • • • • • • 18
10. Example of application circuit • • • • • • • • • • • • • • • 23
Note
• Parts tolerance and characteristics are not defined in all application described in this Data book. When design an
actual circuit for a product, you must determine parts tolerances and characteristics for safe and economical
operation.
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FA5502P/M
1. Description
FA5502P/M is a control IC for a power factor correction system. This IC uses a CMOS device with high dielectric
strength (30V) to implement low power consumption. This IC uses the average current control system to ensure stable
operation. With this system, a power factor of 99% or better can be achieved.
2. Features
• Low current consumption by CMOS process
• Stand-by : 3µA(max), Start-up : 30µA(max), Operating : 4mA(typ)
• Good regulation of PFC output voltage from no-load to full-load
• Drive circuit for connecting a power MOSFET(IOUT = ±1.5A)
• Pulse-by-pulse overcurrent and overvoltage limiting function
• ±2% accuracy reference voltage for setting DC output and overvoltage protection
• Output ON/OFF control function by external signal
• External synchronizing input pin for synchronous operation with other circuits
• Undervoltage lockout function (ON:16.5V, OFF:8.9V)
• 16-pin package (DIP/SOP)
3. Outline
DIP-16 (FA5502P) SOP-16 (FA5502M)
6.5 ± 0.2
0.3 ± 0.1
7.6 ± 0.2
4.0 ± 0.3
16
1
7.3 ± 0.5
1.5 ± 0.3
2.54 TYP 0.5 ± 0.1
3.4 ± 0.1
19.4 ± 0.3
9
8
17.78 ± 0.3
0º - 15º
0.75 ± 0.1
1.80 ± 0.05
5.3 ± 0.1
1.27
10º-0º
0.08
0.40 ± 0.05
0.10 ± 0.10 7.8 ± 0.2
10.2 ± 0.1
18
916
0.15 ± 0.05
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FA5502P/M
4. Block diagram
+
--
+
R
SQ
S
MUL
OCP.COMP
PWM.COMP
OVP.COMP
ER.AMP
CUR.AMP
OSC
UVLO REF
ON/OFF
IDET(16) IFB(1) IIN-(2) VDET(3)
OVP
(4)
VFB
(5)
VIN-
(6)
GND
(7)
OUT
(8)
VC
(9)
ON/OFF(12)
VCC(10)
REF(13)
CS(11)
CT(15)
SYNC
(14)
11µA
1.55V
1.64V
1.55V
11k
15k
4.85k
0.39V
5V
16.5V/8.9V
3.95V/
2.8V
5. Pin assignment
Pin No. Symbol Function Description
1 IFB Current error amplifier
output
Output of current error amplifier to connect
compensation network
2 IIN- Inverting input to current
error amplifier
Inverting input of current error amplifier to
connect compensation network
3 VDET Multiplier input Input of multiplier to detect sinusoidal
waveform
4 OVP Overvoltage protection
input
Input to overvoltage protection circuit
5 VFB Voltage error amplifier
output
Output of voltage error amplifier to connect
compensation network
6 VIN- Inverting input to voltage
error amplifier
Inverting input to voltage error amplifier to
detect PFC output voltage
7 GND Ground Ground
8 OUT Output Output for direct driving a power MOSFET
9 VC Power supply to output
circuit
Power supply to output circuit
10 VCC Power Supply Power supply for IC
11 CS Soft-start A pin to connect a capacitor for soft-start
12 ON/OFF Output ON/OFF control
input
Input of ON/OFF control circuit
13 REF Reference voltage Reference voltage output
14 SYNC Oscillator synchronization
input
Input of synchronization signal
15 CT Oscillator timing capacitor
and resistor
A pin to connect timing capacitor and
resistor to set oscillation frequency
16 IDET Non-inverting input to
current error amplifier
Input of inductor current signal
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FA5502P/M
6. Ratings and characteristics
The contents are subject to change without notice. When using a product, be sure to obtain the latest
specifications.
(1) Absolute maximum ratings
Item Symbol Rating Unit
VC pin VC Vcc V
VCC pin
Low impedance source
(Icc>15mA)
VCC1 30 V
Supply
Voltage
VCC pin
Internal zener clamp voltage
(Icc<15mA)
VCC2 Self Limiting V
Output peak current IOUT ±1.5 A
SYNC,VIN-,VDET and OVP pins
Input voltage
VSYNC
VVIN-
VVDET
VOVP
-0.3 to 5.0 V
IDET pin input voltage VIDET -10 to 5.0 V
ON/OFF pin input voltage VON/OFF -0.3 to Vcc V
REF pin source current IREF -10 mA
DIP-16 Pd 850 mW Power dissipation (Ta=25ºC)
SOP-16 650 mW
Ambiance temperature Ta -30 to +105 °C
Maximum junction temperature Tj +150 °C
Storage temperature Tstg -40 to +150 °C
Note) VC and ON/OFF pins voltage must be less than or equal to VCC pin voltage in all the conditions.
Peak current at OUT pin may flow to rated value neither according to supply voltage nor temperature conditions.
Maximum dissipation curve
-30 25 105 150
650mW(SOP)
850mW(DIP)
Maximum power
dissipation
Ambience temperature Ta(ºC)
(2) Recommended operating conditions
Item Symbol MIN TYP. MAX Unit
Supply voltage Vcc,Vc 10 28 V
IDET pin input voltage VIDET -1.0 0 V
VDET pin input voltage VVDET 0 2.4 V
VDET pin peak input voltage VPVDET 0.65 2.4 V
Oscillation frequency fOSC 15 150 kHz
Oscillation timing capacitance CT 330 1000 pF
Oscillation timing resistance RT 10 75 kΩ
Noise filter resistance connected to IDET
pin
Rn 0 27 Ω
REF-GND capacitance Cref 0.1 0.47 µF
Note) If the synchronous operation is not necessary, connect the SYNC pin to GND.
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FA5502P/M
(3) Electrical Characteristics (Unless otherwise specified, Vcc=Vc=18V, Ta=25°C, CT=470pF, RT=22kΩ)
Reference voltage section (REF pin)
Item Symbol Condition MIN TYP MAX Unit
Output voltage VREF 4.8 5 5.2 V
Line regulation Vrdv Vcc=10 to 28V ±25 mV
Load regulation Vrdi ILoad=0.1 to 2mA -50 -25 mV
Temperature stability VrdT Ta=-30 to 105°C ±0.5 mV/°C
Oscillator section (CT, SYNC pin)
Item Symbol Condition MIN TYP MAX Unit
Oscillation frequency fOSC CT=470pF,
RT=22kΩ, Ta=25°C 71 78 85 kHz
Voltage stability fdv Vcc=10 to 28V ±1 ±3 %
Temperature stability fdT Ta=-30 to +105°C ±0.04 ±0.07 %/°C
Output peak voltage VOSC 3.4 V
Synchronizing input
threshold voltage VTHSYNC SYNC pin voltage 1.0 1.5 2.0 V
SYNC pin input current ISYNC SYNC pin=2V 75 125
175 µA
Pulse width modulation cir cuit section (OUT pin)
Item Symbol Condition MIN TYP MAX Unit
Maximum duty cycle DMAX 91 94 97 %
Overcurrent limiter circuit section (IDET pin)
Item Symbol Condition MIN TYP MAX Unit
Input threshold voltage VTHOCP IDET pin voltage -1.20 -1.10 -1.00 V
Delay time TpdOCP 150 ns
Soft start circuit section (CS pin)
Item Symbol Condition MIN TYP MAX Unit
Charge current ICHG CS pin=0V -11 µA
VTHCS0 Dutycycle=0% 0.34 V
Input threshold voltage VTHCSM Dutycycle=DMAX 3.40 V
Output ON/OFF control circ uit section (ON/ OFF pin)
Item Symbol Condition MIN TYP MAX Unit
On-state input current ITHON ON/OFF pin=VTHON ±500 nA
VTHON OFF→ON 3.55 3.95 4.35 V
ON/OFF control
threshold voltage VTHOFF ON→OFF 2.40 2.80 3.20 V
Voltage error amplifier secti on (VIN- , VFB pin)
Item Symbol Condition MIN TYP MAX Unit
Reference voltage Vr 1.519 1.550 1.581 V
Line regulation Vredv Vcc=10 to 28V ±0.5 mV
Temperature stability VredT Ta=-30 to 105°C ±0.2 mV/°C
Input bias current IBE ±500 nA
Open loop gain Ave 60 dB
VOE+ No load 3.7 4.1 V
Output voltage VOE- No load 50 200 mV
Output source current IOE+ VFB pin=0V -2.8 mA
Output sink current IOE- VFB pin=2V 280 µA
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FA5502P/M
Current error amplifier section (IIN-, IFB, IDET p in)
Item Symbol Condition MIN TYP MAX Unit
Input threshold voltage VTHIDET
VDET pin=0V
VFB pin=Vr
Rn=30Ω
-50 0 50 mV
Input bias current IBC IDET pin=0V -350 -250 -150 µA
Open loop gain Avc 60 dB
VOC+ No load 3.55 3.8 V
Output voltage VOC- No load 50 200 mV
Output source current IOC+ IFB pin=0V -5.1 mA
Output sink current IOC- IFB pin=2V 800 µA
Multiplier section (VDET, IIN-, VFB pin)
Item Symbol Condition MIN TYP MAX Unit
VDET pin input voltage VMVDET 0 2.4 V
VFB pin input voltage VMVFB 1.5 3.5 V
Input bias current IBVDET VDET pin=0V -1.5 -0.5 µA
Output current IM IIN- pin=0V -44 µA
Output voltage factor K -1.2 -
Overvoltage protection circuit section (OVP pin)
Item Symbol Condition MIN TYP MAX Unit
Input threshold voltage VTHOVP OVP pin voltage 1.607 1.640 1.673 V
VTHOVP/Vr ratio α 1.037 1.058 1.079 -
Input bias current IBOVP OVP pin=0V -1.0 -0.3 µA
Delay time Tpdovp 150 ns
Undervoltage lockout circui t section (VCC pin )
Item Symbol Condition MIN TYP MAX Unit
Start-up threshold
voltage VTHUON 15.5 16.5 17.5 V
Shutdown threshold
voltage VTHUOFF 8.2 8.9 9.6 V
Hysteresis voltage VUHYS 6.8 7.6 8.4 V
Output circuit section ( OUT, VC pin)
Item Symbol Condition MIN TYP MAX Unit
Low output voltage VOL I
OL=100mA 0.5 1.0 V
High output voltage VOH IOH=-100mA,
Vcc=18V 15.5 16.5 V
Rise time tr No load 50 ns
Fall time tf No load 50 ns
Power supply current (VCC pin)
Item Symbol Condition MIN TYP MAX Unit
Stand-by current ICCST Vcc=14V 3 µA
Starting-up current ICCSTA Vcc=start threshold 10 30 µA
Operating-state supply
current ICCOP No load 4 6 mA
OFF-state supply current ICCOFF ON/OFF pin=0V 80 200 µA
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FA5502P/M
7. Characteristic curves
(Unless otherwise specified, Vcc=Vc=18V, Ta=25°C, CT=470pF, RT=22kΩ)
Oscillation frequency (fosc) vs.
timing resistor (R
T
)
10
100
10 100
R
T
fosc(kHz)
C
T
=1000pF
C
T
=680pF
C
T
=470pF
C
T
=330pF
)k( Ω
Oscillation frequency(fosc) vs.
junction temperature(Tj)
75
76
77
78
79
80
-50050100150
Tj (°C)
fosc (kHz)
Maximum duty cycle(DMA X) vs.
Junction temperature(Tj)
90
91
92
93
94
95
-50050100150
Tj (°C)
DMAX (%)
Oscillation frequency(fosc) vs.
supply voltage(Vcc)
77.4
77.6
77.8
78.0
78.2
78.4
10 15 20 25 30
Vcc (V)
fosc (kHz)
Maximum duty cycle(DMA X) vs.
timing resistor(RT)
84
86
88
90
92
94
96
98
100
10 100
RT (kΩ)
DMAX (%)
CT=330pF
to 1000pF
Output duty cycle(D) vs.
CS pin voltage(VCS)
0
10
20
30
40
50
60
70
80
90
100
012345
VCS (V)
D (%)
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FA5502P/M
Multiplier input voltage(VVDET
) vs.
output voltage(VIIN- )
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0123
VVDET (V)
VIIN-
(V)
VVFB=1.7V
VVFB=1.9V
VVFB=1.5V
VVFB=2.1V
VVFB=1.1V VVFB=0.5V
VVFB=2.4V
VVFB=2.9V
1.544
1.546
1.548
1.550
1.552
1.554
10 15 20 25 30
Vcc (V)
Vr (V)
Voltage error amplifier
reference voltage(Vr) vs. supply voltage(Vcc)
OVP input threshold voltage(VTHOVP) vs.
junction temperature(Tj)
1.61
1.62
1.63
1.64
1.65
1.66
-50 0 50 100 150
Tj (°C)
VTHOVP
(V)
IDET pin voltage(VIDET) vs.
IIN- pin voltage(VIIN- )
-1.5
-1.0
-0.5
0.0
00.5 11.5
VIIN- (V)
VIDET
(V)
(Normal operation)
1.52
1.53
1.54
1.55
1.56
-50050100150
Tj (°C)
Vr (V)
Voltage error amplifier
reference voltage(Vr) vs. junction temperature(Tj)
OCP input threshold voltage(VTHOCP) vs.
junction temperature(Tj)
-1.12
-1.11
-1.10
-1.09
-1.08
-1.07
-50 0 50 100 150
Tj (°C)
VTHOCP
(V)
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FA5502P/M
2.0
2.5
3.0
3.5
4.0
4.5
-50 0 50 100 150
Tj (°C)
VTHON
(V)
ON/OFF control circuit
ON threshold voltage(VTHON) vs.
junction temperature(Tj)
L-level output voltage(VOL) vs.
supply voltage(Vcc)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
10 15 20 25 30
Vcc (V)
VOL (V)
IOL=100mA
16.0
16.2
16.4
16.6
16.8
17.0
-50 0 50 100 150
Tj (°C)
VTHUON
(V)
UVLO startup threshold voltage(VTHUON) vs.
junction temperature(Tj)
1.0
1.5
2.0
2.5
3.0
3.5
-50 0 50 100 150
Tj (°C)
VTHOFF
(V)
ON/OFF control circuit
OFF threshold voltage(VTHOFF) vs.
junction temperature(Tj)
H-level output voltage(VOH) vs.
supply voltage(Vcc)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
10 15 20 25 30
Vcc (V)
Vcc-VOH
(V)
IOH=-100mA
8.80
8.85
8.90
8.95
9.00
-50 0 50 100 150
Tj (°C)
VTHUOFF
(V)
UVLO shutdown threshold voltage(VTHUOFF) vs.
junction temperature(Tj)
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FA5502P/M
Supply current(Icc) vs. supply voltage(Vcc)
0
2
4
6
8
10
12
14
16
0 10203040
Vcc (V)
Icc (mA)
ON/OFF pin:
pull up to Vcc
Operating-state supply current(Iccop) vs.
junction temperature(Tj)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-50 0 50 100 150
Tj (°C)
Iccop (mA)
OFF-state supply current(ICCOFF) vs.
supply voltage(Vcc)
0
100
200
300
400
500
600
700
10 15 20 25 30
Vcc (V)
ICCOFF
(µA)
Supply current(Icc) vs. supply voltage(Vcc)
(enlarged)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 10203040
Vcc (V)
Icc (mA)
ON/OFF pin:
pull up to Vcc
OFF-state supply current(ICCOFF) vs.
supply voltage(Vcc) (enlarged)
0
50
100
150
200
250
10 15 20 25 30
Vcc (V)
ICCOFF
(µA)
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FA5502P/M
8. Description of each circuit
(1) Oscillator section
The oscillator generates sawtooth waveform
between 0.3V and 3.4V by charging and discharging
capacitor. Fig.1 shows the connection. The oscillation
frequency is determined by CT and RT.
(see characteristics curve).
The oscillator waveform is input to the PWM
comparator. The oscillator is also used for determining
the maximum duty cycle of output pulses. Concretely,
a signal is sent to the output circuit section and the
OUT pin is forced to be Low level during the CT
discharge period (fall time of CT pin voltage).
13
15
REF
CT OSC
RT
CT
t
3.4V
0.3V
CT pin voltage
0
Dmax Dead time
Fig.1 Oscillator circuit
SYNC pin (pin 14) is a synchronizing signal input pin.
It is usable for synchronized operation. When it is
desired to adopt synchronized operation, the
free-running frequency (determined by CT and RT)
must be set about 10% lower than that of external
synchronizing signal.
The input resistance in SYNC pin is approximately
16kΩ. Usually, a square-wave synchronizing signal is
differentiated by R and C, and the voltage input to
SYNC pin is so arranged to be below 1V within CT
discharge period. Concretely, the waveform must
satisfy the condition in Fig.3.
Depending on the amplitude, etc. of square-wave
signal used as external synchronizing signal, the RC
differentiating circuit shown in Fig.2 could not generate
a waveform in Fig.3. In such a case, add a resistor
between SYNC pin and GND so as to clear the
condition in Fig.3.
Fig.5 shows timing chart of synchronized operation.
Note that diode D2 in Fig.2 is required so that no
negative voltage will be applied to SYNC pin while in
the discharge period of capacitor Csy in the
differentiating circuit. Considering the rated voltage of
SYNC pin, use a Schottky diode of a low forward
voltage.
Unless the external synchronization function is used,
connect SYNC pin to GND pin to avoid a malfunction.
14
SYNC
OSC
16k
synchronizing
signal
D2
CsyRsy
SYNC pin
signal
V
SYNC
=1.5V(typ)
Fig.2 SYNC pin circuit (1 )
less than 200ns
more than 50ns2V
1V
less
than
5V
t
SYNC pin voltage
0
SYNC pin voltage waveform
Fig.3 Condition for SYN C pi n signal
14
SYNC
OSC
16k
synchronizing
signal
Rsy Csy
R14
D2
Fig.4 SYNC pin circuit (2 )
CT pin voltage
Synchronizing
signal
SYNC pin
voltage
OUT pin
voltage
t
t
t
t
Fig.5 Timing chart of synchronized operati on
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FA5502P/M
(2) Voltage error amplifier and overvoltage
limit in g c i rc u it
ER.AMP is an error amplifier which constitutes a
voltage feedback loop for keeping the output voltage
constant. The non-inverting input is internally
connected to reference voltage Vr of 1.55V (typ.).
Fig.6 shows the connection. The output voltage is
determined by:
Vr
1R
2R1R
VO×
+
=• • • • • (1)
The error amplifier output is pinned out at VFB pin
(pin 5). Between VFB pin and VIN- pin, RC network
are connected for loop compensation. The voltage
gain Av is expressed by
()
4R1Cj13R
4R
AV×ω+
= • • • • • (2)
Cutoff frequency fc is expressed by:
4R1C2
1
fC×π
= • • • • • (3)
If 100Hz or 120Hz ripples appear at the error
amplifier output, the PFC converter will not operate
stably. Therefore, determine C1 and R4 so that voltage
gain Av at 100 Hz or 120 Hz will be small enough. Also
set fc to approximately 1Hz to ensure a stable
operation. Practically, the optimum value should be
determined by evaluation in the actual circuit.
To limit the output voltage when it has risen above
the normal voltage, overvoltage limiting comparator
OVP.COMP is incorporated. Its threshold voltage Vp is
as follows:
VrVP×α= (α=1.058(typ)) • • • • • (4)
According to the connection in Fig.6, therefore, the
output overvoltage is limited to 1.058 times (typ.) the
normal output voltage.
5
6
4
Vo
VFB
VIN-
OVP
R4
C1
R3
R2
R1
MUL
F.F.
Vr
=1.55V(typ.)
Vp
=1.058Vr(typ.)
ER.AMP
OVP.COMP
Fig.6 Voltage error amplifier and overvoltage limiting
circuit
(3) Current error amplifier and overcurrent
limiter circ u it
CUR.AMP is an error amplifier which constitutes a
current loop to control the line current to a sinusoidal
waveform. As shown in Fig.7, to IIN- pin (pin 2), a
multiplier output is connected via resistor RA as a
current reference signal. Inductor current is monitored
by IDET pin (pin 16). The IDET pin should be used
within the voltage range from 0V to –1.0V in normal
operation. RC network for loop compensation is
connected between IFB pin and IIN- pin. According to
the circuit in Fig.7, the characteristics of voltage gain
AV are as shown in Fig.8. Where,
3C5R2
1
Z×π
= • • • • • (5)
C5R2
1
P×π
= 3C2C
3C2C
C+
×
= • • • • • (6)
Voltage gain (G1) between Z and P (gain between
IDET pin and IFB pin) in Fig.8 is:
+= 1
RA
5R
75.0log201G • • • • • (7)
Select C2 and C3 so that P/Z will be about 10 for
adequate phase margin. The output of current error
amplifier is input to PWM comparator.
The optimum value of loop compensation should be
determined by evaluation in actual circuit referring to
application circuit, etc.
To limit the overcurrent, overcurrent limiting
comparator OCP.COMP is provided. The threshold
voltage at IDET pin is -1.10V (typ.). If a noise is picked
up at IDET pin, suppress it by connecting Rn and Cn.
Rn must be lower than 27 Ω.
1
2
16
IFB
IIN-
IDET
R5
C2
C3
PWM
comparator
F.F.
0.39V
MUL
RC RB
4.85k 15k
REF
5V
RA
11k
Cn
Rn
currnet
detection
CUR.AMP
OCP.COMP
Vm
Fig.7 Current error amplifier and overcurrent limiting
circuit
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FA5502P/M
ZP
frequency
voltage gain[dB]
G1
Fig.8 Voltage gain of CUR. AMP
(4) PWM comparator
Fig.9 shows the configuration of PWM comparator.
Oscillator output VCT and current error amplifier output
VIFB are compared. While VCT < VIFB, PWM
comparator output goes High and OUT pin also goes
High. Note that, during the oscillator discharge period,
OUT pin is forced to be Low, thereby determining the
maximum duty cycle. (see characteristics curve).
CS pin (pin 11) is a soft start pin. When start up, an
internal constant current (11µA (typ.)) charges
capacitor C4 for soft start. Priority is given to VCS or
VIFB whichever is lower. Fig.10 shows PWM
comparator timing chart.
11
11µA
CS
Oscillator output
(CT pin)
CUR.AMP output
(IFB pin)
C4
Output
circuit
V
CT
V
IFB
V
CS
PWM.COMP
7.5V
Fig.9 PWM comparator circuit
V
CT
V
CS
V
IFB
OUT
pin
Normal operation
t
t
V
CT
V
CS
V
IFB
OUT
pin
Operation with Dmax
t
t
Fig.10 PWM comparator timing chart
(5) Mu ltip lier
The multiplier generates a current reference signal.
The rectified line voltage is divided down by resistor
and monitored by VDET pin (pin 3). Considering the
dynamic range of multiplier, design the R6 and R7 in
Fig.11 so that the peak voltage at VDET pin within a
range from 0.65V to 2.4V over the entire range of line
voltage. VFB pin is normally above 1.55V and, at this
status, multiplier output voltage Vm is approximately
expressed by:
VDETVFB V)55.1V(K25.1Vm ×−×−= • • • • • (8)
Where
K: Output voltage factor (multiplier section)
When VFB pin is lower than 1.55V, compensation
circuit for light load operates.
As shown in Fig.7, Vm is applied via a resistor of
11 kΩ to inverting input (IIN-) of current error amplifier
CUR. AMP. (For input/output characteristics of
multiplier, see characteristics curve.)
ER.AMP output
(VFB pin)
MUL
3
V
VFB
V
VDET
VDET
Vm
V
IN
R7
R6
Fig.11 Multiplier circuit
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(6) ON/OFF control circuit
Fig.12 shows the configuration of the ON/OFF
control circuit. The ON/OFF control circuit consists of a
comparator with hysteresis. To turn the IC from OFF
mode to operating mode, pull up the ON/OFF pin
voltage to 3.95V (typ.) or higher. On the other hand, to
turn the IC from operating mode to OFF mode, pull
down the ON/OFF pin to 2.80V (typ.) or lower.
In the OFF mode, the reference (REF) voltage is cut
off, and the CS pin and OUT pin go approximately 0V.
IC consumption current during OFF mode is 200µA
(max.) which is much smaller than at an operating
mode.
The input current at ON/OFF pin is a very small
value of 500nA.
In the case that external signal is applied to ON/OFF
pin, the ON/OFF pin voltage must not exceed the VCC
pin voltage, even when start up or stop operation.
If ON/OFF operation is not made by external signal,
the ON/OFF pin is normally pulled up to Vcc pin
through 10kΩ to 1MΩ. Then ON/OFF pin voltage goes
to approximately Vcc voltage.
12
REF circuit
Output circuit
ON/OFF
3.95/2.80V
Fig.12 ON/OFF control circ uit
(7) Output circu it
As shown in Fig.13, VC pin (pin 9) is configured as
the high power terminal, independent of the IC power
terminal (VCC pin). This pin allows an independent
drive resistance when the power MOSFET is ON and
OFF. Suppose the drive resistance when ON and OFF
are Rg (on) and Rg (off),
Rg(on)=Rg1+Rg2 • • • • • (9)
Rg(off)=Rg2 • • • • • (10)
At standby, the OUT pin is kept Low.
If the drain voltage of power MOSFET oscillates, a
parasitic capacitance between gate and drain may
swing the OUT pin (pin 8) of IC below 0V. If OUT pin
voltage falls below -0.3V, a current may flow to the
parasitic element in IC, whereby the IC may
malfunction. In such a case, Schottky diode must be
connected between OUT pin and GND so as not to
allow a parasitic current to flow to IC.
If VC pin is fed with a source which is independent
of VCC pin, the voltage of VC pin must not exceed that
of VCC pin even start up or stop operation.
8
9
7
10
Rg1 C5
Rg2
Shottky
diode
GND
OUT
VC
VCC
Fig.13 Output circuit
(8) Undervoltage lockout circuit
This IC contains an undervoltage lockout circuit to
prevent malfunction when the Vcc voltage drops.
When the Vcc voltage rises from 0V, this IC starts
operation at 16.5V (typ.). If the Vcc voltage drops after
the IC starts up, this IC stops operation at 8.9V(typ.).
When IC stops operation by undervoltage lockout
circuit, OUT pin and CS pin is kept low
(9) Compensation circuit for light load
If the output of multiplier and the input of current
error amplifier do not have offset voltage, the input
current to the converter is approximately zero under
condition that the PFC converter operates in no load.
But an actual multiplier and current error amplifier may
have offset voltage. If the offset voltage is negative,
the input current, which corresponds to the offset
voltage, flows into the converter even when the PFC
converter operates in no load. In this case, the PFC
output voltage rises abnormally because of too much
input current.
To avoid these, this IC has an automatic offset
correction circuit for light load. The output voltage of
error amplifier is approximately 1.55V or higher in
normal operation.
If the output voltage drops below 1.55V, this circuit
operates. If there is a negative offset voltage, the
output voltage of error amplifier falls below 1.55V in
the case that the PFC converter operates in no load or
light load. Then, the offset voltage is corrected in the
multiplier circuit. Because of this operation, even
under no load or light load, the PFC output voltage
does not rise abnormally, but is always kept stable.
The amount of correction changes linearly according
to the output of error amplifier, which can make
operation stable.
Fig.14 shows the outline of the effect of this circuit.
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FA5502P/M
full load
no-load
AC line current
offset current
0t
1/2 of line frequency
Without compensation
1/2 of line frequency
full load
no-load
result of compensation
0t
With compensation
AC line current
0
PFC output voltage
PFC output power
Without compensation
With compensation
Fig.14 Operation outline of compensation circuit
for light load
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FA5502P/M
9. Design advice
(1) Vcc circui t
Vcc voltage can be supplied from an auxiliary
winding of the inductor. An example circuit is shown in
Fig.15.
FA5502
10
7
GND
VCC
Rs
R8
L
(sub)
D3 Q1
D1
Co
C5
Vac
Fig.15 Vcc circuit (1)
In this circuit, R8 is a start up resistor. The start up
resistor R8 should be satisfied the following formula in
order to supply with at least 30µA of IC start up
current.
6
1030
5.17(min)Vac2
8R −
×−×
< • • • • • (11)
Note that this formula is a minimum condition for
starting the IC. Practically, determine the value upon
taking into account the start up time required for
converter. The start up time must be determined upon
measurement at actual circuit operation.
In steady state, Vcc is supplied from the auxiliary
winding (sub) of inductor. When the IC is just starting
up, however, it takes time for the voltage from auxiliary
winding to rise enough. The value of capacitor C5
connected to Vcc pin should be determined to prevent
Vcc from falling below the OFF threshold voltage of
UVLO during this period. The capacity of C5 should be
determined by evaluation in the actual circuit because
the time lag is different in each circuit.
UVLO
ON
UVLO
OFF
Auxiliary winding voltage
Vcc
t
Vcc must not drop
below UVLO OFF.
Fig.16 Vcc voltage at start up
Even after PFC starts up, Vcc may fall due to step
changes of the load or inputs. To prevent the IC from
stopping in those cases, the circuit shown in Fig.17 is
effective to prolong the hold time of the Vcc voltage.
After the PFC converter starts up, Vcc is supplied
through C6. Therefore, you can prolong the hold time
of Vcc by using a large capacity for C6.
R8
D3 D4
C5 C6 sub
VCC
Fig.17 Vcc circuit (2)
In some case, the Vcc voltage cannot be supplied
enough in light load condition. In this case, the circuit
shown in Fig.18 may be effective to improve the Vcc.
The appropriate value of C7 and R9 should be
determined by evaluation in actual circuit because
they depend on each circuit.
R8
D3
D5
C5
C7
sub
VCC R9
Fig.18 Vcc circuit (3)
(2) Supplying Vcc from external power supply
If Vcc is not supplied from the auxiliary winding of
inductor but from an external power supply, pay
attention to the followings.
• In order to start up the IC, Vcc must be above the ON
threshold voltage VTHUON (17.5V (max.)) of
undervoltage lockout circuit (UVLO). When starting
up, apply at least this VTHUON. After starting up,
the operation is available within the recommended
range of 10 to 28V.
• If a noise is applied to Vcc pin, it may cause
malfunction. To avoid a noise, connect a capacitor
near VCC pin even when Vcc is supplied from an
external power supply. To prevent a malfunction,
suppress the noise below about ±0.6V. And, make
sure there is no malfunction attributable to noise.
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FA5502P/M
(3) Designing a boost converter
Fig.19 shows a basic circuit of boost converter used
as an PFC converter. The following describes how to
determine each values of the circuit.
LD
QCo Vo
Vin
Rs
Fig.19 Boost converter ci rc uit
(3-1) Output voltage
Set the output voltage of boost converter at least
10V higher than the peak value of maximum input
voltage to ensure a stable operation. When it is used
as PFC converter, the input voltage has a sinusoidal
waveform. Therefore, set the output voltage Vo by:
]Vrms[voltageinputACMaximu:Vin
]V[10Vin2Vo
(max)
(max) +×≥ • • (12)
(3-2) Inductor
When PFC converter operates in the continuous
current mode, select an approximate inductance
considering the ratio of inductor ripple current to the
peak input current by:
(
)
VoPinfs
Vin2VoVin
L
2
×××γ ×−
≥ • • • • • (13)
Where,
Vin: AC input voltage [Vrms]
γ: Ratio of ripple content to peak input current.
(Set to approx. 0.2, see Fig.20)
fs: Switching frequency [Hz]
Pin: Maximum input power [W]
Ir
Iac(peak)
Inductor current
t
line current
)peak(Iac/Ir=γ
Fig.20 Outline of inductor a nd AC line current
(3-3) Current detecting resistance Rs
Rs is a resistor which allows to detect an inductor
current to control the line current into sinusoidal.
Because the threshold voltage for overcurrent limiting
circuit is -1.1V (typ.), peak inductor current limit Ip is
calculated by:
]A[
R
1.1
Ip
S
= • • • • • (14)
So that the voltage inputted to IDET pin will not be
beyond -1V, whereby the overcurrent limiting circuit
will not operate at a normal operation, calculate Rs by:
][
Pin2
Vin
R
(max)
(min)
SΩ
×
≤ • • • • • (15)
Where,
Vin (min): Minimum AC input voltage [Vrms]
Pin (max): Maximum input position [W]
As a matter of fact, the peak current changes with
switching ripple current contained in the inductor
current, circuit efficiency, etc. Definitely determine it by
evaluation on a actual circuit.
(3-4) Smoothing capacitor
PFC converter output contains ripple voltage of
twice the line frequency as shown in Fig.21.
Instantaneous value Vo(t) of output voltage is
approximated by:
)t2sin(
Co2
Io
Vo)t(Vo 0
0
×ω×
×ω
−= • • • • • (16)
Where,
Io: Output current [A]
ω0 = 2πf0 (f0: AC line frequency [Hz])
Co: Output smoothing capacitance [F]
Therefore, output ripple voltage Vrp (p-p) is:
Co
Io
Vrp
0×ω
= • • • • • (17)
Using formula (17), determine the necessary value.
The overvoltage limiting circuit of FA5502 monitors the
instantaneous output voltage. Therefore, determine
the capacitance of smoothing capacitor Co so that the
instantaneous output voltage including the ripple at a
normal operation will not reach the overvoltage limit.
2xfac
V
rp
Vo
Fig.21 Output ripple voltage
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FA5502P/M
(4) Outpu t over voltag e a t ligh t load
A compensation circuit for light load is incorporated
for preventing an overvoltage when light or no load.
Though, according to the condition, this circuit may not
compensate enough and overvoltage may occur. To
prevent overvoltage, the following condition must be
satisfied.
- Noise filter resistor Rn connected to IDET pin (pin
16) must be below 27Ω.
- As shown in Fig.22, DC gain limiting resistor R10
for current error amplifier must not be connected
between IFB pin (pin 1) and IIN- pin (pin 2).
2
1
IIN-
IFB
FA5502
C2R5
C3
R10
Fig.22 Prevention of overvoltage at light l oad
(5) Notes for setting the output voltage and
overvoltage limit
In the actual circuit, the output voltage drops
depending on the line voltage or load current.
Therefore, the output voltage may be lower than the
voltage calculated by expression (1) in "8-(2)". When
setting the output voltage, sufficiently evaluate it on an
actual circuit.
On the circuit shown in Fig.6 in "8-(2)", the
overvoltage setting is fixed at 1.058 times the output
voltage setting.
For setting the overvoltage independently of the
output voltage setting, connect voltage divider
additionally to OVP pin as shown in Fig.23.
On the circuit in Fig.23, even if the voltage divider
for setting the output voltage has troubled, the
overvoltage limiting circuit operates properly, thereby
preventing the output voltage from rising excessively.
5
6
4
Vo
VFB
VIN-
OVP
R4
C1
R3
R2
R1
MUL
F.F.
Vr
=1.55V(typ.)
Vp
=1.058Vr(typ.)
R12
R11
OVP.COMP
ER.AMP
Fig.23 Independent setting of OVP limit
(6) Improvement of out put voltage regulation
As stated in “9-(5)”, the output voltage may change
with input voltage or load current on the circuit in Fig.6
in "8-(2)", thereby causing a problem in some case. In
such a case, the circuit in Fig.24 may improve the
regulation.
5
6
Vo
VFB
VIN-
R3
R2
R1
MUL
Vr
=1.55V(typ.)
C9
R13
C8
Fig.24 ER.AMP circuit for i mprovement of regulation
Voltage gainAv2 of this circuit is expressed by:
3R)13R9C8Cj)9C8C((j
13R9Cj1
A2V ××ω++ω ×ω+
= • • • (18)
Optimum values depend on an each circuit.
Referring the following relations or the example
applied to “10 Example of application circuit”, adjust
the values on actual circuit.
- Set the voltage gain Av2 at 100 or 120 Hz almost
the same as before changing the compensation
circuit.
- Determine C8, C9 and R13 so as to satisfy the
following relations.
• Set fz determined by the following expression to
several Hz to several ten Hz.
13R9C2
1
fZ×π
= • • • • • (19)
• Set fp determined by the following expression so
that the fp/fz ratio is about 10.
9C8C
9C8C
C
13RC2
1
fp +
×
=
×π
=• • • • • (20)
*Example of values applied to “10 Example of
application circuit”
C8=0.033µF, C9=0.15µF,
R13=330kΩ, R3=100kΩ
(These values are given as references and not
intended for guaranteeing the operation in any
circuit.)
In this circuit, not only the output voltage
characteristics at a steady status but also transient
response to line voltage and load current may change.
Before determining the circuit values, evaluate
sufficiently.
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FA5502P/M
(7) Prevent ion of intermittent sw itching of low
frequency
An intermittent switching below 10 Hz may occur in
some application. It may be avoided by the following
methods. They are given as typical preventions of
intermittent switching and may not be effective for
certain circuits. They may also affect the
characteristics of PFC converter. Sufficiently check the
operation on a actual circuit.
(7-1) Lowering the dc gain of voltage er ror amplifier
Lower the dc gain of the voltage error amplifier.
Concretely, reduce the resistance of R4 on the circuit
in Fig.6 in "8-(2)". Note that, in this case, the line and
load regulation will be lowerd.
(7-2) Connection of Rofst
Adjust the offset of the current error amplifier.
Concretely, connect a resistor Rofst of 1MΩ or higher
between REF pin and IIN- pin as shown in Fig.25.
Note that, in this case, the input current will be
distorted and the power factor will be slightly lowered.
13
2
1
REF
IIN-
IFB
FA5502
Rofst
R5
C3
C2
Fig.25 Connection of Rofst
(7-3) Change of compensation network of voltage
error amplifie r
Replace the compensation network connected to the
voltage error amplifier with the circuit in Fig.24 in
"9-(6)”. Note that, in this case, the transient response
may be different from that before the change.
(8) Improvement of operation around zero
crossing
In some application, surge current may appear on
the line current around zero crossing. This surge
current may cause harmonic current especially in high
order. In such a case, the following method may
suppress this surge current.
(8-1) Connection of Rofst
As shown in Fig.25, connect resistor Rofst between
REF pin and IIN- pin. Use a resistor of about 1MΩ or
higher.
(8-2) Increase of Dmax
Increase the maximum duty cycle. Concretely, select
such a network of RT and CT for the same frequency
that CT is a smaller and RT a larger.
(See (9) Oscillator setting and maximum duty cycle.)
(9) Oscillator setting and maximum duty
cycle
The maximum duty cycle is determined by forcing
the OUT pin to be Low during the oscillator discharge
period. The oscillator discharge period changes with
RT and CT connected to CT pin. On a network of CT
and RT providing the same oscillation frequency, the
discharge period shortens and the maximum duty
cycle increases by minimizing CT and maximizing RT.
(See characteristics curve.) The maximum duty cycle
may affect the input current waveform, particularly at
zero crossing. Therefore, sufficiently test CT and RT
before determining them. Too small CT could not give
a stable oscillation on account of noise, etc. It should
be 330pF or more according to the recommended
condition.
(10) Npte in use of SYNC pin
If the external synchronizing signal is not a square
waveform or if has a trapezoid shape, a differentiating
circuit of RC network may not satisfy the waveform
condition shown in Fig.3 in “8-(1)”. In such a case,
convert the external synchronizing signal into a square
waveform by means of comparator or the like before
inputting it to a differentiating circuit of RC network.
(See "8-(1) Oscillator section".)
(11) Prevention of malfunction by noise
Noise applied to each pin may cause malfunction of
IC. If noise causes malfunction, see the notes
summarized below and confirm in actual circuit to
prevent malfunction.
Capacitor for noise suppressing should be
connected as close to IC as possible so as to
suppress noise effectively.
(11-1) REF pin
REF pin voltage is supplied to each components of
IC as voltage source and reference voltage. A noise
applied to this pin may cause a malfunction of IC. To
suppress a malfunction by noise, connect a capacitor
of 0.1 µF or more between REF pin and GND.
(11-2) IDET pin
If a noise is applied to IDET pin which detects
induvtor current, the overcurrent limiting circuit may
suffer from a malfunction. In such a case, insert an RC
filter at IDET pin.
(11-3) OVP pin
If a noise applied to OVP pin causes a malfunction,
connect a noise suppressing capacitor between OVP
and GND pins.
(11-4) CT pin
A noise applied to CT pin, which is an oscillator
output, may disturb the oscillation frequency or OUT
pulses. The wiring between oscillator timing capacitor
CT and IC must be as short as possible so as to
suppress the noise to CT pin. Pay utmost attention to
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FA5502P/M
GND wiring so as not to generate a common
impedance with other wires.
(11-5) VCC pin
A noise applied to VCC pin may cause a malfunction.
To suppress this noise, connect a capacitor near VCC
pin even if IC is energized by another power supply.
Determine the capacitance so that the noise generated
at VCC pin will be within about ±0.6V . Then, make
sure no malfunction occurs by noise.
(12) Vo ltage rating of IDET pin
The voltage rating of IDET pin, which monitors an
inductor current, is -10V. In case of a general boost
circuit, a inrush current for charging the output
smoothing capacitor Co flows at the instant when an
AC input voltage is connected. This current may be by
far greater than the input current at a normal operation.
As a result, a voltage much higher than normal may be
applied to IDET pin. Pay attention so that a voltage
beyond the maximum voltage rating of -10V will not be
applied to IDET pin even at an instant when an AC
input voltage has been connected. If there are cases
where a voltage higher than rating is applied to IDET
pin, insert a limiting circuit for inrush current, or add a
Zener diode as shown in Fig.26 or 27 to suppress the
voltage applied to IDET pin.
LD
Q
Rs
7
16
IDET
GND
ZD
Rn
Cn
FA5502
Co
Fig.26 IDET pin protec tion (1)
LD
Q
Rs
7
16
IDET
GND
ZD
Rn
Cn
FA5502
Co
Fig.27 IDET pin protec tion (2)
(13) Prevention of malfunction by negative
voltage of each pin
IDET pin is so designed as to input a negative
voltage. In the case of other pins, however, if large
negative voltage is applied, parasitic elements in IC
may operate and it may cause a malfunction. Pay
attention so that the voltage applied to pins other than
IDET pin will not be lower than -0.3V.
23
Q
ualit
y
is our messa
g
e
Q
ualit
y
is our messa
g
e
Q
ualit
y
is our messa
g
e
Q
ualit
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is our messa
g
e
FA5502P/M
10. Example of application circui t
IDET CT SYNC REF ON/OFF CS VCC VC
IFB IIN- VDET OVP VFB VIN- GND OUT
FA5502
F1
L2
C11
D2-D5
R8
R7
C12
L1
Rs
R25
Cn Rn
C
T
R
T
C
REF
C4
Rg1
Cv
R3
R4
C1
C2
R5
C3
R6
Rg2
D6
Q1
D1
C13
R9 R16
R2 R17
R1 R18
5A
0.1µF 240k
0.22
1mH
4.7
ERA81-004
2SK3520
220µ
YG962S6
270k
240k
220k
150k
100µ
2k1.5k
33k
470k0.15µ
68p
10k
470p
2.7k
0.01µ 27
330p
22k
0.1µ
0.15µ
390
100k
240k
0.47µ
ERD03-06
AC IN
85 - 264V
ON/OFF
Vcc
18V
Vout
385V
200W
0V
GND
C5
0.022µ
Note
This application circuit exemplifies the use of IC for your reference only. Parts tolerance, parts characteristics,
influence of noise, etc. are not defined in this application circuit. When design an actual circuit for a product, you must
determine parts tolerance, parts characteristics, influence of noise, etc. for safe and economical operation. Neither Fuji
nor its agents shall be liable for any injury caused by any use of this circuit.
