1
FEATURES APPLICATIONS
DESCRIPTION
Analog Input (L)
Analog Input (R) Analog Front-End Delta-Sigma
Modulator
Digital
Decimation
Filter
Serial Interface
and
Format Control
Digital Output
Mode/Format Control
System Clock
B0003-01
PCM1800
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............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008
SINGLE-ENDED ANALOG-INPUT 20-BIT STEREO ANALOG-TO-DIGITAL CONVERTER
•DVD Recorders23
•Dual 20-Bit Monolithic Δ Σ ADC
•DVD Receivers•Single-Ended Voltage Input
•AV Amplifier Receivers•64 × Oversampling Decimation Filter:
•Electric Musical Instruments– Pass-Band Ripple: ± 0.05 dB– Stop-Band Attenuation: – 65 dB•High Performance:
The PCM1800 is a low-cost, single-chip stereo– THD+N: – 88 dB (typical)
analog-to-digital converter (ADC) with single-ended– SNR: 95 dB (typical)
analog voltage inputs. The PCM1800 uses adelta-sigma modulator with 64 times oversampling,– Dynamic Range: 95 dB (typical)
including a digital decimation filter and a serial– Internal High-Pass Filter
interface which supports both master and slave•PCM Audio Interface:
modes and four data formats. The PCM1800 issuitable for a wide variety of cost-sensitive consumer– Master/Slave Modes
applications where good performance is required.– Four Data Formats
The PCM1800 is fabricated using a highly advanced•Sampling Rate: 4 kHz to 48 kHz
CMOS process and is available in a small 24-pin•System Clock: 256 f
S
, 384 f
S
, or 512 f
S
SSOP package.•Single 5-V Power Supply•Small 24-Pin SSOP Package
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2System Two, Audio Precision are trademarks of Audio Precision, Inc.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ELECTRICAL CHARACTERISTICS
PCM1800
SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ...............................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
All specifications at T
A
= 25 ° C, V
DD
= V
CC
= 5 V, slave mode, f
S
= 44.1 kHz, 20-bit input data, and SYSCLK = 384 f
S
, unlessotherwise noted
PCM1800EPARAMETER TEST CONDITIONS UNITSMIN TYP MAX
RESOLUTION 20 Bits
DIGITAL INPUT/OUTPUT
V
IH
(1)
2Input logic level VDCV
IL
(1)
0.8I
IN
(2)
± 1Input logic current µAI
IN
(3)
100V
OH
(4)
I
OH
= – 1.6 mA 4.5Output logic level VDCV
OL
(4)
I
OL
= 3.2 mA 0.5f
S
Sampling frequency 4 44.1 48 kHz256 f
S
1.024 11.2896 12.288System clock frequency 384 f
S
1.536 16.9344 18.432 MHz512 f
S
2.048 22.5792 24.576
DC ACCURACY
Gain mismatch, channel-to-channel ± 1 ± 2.5 % of FSRGain error ± 2 ± 5 % of FSRGain drift ± 20 ppm of FSR/ ° CBipolar zero error High-pass filter bypassed ± 2 % of FSRBipolar zero drift High-pass filter bypassed ± 20 ppm of FSR/ ° C
DYNAMIC PERFORMANCE
(5)
THD+N at FS ( – 0.5 dB) – 88 – 80 dBTHD+N at – 60 dB – 92 dBDynamic range A-weighted 90 95 dBSignal-to-noise ratio A-weighted 90 95 dBChannel separation 88 93 dB
DYNAMIC PERFORMANCE
(5)
Dynamic range 16-bit, A-weighted 94 dBSignal-to-noise ratio 16-bit, A-weighted 94 dBChannel separation 16-bit 92 dB
ANALOG INPUT
Input range FS (V
IN
= 0 dB) 2.828 Vp-pCenter voltage 2.1 VDCInput impedance 30 k Ω
Antialiasing filter frequency response C
EXT
= 470 pF, – 3 dB 170 kHz
DIGITAL FILTER PERFORMANCE
(1) Pins 6, 7, 8, 9, 10, 11, 16 and 12, 13, 14: RSTB, BYPAS, FMT0, FMT1, MODE0, MODE1, SYSCLK, and FSYNC, LRCK, BCK in slavemode
(2) Pins 16 and 12, 13, 14: SYSCLK and FSYNC, LRCK, BCK in slave mode (Schmitt-trigger input)(3) Pins 6, 7, 8, 9, 10, 11: RSTB, BYPAS, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, with 100-k Ωtypical pulldown resistor)(4) Pins 15 and 12, 13, 14: DOUT and FSYNC, LRCK, BCK in master mode(5) f
IN
= 1 kHz, using the System Two™ audio measurement system by Audio Precision™, rms mode with 20-kHz LPF and 400-Hz HPF inthe performance calculation.
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Product Folder Link(s): PCM1800
PCM1800
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............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25 ° C, V
DD
= V
CC
= 5 V, slave mode, f
S
= 44.1 kHz, 20-bit input data, and SYSCLK = 384 f
S
, unlessotherwise noted
PCM1800EPARAMETER TEST CONDITIONS UNITSMIN TYP MAX
Pass band 0.454 f
S
HzStop band 0.583 f
S
HzPass-band ripple ± 0.05 dBStop-band attenuation – 65 dBDelay time (latency) 17.4/f
S
sHigh-pass frequency response – 3 dB 0.019 f
S
mHz
POWER SUPPLY REQUIREMENTS
V
CC
4.5 5 5.5Voltage range VDCV
DD
4.5 5 5.5Supply current
(6)
V
CC
= V
DD
= 5 V 18 25 mAPower dissipation V
CC
= V
DD
= 5 V 90 125 mW
TEMPERATURE RANGE
T
A
Operation – 25 85 ° CT
stg
Storage – 55 125 ° Cθ
JA
Thermal resistance 100 ° C/W
(6) No load on DOUT (pin 15) in the slave mode
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Product Folder Link(s): PCM1800
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VINL
VREF1
REFCOM
VREF2
VINR
RSTB
BYPAS
FMT0
FMT1
MODE0
MODE1
FSYNC
AGND
VCC
CINPL
CINNL
CINPR
CINNR
VDD
DGND
SYSCLK
DOUT
BCK
LRCK
PCM1800
(TOP VIEW)
P0004-01
PCM1800
SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ...............................................................................................................................................
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PIN ASSIGNMENTS
NAME PIN I/O DESCRIPTION
AGND 24 – Analog groundBCK 14 I/O Bit clock input/outputBYPAS 7 I High-pass filter bypass control
(1)
C
IN
NL 21 – Antialias filter capacitor ( – ), LchC
IN
NR 19 – Antialias filter capacitor ( – ), RchC
IN
PL 22 – Antialias filter capacitor (+), LchC
IN
PR 20 – Antialias filter capacitor (+), RchDGND 17 – Digital groundDOUT 15 O Audio data outputFMT0 8 I Audio data format 0
(1)
FMT1 9 I Audio data format 1
(1)
FSYNC 12 I/O Frame synchronization, input/outputLRCK 13 I/O Sampling clock input/output (f
S
)MODE0 10 I Master/slave mode selection 0
(1)
MODE1 11 I Master/slave mode selection 1
(1)
REFCOM 3 – Reference decoupling commonSYSCLK 16 I System clock input, 256 f
S
, 384 f
S
, or 512 f
S
RSTB 6 I Reset input, active LOW
(1)
V
CC
23 – Analog power supplyV
DD
18 – Digital power supplyV
IN
L 1 I Analog input, LchV
IN
R 5 I Analog input, RchV
REF
1 2 – Reference 1 decoupling capacitorV
REF
2 4 – Reference 2 decoupling capacitor
(1) With 100-k Ωtypical pulldown resistor
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE PACKAGE ORDERING TRANSPORT QUANTITYTYPE CODE MARKING NUMBER MEDIA
PCM1800E Rails 58PCM1800E 24-pin SSOP DB PCM1800E
PCM1800E/2K Tape and reel 2000
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Product Folder Link(s): PCM1800
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
PCM1800
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............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008
Supply voltage: V
DD
, V
CC
– 0.3 V to 6.5 VSupply voltage differences ± 0.1 VGND voltage differences ± 0.1 VDigital input voltage – 0.3 V to (V
DD
+ 0.3 V), < 6.5 VAnalog input voltage – 0.3 V to (V
CC
+ 0.3 V), < 6.5 VInput current (any pin except supplies) ± 10 mAPower dissipation 300 mWOperating temperature range – 25 ° C to 85 ° CStorage temperature – 55 ° C to 125 ° CLead temperature, soldering 260 ° C, 5 sPackage temperature (IR reflow, peak) 235 ° C
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Analog supply voltage, V
CC
4.5 5 5.5 VDigital supply voltage, V
DD
4.5 5 5.5 VAnalog input voltage, full-scale ( – 0 dB) 2.828 Vp-pDigital input logic family TTLSystem clock 8.192 24.576 MHzDigital input clock frequency
Sampling clock 32 48 kHzDigital output load capacitance 10 pFOperating free-air temperature, T
A
– 25 85 ° C
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FMT0
FMT1
Single-End/
Differential
Converter BCK
VINL
Reference
Single-End/
Differential
Converter
VREF1
VREF2
VINR
5th Order
Delta-Sigma
Modulator
5th Order
Delta-Sigma
Modulator
×1/64
Decimation
and
High-Pass
Filter
Power Supply
AGNDVCC VDD
DGND
Clock/Timing Control
Reset/Power Control
Serial Data
Interface
LRCK
FSYNC
DOUT
MODE0
MODE1
BYPAS
SYSCLK
RSTB
REFCOM
CINNL
CINPL
(+)
(−)
(−)
(+)
CINNR
CINPR
ADC
Mode/Format
Control
Interface
B0004-01
PCM1800
SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ...............................................................................................................................................
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BLOCK DIAGRAM
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Product Folder Link(s): PCM1800
30 kΩ
1 kΩ
CEXT
470 pF
2122
VINL
VREF1
CINPL CINNL
1
2
3
4
Delta-Sigma
Modulator
(+)
VREF
REFCOM
VREF2
+
1.0 µF
4.7 µF
+
4.7 µF
+
+
−
(−)
+
−
1 kΩ
S0011-01
TYPICAL PERFORMANCE CURVES
90
92
94
96
98
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
Dynamic Range − dB
SNR
98
96
94
90
92
Dynamic Range
SNR − Signal-to-Noise Ratio − dB
G002
0.002
0.004
0.006
0.008
0.010
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
−0.5 dB
4
3
2
0
1
−60 dB
G001
THD+N − Total Harm. Dist. + Noise at −60 dB − %
PCM1800
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............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008
ANALOG FRONT-END (Single Channel)
All specifications at T
A
= 25 ° C, V
DD
= V
CC
= 5 V, slave mode, f
S
= 44.1 kHz, 20-bit input data, and SYSCLK = 384 f
S
, unlessotherwise noted
THD+N DYNAMIC RANGE AND SNRvs vsTEMPERATURE TEMPERATURE
Figure 1. Figure 2.
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TYPICAL PERFORMANCE CURVES (continued)
90
92
94
96
98
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC − Supply Voltage − V
Dynamic Range − dB
98
96
94
90
92
SNR − Signal-to-Noise Ratio − dB
G004
Dynamic Range
SNR
0.002
0.004
0.006
0.008
0.010
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC − Supply Voltage − V
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
4
3
2
0
1
THD+N − Total Harm. Dist. + Noise at −60 dB − %
G003
−60 dB
−0.5 dB
0.002
0.004
0.006
0.008
0.010
System Clock
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
4
3
2
0
1
G005
THD+N − Total Harm. Dist. + Noise at −60 dB − %
−60 dB
−0.5 dB
44.1 kHz
32 kHz
48 kHz 44.1 kHz
32 kHz
48 kHz
512 fS
256 fS384 fS
0.002
0.004
0.006
0.008
0.010
Resolution
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
4
3
2
0
1
G006
THD+N − Total Harm. Dist. + Noise at −60 dB − %
−60 dB
20-Bit16-Bit
−0.5 dB
PCM1800
SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ...............................................................................................................................................
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All specifications at T
A
= 25 ° C, V
DD
= V
CC
= 5 V, slave mode, f
S
= 44.1 kHz, 20-bit input data, and SYSCLK = 384 f
S
, unlessotherwise noted
THD+N DYNAMIC RANGE AND SNRvs vsPOWER SUPPLY POWER SUPPLY
Figure 3. Figure 4.
THD+N THD+Nvs vsSYSTEM CLOCK and SAMPLING FREQUENCY OUTPUT DATA RESOLUTION
Figure 5. Figure 6.
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Product Folder Link(s): PCM1800
TYPICAL PERFORMANCE CURVES (continued)
f − Frequency − kHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 2 4 6 8 10 12 14 16 18 20
Amplitude − dB
G007
PCM1800
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............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008
All specifications at T
A
= 25 ° C, V
DD
= V
CC
= 5 V, slave mode, f
S
= 44.1 kHz, 20-bit input data, and SYSCLK = 384 f
S
, unlessotherwise noted
THD+N
vs– 60 dBFS FFT AMPLITUDE
Figure 7. Figure 8.
THD+N
vsFREQUENCY
Figure 9.
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TYPICAL PERFORMANCE CURVES FOR INTERNAL FILTERS
DECIMATION FILTER
Normalized Frequency [× fS Hz]
−100
−75
−50
−25
0
0.00 0.25 0.50 0.75 1.00
Amplitude − dB
G011
PCM1800
SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ...............................................................................................................................................
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All specifications at T
A
= 25 ° C, V
DD
= V
CC
= 5 V, slave mode, f
S
= 44.1 kHz, 20-bit input data, and SYSCLK = 384 f
S
, unlessotherwise noted
OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS
Figure 10. Figure 11.
PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS
Figure 12. Figure 13.
All specifications at T
A
= 25 ° C, V
DD
= V
CC
= 5 V, slave mode, f
S
= 44.1 kHz, 20-bit input data, and SYSCLK = 384 f
S
, unless
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Product Folder Link(s): PCM1800
HIGH-PASS FILTER
ANTIALIASING FILTER
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
f − Frequency − Hz
Amplitude − dB
1 10 100 100k1k 10k
G017
470 pF
1000 pF
PCM1800
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............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008
TYPICAL PERFORMANCE CURVES FOR INTERNAL FILTERS (continued)All specifications at T
A
= 25 ° C, V
DD
= V
CC
= 5 V, slave mode, f
S
= 44.1 kHz, 20-bit input data, and SYSCLK = 384 f
S
, unlessotherwise noted
otherwise noted
HIGH-PASS FILTER RESPONSE HIGH-PASS FILTER RESPONSE
Figure 14. Figure 15.
ANTIALIASING FILTER OVERALL ANTIALIASING FILTER PASS-BANDFREQUENCY RESPONSE (C
EXT
= 470 pF, 1000 pF) FREQUENCY RESPONSE (C
EXT
= 470 pF, 1000 pF)
Figure 16. Figure 17.
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Product Folder Link(s): PCM1800
THEORY OF OPERATION
1st
SW-CAP
Integrator
Analog
In
X(z) +
−
+−2nd
SW-CAP
Integrator
3rd
SW-CAP
Integrator
+−4th
SW-CAP
Integrator
++++
++++
5th
SW-CAP
Integrator
Digital
Out
Y(z)
Comparator
Qn(z)
H(z)
1-Bit
DAC
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function B0005-01
SYSTEM CLOCK
PCM1800
SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ...............................................................................................................................................
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The PCM1800 consists of a band-gap reference, two channels of a single-to-differential converter, a fullydifferential 5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interfacecircuit. The block diagram illustrates the total architecture of the PCM1800 and the analog front-end diagramillustrates the architecture of the single-to-differential converter and the antialiasing filter. Figure 18 illustrates thearchitecture of the 5th-order delta-sigma modulator and transfer functions.
An internal high-precision reference with two external capacitors provides all the reference voltages that arerequired by the converter, and defines the full-scale voltage range of both channels. The internalsingle-to-differential voltage converter saves the design, space, and extra parts needed for external circuitryrequired by many delta-sigma converters. The internal full-differential architecture provides a wide dynamic rangeand excellent power-supply rejection performance.
The input signal is sampled at a 64 × oversampling rate, eliminating the need for a sample-and-hold circuit, andsimplifying antialias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integratorswhich use a switched-capacitor topology, a comparator, and a feedback loop consisting of a 1-bit DAC. Thedelta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain.The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels.
The 64-f
S
, 1-bit stream from the modulator is converted to 1-f
S
, 20-bit digital data by the decimation filter, whichalso acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed by ahigh-pass filter, and the filtered output is converted to time-multiplexed serial signals through a serial interfacewhich provides flexible serial formats and master/slave modes.
Figure 18. Simplified Diagram of the PCM1800 5th-Order Delta-Sigma Modulator
The system clock for the PCM1800 must be either 256 f
S
, 384 f
S
, or 512 f
S
, where f
S
is the audio samplingfrequency. The system clock must be supplied on SYSCLK (pin 16).
The PCM1800 also has a system-clock detection circuit which automatically senses if the system clock isoperating at 256 f
S
, 384 f
S
, or 512 f
S
.
When the 384-f
S
or 512-f
S
system clock is in slave mode, the system clock is divided into 256 f
S
automatically.The 256-f
S
clock is used to operate the digital filter and the modulator. Table 1 lists the relationship of typicalsampling frequencies and system clock frequencies. Figure 19 illustrates the system clock timing.
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Product Folder Link(s): PCM1800
SYSCLK 0.8 V
2.0 V
tCLKIL
tCLKIH
T0005-03
RESET AND POWER DOWN
1024 System Clock Periods
Reset Reset Removal
4.4 V
4.0 V
3.6 V
VCC / VDD
Internal Reset
System Clock
T0014-01
3 Clocks Minimum
PCM1800
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............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008
Table 1. System Clock Frequencies
SAMPLING RATE FREQUENCY SYSTEM CLOCK FREQUENCY (MHz)(kHz)
256 f
s
384 f
s
512 f
s
32 8.1920 12.2880 16.384044.1 11.2896 16.9344 22.579248 12.2880 18.4320 24.5760
System clock pulse duration, HIGH t
(CLKIH)
12 ns (min)System clock pulse duration, LOW t
(CLKIL)
12 ns (min)
Figure 19. System Clock Timing
The PCM1800 has both an internal power-on reset circuit and an external forced reset (RSTB, pin 6). Theinternal power-on reset initializes (resets) when the supply voltage (V
CC
/V
DD
) exceeds 4 V (typical). To initiate thereset sequence externally, apply a logic-level LOW to the RSTB pin.
The RSTB pin is terminated by an internal pulldown resistor. If the RSTB pin is unconnected, the ADC remains inthe reset state. Because the system clock is used as the clock signal for the reset circuit, the system clock mustbe supplied as soon as power is applied; more specifically, the device must receive at least three system clockcycles before V
DD
> 4 V and RSTB = HIGH. If this system clock requirement cannot be assured in an application,RSTB must be held LOW until the system clock is supplied. While V
CC
/V
DD
< 4 V (typical), RSTB = LOW, and for1024 system clock periods after V
CC
/V
DD
> 4.0 V and RSTB = HIGH, the PCM1800 stays in the reset state andthe digital output is forced to zero. The digital output is valid 18,436 f
S
periods after release from the reset state.During reset, the logic circuits and the digital filter stop operating and enter the power-down mode. Figure 20 andFigure 21 illustrate the internal power-on reset and external reset timing.
Figure 20. Internal Power-On Reset Timing
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Product Folder Link(s): PCM1800
t(RST)
Reset Removal
1024 System Clock Periods
RSTB-Pin
Internal Reset
System Clock
t(RST) = 40 ns (min)
Reset
T0015-01
RSTB Pulse Duration
SERIAL AUDIO DATA INTERFACE
INTERFACE MODE
DATA FORMAT
PCM1800
SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ...............................................................................................................................................
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Figure 21. RSTB-Pin Reset Timing
The PCM1800 interfaces with the audio system through BCK (pin 14), LRCK (pin 13), FSYNC (pin 12), andDOUT (pin 15).
The PCM1800 supports master and slave modes as interface modes, which are selected by MODE1 (pin 11)and MODE0 (pin 10), as shown in Table 2 . When in master mode, the PCM1800 provides the timing for serialaudio data communications between the PCM1800 and the digital audio processor or external circuit. When inslave mode, the PCM1800 receives the timing for data transfer from an external controller.
Table 2. Interface Mode
MODE1 MODE0 INTERFACE MODE
0 0 Slave mode (256/384/512 f
S
)0 1 Master mode (512 f
S
)1 0 Master mode (384 f
S
)1 1 Master mode (256 f
S
)
MASTER MODE
In master mode, BCK, LRCK, and FSYNC are output pins and are controlled by timing generated in the clockcircuitry of the PCM1800.
FSYNC is used to designate the valid data from the PCM1800. The rising edge of FSYNC indicates the startingpoint of the converted audio data, and the following edge of this signal indicates the ending point of data. Thefrequency of this signal is fixed at 2 × LRCK, and the duty-cycle ratio depends on the data bit length. Thefrequency of BCK is fixed at 64 × LRCK.
SLAVE MODE
In slave mode, BCK, LRCK, and FSYNC are input pins. The PCM1800 accepts 64-BCK/LRCK, 48-BCK/LRCK(only for a 384-f
S
system clock) or 32-BCK/LRCK format (only for 16-bit, right-justified format). FSYNC is used toenable the BCK signal, and the PCM1800 can shift out the converted data when FSYNC is HIGH.
The PCM1800 supports four audio data formats in both master and slave modes. These data formats areselected by FMT1 (pin 9) and FMT0 (pin 8), as shown in Table 3 .Figure 22 and Figure 23 illustrate the dataformats in slave mode and master mode, respectively.
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Product Folder Link(s): PCM1800
20-Bit, MSB-First, Left-Justified
BCK
LRCK Right-ChannelLeft-Channel
DOUT 1
18 19 20321
MSB LSB MSB LSB
FSYNC
FORMAT 0: FMT[1:0] = 00
18 19 20321
LRCK Right-ChannelLeft-Channel
BCK
DOUT
MSB LSB MSB LSB
FSYNC
20-Bit, MSB-First, I2S
FORMAT 1: FMT[1:0] = 01
18 19 20321 18 19 20321
16-Bit, MSB-First, Right-Justified
FORMAT 2: FMT[1:0] = 10
LRCK Right-ChannelLeft-Channel
BCK
DOUT
MSB LSB MSB LSB
FSYNC
18 19 20321 18 19 2032120
20-Bit, MSB-First, Right-Justified
FORMAT 3: FMT[1:0] = 11
LRCK Right-ChannelLeft-Channel
BCK
DOUT
MSB LSB MSB LSB
FSYNC
321 16151416 321 161514
T0016-01
PCM1800
www.ti.com
............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008
Table 3. Data Format
FORMAT NO. FMT1
(1)
FMT0
(1)
DATA FORMAT
0 0 0 20-bit, left-justified1 0 1 20-bit, I
2
S2 1 0 16-bit, right-justified3 1 1 20-bit, right-justified
(1) FMT1 and FMT0 must be stable when RSTB changes from LOW to HIGH.
Figure 22. Audio Data Format (Slave Mode: FSYNC, LRCK, and BCK Are Inputs)
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): PCM1800
20-Bit, MSB-First, Left-Justified
BCK
LRCK Right-ChannelLeft-Channel
DOUT 1
18 19 20321
MSB LSB MSB LSB
FSYNC
FORMAT 0: FMT[1:0] = 00
18 19 20321
LRCK Right-ChannelLeft-Channel
BCK
DOUT
MSB LSB MSB LSB
FSYNC
20-Bit, MSB-First, I2S
FORMAT 1: FMT[1:0] = 01
18 19 20321 18 19 20321
16-Bit, MSB-First, Right-Justified
FORMAT 2: FMT[1:0] = 10
LRCK Right-ChannelLeft-Channel
BCK
DOUT
MSB LSB MSB LSB
FSYNC
18 19 20321 18 19 2032120
20-Bit, MSB-First, Right-Justified
FORMAT 3: FMT[1:0] = 11
LRCK Right-ChannelLeft-Channel
BCK
DOUT
MSB LSB MSB LSB
FSYNC
321 16151416 321 161514
T0016-02
PCM1800
SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ...............................................................................................................................................
www.ti.com
Figure 23. Audio Data Format (Master Mode: FSYNC, LRCK, and BCK Are Outputs)
16 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCM1800
INTERFACE TIMING
BCK
FSYNC
LRCK
DOUT
t(FSSU)
t(BCKH)
t(BCKL)
t(LRHD)
t(FSHD)
t(LRCP)
t(LRSU)
t(BCKP) t(CKDO) t(LRDO)
1.4 V
1.4 V
1.4 V
0.5 VDD
T0017-01
PCM1800
www.ti.com
............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008
Figure 24 and Figure 25 illustrate the interface timing in slave mode and master mode, respectively.
DESCRIPTION SYMBOL MIN TYP MAX UNITS
BCK period t
(BCKP)
300 nsBCK pulse duration, HIGH t
(BCKH)
120 nsBCK pulse duration, LOW t
(BCKL)
120 nsLRCK setup time to BCK rising edge t
(LRSU)
80 nsLRCK hold time to BCK rising edge t
(LRHD)
40 nsLRCK period t
(LRCP)
20 µsFSYNC setup time to BCK rising edge t
(FSSU)
40 nsFSYNC hold time to BCK rising edge t
(FSHD)
40 nsDelay time, BCK falling edge to DOUT valid t
(CKDO)
– 20 40 nsDelay time, LRCK edge to DOUT valid t
(LRDO)
– 20 40 nsRising time of all signals t
(RISE)
20 nsFalling time of all signals t
(FALL)
20 ns
NOTE: Timing measurement reference level is (V
IH
+ V
IL
)/2. Rising and falling time is measured from 10% to 90% of the I/Osignal swing. Load capacitance of the DOUT signal is 20 pF.
Figure 24. Audio Data Interface Timing (Slave Mode: FSYNC, LRCK, and BCK Are Inputs)
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): PCM1800
BCK
FSYNC
LRCK
DOUT
t(CKFS)
t(BCKH)
t(BCKL)
t(CKLR)
t(LRCP)
t(BCKP) t(CKDO) t(LRDO)
0.5 VDD
0.5 VDD
0.5 VDD
0.5 VDD
t(FSYP)
T0018-01
SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
ADC DATA OUTPUT AT RESET
PCM1800
SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ...............................................................................................................................................
www.ti.com
DESCRIPTION SYMBOL MIN TYP MAX UNITS
BCK period t
(BCKP)
300 1/64 f
S
4800 nsBCK pulse duration, HIGH t
(BCKH)
150 2400 nsBCK pulse duration, LOW t
(BCKL)
150 2400 nsDelay time, BCK falling edge to LRCK valid t
(CKLR)
– 20 40 nsLRCK period t
(LRCP)
20 1/f
S
320 µsDelay time, BCK falling edge to FSYNC valid t
(CKFS)
– 20 40 nsFSYNC period t
(FSYP)
10 1/2 f
S
160 µsDelay time, BCK falling edge to DOUT valid t
(CKDO)
– 20 40 nsDelay time, LRCK edge to DOUT valid t
(LRDO)
– 20 40 nsRising time of all signals t
(RISE)
20 nsFalling time of all signals t
(FALL)
20 ns
NOTE: Timing measurement reference level is (V
IH
+ V
IL
)/2. Rising and falling time is measured from 10% to 90% of the I/Osignal swing. Load capacitance of the DOUT signal is 20 pF.
Figure 25. Audio Data Interface Timing (Master Mode: FSYNC, LRCK, and BCK Are Outputs)
In slave mode, the PCM1800 operates with LRCK synchronized to the system clock (SYSCLK). The PCM1800does not require a specific phase relationship between LRCK and SYSCLK, but does require the synchronizationof LRCK and SYSCLK. If the relationship between LRCK and SYSCLK changes more than 6 bit clocks (BCK)during one sample period due to LRCK or SYSCLK jitter, internal operation of the ADC halts within 1/f
S
and thedigital output is forced into the BPZ mode until resynchronization between LRCK and SYSCLK is completed. Incase of changes less than 5 bit clocks (BCK), resynchronization does not occur, and the previously describeddigital output control and discontinuity does not occur.
Figure 26 and Figure 27 illustrate the ADC digital output when the reset operation is done and whensynchronization is lost, respectively. During undefined data, some noise may be generated in the audio signal.Also, the transition of normal to undefined data and undefined or zero data to normal makes a discontinuity in thedata on the digital output, and may generate some noise in the audio signal.
18 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCM1800
T0019-01
Reset Ready/Operation
Internal Reset
DOUT(1) Zero Data Normal Data(2)
18436/fS
Reset Release
Power ON
RSTB ON
1/fS32/fS
Normal Data(2)
Zero Data
Undefined
Data
Normal Data
SynchronousAsynchronousSynchronous
Resynchronization
Synchronization Lost
DOUT(1)
State of Synchronization
T0020-01
HPF BYPASS CONTROL
PCM1800
www.ti.com
............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008
(1) In the master mode, FSYNC, BCK, and LRCK are outputs similar to DOUT.(2) The HPF transient response (exponentially attenuated signal from ± 0.2% dc of FSR with 200-ms time constant)appears initially.
Figure 26. ADC Digital Output for Power-On Reset and RSTB Control
(1) Applies only for slave mode — the loss of synchronization never occurs in master mode.(2) The HPF transient response (exponentially attenuated signal from ± 0.2% dc of FSR with 200-ms time constant)appears initially.
Figure 27. ADC Digital Output During Loss of Synchronization Resynchronization
The built-in function for dc component rejection can be bypassed by BYPAS (pin 7) control (see Table 4 ). Inbypass mode, the dc component of the input analog signal, the internal dc offset, etc., are also converted andoutput in the digital output data.
Table 4. HPF Bypass Control
BYPAS HIGH-PASS FILTER (HPF) MODE
Low Normal (dc cut) modeHigh Bypass (through) mode
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): PCM1800
APPLICATION INFORMATION
BOARD DESIGN AND LAYOUT CONSIDERATIONS
V
CC
, V
DD
PINS
AGND, DGND PINS
V
IN
PINS
V
REF
INPUTS
C
IN
P and C
IN
N INPUTS
DOUT, BCK, LRCK, FSYNC PINS
SYSTEM CLOCK
RSTB CONTROL
PCM1800
SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ...............................................................................................................................................
www.ti.com
The digital and analog power supply lines to the PCM1800 should be bypassed to the corresponding ground pinswith both 0.1- µF ceramic and 10- µF tantalum capacitors as close to the pins as possible to maximize thedynamic performance of the ADC. Although the PCM1800 has two power lines to maximize the potential ofdynamic performance, using one common power supply is recommended to avoid unexpected power supplyproblems, such as latch-up or power supply sequence.
To maximize the dynamic performance of the PCM1800, the analog and digital grounds are not internallyconnected. These points should have low impedance to avoid digital noise feedback into the analog ground.They should be connected directly to each other under the part to reduce potential noise problems.
A 1- µF tantalum capacitor is recommended as an ac-coupling capacitor, which establishes a 5.3-Hz cutofffrequency. If a higher full-scale input voltage is required, the input voltage range can be increased by adding aseries resistor to the V
IN
pins.
A 4.7- µF tantalum capacitor is recommended between V
REF
1, V
REF
2, and REFCOM to ensure low sourceimpedance for the ADC references. These capacitors should be located as close as possible to the V
REF
1 andV
REF
2 pins to reduce dynamic errors on the ADC references. The REFCOM pin also should be connecteddirectly to AGND under the part.
A 470-pF to 1000-pF film capacitor is recommended between C
IN
PL and C
IN
NL, C
IN
PR and C
IN
NR to create anantialiasing filter which has a 170-kHz to 80-kHz cutoff frequency. These capacitors should be located as closeas possible to the C
IN
P and C
IN
N pins to avoid introducing unexpected noise or dynamic errors into thedelta-sigma modulator. Four 10-pF – 47-pF capacitors between C
IN
XX and AGND may improve dynamicperformance under disadvantageous actual conditions.
In master mode, the DOUT, BCK, LRCK and FSYNC pins have a large load-drive capability, but locating thebuffer near the PCM1800 and minimizing the load capacitance is recommended in order to minimize thedigital-analog crosstalk and to maximize dynamic performance potential.
The quality of the system clock can influence dynamic performance in the PCM1800. The duty cycle, jitter, andthreshold voltage at the system clock input pin must be carefully managed. When power is supplied to the part,the system clock, bit clock (BCK), and word clock (LRCK) should also be supplied simultaneously. Failure tosupply the audio clocks results in a power dissipation increase of up to three times normal dissipation and candegrade long-term reliability if the maximum power dissipation limit is exceeded.
If the capacitance between V
REF
1 and V
REF
2 exceeds 4.7 µF, an external reset control with a delay-time circuitmust be used.
20 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCM1800
TYPICAL CIRCUIT CONNECTION DIAGRAM
S0012-01
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SYSCLK
DOUT
BCK
LRCK
RSTB
BYPAS
FMT0
FMT1
MODE0
MODE1
SYNC
+
4.7 µF
+
1.0 µF(2)
Analog
Front-End
Delta-Sigma
Decimation Filter
Digital Audio Interface
Reset
Clock
Audio
Data
Processor
Pin Program
or Control
Line In Left-Channel
+
1.0 µF(2)
Line In Right-Channel
GND
+5 V
+
4.7 µF
Ref
0.1 µF/10 µF(1)
0.1 µF/10 µF(1)
+
+
CEXT
470 pF
CEXT
470 pF
Signal Gnd
Analog
Front-End
PCM1800
www.ti.com
............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008
Figure 28 is a typical circuit connection diagram for which the cutoff frequency of the input HPF is about 5 Hz.
(1) Bypass capacitor = 0.1- µF ceramic and 10- µF tantalum, depending on layout and power supply.(2) A 1- µF capacitor gives a 5.3-Hz cutoff frequency for the input HPF in normal operation and requires a power-onsettling period with a 30-ms time constant during power-on initialization.
Figure 28. Typical Circuit Connection
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): PCM1800
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCM1800E NRND SSOP DB 24 58 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1800E/2K NRND SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1800E/2KG4 NRND SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1800EG4 NRND SSOP DB 24 58 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM1800E/2K SSOP DB 24 2000 330.0 17.4 8.5 8.6 2.4 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM1800E/2K SSOP DB 24 2000 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2008
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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