NPRSP - Agere Systems, Inc.

Product Brief

April 2001

PayloadPlus™ Routing Switch Processor

Introduction

The Agere Systems PayloadPlus architecture

provides a unique hardware and software

com bination that delivers high-speed processing

for multiple communication protocols with full

programmability. This combination gives you the

programmability of traditional RISC processors

with the speed that, until now, only ASICs could

deliver.

Agere Systems PayloadPlus product family

represents a technology revolution for the

constr uc tion of intell ig ent co mmu nic ati on

equipment with Layer 3 or above processing

capabilities. Agere’s products focus on the wire-

speed datapath functions and work in conjunction

with physical interface devices, low-speed

microprocessors, and backplane fabric offerings

to provide a complete solution for networking and

communication applications. The PayloadPlus

processor family includes the Fast Pattern

Processor (FPP), Routing Switch Processor

(RSP), and the Agere System Interface (ASI).

PayloadPlus processors are designed to handle

wire-speed data streams at up to OC-48c rates.

Each chip provides a complementary function: the

FPP for high-speed classification, the RSP for

processing and routing traffic, and the ASI to

provide policing, manage state information, and

provide a PCI connection to a host processor.

The FPP accepts a data stream of protocol data

units (PDUs) from an industry-standard POS-

PHY/UTOPIA Level 3 interface. The PDUs are

analyzed and classified, and the FPP outputs the

packets and conclusions to the RSP on a POS-

PHY Level 3 interface.

The Routing Switch Processor

The Routing Switch Processor works with the

Fast Pattern Processor and Agere System

Interface to process the wire-speed data stream.

The RSP uses the FPP’s classi fication and

analysis of incoming PDUs to identify the

necessary processing for the PDU. The RSP

suppor ts up to 64K program mab le que ues for

PDU processing and routing.

Features and Benefits of the RSP

The RSP has four major capabilities: queuing,

traffic management, traffic shaping, and packet

modification. Key features include the following:

■Transmit data queuing including QoS and CoS

■Support for up to 65,535 queues for a large

number of connections

■Programmable QoS and CoS parameters for

each queue

■Fully programmable discard policies including

RED, EPD, and WRED

■Fully programmable outgoing data

modifications

■Support for multicasting

■Support for real-time traffic, such as VBR-rt

■Support for virtual paths

■Support for independently scheduling up to 256

output channels

■Segmentation capabilities for interfacing to cell-

based fabrics or ATM/ POS-PHYs

■Generation of required checksums and CRCs

■OC-48c bandwidth for smart processing at high

bandwidths

■Industry-standard interfaces for input and

output

■Interface to control scheduling from external

logic

Product Brief NPRSP

June 2001 Routing Switch Processor

The information provided by the FPP is used by the RSP to

assign the PDU to a queue that has been programmed with

QoS, CoS, and PDU modification instructions.

The FPP and RSP are configured and updated over a

separate configuration bus that connects to the Agere

System Interface and host processor.

External Interfaces

The RSP features the following external interfaces:

■Input interface: a 32-bit POS-PHY Level 3 interface for the

wire-speed data path input.

■Output interface: a configurable 32-bit POS-PHY/UTOPIA

Level 3 interface for the wire-speed data path output. It can

be configured as a single 32-bit interface, two 16-bit

interfaces, a 16-bit and two 8-bit interfaces, or four 8-bit

interfaces.

■Management Interface: an 8-bit POS-PHY Level 3

interface to allow sending of packets to the ASI for host

processing.

■External Scheduler Interface: an interface that allows

external monitoring and scheduling of the RSP’s queues.

■SDRAM interface: a 64-bit interface for queuing PDUs that

supports up to 133 Mhz.

■SSRAM interfaces: four separate 32-bit SSRAM interfaces

featuring point-to-point memory access at up to 133 Mhz.

■Configuration bus interface: an 8-bit asynchronous bus for

configuring th e RSP from the host processor.

How the RSP Works

The RSP architecture is designed to provide a high level of

PDU processing capabilities at wire speed. The RSP accepts

PDUs and their classification information on up to 64 logical

input ports. It enqueues them on up to 64K programmable

queues, then outputs the modified PDUs on up to 256 logical

output ports mapped to up to 32 physical output ports.

The RSP receives PDUs and classification information on a

32-bit POS- PHY Le vel 3 int erf ace. Proc esse d tra f fi c is ou tput

on a configurable 32-bit POS-PHY Level 3/UTOPIA Level 3

interface. The RSP also has an 8-bit POS-PHY Level 3

management interface. Internally , the RSP uses custom logic

and three programmable V ery Large Instruction Word (VLIW)

compute engines to process PDUs while maintaining a high

throughput. Each compute engine is dedicated to a

processing function:

■A Traffic Management Compute Engine enforces discard

policies, and keeps queue statistics.

■A Traf fic Shaper Compute Engine ensures QoS and CoS

for each queue.

■A Stream Editor Compute Engine performs any necessary

PDU modifications.

The compute engines operate in a pipelined fashion. This

architecture allows the RSP to provide a high level of

processing capabilities, while maintaining wire-speed

performance.

The RSP is a building block designed to work with the other

Payload Plus Processors — the Fast Pattern Processor and

the Agere System Interface. It can also be used with other

logic.

ASI

RSPFPP

Physical

Interface

8-bit POS-PHY 8-bit POS-PHY

PCI to Host CPU

FBI

Configura tion Bu s

POS-PHY POS-PHY

UTOPIA UTOPIA

Fabric

System Overview

Fabric

Interface

Controller

Product Brief NPRSP

June 2001 Routing Switch Processor

Data Flow Through the RSP

The RSP receives PDUs on 64 logical ports. For each PDU,

the FPP, or other logic, sends the classification conclusions in

the form of a transmit command. This command instructs the

RSP how to process the PDU.

The PDU is added to a queue and stored in the PDU

SDRAM. The transmit command determines the queue

parameters that determine QoS, CoS, and PDU

modifications.

The figure that follows illustrates how the data flow

processing operates.

The RSP routes and processes PDUs in three major

processing stages. To process traffic, the RSP performs the

following tasks:

■Prepares and queues the PDU for scheduling:

—Assembles the blocks into a PDU in SDRAM.

—Determines the destination queue for the PDU.

—Determines if the PDU should be queued. If it should be

queued, it is added to the appropriate queue for

scheduling.

■Selects the next PDU block to be transmitted:

—Determines the physical port to be serviced.

—Determines the logical port to be serviced.

—Determines the scheduler to be serviced.

—Determines the queue to be serviced.

■Modifies and transmits the PDU on the appropriate output

port:

—Adjusts the QoS transmit intervals and CoS priority, if

necessary.

—Performs any necessary PDU modifications.

—Performs AAL5 CRC, if necessary.

PDU Scheduling Hierarchy

The RSP supports two modes for scheduling. The RSP’s

scheduling can be controlled internally, or by external logic,

depending on the mode you use.

Using the RSP’s Internal Scheduling Logic

The RSP uses the following elements to schedule and

transmit PDUs:

■Channels—the output interface supports a 32-bit data

output and an 8-bit management output. These physical

interfaces are configured into channels. The 32-bit

interface supports 1-4 POS-PHY or UTOPIA channels.

The management output supports a single 8-bit POS-PHY

channel.

■Physical Ports—the physical output ports are assigned to

channels. The RSP supports up to 32 physical output ports

to correspond to the number of back pressure signals.

Each physical port must be assigned at least one logical

output port, and can support multiple logical output ports.

■Logical Ports—each logical output port is mapped to a

single physical output port. The RSP supports up to 256

logical output ports.

■Schedulers—a set of schedulers is defined for each logical

port. Each scheduler supports a single type of traffic. The

RSP supports constant-bit-rate, variable-bit-rate, and

unspecified-bit-rate schedulers.

■QoS queues—each of the QoS queues is assigned to a

single scheduler. The scheduler is configured by

connection rate type, such as constant bit rate, variable bit

rate, or undefined bit rate.

■CoS queues—up to sixteen CoS queues feed a single QoS

queue to support PDU-based shaping policies. These

queues are optional.

The chart that follows shows the relationships between these

PDU scheduling elements.

The scheduling decision process is made in the opposite

direction from the data flow—from a physical port to a queue.

The RSP schedules data according to the following steps:

1. Select a physical port.

2. Select one of the physical port’s logical ports.

3. Select one of the logical port’s schedulers.

4. Select one of the scheduler’s QoS queues.

5. If the QoS queue has CoS queues, select a CoS queue.

Using External Scheduling Logic

The RSP features an External Scheduling Interface that

allows you to monitor and schedule queues for transmission

Determine

Queue ID

Perform

Traffic

Mgmt

Queue or

Discard

PDU

Assemble

the PDU

PDU Input

Queuing a PDU

Scheduling, Modifying

Pick the

Logical

Port

Pick

Scheduler

and Block

Get the

Block from

SDRAM

Pick the

Physical

Port

Modify

the

Block

Update

QoS and

CoS for

the flow

Traffic Management

Traffic Shaping PDU Modification

Transmit

the

Block

PDU Preparation

and Transmitting

a PDU Block

PDU Que uing and Block Scheduling

Product Brief NPRSP

June 2001 Routing Switch Processor

using external logic instead of the RSP’s internal scheduling

logic.

This feature allows you to use custom algorithms or to

dynamically set priorities based on traffic conditions. For

example, the External Scheduling Interface can be used to

connect to a switch fabric that is making global decisions

about traffic scheduling.

Programmable PDU Processing

The RSP’s flexibility and power are based on the capability to

program queues to process PDUs in different ways. Each

queue definition includes a destination, scheduling

information, and pointers to programs for each of the RSPs

VLIW compute engines. By selecting a queue definition that

performs the processing you want for each queue, you can

configure the RSP to process a wide variety of protocols. In

addition, the host processor can dynamically add queue

definitions as they are needed, for example, to set up virtual

circuits for ATM .

Defining Compute Engine Programs

To execute, the compute engines require the following:

■A program, or list of instructions.

■Parameters for the program.

At configuration, you define the set of programs you want to

use for each of the three compute engines. You can define

many compute engine programs, the exact number

depending on internal RAM and the length of the programs.

The parameters for the compute engines can be loaded at

configuration time or during operation.

Configuring Ports and Schedulers

Before you can define the queues, you must accomplish the

following:

■Configure the channels and physical ports.

■Create the logical ports and assign them to physical ports.

■Load the compute engine programs.

■ Create schedulers for each logical port. The definitions of

the schedulers include the program selection for the traffic

management and traffic shaping compute engines that

defines:

—QoS instructions

—CoS ins tr uc ti ons

—A traffic management policy

These steps take place during the initial configuration of the

RSP. The compute engine programs are loaded at

configuration, but can be selected for queues dynamically.

Defining Queues

Queues are defined by the following:

■Adding the queue to the stream editor destination ID table.

This table includes a pointer to the stream editor compute

engine modification instructions for the queue.

■Defining the compute engine program parameters. These

parameters are used for such things as setting thresholds

for discard policies, or defining bytes to add or replace

when modifying the PDU.

■Assigning the queue to a scheduler. By assigning a

scheduler, you select the traffic management and traffic

shaping compute engine programming, as well as the

logical and physical ports for the queue.

These steps can take place during the initial configuration of

the RSP, or dynamically, during operation.

RSP Internal Architecture

The following diagram illustrates the major internal

components of the RSP.

Physical

Ports

Logical

Ports

QoS Queues

Schedulers

CoS Queues

PDU Schedul i ng Flow

Scheduling Decisions

PDU Scheduling Hierarchy

Product Brief NPRSP

June 2001 Routing Switch Processor

Input

Interface PDU

Assembler

Stream

Editor

Compute Output

Interface

POS-PHY

PDU Data and

Classification

Conclusions

Queue

Manager

Logic

Traffic

Manager

Compute

Engine

Traffic

Shaper

Compute

Engine

Transmit Queue Logic

PDU

Conclusions

Buffer

Management Transmit

Request

PDU

SDRAM SED

SSRAM

Scheduler/

Parameter

SSRAM

External

Scheduling Interface Queue

Entry

SSRAM

Link

List

SSRAM

POS-PHY/

POS-PHY

Data

Output

Mgmt.

Output

RSP

Configuration

Bus Interface

UTOPIA

RSP Intern a l Architecture

Agere Systems, Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or

application. PayloadPlus is a Trademark of Agere Systems.

Printed in U.S.A.

6/1/01

PB01-133NP Printed On

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