Product Brief April 2001 PayloadPlusTM Routing Switch Processor Introduction The Routing Switch Processor The Agere Systems PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full programmability. This combination gives you the programmability of traditional RISC processors with the speed that, until now, only ASICs could deliver. The Routing Switch Processor works with the Fast Pattern Processor and Agere System Interface to process the wire-speed data stream. The RSP uses the FPP's classification and analysis of incoming PDUs to identify the necessary processing for the PDU. The RSP supports up to 64K programmable queues for PDU processing and routing. Agere Systems PayloadPlus product family represents a technology revolution for the construction of intelligent communication equipment with Layer 3 or above processing capabilities. Agere's products focus on the wirespeed datapath functions and work in conjunction with physical interface devices, low-speed microprocessors, and backplane fabric offerings to provide a complete solution for networking and communication applications. The PayloadPlus processor family includes the Fast Pattern Processor (FPP), Routing Switch Processor (RSP), and the Agere System Interface (ASI). Features and Benefits of the RSP PayloadPlus processors are designed to handle wire-speed data streams at up to OC-48c rates. Each chip provides a complementary function: the FPP for high-speed classification, the RSP for processing and routing traffic, and the ASI to provide policing, manage state information, and provide a PCI connection to a host processor. The FPP accepts a data stream of protocol data units (PDUs) from an industry-standard POSPHY/UTOPIA Level 3 interface. The PDUs are analyzed and classified, and the FPP outputs the packets and conclusions to the RSP on a POSPHY Level 3 interface. The RSP has four major capabilities: queuing, traffic management, traffic shaping, and packet modification. Key features include the following: Transmit data queuing including QoS and CoS Support for up to 65,535 queues for a large number of connections Programmable QoS and CoS parameters for each queue Fully programmable discard policies including RED, EPD, and WRED Fully programmable outgoing data modifications Support for multicasting Support for real-time traffic, such as VBR-rt Support for virtual paths Support for independently scheduling up to 256 output channels Segmentation capabilities for interfacing to cellbased fabrics or ATM/ POS-PHYs Generation of required checksums and CRCs OC-48c bandwidth for smart processing at high bandwidths Industry-standard interfaces for input and output Interface to control scheduling from external logic Product Brief June 2001 NPRSP Routing Switch Processor Physical Interface POS-PHY UTOPIA FPP RSP POS-PHY UTOPIA Fabric Interface Controller Fabric Configuration Bus FBI ASI 8-bit POS-PHY 8-bit POS-PHY PCI to Host CPU System Overview The information provided by the FPP is used by the RSP to assign the PDU to a queue that has been programmed with QoS, CoS, and PDU modification instructions. The FPP and RSP are configured and updated over a separate configuration bus that connects to the Agere System Interface and host processor. External Interfaces The RSP features the following external interfaces: 2 Input interface: a 32-bit POS-PHY Level 3 interface for the wire-speed data path input. Output interface: a configurable 32-bit POS-PHY/UTOPIA Level 3 interface for the wire-speed data path output. It can be configured as a single 32-bit interface, two 16-bit interfaces, a 16-bit and two 8-bit interfaces, or four 8-bit interfaces. Management Interface: an 8-bit POS-PHY Level 3 interface to allow sending of packets to the ASI for host processing. External Scheduler Interface: an interface that allows external monitoring and scheduling of the RSP's queues. SDRAM interface: a 64-bit interface for queuing PDUs that supports up to 133 Mhz. SSRAM interfaces: four separate 32-bit SSRAM interfaces featuring point-to-point memory access at up to 133 Mhz. Configuration bus interface: an 8-bit asynchronous bus for configuring the RSP from the host processor. How the RSP Works The RSP architecture is designed to provide a high level of PDU processing capabilities at wire speed. The RSP accepts PDUs and their classification information on up to 64 logical input ports. It enqueues them on up to 64K programmable queues, then outputs the modified PDUs on up to 256 logical output ports mapped to up to 32 physical output ports. The RSP receives PDUs and classification information on a 32-bit POS-PHY Level 3 interface. Processed traffic is output on a configurable 32-bit POS-PHY Level 3/UTOPIA Level 3 interface. The RSP also has an 8-bit POS-PHY Level 3 management interface. Internally, the RSP uses custom logic and three programmable Very Large Instruction Word (VLIW) compute engines to process PDUs while maintaining a high throughput. Each compute engine is dedicated to a processing function: A Traffic Management Compute Engine enforces discard policies, and keeps queue statistics. A Traffic Shaper Compute Engine ensures QoS and CoS for each queue. A Stream Editor Compute Engine performs any necessary PDU modifications. The compute engines operate in a pipelined fashion. This architecture allows the RSP to provide a high level of processing capabilities, while maintaining wire-speed performance. The RSP is a building block designed to work with the other Payload Plus Processors -- the Fast Pattern Processor and the Agere System Interface. It can also be used with other logic. Product Brief June 2001 NPRSP Routing Switch Processor Data Flow Through the RSP PDU Scheduling Hierarchy The RSP receives PDUs on 64 logical ports. For each PDU, the FPP, or other logic, sends the classification conclusions in the form of a transmit command. This command instructs the RSP how to process the PDU. The RSP supports two modes for scheduling. The RSP's scheduling can be controlled internally, or by external logic, depending on the mode you use. The PDU is added to a queue and stored in the PDU SDRAM. The transmit command determines the queue parameters that determine QoS, CoS, and PDU modifications. Using the RSP's Internal Scheduling Logic The RSP uses the following elements to schedule and transmit PDUs: The figure that follows illustrates how the data flow processing operates. The RSP routes and processes PDUs in three major processing stages. To process traffic, the RSP performs the following tasks: Prepares and queues the PDU for scheduling: --Assembles the blocks into a PDU in SDRAM. --Determines the destination queue for the PDU. --Determines if the PDU should be queued. If it should be queued, it is added to the appropriate queue for scheduling. Selects the next PDU block to be transmitted: --Determines the physical port to be serviced. --Determines the logical port to be serviced. --Determines the scheduler to be serviced. --Determines the queue to be serviced. Modifies and transmits the PDU on the appropriate output port: --Adjusts the QoS transmit intervals and CoS priority, if necessary. --Performs any necessary PDU modifications. The chart that follows shows the relationships between these PDU scheduling elements. --Performs any necessary PDU modifications. --Performs AAL5 CRC, if necessary. The scheduling decision process is made in the opposite direction from the data flow--from a physical port to a queue. Traffic Management PDU Preparation Queuing a PDU Channels--the output interface supports a 32-bit data output and an 8-bit management output. These physical interfaces are configured into channels. The 32-bit interface supports 1-4 POS-PHY or UTOPIA channels. The management output supports a single 8-bit POS-PHY channel. Physical Ports--the physical output ports are assigned to channels. The RSP supports up to 32 physical output ports to correspond to the number of back pressure signals. Each physical port must be assigned at least one logical output port, and can support multiple logical output ports. Logical Ports--each logical output port is mapped to a single physical output port. The RSP supports up to 256 logical output ports. Schedulers--a set of schedulers is defined for each logical port. Each scheduler supports a single type of traffic. The RSP supports constant-bit-rate, variable-bit-rate, and unspecified-bit-rate schedulers. QoS queues--each of the QoS queues is assigned to a single scheduler. The scheduler is configured by connection rate type, such as constant bit rate, variable bit rate, or undefined bit rate. CoS queues--up to sixteen CoS queues feed a single QoS queue to support PDU-based shaping policies. These queues are optional. The RSP schedules data according to the following steps: PDU Input Assemble the PDU Determine Queue ID Perform Traffic Mgmt Queue or Discard PDU Scheduling, Modifying PDU Modification Traffic Shaping and Transmitting a PDU Block Pick the Physical Port Pick the Logical Port Pick Get the Scheduler Block from and Block SDRAM Update QoS and CoS for the flow PDU Queuing and Block Scheduling Modify the Block Transmit the Block 1. 2. 3. 4. 5. Select a physical port. Select one of the physical port's logical ports. Select one of the logical port's schedulers. Select one of the scheduler's QoS queues. If the QoS queue has CoS queues, select a CoS queue. Using External Scheduling Logic The RSP features an External Scheduling Interface that allows you to monitor and schedule queues for transmission 3 Product Brief June 2001 NPRSP Routing Switch Processor using external logic instead of the RSP's internal scheduling logic. This feature allows you to use custom algorithms or to dynamically set priorities based on traffic conditions. For example, the External Scheduling Interface can be used to connect to a switch fabric that is making global decisions about traffic scheduling. Configuring Ports and Schedulers Before you can define the queues, you must accomplish the following: PDU Scheduling Flow Logical Ports QoS Queues CoS Queues Physical Ports Schedulers Configure the channels and physical ports. Create the logical ports and assign them to physical ports. Load the compute engine programs. Create schedulers for each logical port. The definitions of the schedulers include the program selection for the traffic management and traffic shaping compute engines that defines: --QoS instructions --CoS instructions --A traffic management policy Scheduling Decisions These steps take place during the initial configuration of the RSP. The compute engine programs are loaded at configuration, but can be selected for queues dynamically. PDU Scheduling Hierarchy Defining Queues Programmable PDU Processing Queues are defined by the following: Adding the queue to the stream editor destination ID table. This table includes a pointer to the stream editor compute engine modification instructions for the queue. Defining the compute engine program parameters. These parameters are used for such things as setting thresholds for discard policies, or defining bytes to add or replace when modifying the PDU. Assigning the queue to a scheduler. By assigning a scheduler, you select the traffic management and traffic shaping compute engine programming, as well as the logical and physical ports for the queue. These steps can take place during the initial configuration of the RSP, or dynamically, during operation. The RSP's flexibility and power are based on the capability to program queues to process PDUs in different ways. Each queue definition includes a destination, scheduling information, and pointers to programs for each of the RSPs VLIW compute engines. By selecting a queue definition that performs the processing you want for each queue, you can configure the RSP to process a wide variety of protocols. In addition, the host processor can dynamically add queue definitions as they are needed, for example, to set up virtual circuits for ATM. Defining Compute Engine Programs To execute, the compute engines require the following: A program, or list of instructions. Parameters for the program. At configuration, you define the set of programs you want to use for each of the three compute engines. You can define many compute engine programs, the exact number depending on internal RAM and the length of the programs. The parameters for the compute engines can be loaded at configuration time or during operation. RSP Internal Architecture 4 The following diagram illustrates the major internal components of the RSP. Product Brief June 2001 NPRSP Routing Switch Processor PDU SDRAM PDU Data and Classification POS-PHY Conclusions Input Interface PDU Assembler SED SSRAM Stream Editor Compute Output Interface POS-PHY/ Data Output UTOPIA POS-PHY RSP PDU Conclusions Buffer Management Mgmt. Output Transmit Request Transmit Queue Logic Configuration Bus Interface Queue Manager Logic Scheduler/ Parameter SSRAM External Scheduling Interface Traffic Manager Compute Engine Traffic Shaper Compute Engine Queue Entry SSRAM Link List SSRAM RSP Internal Architecture For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com N. AMERICA: Agere Systems, Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems, Inc., Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems, Inc. (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Agere Systems, Inc. Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: Agere Systems, Inc. DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), Agere Systems, Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. PayloadPlus is a Trademark of Agere Systems. Copyright (c) 2001 Agere Systems, Inc. All Rights Reserved Printed in U.S.A. 6/1/01 PB01-133NP Printed On Recycled Paper 5