Preliminary Data Sheet PD120Nxx Series R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A) Description The PD120Nxx series provides low-voltage output regulators with the output current capacitance of 0.3 A. The output voltage varies according to the product (1.5 V, 1.8 V, 2.5 V, or 3.3 V). The circuit current is low due to the CMOS structure, so the power consumption in the ICs can be reduced. Moreover, since ICs are mounted in the small package of the PD120Nxx series, this contributes to the miniaturization of the application set. Features * Output current: 0.3 A * On-chip overcurrent protection circuit * On-chip thermal protection circuit * Small circuit operation current: 60 A TYP. Applications Digital TV, Audio, HDD, DVD, etc. Pin Configurations (Marking Side) SC-74A N.C. GND GND 5 1 SC-62 4 2 3 OUTPUT 1 INPUT 2 OUTPUT GND 3 INPUT GND Block Diagram INPUT Overcurrent Protection Circuit Reference Voltage Circuit Error Amp. OUTPUT Thermal Protection Circuit GND The mark shows major revised points. The revised points can be easily searched by copying an "" in the PDF file and specifying it in the "Find what:" field. R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 Page 1 of 13 PD120Nxx Series Chapter Title Ordering Information Part Number Package Output Voltage Marking PD120N15TA SC-74A 1.5 V K71 PD120N15T1B SC-62 1.5 V 7D PD120N18TA SC-74A 1.8 V K72 PD120N18T1B SC-62 1.8 V 7E PD120N25TA SC-74A 2.5 V K73 PD120N25T1B SC-62 2.5 V 7F PD120N33TA SC-74A .3.3 V K74 PD120N33T1B SC-62 3.3 V 7G Remark -E1 or -E2 is suffixed to the end of the part number of taping products, and -A, -AT, -AY or -AZ to that of Pbfree products. See the table below for details. Note1 Part Number PD120NxxTA-A Note2 PD120NxxTA-AT Note2 PD120NxxTA-E1-A Note2 Package Package Type SC-74A * Unit SC-74A * Unit SC-74A * 8 mm wide embossed taping * Pin 1 on take-up side * 3000 pcs/reel (MAX.) PD120NxxTA-E1-AT Note2 SC-74A * 8 mm wide embossed taping * Pin 1 on take-up side * 3000 pcs/reel (MAX.) PD120NxxTA-E2-A Note2 SC-74A * 8 mm wide embossed taping * Pin 1 on draw-out side * 3000 pcs/reel (MAX.) PD120NxxTA-E2-AT Note2 SC-74A * 8 mm wide embossed taping * Pin 1 on draw-out side * 3000 pcs/reel (MAX.) PD120NxxT1B-AY Note3 PD120NxxT1B-AZ Note3 PD120NxxT1B-E1-AY Note3 SC-62 * Unit SC-62 * Unit SC-62 * 12 mm wide embossed taping * Pin 1 on take-up side * 1000 pcs/reel (MAX.) PD120NxxT1B-E1-AZ Note3 SC-62 * 12 mm wide embossed taping * Pin 1 on take-up side * 1000 pcs/reel (MAX.) PD120NxxT1B-E2-AY Note3 SC-62 * 12 mm wide embossed taping * Pin 1 on draw-out side * 1000 pcs/reel (MAX.) PD120NxxT1B-E2-AZ Note3 SC-62 * 12 mm wide embossed taping * Pin 1 on draw-out side * 1000 pcs/reel (MAX.) Notes 1. xx stands for symbols that indicate the output voltage. 2. Pb-free (This product does not contain Pb in external electrode and other parts.) 3. Pb-free (This product does not contain Pb in external electrode.) R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 Page 2 of 13 PD120Nxx Series Chapter Title Absolute Maximum Ratings (TA = 25C, unless otherwise specified.) Parameter Symbol Rating Unit PD120NxxTA Input Voltage Power Dissipation -0.3 to +6 VIN Note1 PD120NxxT1B 180/510 PT Note2 V 400/2000 Note3 mW Operating Ambient Temperature TA -40 to +85 C Operating Junction Temperature TJ -40 to +150 C Storage Temperature Tstg Thermal Resistance (junction to ambient) -55 to +150 695/245 Rth(J-A) Note2 C 315/62.5 Note3 C/W Note 1. Internally limited. When the operating junction temperature rises over 150C, the internal circuit shuts down the output voltage. 2 2. Mounted on ceramic substrate of 75 mm x 0.7 mm 3. Mounted on ceramic substrate of 16 cm2 x 0.7 mm Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Typical Connection D1 PD120Nxx INPUT CIN OUTPUT COUT D2 CIN: 0.1 F or higher. Set this value according to the length of the line between the regulator and INPUT pin. Be sure to connect CIN to prevent parasitic oscillation. If using a laminated ceramic capacitor, it is necessary to ensure that CIN is 0.1 F or higher for the voltage and temperature range to be used. COUT: 10 F or higher. Be sure to connect COUT to prevent oscillation and improve excessive load regulation. Place CIN and COUT as close as possible to the IC pins (within 2 cm). Be sure to use the capacitor of 10 F or higher of capacity values and 1 to 8 of equivalent series resistance under an operating condition. D1: If the OUTPUT pin has a higher voltage than the INPUT pin, connect a diode. D2: If the OUTPUT pin has a lower voltage than the GND pin, connect a schottky barrier diode. Caution Make sure that no voltage is applied to the OUTPUT pin from external. R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 Page 3 of 13 PD120Nxx Series Chapter Title Recommended Operating Conditions Parameter Input Voltage Symbol VIN Type Number MIN. TYP. MAX. Unit V PD120N15 3.0 5.5 PD120N18 3.2 5.5 V PD120N25 4.5 5.5 V PD120N33 4.5 5.5 V IO All 0 0.3 A Operating Ambient Temperature TA All - 40 + 85 C Operating Junction Temperature TJ All - 40 + 125 C Output Current Caution Use of conditions other than the above-listed recommended operating conditions is not a problem as long as the absolute maximum ratings are not exceeded. However, since the use of such conditions diminishes the margin of safety, careful evaluation is required before such conditions are used. Moreover, using the MAX. value for all the recommended operating conditions is not guaranteed to be safe. Electrical Characteristics PD120N15 (TJ = 25C, VIN = 5.0 V, IO = 0.15 A, CIN = 0.1 F, COUT = 10 F, unless otherwise specified.) Parameter Output Voltage Symbol Conditions VO1 MIN. TYP. MAX. 1.47 1.5 1.53 Unit V 1.455 - 1.545 V VO2 3.0 V VIN 5.5 V, 0 A IO 0.3 A Line Regulation REGIN 3.0 V VIN 5.5 V - 1 30 mV Load Regulation REGL 0 A IO 0.3 A - 2 30 mV Quiescent Current IBIAS IO = 0 A - 60 120 A Quiescent Current Change IBIAS 3.0 V VIN 5.5 V - - 25 A Output Noise Voltage Vn 10 Hz f 100 kHz - 100 - Vr.m.s. Ripple Rejection R*R f = 1 kHz, 3.0 V VIN 5.5 V - 63 - dB Dropout Voltage VDIF IO = 0.15 A - 0.6 0.9 V IO = 0.3 A - 1.0 - V VIN = 5 V - 0.2 - A 0.3 - - A - - 0.03 - mV/C Short Circuit Current IOshort Peak Output Current IOpeak VIN = 5 V Temperature Coefficient of VO/T IO = 0 A, 0C TJ 125C Output Voltage PD120N18 (TJ = 25C, VIN = 5.0 V, IO = 0.15 A, CIN = 0.1 F, COUT = 10 F, unless otherwise specified.) Parameter Output Voltage Symbol Conditions VO1 MIN. TYP. MAX. Unit 1.764 1.8 1.836 V 1.746 - 1.854 V - 1 30 mV 2 30 mV 60 120 A VO2 3.2 V VIN 5.5 V, 0 A IO 0.3 A Line Regulation REGIN 3.2 V VIN 5.5 V Load Regulation REGL 0 A IO 0.3 A - Quiescent Current IBIAS IO = 0 A - Quiescent Current Change IBIAS 3.2 V VIN 5.5 V - - 25 A Output Noise Voltage Vn 10 Hz f 100 kHz - 120 - Vr.m.s. Ripple Rejection R*R f = 1 kHz, 3.2 V VIN 5.5 V - 63 - dB Dropout Voltage VDIF IO = 0.15 A - 0.4 0.65 V Short Circuit Current IOshort VIN = 5 V - 0.2 - A Peak Output Current IOpeak VIN = 5 V 0.3 - - A Temperature Coefficient of VO/T IO = 0 A, 0C TJ 125C - - 0.06 - mV/C Output Voltage R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 Page 4 of 13 PD120Nxx Series Chapter Title PD120N25 (TJ = 25C, VIN = 5.0 V, IO = 0.15 A, CIN = 0.1 F, COUT = 10 F, unless otherwise specified.) Parameter Output Voltage Symbol Conditions VO1 MIN. TYP. MAX. Unit 2.45 2.5 2.55 V 2.425 - 2.575 V VO2 4.5 V VIN 5.5 V, 0 A IO 0.3 A Line Regulation REGIN 4.5 V VIN 5.5 V - 1 30 mV Load Regulation REGL 0 A IO 0.3 A - 2 30 mV Quiescent Current IBIAS IO = 0 A - 60 120 A Quiescent Current Change IBIAS 4.5 V VIN 5.5 V - - 25 A Output Noise Voltage Vn 10 Hz f 100 kHz - 170 - Vr.m.s. Ripple Rejection R*R f = 1 kHz, 4.5 V VIN 5.5 V - 60 - dB Dropout Voltage VDIF IO = 0.15 A - 0.3 0.7 V Short Circuit Current IOshort VIN = 5 V - 0.2 - A Peak Output Current IOpeak VIN = 5 V 0.3 - - A - - 0.07 - mV/C Temperature Coefficient of VO/T IO = 0 A, 0C TJ 125C Output Voltage PD120N33 (TJ = 25C, VIN = 5.0 V, IO = 0.15 A, CIN = 0.1 F, COUT = 10 F, unless otherwise specified.) Parameter Output Voltage Symbol Conditions VO1 MIN. TYP. MAX. Unit 3.234 3.3 3.366 V 3.201 - 3.399 V VO2 4.5 V VIN 5.5 V, 0 A IO 0.3 A Line Regulation REGIN 4.5 V VIN 5.5 V - 1 30 mV Load Regulation REGL 0 A IO 0.3 A - 2 30 mV Quiescent Current IBIAS IO = 0 A - 60 120 A Quiescent Current Change IBIAS 4.5 V VIN 5.5 V - - 25 A Output Noise Voltage Vn 10 Hz f 100 kHz - 220 - Vr.m.s. Ripple Rejection R*R f = 1 kHz, 4.5 V VIN 5.5 V - 60 - dB Dropout Voltage VDIF IO = 0.15 A - 0.2 0.6 V Short Circuit Current IOshort VIN = 5 V - 0.2 - A Peak Output Current IOpeak VIN = 5 V 0.3 - - A - - 0.06 - mV/C Temperature Coefficient of VO/T IO = 0 A, 0C TJ 125C Output Voltage R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 Page 5 of 13 PD120Nxx Series Chapter Title Typical Characteristics Pd vs. TA ( PD120NxxT1B) 0.6 Pd - Internal Power Consumption - W Pd - Internal Power Consumption - W Pd vs. TA ( PD120NxxTA) 2 (Mounted on ceramic substrate of 75 mm x 0.7 0.5 245C/W 0.4 0.3 (Without heatsink) 0.2 695C/W 0.1 0 0 20 40 60 80 2.5 (Mounted on ceramic substrate of 16 cm2 x 0.7 2 62.5C/W 1.5 1 (Without heatsink) 0.5 0 100 0 TA - Operating Ambient Temperature - C 20 40 60 80 100 TA - Operating Ambient Temperature - C VO vs. TJ VO vs. TJ 10 10 VO - Output Voltage Variation - mV VO - Output Voltage Variation - mV 315C/W IO = 0.15 A 5 0 PD120N15 -5 PD120N18 -10 IO = 0.15 A 5 0 PD120N33 -5 PD120N25 -10 -50 0 50 100 150 -50 0 50 100 150 TJ - Operating Junction Temperature - C TJ - Operating Junction Temperature - C VO vs. VIN (PD120N15) VO vs. VIN (PD120N18) 2 2 VO - Output Voltage - V VO - Output Voltage - V TJ = 25C IO = 5 mA IO = 150 mA IO = 300 mA 1 0 0 1 2 3 4 VIN - Input Voltage - V R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 5 6 TJ = 25C IO = 5 mA IO = 150 mA IO = 300 mA 1 0 0 1 2 3 4 5 6 VIN - Input Voltage - V Page 6 of 13 PD120Nxx Series Chapter Title VO vs. VIN (PD120N25) VO vs. VIN (PD120N33) 5 4 TJ = 25C VO - Output Voltage - V VO - Output Voltage - V TJ = 25C 3 2 IO = 5 mA IO = 150 mA IO = 300 mA 1 4 3 2 IO = 5 mA IO = 150 mA IO = 300 mA 1 0 0 0 1 2 3 4 5 1 0 6 2 3 4 5 VIN - Input Voltage - V VIN - Input Voltage - V IBIAS (IBIAS(S)) vs. VIN (PD120N15) IBIAS (IBIAS(S)) vs. VIN (PD120N18) 1000 1000 TJ = 25C IBIAS - Quiescent Current - A IBIAS - Quiescent Current - A TJ = 25C 800 600 IO = 300 mA 400 IO = 150 mA 200 800 600 IO = 300 mA 400 IO = 150 mA 200 IO = 5 mA IO = 5 mA 0 0 0 1 2 3 4 5 6 0 1 VIN - Input Voltage - V 2 3 4 5 6 VIN - Input Voltage - V IBIAS (IBIAS(S)) vs. VIN (PD120N25) IBIAS (IBIAS(S)) vs. VIN (PD120N33) 1000 1000 TJ = 25C TJ = 25C IBIAS - Quiescent Current - A IBIAS - Quiescent Current - A 6 800 600 IO = 300 mA 400 IO = 150 mA 200 800 IO = 300 mA 600 400 IO = 150 mA 200 IO = 5 mA IO = 5 mA 0 0 1 2 3 4 VIN - Input Voltage - V R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 5 6 0 0 1 2 3 4 5 6 VIN - Input Voltage - V Page 7 of 13 PD120Nxx Series Chapter Title IOpeak vs. VDIF (PD120N15) VDIF vs. TJ 0.7 1 IOpeak - Peak Output Current - A VDIF - Dropout Voltage - V IO = 0.15 A 0.8 PD120N15 0.6 PD120N18 0.4 PD120N25 0.2 PD120N33 TJ = 0C 0.6 0.5 TJ = 25C 0.4 TJ = 125C 0.3 0.2 0.1 0 0 -25 0 25 50 75 100 125 0 150 2 IOpeak vs. VDIF (PD120N18) 4 5 IOpeak vs. VDIF (PD120N25) 0.7 0.7 0.5 IOpeak - Peak Output Current - A TJ = 0C 0.6 TJ = 25C 0.4 TJ = 125C 0.3 0.2 0.1 0 TJ = 0C 0.6 0.5 TJ = 25C 0.4 TJ = 125C 0.3 0.2 0.1 0 0 1 2 3 4 5 0 VDIF - Dropout Voltage - V 1 2 3 R*R vs. f 80 0.7 R*R - Ripple Rejection - dB TJ = 0C 0.6 TJ = 25C 0.5 0.4 4 VDIF - Dropout Voltage - V IOpeak vs. VDIF (PD120N33) IOpeak - Peak Output Current - A 3 VDIF - Dropout Voltage - V TJ - Operating Junction Temperature - C IOpeak - Peak Output Current - A 1 TJ = 125C 0.3 0.2 0.1 TJ = 25C IO = 0.15 A PD120N15 70 60 PD120N25 50 40 30 20 10 0 0 0 1 2 VDIF - Dropout Voltage - V R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 3 10 100 1000 10000 100000 f - Frequency - Hz Page 8 of 13 PD120Nxx Series Chapter Title R*R vs. f VDIF vs. IO 80 1 60 VDIF - Dropout Voltage - V R*R - Ripple Rejection - dB TJ = 25C IO = 0.15 A PD120N18 70 PD120N33 50 40 30 20 10 0.8 PD120N15 PD120N18 PD120N25 PD120N33 0.6 0.4 0.2 0 10 100 1000 10000 100000 0 0 0.05 0.1 0.15 0.2 0.25 0.3 f - Frequency - Hz IO - Output Current - A VO vs. IO (PD120N15) VO vs. IO (PD120N18) 3 VO - Output Voltage - V VO - Output Voltage - V 3 2 1 0 0 200 400 600 2 1 0 800 0 IO - Output Current - A 400 600 800 IO - Output Current - A VO vs. IO (PD120N25) VO vs. IO (PD120N33) 4 5 VO - Output Voltage - V VO - Output Voltage - V 200 3 2 1 4 3 2 1 0 0 0 200 400 600 IO - Output Current - A R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 800 0 200 400 600 800 IO - Output Current - A Page 9 of 13 PD120Nxx Series Chapter Title Package Drawings (Unit: mm) SC-74A 5 PIN PLASTIC MINI MOLD detail of lead end F G R L E A H I B J S N C D M M K S ITEM A MILLIMETERS B 2.90.2 0.3 C 0.95 (T.P.) D 0.32 +0.05 -0.02 E 0.050.05 F 1.4 MAX. G 1.1+0.2 -0.1 H 2.80.2 I 1.5+0.2 -0.1 J 0.65 +0.1 -0.15 K 0.16 +0.1 -0.06 L 0.40.2 M N 0.19 0.1 R 55 S5TA-95-15A R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 Page 10 of 13 PD120Nxx Series Chapter Title SC-62 4.5 0.1 0.42 0.06 0.47 0.06 1.5 TYP. 0.8 MIN. 0.42 0.06 4.0 0.25 1.5 0.1 2.5 0.1 1.6 0.2 0.41 +0.03 -0.05 3.0 TYP. R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 Page 11 of 13 PD120Nxx Series Chapter Title Recommended Soldering Conditions The PD120Nxx series should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact a Renesas Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.renesas.com/prod/package/manual/) Surface Mount Device PD120N15TA-A, PD120N18TA-A, PD120N25TA-A, PD120N33TA-A: SC-74A Note1 PD120N15TA-AT, PD120N18TA-AT, PD120N25TA-AT, PD120N33TA-AT: SC-74A Note2 PD120N15T1B-AY, PD120N18T1B-AY, PD120N25T1B-AY, PD120N33T1B-AY: SC-62 Note2 PD120N15T1B-AZ, PD120N18T1B-AZ, PD120N25T1B-AZ, PD120N33T1B-AZ: SC-62 Note1 Process Infrared Ray Reflow Conditions Symbol Peak temperature: 260C or below (Package surface temperature), IR60-00-3 Reflow time: 60 seconds or less (at 220C or higher), Maximum number of reflows processes: 3 times or less. Partial Heating Method Pin temperature: 350C or below, P350 Heat time: 3 seconds or less (Per each side of the device). Notes 1. Pb-free (This product does not contain Pb in external electrode and other parts.) 2. Pb-free (This product does not contain Pb in external electrode.) Caution Do not use different soldering methods together (except for partial heating). Remark Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is recommended. Reference Documents USER'S MANUAL USAGE OF THREE TERMINAL REGULATORS Document No.G12702E Note INFORMATION VOLTAGE REGULATOR OF SMD Document No.G11872E Note SEMICONDUCTOR PACKAGE MOUNT MANUAL http://www.renesas.com/prod/package/index.html Note Published by the former NEC Electronics Corporation. R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 Page 12 of 13 PD120Nxx Series Chapter Title NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. R03DS0030EJ0400 Rev.4.00 Apr 15, 2011 Page 13 of 13 PD120Nxx Series Data Sheet Revision History Rev. Date Page - 4.00 Jun 2007 Apr 15, 2011 - Throughout pp.4, 5 Description Summary Previous No. : S17145EJ3V0DS00 Addition of Pb-free products (-AT, -AY) Modification of Absolute Maximum Ratings Output Noise Voltage 10 kHz f 100 kHz -> 10 Hz f 100 kHz All trademarks and registered trademarks are the property of their respective owners. C-1 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 (c) 2011 Renesas Electronics Corporation. All rights reserved. Colophon 1.0