R03DS0030EJ0400 Rev.4.00 Page 1 of 13
Apr 15, 2011
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Preliminary Data Sheet
μ
PD120Nxx Series
THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A)
Description
The
μ
PD120Nxx series provides low-voltage output regulators with the output current capacitance of 0.3 A. The output
voltage varies according to the product (1.5 V, 1.8 V, 2.5 V, or 3.3 V). The circuit current is low due to the CMOS
structure, so the power consumption in the ICs can be reduced. Moreover, since ICs are mounted in the small package
of the
μ
PD120Nxx series, this contributes to the miniaturization of the application set.
Features
Output current: 0.3 A
On-chip overcurrent protection circuit
On-chip thermal protection circuit
Small circuit operation current: 60
μ
A TYP.
Applications
Digital TV, Audio, HDD, DVD, etc.
Pin Configurations (Marking Side)
SC-62
GND
GND
OUTPUT INPUT
321
SC-74A
GND
N.C.
GND
OUTPUT INPUT
123
54
Block Diagram
INPUT
OUTPUT
GND
Overcurrent
Protection Circuit
Thermal
Protection Circuit
Error
Amp.
Reference
Voltage
Circuit
R03DS0030EJ0400
Rev.4.00
Apr 15, 2011
μPD120Nxx Series Chapter Title
R03DS0030EJ0400 Rev.4.00 Page 2 of 13
Apr 15, 2011
Ordering Information
Part Number Package Output Voltage Marking
μ
PD120N15TA SC-74A 1.5 V K71
μ
PD120N15T1B SC-62 1.5 V 7D
μ
PD120N18TA SC-74A 1.8 V K72
μ
PD120N18T1B SC-62 1.8 V 7E
μ
PD120N25TA SC-74A 2.5 V K73
μ
PD120N25T1B SC-62 2.5 V 7F
μ
PD120N33TA SC-74A .3.3 V K74
μ
PD120N33T1B SC-62 3.3 V 7G
Remark -E1 or -E2 is suffixed to the end of the part number of taping products, and -A, -AT, -AY or -AZ to that of Pb-
free products. See the table below for details.
Part Number Note1 Package Package Type
μ
PD120NxxTA-A Note2
SC-74A Unit
μ
PD120NxxTA-AT Note2
SC-74A Unit
μ
PD120NxxTA-E1-A Note2
SC-74A 8 mm wide embossed taping
Pin 1 on take-up side
3000 pcs/reel (MAX.)
μ
PD120NxxTA-E1-AT Note2
SC-74A 8 mm wide embossed taping
Pin 1 on take-up side
3000 pcs/reel (MAX.)
μ
PD120NxxTA-E2-A Note2
SC-74A 8 mm wide embossed taping
Pin 1 on draw-out side
3000 pcs/reel (MAX.)
μ
PD120NxxTA-E2-AT Note2
SC-74A 8 mm wide embossed taping
Pin 1 on draw-out side
3000 pcs/reel (MAX.)
μ
PD120NxxT1B-AY Note3
SC-62 Unit
μ
PD120NxxT1B-AZ Note3
SC-62 Unit
μ
PD120NxxT1B-E1-AY Note3
SC-62 12 mm wide embossed taping
Pin 1 on take-up side
1000 pcs/reel (MAX.)
μ
PD120NxxT1B-E1-AZ Note3
SC-62 12 mm wide embossed taping
Pin 1 on take-up side
1000 pcs/reel (MAX.)
μ
PD120NxxT1B-E2-AY Note3
SC-62 12 mm wide embossed taping
Pin 1 on draw-out side
1000 pcs/reel (MAX.)
μ
PD120NxxT1B-E2-AZ Note3
SC-62 12 mm wide embossed taping
Pin 1 on draw-out side
1000 pcs/reel (MAX.)
Notes 1. xx stands for symbols that indicate the output voltage.
2. Pb-free (This product does not contain Pb in external electrode and other parts.)
3. Pb-free (This product does not contain Pb in external electrode.)
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μPD120Nxx Series Chapter Title
R03DS0030EJ0400 Rev.4.00 Page 3 of 13
Apr 15, 2011
Absolute Maximum Ratings (TA = 25°C, unless otherwise specified.)
Rating Parameter Symbol
μ
PD120NxxTA
μ
PD120NxxT1B
Unit
Input Voltage VIN 0.3 to +6 V
Power Dissipation Note1 PT 180/510 Note2 400/2000 Note3 mW
Operating Ambient Temperature TA –40 to +85 °C
Operating Junction Temperature TJ –40 to +150 °C
Storage Temperature Tstg –55 to +150 °C
Thermal Resistance (junction to ambient) Rth(J-A) 695/245 Note2 315/62.5 Note3 °C/W
Note 1. Internally limited. When the operating junction temperature rises over 150°C, the internal circuit shuts down the
output voltage.
2. Mounted on ceramic substrate of 75 mm2 x 0.7 mm
3. Mounted on ceramic substrate of 16 cm2 x 0.7 mm
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Typical Connection
D
2
D
1
C
IN
C
OUT
INPUT OUTPUT
PD120Nxx
μ
CIN: 0.1
μ
F or higher. Set this value according to the length of the line between the regulator and INPUT pin. Be sure to
connect CIN to prevent parasitic oscillation. If using a laminated ceramic capacitor, it is necessary to ensure that CIN
is 0.1
μ
F or higher for the voltage and temperature range to be used.
COUT: 10
μ
F or higher. Be sure to connect COUT to prevent oscillation and improve excessive load regulation. Place CIN
and COUT as close as possible to the IC pins (within 2 cm). Be sure to use the capacitor of 10
μ
F or higher of
capacity values and 1 to 8 Ω of equivalent series resistance under an operating condition.
D1: If the OUTPUT pin has a higher voltage than the INPUT pin, connect a diode.
D2: If the OUTPUT pin has a lower voltage than the GND pin, connect a schottky barrier diode.
Caution Make sure that no voltage is applied to the OUTPUT pin from external.
μPD120Nxx Series Chapter Title
R03DS0030EJ0400 Rev.4.00 Page 4 of 13
Apr 15, 2011
Recommended Operating Conditions
Parameter Symbol Type Number MIN. TYP. MAX. Unit
μ
PD120N15 3.0 5.5 V
μ
PD120N18 3.2 5.5 V
μ
PD120N25
4.5 5.5 V
Input Voltage VIN
μ
PD120N33 4.5 5.5 V
Output Current IO All 0 0.3 A
Operating Ambient Temperature TA All 40 +85 °C
Operating Junction Temperature TJ All 40 +125 °C
Caution Use of conditions other than the above-listed recommended operating conditions is not a problem as
long as the absolute maximum ratings are not exceeded. However, since the use of such conditions
diminishes the margin of safety, careful evaluation is required before such conditions are used.
Moreover, using the MAX. value for all the recommended operating conditions is not guaranteed to be
safe.
Electrical Characteristics
μ
PD120N15 (TJ = 25°C, VIN = 5.0 V, IO = 0.15 A, CIN = 0.1
μ
F, COUT = 10
μ
F, unless otherwise specified.)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VO1 1.47 1.5 1.53 V Output Voltage
VO2 3.0 V VIN 5.5 V, 0 A IO 0.3 A 1.455 1.545 V
Line Regulation REGIN 3.0 V VIN 5.5 V 1 30 mV
Load Regulation REGL 0 A IO 0.3 A 2 30 mV
Quiescent Current IBIAS IO = 0 A 60 120
μ
A
Quiescent Current Change
Δ
IBIAS 3.0 V VIN 5.5 V 25
μ
A
Output Noise Voltage Vn 10 Hz f 100 kHz 100
μ
Vr.m.s.
Ripple Rejection R•R f = 1 kHz, 3.0 V VIN 5.5 V 63 dB
IO = 0.15 A 0.6 0.9 V Dropout Voltage VDIF
IO = 0.3 A 1.0 V
Short Circuit Current IOshort VIN = 5 V 0.2 A
Peak Output Current IOpeak VIN = 5 V 0.3 A
Temperature Coefficient of
Output Voltage
Δ
VO/
Δ
T IO = 0 A, 0°C TJ 125°C 0.03 mV/°C
μ
PD120N18 (TJ = 25°C, VIN = 5.0 V, IO = 0.15 A, CIN = 0.1
μ
F, COUT = 10
μ
F, unless otherwise specified.)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VO1 1.764 1.8 1.836 V Output Voltage
VO2 3.2 V VIN 5.5 V, 0 A IO 0.3 A 1.746 1.854 V
Line Regulation REGIN 3.2 V VIN 5.5 V 1 30 mV
Load Regulation REGL 0 A IO 0.3 A 2 30 mV
Quiescent Current IBIAS IO = 0 A 60 120
μ
A
Quiescent Current Change
Δ
IBIAS 3.2 V VIN 5.5 V 25
μ
A
Output Noise Voltage Vn 10 Hz f 100 kHz 120
μ
Vr.m.s.
Ripple Rejection R•R f = 1 kHz, 3.2 V VIN 5.5 V 63 dB
Dropout Voltage VDIF IO = 0.15 A 0.4 0.65 V
Short Circuit Current IOshort VIN = 5 V 0.2 A
Peak Output Current IOpeak VIN = 5 V 0.3 A
Temperature Coefficient of
Output Voltage
Δ
VO/
Δ
T IO = 0 A, 0°C TJ 125°C 0.06 mV/°C
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μPD120Nxx Series Chapter Title
R03DS0030EJ0400 Rev.4.00 Page 5 of 13
Apr 15, 2011
μ
PD120N25 (TJ = 25°C, VIN = 5.0 V, IO = 0.15 A, CIN = 0.1
μ
F, COUT = 10
μ
F, unless otherwise specified.)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VO1 2.45 2.5 2.55 V Output Voltage
VO2 4.5 V VIN 5.5 V, 0 A IO 0.3 A 2.425 2.575 V
Line Regulation REGIN 4.5 V VIN 5.5 V 1 30 mV
Load Regulation REGL 0 A IO 0.3 A 2 30 mV
Quiescent Current IBIAS IO = 0 A 60 120
μ
A
Quiescent Current Change
Δ
IBIAS 4.5 V VIN 5.5 V 25
μ
A
Output Noise Voltage Vn 10 Hz f 100 kHz 170
μ
Vr.m.s.
Ripple Rejection R•R f = 1 kHz, 4.5 V VIN 5.5 V 60 dB
Dropout Voltage VDIF IO = 0.15 A 0.3 0.7 V
Short Circuit Current IOshort VIN = 5 V 0.2 A
Peak Output Current IOpeak VIN = 5 V 0.3 A
Temperature Coefficient of
Output Voltage
Δ
VO/
Δ
T IO = 0 A, 0°C TJ 125°C 0.07 mV/°C
μ
PD120N33 (TJ = 25°C, VIN = 5.0 V, IO = 0.15 A, CIN = 0.1
μ
F, COUT = 10
μ
F, unless otherwise specified.)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VO1 3.234 3.3 3.366 V Output Voltage
VO2 4.5 V VIN 5.5 V, 0 A IO 0.3 A 3.201 3.399 V
Line Regulation REGIN 4.5 V VIN 5.5 V 1 30 mV
Load Regulation REGL 0 A IO 0.3 A 2 30 mV
Quiescent Current IBIAS IO = 0 A 60 120
μ
A
Quiescent Current Change
Δ
IBIAS 4.5 V VIN 5.5 V 25
μ
A
Output Noise Voltage Vn 10 Hz f 100 kHz 220
μ
Vr.m.s.
Ripple Rejection R•R f = 1 kHz, 4.5 V VIN 5.5 V 60 dB
Dropout Voltage VDIF IO = 0.15 A 0.2 0.6 V
Short Circuit Current IOshort VIN = 5 V 0.2 A
Peak Output Current IOpeak VIN = 5 V 0.3 A
Temperature Coefficient of
Output Voltage
Δ
VO/
Δ
T IO = 0 A, 0°C TJ 125°C 0.06 mV/°C
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μPD120Nxx Series Chapter Title
R03DS0030EJ0400 Rev.4.00 Page 6 of 13
Apr 15, 2011
Typical Characteristics
Pd vs. TA (
μ
PD120NxxTA) Pd vs. TA (
μ
PD120NxxT1B)
Pd - Internal Power Consumption - W
0
0.1
0.2
0.3
0.4
0.5
0.6
0 20406080100
(Mounted on ceramic substrate of 75 mm
2
x 0.7
(Without heatsink)
245°C/W
695°C/W
TA - Operating Ambient Temperature - °C
Pd - Internal Power Consumption - W
0
0.5
1
1.5
2
2.5
0 20406080100
62.5°C/W
315°C/W
(Mounted on ceramic substrate of 16 cm
2
x 0.7
(Without heatsink)
T
A - Operating Ambient Temperature - °C
Δ
VO vs. TJ
Δ
VO vs. TJ
Δ
VO - Output Voltage Variation - mV
-10
-5
0
5
10
-50 0 50 100 150
I
O
= 0.15 A
μPD120N18
μPD120N15
TJ - Operating Junction Temperature - °C
Δ
VO - Output Voltage Variation - mV
-10
-5
0
5
10
-50 0 50 100 150
I
O
= 0.15 A
μPD120N25
μPD120N33
TJ - Operating Junction Temperature - °C
VO vs. VIN (
μ
PD120N15)
VO vs. VIN (
μ
PD120N18)
VO - Output Voltage - V
0
0
1
2
12345 6
TJ = 25˚C
IO = 5 mA
IO = 150 mA
IO = 300 mA
VIN - Input Voltage - V
VO - Output Voltage - V
0
0
1
2
12 345 6
T
J
= 25˚C
I
O
= 5 mA
I
O
= 150 mA
I
O
= 300 mA
VIN - Input Voltage - V
μPD120Nxx Series Chapter Title
R03DS0030EJ0400 Rev.4.00 Page 7 of 13
Apr 15, 2011
VO vs. VIN (
μ
PD120N25)
VO vs. VIN (
μ
PD120N33)
VO - Output Voltage - V
0
0
1
2
3
4
12 3 45 6
TJ = 25˚C
IO = 5 mA
IO = 150 mA
IO = 300 mA
VIN - Input Voltage - V
VO - Output Voltage - V
0
0
1
2
3
5
4
123456
T
J
= 25˚C
I
O
= 5 mA
I
O
= 150 mA
I
O
= 300 mA
VIN - Input Voltage - V
IBIAS (IBIAS(S)) vs. VIN (
μ
PD120N15)
IBIAS (IBIAS(S)) vs. VIN (
μ
PD120N18)
IBIAS - Quiescent Current -
μ
A
0
0
200
400
600
800
1000
1234 5 6
TJ = 25˚C
IO = 300 mA
IO = 150 mA
IO = 5 mA
VIN - Input Voltage - V
IBIAS - Quiescent Current -
μ
A
0
0
200
400
600
800
1000
123456
T
J
= 25˚C
I
O
= 300 mA
I
O
= 150 mA
I
O
= 5 mA
V
IN - Input Voltage - V
I
BIAS (IBIAS(S)) vs. VIN (
μ
PD120N25) IBIAS (IBIAS(S)) vs. VIN (
μ
PD120N33)
IBIAS - Quiescent Current -
μ
A
0
0
200
400
600
800
1000
123456
T
J
= 25˚C
I
O
= 300 mA
I
O
= 150 mA
I
O
= 5 mA
VIN - Input Voltage - V
IBIAS - Quiescent Current -
μ
A
0
0
200
400
600
800
1000
1234 56
TJ = 25˚C
IO = 300 mA
IO = 150 mA
IO = 5 mA
VIN - Input Voltage - V
μPD120Nxx Series Chapter Title
R03DS0030EJ0400 Rev.4.00 Page 8 of 13
Apr 15, 2011
VDIF vs. TJ IOpeak vs. VDIF (
μ
PD120N15)
VDIF - Dropout Voltage - V
0
0.2
0.4
0.6
0.8
1
-25 0 25 50 75 100 125 150
I
O
= 0.15 A
μPD120N15
μPD120N25
μPD120N18
μPD120N33
TJ - Operating Junction Temperature - °C
IOpeak - Peak Output Current - A
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
012345
TJ = 0°C
TJ = 25°C
TJ = 125°C
V
DIF - Dropout Voltage - V
IOpeak vs. VDIF (
μ
PD120N18) IOpeak vs. VDIF (
μ
PD120N25)
IOpeak - Peak Output Current - A
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
012345
T
J
= 0°C
T
J
= 25°C
T
J
= 125°C
VDIF - Dropout Voltage - V
IOpeak - Peak Output Current - A
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
01234
T
J
= 0°C
T
J
= 25°C
T
J
= 125°C
VDIF - Dropout Voltage - V
IOpeak vs. VDIF (
μ
PD120N33)
R•R vs. f
IOpeak - Peak Output Current - A
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0123
T
J
= 0°C
T
J
= 25°C
T
J
= 125°C
VDIF - Dropout Voltage - V
R•R - Ripple Rejection - dB
0
10
20
30
40
50
60
70
80
10 100 1000 10000 100000
T
J
= 25°C
I
O
= 0.15
A
μPD120N25
μPD120N15
f - Frequency - Hz
μPD120Nxx Series Chapter Title
R03DS0030EJ0400 Rev.4.00 Page 9 of 13
Apr 15, 2011
R•R vs. f VDIF vs. IO
R•R - Ripple Rejection - dB
0
10
20
30
40
50
60
70
80
10 100 1000 10000 100000
T
J
= 25°C
I
O
= 0.15 A
μPD120N33
μPD120N18
f - Frequency - Hz
VDIF - Dropout Voltage - V
0
0.2
0.4
0.6
0.8
1
0 0.05 0.1 0.15 0.2 0.25 0.3
μ
PD120N15
μ
PD120N18
μ
PD120N25
μ
PD120N33
I
O - Output Current - A
VO vs. IO (
μ
PD120N15) VO vs. IO (
μ
PD120N18)
VO - Output Voltage - V
0
0
1
2
3
200 400 600 800
IO - Output Current - A
VO - Output Voltage - V
0
0
1
2
3
200 400 600 800
IO - Output Current - A
VO vs. IO (
μ
PD120N25)
VO vs. IO (
μ
PD120N33)
VO - Output Voltage - V
0
0
1
2
3
4
200 400 600 800
IO - Output Current - A
VO - Output Voltage - V
0
0
1
2
3
4
5
200 400 600 800
IO - Output Current - A
μPD120Nxx Series Chapter Title
R03DS0030EJ0400 Rev.4.00 Page 10 of 13
Apr 15, 2011
Package Drawings (Unit: mm)
SC-74A
5 PIN PLASTIC MINI MOLD
B
A
C 0.95 (T.P.)
2.9±0.2
0.3
S5TA-95-15A
ITEM MILLIMETERS
B
R
K
M
L
detail of lead end
J
C
D
F
N
D 0.32+0.05
0.02
E
F 1.4 MAX.
0.05±0.05
G 1.1+0.2
0.1
H 2.8±0.2
I 1.5+0.2
0.1
J 0.65+0.1
0.15
K 0.16+0.1
0.06
M
N
R5°±5°
S
M
S
G
E
A
H
I
L 0.4±0.2
0.19
0.1
μPD120Nxx Series Chapter Title
R03DS0030EJ0400 Rev.4.00 Page 11 of 13
Apr 15, 2011
SC-62
1.6 ±0.2 1.5 ±0.1
0.8 MIN. 2.5 ±0.1
4.0 ±0.25
3.0 TYP.
1.5 TYP.
4.5 ±0.1
0.41
+0.03
–0.05
0.47
±0.06
0.42
±0.06
0.42
±0.06
μPD120Nxx Series Chapter Title
R03DS0030EJ0400 Rev.4.00 Page 12 of 13
Apr 15, 2011
Recommended Soldering Conditions
The
μ
PD120Nxx series should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact a Renesas Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.renesas.com/prod/package/manual/)
Surface Mount Device
μ
PD120N15TA-A,
μ
PD120N18TA-A,
μ
PD120N25TA-A,
μ
PD120N33TA-A: SC-74A Note1
μ
PD120N15TA-AT,
μ
PD120N18TA-AT,
μ
PD120N25TA-AT,
μ
PD120N33TA-AT: SC-74A Note1
μ
PD120N15T1B-AY,
μ
PD120N18T1B-AY,
μ
PD120N25T1B-AY,
μ
PD120N33T1B-AY: SC-62 Note2
μ
PD120N15T1B-AZ,
μ
PD120N18T1B-AZ,
μ
PD120N25T1B-AZ,
μ
PD120N33T1B-AZ: SC-62 Note2
Process Conditions Symbol
Infrared Ray Reflow Peak temperature: 260°C or below (Package surface temperature),
Reflow time: 60 seconds or less (at 220°C or higher),
Maximum number of reflows processes: 3 times or less.
IR60-00-3
Partial Heating Method Pin temperature: 350°C or below,
Heat time: 3 seconds or less (Per each side of the device).
P350
Notes 1. Pb-free (This product does not contain Pb in external electrode and other parts.)
2. Pb-free (This product does not contain Pb in external electrode.)
Caution Do not use different soldering methods together (except for partial heating).
Remark Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is recommended.
Reference Documents
USER’S MANUAL USAGE OF THREE TERMINAL REGULATORS Document No.G12702E Note
INFORMATION VOLTAGE REGULATOR OF SMD Document No.G11872E Note
SEMICONDUCTOR PACKAGE MOUNT MANUAL
http://www.renesas.com/prod/package/index.html
Note Published by the former NEC Electronics Corporation.
<R>
μPD120Nxx Series Chapter Title
R03DS0030EJ0400 Rev.4.00 Page 13 of 13
Apr 15, 2011
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected
wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH
(MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the
device when the input level is fixed, and also in the transition period when the input level passes through the
area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of
static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control
must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators
that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work benches
and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with
mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device.
Immediately after the power source is turned ON, devices with reset functions have not yet been initialized.
Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not
initialized until the reset signal is received. A reset operation must be executed immediately after power-on
for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for
each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while
the device is not powered. The current injection that results from input of such a signal or I/O pull-up power
supply may cause malfunction and the abnormal current that passes in the device at this time may cause
degradation of internal elements. Input of signals during the power off state must be judged separately for
each device and according to related specifications governing the device.
All trademarks and registered trademarks are the property of their respective owners.
C - 1
Revision History μPD120Nxx Series Data Sheet
Description
Rev. Date Page Summary
Jun 2007 Previous No. : S17145EJ3V0DS00
4.00 Apr 15, 2011 Throughout Addition of Pb-free products (-AT, -AY)
pp.4, 5 Modification of Absolute Maximum Ratings Output Noise Voltage
10 kHz f 100 kHz -> 10 Hz f 100 kHz
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