1www.semtech.com
PROTECTION PRODUCTS
SR2.8
RailClamp™
Low Capacitance TVS Diode Array
Description Features
Circuit Diagram Schematic & PIN Configuration
Revision 9/2000
RailClamps are surge rated diode arrays designed to
protect high speed data interfaces. The SR series has
been specifically designed to protect sensitive compo-
nents which are connected to data and transmission
lines from overvoltage caused by ESD (electrostatic
discharge), EFT (electrical fast transients), and tertiary
lightning.
The unique design of the SR series devices incorpo-
rates four surge rated, low capacitance steering diodes
and a T VS diode in a single package. The T VS diode is
constructed using Semtech’s proprietary low voltage
EPD technology for superior electrical characteristics at
2.8 volts.
During transient conditions, the steering diodes direct
the transient to either the positive side of the power
supply line or to ground. The internal TVS diode pre-
vents over-voltage on the power line, protecting any
downstream components.
The low capacitance array configuration allows the user
to protect two high-speed data or transmission lines.
The low inductance construction minimizes voltage
overshoot during high current surges.
Applications
Mechanical Characteristics
!10/100 Ethernet
!Firewire
!Sensitive Analog Inputs
!Video Line Protection
!Portable Electronics
!Microcontroller Input Protection
!WAN/LAN Equipment
!ESD protection to IEC 61000-4-2, Level 4
!Array of surge rated diodes with internal
EPD TVS diode
!Protects two I/O lines
!Low capacitance (<10pF) for high-speed interfaces
!Low leakage current (< 1µA)
!Low operating voltage: 2.8V
!Solid-state technology
!JEDEC SOT-143 package
!Molding compound flammability rating: UL 94V-0
!Marking : R2.8
!Packaging : Tape and Reel per EIA 481
Pin 4
Pin 2 Pin 3
Pin 1
1
23
4
SOT-143 (Top View)
22000 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
SR2.8
Absolute Maximum Rating
Electrical Characteristics
8.2RS
retemaraPlobmySsnoitidnoCmuminiMlacipyTmumixaMstinU
egatloVffO-dnatSesreveRV
MWR
8.2V
egatloVhguorhT-hcnuPV
TP
I
TP
Aµ2=0.3V
egatloVkcaB-panSV
BS
I
BS
Am05=8.2V
tnerruCegakaeLesreveRI
R
V
MWR
C°52=T,V8.2=1Aµ
egatloVgnipmalCV
C
I
PP
sµ02/8=pt,A1=0.5V
egatloVgnipmalCV
C
I
PP
sµ02/8=pt,A5=5.8V
tnerruCesluPkaePmumixaMI
PP
sµ02/8=pt41A
ecnaticapaCnoitcnuJC
j
dnasnipO/IneewteB dnG
V
R
zHM1=f,V0=
601Fp
snipO/IneewteB
V
R
zHM1=f,V0= 3Fp
gnitaRlobmySeulaVstinU
)sµ02/8=pt(rewoPesluPkaePP
kp
002sttaW
)sµ02/8=pt(tnerruCesluPkaePI
PP
41A
I(egatloVdrawroFkaeP
F
)sµ02/8=pt,A1=V
PF
5.1V
erutarepmeTgniredloSdaeLT
L
).ces01(062C°
erutarepmeTgnitarepOT
J
521+ot55-C°
erutarepmeTegarotST
GTS
051+ot55-C°
32000 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
SR2.8
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve
0.01
0.1
1
10
0.1 1 10 100 1000
Pulse Duration - tp (µ
µµ
µs)
Peak Pulse Power - PPP (kW)
0
10
20
30
40
50
60
70
80
90
100
110
0 25 50 75 100 125 150
Ambient Temperature - TA (oC)
% of Rated Power or I
PP
Clamping Voltage vs. Peak Pulse Current
0
10
20
30
40
50
60
70
80
90
100
110
0 5 10 15 20 25 30
Tim e (µ
µµ
µs)
Percent of IPP
e-t
td = IPP/2
Waveform
Parameters:
tr = 8 µs
td = 20µs
Pulse Waveform
Forward Voltage vs. Forward Current
0
2
4
6
8
10
12
14
16
18
20
0 5 10 15 20
P eak Pulse Curren t - I PP (A )
Clamping Voltage - VC (V)
Waveform
Parameters:
tr = 8µs
td = 20
µ
s
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35 40 45 50
Forward Curre nt - IF (A)
Forward Voltage - VF (V)
Waveform
Parameters:
tr = 8µs
td = 20
µ
s
42000 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
SR2.8
Data Line and Power Supply Protection Using Vcc as
reference
Data Line Protection with Bias and Power Supply
Isolation Resistor
Data Line Protection Using Internal T VS Diode as
Reference
Device Connection Options for Protection of Two
High-Speed Data Lines
The SR2.8 TVS is designed to protect two data lines
from transient over-voltages by clamping them to a
fixed reference. When the voltage on the protected
line exceeds the reference voltage (plus diode VF) the
steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 2 and 3. The nega-
tive reference (REF1) is connected at pin 1. This pin
should be connected directly to a ground plane on the
board for best results. The path length is kept as short
as possible to minimize parasitic inductance.
The positive reference (REF2) is connected at pin 4.
The options for connecting the positive reference are
as follows:
1. To protect data lines and the power line, connect
pin 4 directly to the positive supply rail (VCC). In this
configuration the data lines are referenced to the
supply voltage. The internal TVS diode prevents
over-voltage on the supply rail.
2. The SR2.8 can be isolated from the power supply
by adding a series resistor between pin 4 and VCC.
A value of 10kΩ is recommended. The internal
TVS and steering diodes remain biased, providing
the advantage of lower capacitance.
3. In applications where no positive supply reference
is available, or complete supply isolation is desired,
the internal TVS may be used as the reference. In
this case, pin 4 is not connected. The steering
diodes will begin to conduct when the voltage on
the protected line exceeds the working voltage of
the TVS (plus one diode drop).
Board Layout Considerations for ESD Protection
Board layout plays an important role in the suppression
of extremely fast rise-time ESD transients. Recall that
the voltage developed across an inductive load is
proportional to the time rate of change of current
through the load (V = L di/dt). The total clamping
voltage seen by the protected load will be the sum of
Applications Information
52000 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
SR2.8
PIN Descriptions
Applications Information (continued)
IPP
ISB
IPT
IR
VRWM VV PT VC
VBRR
IBRR
SB
Figure 1 - EPD TVS IV Characteristic Curve
the TVS clamping voltage and the voltage due to the
parasitic inductance (VC(TOT) = VC + L di/dt) . Parasitic
inductance in the protection path can result in signifi-
cant voltage overshoot, reducing the effectiveness of
the suppression circuit. An ESD induced transient for
example reaches a peak in approximately 1ns. For a
30A pulse (per IEC 61000-4-2 Level 4), 1nH of series
inductance will increase the effective clamping voltage
by 30V
(V = 1x10-9 (30/1x10-9)). For maximum effectiveness,
the following board layout guidelines are recom-
mended:
"Minimize the path length between the SR2.8 and
the protected line.
"Place the SR2.8 near the RJ45 connector to
restrict transient coupling in nearby traces.
"Minimize the path length (inductance) between the
RJ45 connector and the SR2.8.
EPD TVS Characteristics
The internal TVS of the SR2.8 is constructed using
Semtech’s proprietary EPD technology. The structure
of the EPD TVS is vastly different from the traditional
pn-junction devices. At voltages below 5V, high leak-
age current and junction capacitance render conven-
tional avalanche technology impractical for most
applications. However, by utilizing the EPD technology,
the SR2.8 can effectively operate at 2.8V while main-
taining excellent electrical characteristics.
The EPD TVS employs a complex nppn structure in
contrast to the pn structure normally found in tradi-
tional silicon-avalanche TVS diodes. The EPD mecha-
nism is achieved by engineering the center region of
the device such that the reverse biased junction does
not avalanche, but will “punch-through” to a conduct-
ing state. This structure results in a device with supe-
rior dc electrical parameters at low voltages while
maintaining the capability to absorb high transient
currents.
The IV characteristic curve of the EPD device is shown
in Figure 1. The device represents a high impedance
to the circuit up to the working voltage (VRWM). During a
transient event, the device will begin to conduct as it is
biased in the reverse direction. When the punch-
through voltage (VPT) is exceeded, the device enters a
low impedance state, diverting the transient current
away from the protected circuit. When the device is
conducting current, it will exhibit a slight “snap-back” or
negative resistance characteristic due to its structure.
This must be considered when connecting the device
to a power supply rail. To return to a non-conducting
state, the current through the device must fall below
the snap-back current (approximately < 50mA).
62000 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
SR2.8
10/100 Ethernet ESD Protection
10/100 Ethernet ICs are vulnerable to damage from electrostatic discharge (ESD). The fatal discharge may
originate from a charged cable (cable discharge event or CDE) or the body of a user. Charges can exceed
several thousand volts under the right conditions. If the circuit is left unprotected, the voltage will be capaci-
tively coupled thru the transformer, potentially damaging or latching-up the Ethernet Phy chip. The figure above
illustrates how to use the SR2.8 to protect one 10/100 Ethernet line pair. The devices are connected differen-
tially between transmit and receive line pairs. When the voltage on the data lines exceeds the TVS punch-
through (plus one diode drop), the internal rectifiers are forward biased conducting the transient current away
from the protected chip. The design takes advantage of the isolation provided by the line transformer to
suppress common mode surges.
Typical Applications
72000 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
SR2.8
Notes:
(1) Controlling dimension: Inch (unless otherwise specified).
(2) Dimension A and B do not include mold protrusions. Mold protrusions are .006” max.
Outline Drawing - SOT- 143
Land Pattern - SOT-143
82000 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
SR2.8
Contact Information
Semtech Corporation
Protection Products Division
652 Mitchell Rd., Newbury Park, CA 9 1320
Phone: (805)498-2111 FAX (805)498-3804
traP rebmuN gnikroW egatloV repytQ leeR eziSleeR
CT.8.2RSV8.2000,3hcnI7
GT.8.2RSV8.2000,01hcnI31
Marking Codes
rebmuNtraP gnikraM edoC
8.2RS8.2R
Ordering Information