CY5057 High-frequency Flash Programmable PLL Die with Spread Spectrum Features Benefits * Flash-programmable die for in-package programming of crystal oscillators Enables quick turnaround of custom oscillators, and lowers inventory costs through stocking blank parts. In addition, the part can be programmed up to 100 times, which reduces programming errors and provides an easy upgrade path for existing designs * High-resolution phase-locked loop (PLL) with 10-bit multiplier and seven-bit divider Enables synthesis of highly accurate and stable output clock frequencies with zero or low PPM * Flash-programmable capacitor tuning array Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal * Simple two-pin programming interface (excluding VDD and VSS pins) Allows the device to go into standard four- or six-pin packages. * On-chip oscillator used with external 25.1-MHz fundamental tuned crystal Lowers cost of oscillator, as PLL can be programmed to a high frequency using a low-frequency, low-cost crystal * Flash-programmable spread spectrum with eight discrete spread percentages and 30- to 33-kHz modulation frequencies Provides various spread percentage and modulation frequencies * Spread Spectrum On/Off function Provides ability to enable or disable Spread Spectrum with an external pin * Operating frequency -- 1-170 MHz at 3.3V 10% Services most PC, networking, and consumer applications * Seven-bit linear post divider with divide options from divide-by-2 to divide-by-127 Provides flexibility in output configurations and testing * Programmable PD# or OE pin Enables low-power operation or output enable function * Programmable asynchronous or synchronous OE and PD# modes Provides flexibility for system applications, through selectable instantaneous or synchronous change in outputs * Low jitter outputs -- < 200 ps (pk-pk) at 3.3V 10% Suitable for most PC, consumer, and networking applications * Controlled rise and fall times and output slew rate Has lower EMI than oscillators Die Pad Description VDD 1 10 VDD 2 9 SSON# OUT XOUT 3 8 NC Y Note: Active Die Size: X=77 mils / 1956 um Y= 67mils / 1702 um XIN 4 7 VSS PD#/OE 5 6 VSS Scribe: X ,Y = 2.567 mils / 65 um Bond pad opening: 85 um x 85 um Pad pitch: 125 um x 125 um (Pad center to pad center) X Cypress Semiconductor Corporation Document #: 38-07363 Rev. ** * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised April 26, 2002 CY5057 XIN XOUT SSON# Crystal Osc with 10-bit Cap Array 7-bit /Q 10-bit /P 7-bit Output Divider Block 100 to 400MHz PLL OUT Spread Spectrum PD#/OE Flash Configuration/ Spread Spectrum Storage Die Pad Summary Name Die Pad Description VDD 1,2 Power supply VSS 6,7 Ground XIN 4 Crystal gate pin XOUT 3 Crystal drain pin PD#/OE 5 Flash-programmable to function as power down or output enable. Acts as the VPP (super voltage) input and data pin in programming mode. There is an internal pull-up resistor on this pin. SSON# 10 Active LOW Spread Spectrum control. Asserting LOW turns the internal modulation waveform on. Acts as the clock pin in programming mode. Should be double bonded to the OUT pad for pinouts not using the SSON# function. There is an internal pull-down resistor on this pad. OUT 9 Clock output. There is an internal pull-down resistor on this pad. NC 8 No connect pin. (Do not connect this pad.) Functional Description The CY5057 is a flash-programmable, high-accuracy, PLL-based die designed for the crystal oscillator market. It also contains Spread Spectrum circuitry that can be enabled or disabled with an external pin. The die is packaged with a low-cost 25.1-MHz fundamental tuned crystal in a four- or six-pin through-hole or surface mount package. The oscillator devices can be stocked as blank parts and custom frequencies can be programmed in-package at the last stage before shipping. This enables fast-turn manufacturing of custom and standard crystal oscillators without the need for dedicated, expensive crystals. The CY5057 contains an on-chip oscillator and unique oscillator tuning circuit for fine-tuning the output frequency. The crystal Cload can be selectively adjusted by programming a set of flash memory bits. This feature can be used to compensate for crystal variations or to obtain a more accurate synthesized frequency. The CY5057 uses a simple two-pin programming interface excluding the VSS and VDD pins. Clock outputs can be generated from 1 MHz to 170 MHz at 3.3V 10% operating voltage. The entire Flash configuration can be reprogrammed multiple times, allowing programmed inventory to be altered or reused. Document #: 38-07363 Rev. ** The CY5057 PLL die has been designed for very high resolution. It has a 10-bit feedback counter multiplier and a seven-bit reference counter divider. This enables the synthesis of highly accurate and stable output clock frequencies with zero or low PPM error. The output of the PLL or the oscillator can be further modified by a seven-bit linear post divider with a total of 126 divider options (2 to 127). The CY5057 also contains flexible power management controls. These parts include both power-down mode (PD# = 0) and output enable mode (OE = 1). The power-down and output enable modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable the CY5057 to have low jitter and accurate outputs making it suitable for most PC, networking and consumer applications. The CY5057 also has an additional spread spectrum feature that can be disabled or enabled with an external pin. Please refer to Spread Spectrum section for details. Flash Configuration and Spread Spectrum Storage Block The following table summarizes the features which are configurable by flash memory bits. Please refer to the "CY5057 Page 2 of 9 CY5057 Programming Specification" for programming details. The specification can be obtained from your Cypress factory representative. powerdown or output disable occurs immediately (allowing for logic delays) irrespective of position in the clock cycle. However, when the synchronous setting is used, the part waits for a falling edge at the output before powerdown or output enable signal initiated, thus preventing output glitches. In either asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of the output. Flash Programmable Features Feedback counter value (P) Reference counter value (Q) Output divider selection Oscillator Tuning (load capacitance values) Oscillator direct output Power management mode (OE or PD#) Power management timing (synchronous or asynchronous) Spread Spectrum Adjust Frequency Spread Spectrum The CY5057 contains spread spectrum with flash programmable spread percentage and modulation frequency. Center spread non-linear "Hershey kiss" style modulation can be obtained. The modulation frequency range is limited from 30 to 33 kHz. Eight discrete levels of spread percentage are delivered. PLL Output Frequency The CY5057 has a spread spectrum On/Off function. The spread spectrum can be enabled or disabled by users through an external pin. Timing of this feature is shown in "switching waveform" section. The CY5057 contains a high-resolution PLL with a 10-bit multiplier and a seven-bit divider.The output frequency of the PLL is determined by the following formula: 2 * ( P BL + 4 ) + Po FPLL = ------------------------------------------------ * F REF (QL + 2) Generic spread spectrum profile programming software is not available to customers at this time. The modulation profiles for the eight discrete spread percentages are given in the "Spread Spectrum Profile" section and will be delivered by the factory. Crystal Oscillator Tuning Cap Values where QL is the loaded or programmed reference counter value (Q counter), PBL is the loaded or programmed feedback counter value (P counter), and Po is the P offset bit (can only be 0 or 1). In Spread Spectrum mode, the time-averaged P value is used to calculate the average frequency. Bit Capacitance per Bit (pF) 24.32 12.16 6.08 3.04 1.52 0.76 0.38 0.19 0.095 0.0475 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Power Management Features The CY5057 contains Flash-programmable PD# (active LOW) and OE (active HIGH) functions. If power-down mode is selected (PD# = 0), the oscillator and PLL are placed in a low supply current standby mode and the output is tri-stated and weakly pulled low. The oscillator and PLL circuits must re-lock when the part leaves Powerdown Mode. If output enable mode is selected (OE = 0), the output is tri-stated and weakly pulled low. In this mode the oscillator and PLL circuits continue to operate, allowing a rapid return to normal operation when the output is enabled. In addition, the PD# and OE modes can be programmed to occur synchronously or asynchronously with respect to the output signal. When the asynchronous setting is used, the RF XIN XOUT CXOUT CXIN C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 Figure 1. Crystal Oscillator Tuning Circuit Document #: 38-07363 Rev. ** Page 3 of 9 CY5057 Spread Spectrum Profile Tables The modulation profile information based on the eight discrete spreads (table below) and 16 nominal output frequencies (table below) will be delivered to customers. The input reference is limited to 25.1 MHz only. Only one spread profile (for one specific percentage spread and for one output frequency) can be programmed into the device. Spread Percentage (Center Spread Only) + 0.250% + 0.500% + 0.625% + 0.750% + 1.00% + 1.25% + 1.50% + 2.00% Document #: 38-07363 Rev. ** Output Nominal Frequency (Spread On) Fnom = 6.00MHz, Center spread Fnom = 20.00MHz, Center spread Fnom = 20.75MHz, Center spread Fnom = 24.00MHz, Center spread Fnom = 24.576MHz, Center spread Fnom = 33.00MHz, Center spread Fnom = 33.3333MHz, Center spread Fnom = 50.00MHz, Center spread Fnom = 65.7408MHz, Center spread Fnom = 66.00MHz, Center spread Fnom = 66.6666MHz, Center spread Fnom = 75.00MHz, Center spread Fnom = 80.00MHz, Center spread Fnom = 100.00MHz, Center spread Fnom = 120.00MHz, Center spread Fnom = 166.00MHz, Center spread Page 4 of 9 CY5057 Storage Temperature (Non-condensing) .... -55C to +125C Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature ................................ -40C to +100C Data Retention @ Tj = 125C................................> 10 years Supply Voltage ..................................................-0.5 to +7.0V Maximum Programming Cycles........................................100 Input Voltage ............................................ -0.5V to VDD + 0.5 Static Discharge Voltage ......................................... > 2000V (per MIL-STD-883, Method 3015) Operating Conditions Parameter Description Min. Max. Unit VDD Supply Voltage (3.3V) 3.0 3.6 V TAJ [1] Operating Temperature, Junction -40 100 C CLC Max. Capacitive Load on the output (CMOS levels spec) VDD = 3.0V-3.6V, output frequency = 1-170 MHz 15 pF XREF Reference Frequency with spread spectrum disabled. Fundamental tuned crystals only. 25.1 25.1 MHz Cin Input Capacitance (except crystal pins) 7 pF CXIN Crystal input capacitance (all internal caps off) 10 14 pF CXout Crystal output capacitance (all internal caps off) 10 14 pF DC Electrical Characteristics, Tj = -40 to 100C Parameter Description Test Conditions Min. Max. Unit 0.3 VDD VIL Input Low Voltage PD#/OE and SSON# pins CMOS levels, 30% of VDD VDD = 3.0V-3.6V VIH Input High Voltage PD#/OE and SSON# pins CMOS levels, 70% of VDD VDD = 3.0V-3.6V VOL Output Low voltage, OUT pin VDD = 3.0V-3.6V, IOL = 8 mA VOH Output high voltage, CMOS levels VDD = 3.0V-3.6V, IOH = -8 mA IILPDOE Input Low Current, PD#/OE pin VIN = VSS (Internal pull-up = 100k typical) 50 A IIHPDOE Input High Current, PD#/OE pin 10 A IILSR Input Low Current, SSON# pin VIN = VSS (Internal pull-down = 100k typical) 10 A IIHSR Input High Current, SSON# pin VIN = VDD (Internal pull-down = 100k typical) 50 A IDD Supply current No Load, VDD = 3.0V-3.6V, Fout = 170 MHz 50 mA IOZ Output leakage current, OUT pin VDD = 3.0V-3.6V, Output disabled with OE 50 A IPD Stand by current VDD = 3.0V-3.6V, Device powered down with PD# 75 A RUP Pull-up resistor on PD#/OE pin VDD = 3.0V-3.6V, measured at VIN = 0.5VDD 80 150 k RDN Pull-down resistor on SSON# VDD = 3.0V-3.6V, measured at VIN = 0.5VDD and OUT pins 80 150 k Rf Crystal Feedback Resistor 0.7 0.4 VDD - 0.4 VIN = VDD (Internal pull-up = 100k typical) VDD = 3.0V-3.6V, measured at VDD/2. VDD 200 V V k Note: 1. In Cypress standard TSSOP packages with external crystal. Document #: 38-07363 Rev. ** Page 5 of 9 CY5057 AC Electrical Characteristics Tj = -40 to 100C Parameter [1] Description Test Conditions Min. Max. Unit 1 170 MHz 2.7 ns 2.7 ns 55 60 % % Fout Output Frequency 15 pF Load, VDD = 3.0 to 3.6V tr OUT rise time VDD = 3.0V-3.6V, 20% to 80% VDD tf OUT fall time VDD = 3.0V-3.6V, 80% to 20% VDD DC OUT Duty Cycle Divider output, Measured at VDD/2 Crystal direct output, Measured at VDD/2 tJ1[2] Peak to Peak Period Jitter Fout >133 MHz, VDD/2, SS off. 25 MHz < Fout< 133 MHz, VDD/2, SS off. Fout< 25MHz, VDD/2, SS off. 200 400 1% of 1/Fout ps ps s tJ2[2] Cycle to Cycle Jitter Fout >133 MHz, VDD/2, SS on. 25MHz < Fout< 133 MHz, VDD/2, SS on. Fout< 25 MHz, VDD/2, SS on. 200 400 1% of 1/Fout ps ps s FMOD Modulation frequency 33 kHz DL Crystal drive level Measured at 25.1 MHz, with 20 R, CLOAD = 10 pF 150 W -R Negative Resistance Measured at 25.1 MHz -300 Max. Unit 45 40 30 Timing Parameters[1] Parameter Description Min. TSSON1 Time from steady state spread to steady state non-spread 100 us TSSON2 Time from steady state non-spread to steady state spread 100 us TSSON3 Minimum SSON# pulse width (positive or negative) 250 TMOD Spread Spectrum Modulation period 30 33.33 us TSTP,SYNC Time from falling edge on PD# to stopped outputs, synchronous mode, T = 1/Fout T + 350 ns TSTP,ASYNC Time from falling edge on PD# to stopped outputs, asynchronous mode 350 ns TPU,SYNC Time from rising edge on PD# to outputs at valid frequency, synchronous mode 3 ms TPU,ASYNC Time from rising edge on PD# to outputs at valid frequency, asynchronous mode 3 ms TPXZ,SYNC Time from falling edge on OE to high-impedance outputs, synchronous mode, T = 1/Fout T+350 ns TPXZ,ASYNC Time from falling edge on OE to high-impedance outputs, asynchronous mode 350 ns TPZX,SYNC Time from rising edge on OE to running outputs, synchronous mode, T=1/Fout 1.5T + 350 ns TPZX,ASYNC Time from rising edge on OE to running outputs, asynchronous mode 350 ns TPU Power-up time 10 ms us Notes: 2. The jitter spec might be adjusted after the first silicon characterization. Document #: 38-07363 Rev. ** Page 6 of 9 CY5057 Switching Waveforms Duty Cycle Timing (dc) t1A OUTPUT t1B Output Rise/Fall Time VDD OUTPUT 0V tr tf Power-down Timing (synchronous and asynchronous modes) and Power-up Timing POWER DOWN VDD VIH VIL 0V tPU High Impedance CLKOUT (synchronous) weakly pulled low T tSTP 1/f High Impedance CLKOUT (asynchronous) weakly pulled low tSTP 1/f Output Enable Timing (synchronous and asynchronous modes) VDD OUTPUT ENABLE VIH VIL 0V T High Impedance CLKOUT (synchronous) weakly pulled low tPXZ CLKOUT (asynchronous) weakly pulled low tPXZ Document #: 38-07363 Rev. ** tPZX High Impedance tPZX Page 7 of 9 CY5057 Switching Waveforms (continued) Spread Spectrum On/OFF Timing SSON# T SSON3 +100% Internal Modulation W aveform T SSON1 T SSON2 0% -100% Ordering Information Die Information Wafer Thickness 14 0.5 mils Ordering Code Type Operating Range CY5057WAF Wafer -40C to 100C All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07363 Rev. ** Page 8 of 9 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY5057 Document Title: CY5057 High-frequency Flash Programmable PLL Die with Spread Spectrum Document Number: 38-07363 REV. ECN NO. Issue Date Orig. of Change ** 112486 05/01/02 CKN Document #: 38-07363 Rev. ** Description of Change New Data Sheet Page 9 of 9