2019 Microchip Technology Inc. DS20006228A-page 1
MCP14A1201/2
Features
• High Peak Output Current: 12.0A (typical)
• Wide Input Supply Voltage Operating Range:
- 4.5V to 18V
• Low Shoot-Through/Cross-Conduction Current in
Output Stage
• High Capacitive Load Drive Capability:
- 15,000 pF in 25 ns (typical)
• Short Delay Times: 28 ns (tD1), 28 ns (tD2) (typical)
• Low Supply Current: 360 µA (typical)
• Low-Voltage Threshold Input and Enable with
Hysteresis
• Latch-Up Protected: Withstands 500 mA Reverse
Current
• Space-Saving Packages:
- 8-Lead MSOP
- 8-Lead SOIC
- 8-Lead 2 x 3 TDFN
Applications
• Switch Mode Power Supplies
• Pulse Transformer Drive
• Line Drivers
• Level Translator
• Motor and Solenoid Drive
General Description
The MCP14A1201/2 devices are high-speed MOSFET
drivers that are capable of providing up to 12.0A of
peak current while operating from a single 4.5V to 18V
supply. There are two output configurations available;
inverting (MCP14A1201) and noninverting
(MCP14A1202). These devices feature low shoot-
through current, fast rise and fall times, and matched
propagation delays which make them ideal for high
switching frequency applications.
The MCP14A1201/2 family of devices offers enhanced
control with Enable functionality. The active-high
Enable pin can be driven low to drive the output of the
MCP14A1201/2 low, regardless of the status of the
Input pin. An integrated pull-up resistor allows the user
to leave the Enable pin floating for standard operation.
These devices are highly latch-up resistant under any
condition within their power and voltage ratings. They
can accept up to 500 mA of reverse current being
forced back into their outputs without damage or logic
upset. All terminals are fully protected against
electrostatic discharge (ESD) up to 2 kV (HBM) and
200V (MM).
Package Types
* Includes Exposed Thermal Pad (EP); see Table 3-1.
MCP14A1201/MCP14A1202
2 x 3 TDFN*
EN
IN
GND
OUT/OUT
OUT/OUT
1
2
3
4
8
7
6
5GND
VDD
VDD
EP
9
MCP14A1201/MCP14A1202
MSOP/SOIC
EN
IN
GND
OUT/OUT
OUT/OUT
1
2
3
4
8
7
6
5GND
VDD
VDD
12.0A MOSFET Driver with Low Threshold Input and Enable
MCP14A1201/2
DS20006228A-page 2 2019 Microchip Technology Inc.
Functional Block Diagram
Non-Inverting
Enable
Input
VDD
Output-Pin 7
Inverting
VREF
VREF
VDD
GND
Internal
Pull-Up
MCP14A1201 Inverting
MCP14A1202 NonLnverting
GND
Output – Pin 6
2019 Microchip Technology Inc. DS20006228A-page 3
MCP14A1201/2
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD, Supply Voltage.............................................+20V
VIN, Input Voltage...........(VDD + 0.3V) to (GND - 0.3V)
VEN, Enable Voltage....... (VDD + 0.3V) to (GND - 0.3V)
Package Power Dissipation (TA = +50°C)
8L MSOP .....................................................0.63 W
8L SOIC .......................................................1.00 W
8L 2 x 3 TDFN.............................................. 1.86 W
ESD Protection on all pins .........................2 kV (HBM)
....................................................................200V (MM)
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational sections of this
specification is not intended. Exposure to maximum
rating conditions for extended periods may affect
device reliability.
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, TA = +25°C, with 4.5V VDD 18V.
Parameters Sym. Min. Typ. Max. Units Conditions
Input
Input Voltage Range VIN GND - 0.3V — VDD + 0.3 V
Logic ‘1’ High Input Voltage VIH 2.0 1.6 — V
Logic ‘0’ Low Input Voltage VIL —1.30.8V
Input Voltage Hysteresis VHYST(IN) —0.3— V
Input Current IIN -1 — +1 µA 0V VIN VDD
Enable
Enable Voltage Range VEN GND - 0.3V — VDD + 0.3 V
Logic ‘1’ High Enable Voltage VEH 2.0 1.6 — V
Logic ‘0’ Low Enable Voltage VEL —1.30.8V
Enable Voltage Hysteresis VHYST(EN) —0.3— V
Enable Pin Pull-Up Resistance RENBL —1.8—MΩVDD = 18V, ENB = GND
Enable Input Current IEN —10—µAV
DD = 18V, ENB = GND
Propagation Delay tD3 —2833nsV
DD = 18V, VEN = 5V,
see Figure 4-3, (Note 1)
Propagation Delay tD4 —2833nsV
DD = 18V, VEN = 5V,
see Figure 4-3, (Note 1)
Output
High Output Voltage VOH VDD - 0.025 — — V IOUT = 0A
Low Output Voltage VOL ——0.025VI
OUT = 0A
Output Resistance, High ROH —0.91.5ΩIOUT = 10 mA, VDD = 18V
Output Resistance, Low ROL —0.61.2ΩIOUT = 10 mA, VDD = 18V
Peak Output Current IPK —12.0— AV
DD = 18V (Note 1)
Latch-Up Protection Withstand
Reverse Current
IREV 0.5 — — A Duty cycle 2%, t 300 µs
(Note 1)
Switching Time (Note 1)
Rise Time tR—2530nsV
DD = 18V, CL = 15,000 pF,
see Figure 4-1, Figure 4-2
Fall Time tF—2530nsV
DD = 18V, CL = 15,000 pF,
see Figure 4-1, Figure 4-2
Note 1: Tested during characterization, not production tested.
MCP14A1201/2
DS20006228A-page 4 2019 Microchip Technology Inc.
Delay Time tD1 —2833nsV
DD = 18V, VIN = 5V, see
Figure 4-1 and Figure 4-2
tD2 —2833nsV
DD = 18V, VIN = 5V, see
Figure 4-1 and Figure 4-2
Power Supply
Supply Voltage VDD 4.5 — 18 V
Power Supply Current
IDD — 360 600 µA VIN = 3V, VEN = 3V
IDD — 360 600 µA VIN = 0V, VEN = 3V
IDD — 360 600 µA VIN = 3V, VEN = 0V
IDD — 360 600 µA VIN = 0V, VEN = 0V
DC CHARACTERISTICS (OVER OPERATING TEMPERATURE RANGE)
Electrical Specifications: Unless otherwise indicated, over the operating range with 4.5V VDD 18V.
Parameters Sym. Min. Typ. Max. Units Conditions
Input
Input Voltage Range VIN GND - 0.3V — VDD + 0.3 V
Logic ‘1’ High Input Voltage VIH 2.0 1.6 — V
Logic ‘0’ Low Input Voltage VIL —1.30.8V
Input Voltage Hysteresis VHYST(IN) —0.3—V
Input Current IIN -10 — +10 µA 0V VIN VDD
Enable
Enable Voltage Range VEN GND - 0.3V — VDD + 0.3 V
Logic ‘1’ High Enable Voltage VEH 2.0 1.6 — V
Logic ‘0’ Low Enable Voltage VEL —1.30.8V
Enable Voltage Hysteresis VHYST(EN) —0.3—V
Enable Input Current IEN —12—µAV
DD = 18V, ENB = GND
Propagation Delay tD3 —3237nsV
DD = 18V, VEN = 5V, TA = +125°C,
see Figure 4-3, (Note 1)
Propagation Delay tD4 —3237nsV
DD = 18V, VEN = 5V, TA = +125°C,
see Figure 4-3, (Note 1)
Output
High Output Voltage VOH VDD - 0.025 — — V DC Test
Low Output Voltage VOL — — 0.025 V DC Test
Output Resistance, High ROH ——2ΩIOUT = 10 mA, VDD = 18V
Output Resistance, Low ROL ——1.7ΩIOUT = 10 mA, VDD = 18V
Note 1: Tested during characterization, not production tested.
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TA = +25°C, with 4.5V VDD 18V.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: Tested during characterization, not production tested.
2019 Microchip Technology Inc. DS20006228A-page 5
MCP14A1201/2
Switching Time (Note 1)
Rise Time tR—3035nsV
DD = 18V, CL = 15,000 pF,
TA = +125°C, see Figure 4-1,
Figure 4-2
Fall Time tF—3035nsV
DD = 18V, CL = 15,000 pF,
TA = +125°C, see Figure 4-1,
Figure 4-2
Delay Time tD1 —3237nsV
DD = 18V, VIN = 5V, TA = +125°C,
see Figure 4-1, Figure 4-2
tD2 —3237nsV
DD = 18V, VIN = 5V, TA = +125°C,
see Figure 4-1, Figure 4-2
Power Supply
Supply Voltage VDD 4.5 — 18 V
Power Supply Current
IDD ——750uAV
IN = 3V, VEN = 3V
IDD ——750uAV
IN = 0V, VEN = 3V
IDD ——750uAV
IN = 3V, VEN = 0V
IDD ——750uAV
IN = 0V, VEN = 0V
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply with 4.5V VDD 18V
Parameter Sym. Min. Typ. Max. Units Comments
Temperature Ranges
Specified Temperature Range TA-40 — +125 °C
Maximum Junction Temperature TJ——+150°C
Storage Temperature Range TA-65 — +150 °C
Package Thermal Resistances
Junction-to-Ambient Thermal Resistance, 8LD MSOP JA —158—°C/WNote 1
Junction-to-Ambient Thermal Resistance, 8LD SOIC JA —99.8—°C/WNote 1
Junction-to-Ambient Thermal Resistance, 8LD TDFN JA —53.7—°C/WNote 1
Junction-to-Top Characterization Parameter, 8LD MSOP JT —2.4—°C/WNote 1
Junction-to-Top Characterization Parameter, 8LD SOIC JT —5.9—°C/WNote 1
Junction-to-Top Characterization Parameter, 8LD TDFN JT —0.5—°C/WNote 1
Junction-to-Board Characterization Parameter, 8LD MSOP JB —115.2—°C/WNote 1
Junction-to-Board Characterization Parameter, 8LD SOIC JB —64.8—°C/WNote 1
Junction-to-Board Characterization Parameter, 8LD TDFN JB —24.4—°C/WNote 1
Note 1: Parameter is determined using High K 2S2P 4-Layer board as described in JESD 51-7, as well as JESD
51-5 for packages with exposed pads.
DC CHARACTERISTICS (OVER OPERATING TEMPERATURE RANGE) (CONTINUED)
Electrical Specifications: Unless otherwise indicated, over the operating range with 4.5V VDD 18V.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: Tested during characterization, not production tested.
MCP14A1201/2
DS20006228A-page 6 2019 Microchip Technology Inc.
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V.
FIGURE 2-1: Rise Time vs. Supply
Voltage.
FIGURE 2-2: Rise Time vs. Capacitive
Load.
FIGURE 2-3: Fall Time vs. Supply
Voltage.
FIGURE 2-4: Fall Time vs. Capacitive
Load.
FIGURE 2-5: Rise and Fall Time vs.
Temperature.
FIGURE 2-6: Crossover Current vs.
Supply Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
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MCP14A1201/2
Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V.
FIGURE 2-7: Input Propagation Delay vs.
Supply Voltage.
FIGURE 2-8: Input Propagation Delay
Time vs. Input Amplitude.
FIGURE 2-9: Input Propagation Delay vs.
Temperature.
FIGURE 2-10: Enable Propagation Delay
vs. Supply Voltage.
FIGURE 2-11: Enable Propagation Delay
Time vs. Enable Voltage Amplitude.
FIGURE 2-12: Enable Propagation Delay
vs. Temperature.
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DS20006228A-page 8 2019 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V.
FIGURE 2-13: Quiescent Supply Current
vs. Supply Voltage.
FIGURE 2-14: Quiescent Supply Current
vs. Temperature.
FIGURE 2-15: Input Threshold vs.
Temperature.
FIGURE 2-16: Input Threshold vs. Supply
Voltage.
FIGURE 2-17: Enable Threshold vs.
Temperature.
FIGURE 2-18: Enable Threshold vs.
Supply Voltage.
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2019 Microchip Technology Inc. DS20006228A-page 9
MCP14A1201/2
Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V.
FIGURE 2-19: Output Resistance (Output
High) vs. Supply Voltage.
FIGURE 2-20: Output Resistance (Output
Low) vs. Supply Voltage.
FIGURE 2-21: Supply Current vs.
Capacitive Load (VDD = 18V).
FIGURE 2-22: Supply Current vs.
Capacitive Load (VDD = 12V).
FIGURE 2-23: Supply Current vs.
Capacitive Load (VDD = 6V).
FIGURE 2-24: Supply Current vs.
Frequency (VDD = 18V).
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DS20006228A-page 10 2019 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V.
FIGURE 2-25: Supply Current vs.
Frequency (VDD = 12V).
FIGURE 2-26: Supply Current vs.
Frequency (VDD = 6V).
FIGURE 2-27: Enable Current vs. Supply
Voltage.
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2019 Microchip Technology Inc. DS20006228A-page 11
MCP14A1201/2
3.0 12.0A PIN DESCRIPTIONS
The descriptions of the pins are listed in Tabl e 3-1.
3.1 Supply Input Pin (VDD)
VDD is the bias supply input for the MOSFET driver and
has a voltage range of 4.5V to 18V. This input must be
decoupled to ground with a local capacitor. This bypass
capacitor provides a localized low-impedance path for
the peak currents that are provided to the load.
3.2 Control Input Pin (IN)
The MOSFET driver Control Input is a high-impedance
input featuring low threshold levels. The Input also has
hysteresis between the high and low input levels,
allowing them to be driven from slow rising and falling
signals and to provide noise immunity.
3.3 Device Enable Pin (EN)
The MOSFET driver Device Enable is a high-
impedance input featuring low threshold levels. The
Enable input also has hysteresis between the high and
low input levels, allowing them to be driven from slow
rising and falling signals and to provide noise immunity.
Driving the Enable pin below the threshold will disable
the output of the device, pulling OUT/OUT low,
regardless of the status of the Input pin. Driving the
Enable pin above the threshold allows normal
operation of the OUT/OUT pin based on the status of
the Input pin. The Enable pin utilizes an internal pull up
resistor, allowing the pin to be left floating for standard
driver operation.
3.4 Power Ground Pin (GND)
GND is the device return pin for the input and output
stages. The GND pin should have a low-impedance
connection to the bias supply source return. When the
capacitive load is being discharged, high peak currents
will flow through the ground pin.
3.5 Output Pin (OUT, OUT)
The Output is a CMOS push-pull output that is capable
of sourcing and sinking 12.0A of peak current
(VDD = 18V). The low output impedance ensures the
gate of the external MOSFET stays in the intended
state even during large transients. This output also has
a reverse current latch-up rating of 500 mA.
3.6 Exposed Metal Pad Pin (EP)
The exposed metal pad of the DFN package is
internally connected to GND. Therefore, this pad
should be connected to a Ground plane to aid in heat
removal from the package.
TABLE 3-1: PIN FUNCTION TABLE
MCP14A1201/2
Symbol Description
8L 2 x 3 TDFN 8L MSOP/SOIC
1 1 VDD Supply Input
2 2 IN Control Input
3 3 EN Device Enable
4 4 GND Power Ground
5 5 GND Power Ground
6 6 OUT/OUT Push-Pull Output
7 7 OUT/OUT Push-Pull Output
8 8 VDD Supply Input
EP —EP Exposed Thermal Pad (GND)
MCP14A1201/2
DS20006228A-page 12 2019 Microchip Technology Inc.
4.0 APPLICATION INFORMATION
4.1 General Information
MOSFET drivers are high-speed, high-current devices
which are intended to source/sink high-peak currents to
charge/discharge the gate capacitance of external
MOSFETs or Insulated-Gate Bipolar Transistors
(IGBTs). In high frequency switching power supplies,
the Pulse-Width Modulation (PWM) controller may not
have the drive capability to directly drive the power
MOSFET. A MOSFET driver such as the
MCP14A1201/2 family can be used to provide
additional source/sink current capability.
4.2 MOSFET Driver Timing
The ability of a MOSFET driver to transition from a fully-
off state to a fully-on state is characterized by the
driver’s rise time (tR), fall time (tF) and propagation
delays (tD1 and tD2). Figure 4-1 and Figure 4-2 show
the test circuit and timing waveform used to verify the
MCP14A1201/2 timing.
FIGURE 4-1: Inverting Driver Timing
Waveform.
FIGURE 4-2: Noninverting Driver Timing
Waveform.
4.3 Enable Function
The enable pin (EN) provides additional control of the
output pin (OUT). This pin is active high and is
internally pulled up to VDD so that the pin can be left
floating to provide standard MOSFET driver operation.
When the enable pin’s input voltage is above the
enable pin high voltage threshold, (VEN_H), the output
is enabled and allowed to react to the status of the Input
pin. However, when the voltage applied to the Enable
pin falls below the low threshold voltage (VEN_L), the
driver’s output is disabled and does not respond to
changes in the status of the Input pin. When the driver
is disabled, the output is pulled down to a low state.
Refer to Table 4-1 for enable pin logic. The threshold
voltage levels for the Enable pin are similar to the
threshold voltage levels of the Input pin. Hysteresis is
provided to help increase the noise immunity of the
enable function, avoiding false triggers of the enable
signal during driver switching.
There are propagation delays associated with the
driver receiving an enable signal and the output
reacting. These propagation delays, tD3 and tD4, are
graphically represented in Figure 4-3.
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MCP14A1201/2
FIGURE 4-3: Enable Timing Waveform.
4.4 Decoupling Capacitors
Careful PCB layout and decoupling capacitors are
required when using power MOSFET drivers. Large
currents are required to charge and discharge
capacitive loads quickly. For example, approximately
720 mA are needed to charge a 1000 pF load with 18V
in 25 ns.
To operate the MOSFET driver over a wide frequency
range with low supply impedance, it is recommended to
place 1.0 µF and 0.1 µF low ESR ceramic capacitors in
parallel between the driver VDD and GND. These
capacitors should be placed close to the driver to
minimize circuit board parasitics and provide a local
source for the required current.
4.5 PCB Layout Considerations
Proper Printed Circuit Board (PCB) layout is important
in high-current, fast-switching circuits to provide proper
device operation and robustness of design. Improper
component placement may cause errant switching,
excessive voltage ringing or circuit latch-up. The PCB
trace loop length and inductance should be minimized
by the use of ground planes or traces under the
MOSFET gate drive signal. Separate analog and
power grounds and local driver decoupling should also
be used.
Placing a ground plane beneath the MCP14A1201/2
devices will help as a radiated noise shield, as well as
providing some heat sinking for power dissipated within
the device.
4.6 Power Dissipation
The total internal power dissipation in a MOSFET driver
is the summation of three separate power dissipation
elements, as shown in Equation 4-1.
EQUATION 4-1:
4.6.1 CAPACITIVE LOAD DISSIPATION
The power dissipation caused by a capacitive load is a
direct function of the frequency, total capacitive load
and supply voltage. The power lost in the MOSFET
driver for a complete charging and discharging cycle of
a MOSFET is shown in Equation 4-2.
EQUATION 4-2:
4.6.2 QUIESCENT POWER DISSIPATION
The power dissipation associated with the quiescent
current draw depends on the state of the Input and
Enable pins. See Section 1.0 “Electrical
Characteristics” for typical quiescent current draw
values in different operating states. The quiescent
power dissipation is shown in Equation 4-3.
EQUATION 4-3:
TABLE 4-1: ENABLE PIN LOGIC
ENB IN MCP14A1201
OUT
MCP14A1202
OUT
HH L H
HL H L
LX L L
t
D3
10%
90%
Enable
Output
5V
18V
0V
0V
V
EH
(Typ.) V
EL
(Typ.)
t
D4
Enable Signa l: tRI SE = tFALL ≤ 10 ns,
100 Hz, 0-5V Square Wave
PTPLPQPCC
++=
Where:
PT= Total power dissipation
PL= Load power dissipation
PQ= Quiescent power dissipation
PCC = Operating power dissipation
PLfC
T
VDD
2
=
Where:
f = Switching frequency
CT= Total load capacitance
VDD = MOSFET driver supply voltage
PQIQH DI
QL 1D–
+
VDD
=
Where:
IQH = Quiescent current in the High state
D = Duty cycle
IQL = Quiescent current in the Low state
VDD = MOSFET driver supply voltage
MCP14A1201/2
DS20006228A-page 14 2019 Microchip Technology Inc.
4.6.3 OPERATING POWER DISSIPATION
The operating power dissipation occurs each time the
MOSFET driver output transitions because, for a very
short period of time, both MOSFETs in the output stage
are on simultaneously. This cross-conduction current
leads to a power dissipation described in Equation 4-4.
EQUATION 4-4:
PCC VDD ICO
=
Where:
ICO = Crossover Current
VDD = MOSFET driver supply voltage
2019 Microchip Technology Inc. DS20006228A-page 15
MCP14A1201/2
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over
to the next line, thus limiting the number of available characters for customer-specific
information.
3
e
3
e
8-Lead MSOP
NNN
8-Lead SOIC
8-Lead TDFN (2 x 3) Example:
EM3
925
25
Device Code
MCP14A1201-E/MS A1201
MCP14A1201T-E/MS A1201
MCP14A1202-E/MS A1202
MCP14A1202T-E/MS A1202
Note: Applies to 8-Lead MSOP
Device Code
MCP14A1201-E/SN 14A1201
MCP14A1201T-E/SN 14A1201
MCP14A1202-E/SN 14A1202
MCP14A1202T-E/SN 14A1202
Note: Applies to 8-Lead SOIC
Device Code
MCP14A1201T-E/MNY EM3
MCP14A1202T-E/MNY EM4
Note: Applies to 8-Lead 2 x 3 TDFN
A01
5256
Example
Example
14A1201
1925
256
3
e
MCP14A1201/2
DS20006228A-page 16 2019 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc. DS20006228A-page 17
MCP14A1201/2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging