X40431V14I-AT1 - Intersil Corporation

FN8251.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X40430, X40431, X40434, X40435

4Kbit EEPROM

Triple Voltage Monitor with Integrated

CPU Supervisor

FEATURES

• Monitoring voltages: 5V to 9V

• Independent core voltage monitor

• Triple voltage detection and reset assertion

—Standard reset threshold settings. See selec-

tion table on page 2.

—Adjust low voltage reset threshold voltages

using special programming sequence

—Reset signal valid to VCC = 1V

—Monitor three separate voltages

• Fault detection register

• Selectable power-on reset timeout

(0.05s, 0.2s, 0.4s, 0.8s)

• Selectable watchdog timer interval

(25ms, 200ms, 1.4s or off)

• Debounced manual reset input

• Low power CMOS

—25µA typical standby current, watchdog on

—6µA typical standby current, watchdog off

• Memory security

• 4Kbits of EEPROM

—16 byte page write mode

—5ms write cycle time (typical)

• Built-in inadvertent write protection

—Power-up/power-down protection circuitry

—Block lock protect 0, or 1/2, of EEPROM

• 400kHz 2-wire interface

• 2.7V to 5.5V power supply operation

• Available packages

—14 Ld SOIC, TSSOP

• Pb-free plus anneal available (RoHS compliant)

APPLICATIONS

• Communication equipment

—Routers, hubs, switches

—Disk arrays, network storage

• Industrial systems

—Process control

—Intelligent instrumentation

• Computer systems

—Computers

—Network servers

DESCRIPTION

The X40430, X40431, X40434, X40435 combines

power-on reset control, watchdog timer, supply voltage

supervision, second and third voltage supervision,

manual reset, and Block Lock™ protect serial EEPROM

in one package. This combination lowers system cost,

reduces board space requirements, and increases

reliability.

Applying voltage to VCC activates the power-on reset

circuit which holds RESET/RESET active for a period of

time. This allows the power supply and system oscilla-

tor to stabilize before the processor can execute code.

Low VCC detection circuitry protects the user’s system

from low voltage conditions, resetting the system

when VCC falls below the minimum VTRIP1 point.

RESET/RESET is active until VCC returns to proper

operating level and stabilizes. A second and third volt-

age monitor circuit tracks the unregulated supply to

provide a power fail warning or monitors different

power supply voltage. Three common low voltage

combinations are available. However, Intersil’s unique

circuits allows the threshold for either voltage monitor

to be reprogrammed to meet specific system level

requirements or to fine-tune the threshold for applica-

tions requiring higher precision.

A manual reset input provides debounce circuitry for

minimum reset component count.

The Watchdog Timer provides an independent protec-

tion mechanism for microcontrollers. When the micro-

controller fails to restart a timer within a selectable

time out interval, the device activates the WDO signal.

The user selects the interval from three preset values.

Once selected, the interval does not change, even

after cycling the power.

The memory portion of the device is a CMOS Serial

EEPROM array with Intersil’s Block Lock protection.

The array is internally organized as x 8. The device

features a 2-wire interface and software protocol

allowing operation on an I2C bus.

The device utilizes Intersil’s proprietary Direct Write™

cell, providing a minimum endurance of 100,000

cycles and a minimum data retention of 100 years.

Data Sheet May 24, 2006

2FN8251.1

May 24, 2006

BLOCK DIAGRAM

*Voltage monitor requires Vcc to operate. Others are independent of Vcc.

V3FAIL

V2FAIL

WDO

LOWLINE

RESET

X40430/34

X40431/35

V3 Monitor

Logic

V2 Monitor

Logic

Fault Detection

Status

EEPROM

Array

Data

Command

Decode Test

& Control

Logic

Power-on,

Manual Reset

Low Voltage

Reset

Generation

Monitor

Logic

V3MON

V2MON

SDA

SCL

(V1MON)

Watchdog

and

Reset Logic

TRIP3

TRIP2

TRIP1

*X40430, X40431=

V2MON*

V2MON

X40434, X40435 =V

Device

Expected System

Voltages Vtrip1(V) Vtrip2(V) Vtrip3(V)

POR

(system)

X40430, X40431

-A

-B

-C

5V; 3V or 3.3V; 1.8V

5V; 3V; 1.8V

3.3V; 2.5V; 1.8V

2.0–4.75*

4.55–4.65*

4.35–4.45*

2.95–3.05*

1.70–4.75

2.85–2.95

2.55–2.65

2.15–2.25

1.70–4.75

1.65–1.75

RESET = X40430

RESET = X40431

X40434, X40435

-A

-B

-C

5V; 3.3V; 1.5V

5V; 3V or 3.3V; 1.5V

5V; 3 or 3.3V; 1.2V

2.0–4.75*

4.55–4.65*

0.90–3.50*

1.25–1.35*

0.95–1.05*

1.70–4.75

3.05–3.15

2.85–2.95

RESET = X40434

RESET = X40435

X40430, X40431, X40434, X40435

3FN8251.1

May 24, 2006

Ordering Information

PART NUMBER* PART

MARKING MONITORED

VCC RANGE VTRIP1

RANGE VTRIP2

RANGE VTRIP3

RANGE TEMP.

RANGE (°C) PACKAGE PKG.

DWG. #

PART NUMBER WITH RESET

X40430S14-C X40430S C 1.7 to 3.6 2.9V ±50mV 2.2V ±50mV 1.7V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15

X40430S14I-C X40430S IC -40 to +85 14 Ld SOIC (150 mil) M14.15

X40430V14-C X4043 0VC 0 to 70 14 Ld TSSOP

(4.4mm) M14.173

X40430V14I-C X4043 0VIC -40 to +85 14 Ld TSSOP

(4.4mm) M14.173

X40430S14-B X40430S B 1.7 to 5.5 4.4V ±50mV 2.6V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15

X40430S14Z-B

(Note) X40430S ZB 0 to 70 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40430S14I-B X40430S IB -40 to +85 14 Ld SOIC (150 mil) M14.15

X40430S14IZ-B

(Note) X40430S ZIB -40 to +85 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40430V14-B X4043 0VB 0 to 70 14 Ld TSSOP

(4.4mm) M14.173

X40430V14Z-B

(Note) X40430V ZB 0 to 70 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40430V14I-B X4043 0VIB -40 to +85 14 Ld TSSOP

(4.4mm) M14.173

X40430V14IZ-B

(Note) X40430V ZIB -40 to +85 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40434S14-C X40434S C 1.0 to 5.5 4.6V ±50mV 1.0V ±50mV 2.9V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15

X40434S14I-C X40434S IC -40 to +85 14 Ld SOIC (150 mil) M14.15

X40434V14-C X40434V C 0 to 70 14 Ld TSSOP

(4.4mm) M14.173

X40434V14I-C X40434V IC -40 to +85 14 Ld TSSOP

(4.4mm) M14.173

X40434S14-B X40434S B 1.3 to 5.5 1.3V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15

X40434S14Z-B

(Note) X40434S ZB 1.3 to 5.5 0 to 70 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40434S14I-B X40434S IB 1.3 to 5.5 -40 to +85 14 Ld SOIC (150 mil) M14.15

X40434S14IZ-B

(Note) X40434S ZIB 1.3 to 5.5 -40 to +85 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40434V14-B X40434V B 1.3 to 5.5 0 to 70 14 Ld TSSOP

(4.4mm) M14.173

X40434V14Z-B

(Note) X40434V ZB 1.3 to 5.5 0 to 70 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40434V14I-B X40434V IB 1.3 to 5.5 -40 to +85 14 Ld TSSOP

(4.4mm) M14.173

X40434V14IZ-B

(Note) X4043 4V ZIB 1.3 to 5.5 -40 to +85 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40434S14-A X40434S A 1.3 to 5.5 3.1V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15

X40434S14Z-A

(Note) X40434S ZA 1.3 to 5.5 0 to 70 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40434S14I-A X40434S IA 1.3 to 5.5 -40 to +85 14 Ld SOIC (150 mil) M14.15

X40434S14IZ-A

(Note) X40434S ZIA 1.3 to 5.5 -40 to +85 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40430, X40431, X40434, X40435

4FN8251.1

May 24, 2006

X40434V14-A X40434V A 1.3 to 5.5 4.6V ±50mV 1.3V ±50mV 3.1V ±50mV 0 to 70 14 Ld TSSOP

(4.4mm) M14.173

X40434V14Z-A

(Note) X40434V ZA 0 to 70 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40434V14I-A X40434V IA -40 to +85 14 Ld TSSOP

(4.4mm) M14.173

X40434V14IZ-A

(Note) X40434VZIA -40 to +85 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40430S14-A X40430S A 1.7 to 5.5 2.9V ±50mV 1.7V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15

X40430S14Z-A

(Note) X40430S ZA 0 to 70 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40430S14I-A X40430S IA -40 to +85 14 Ld SOIC (150 mil) M14.15

X40430S14IZ-A

(Note) X40430S ZIA -40 to +85 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40430V14-A X4043 0VA 0 to 70 14 Ld TSSOP

(4.4mm) M14.173

X40430V14Z-A

(Note) X40430V ZA 0 to 70 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40430V14I-A X4043 0VIA -40 to +85 14 Ld TSSOP

(4.4mm) M14.173

X40430V14IZ-AT1

(Note) X4043 0VZIA -40 to +85 14 Ld TSSOP Tape

and Reel (4.4mm)

(Pb-free)

M14.173

PART NUMBER WITH RESET

X40431S14-C X40431S C 1.7 to 3.6 2.9V ±50mV 2.2V ±50mV 1.7V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15

X40431S14I-C X40431S IC -40 to +85 14 Ld SOIC (150 mil) M14.15

X40431V14-C X40431V C 0 to 70 14 Ld TSSOP

(4.4mm) M14.173

X40431V14I-C X40431 IC -40 to +85 14 Ld TSSOP

(4.4mm) M14.173

X40431S14-B X40431S B 1.7 to 5.5 4.4V ±50mV 2.6V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15

X40431S14Z-B

(Note) X40431S ZB 0 to 70 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40431S14I-B X40431S IB -40 to +85 14 Ld SOIC (150 mil) M14.15

X40431S14IZ-B

(Note) X40431S ZIB -40 to +85 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40431V14-B X40431V B 0 to 70 14 Ld TSSOP

(4.4mm) M14.173

X40431V14Z-B

(Note) X40431V ZB 0 to 70 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40431V14I-B X40431V IB -40 to +85 14 Ld TSSOP

(4.4mm) M14.173

X40431V14IZ-B

(Note) X40431V ZIB -40 to +85 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40435S14-C X40435 C 1.0 to 5.5 4.6V ±50mV 1.0V ±50mV 2.9V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15

X40435S14I-C X40435 IC -40 to +85 14 Ld SOIC (150 mil) M14.15

X40435V14-C X40435 C 0 to 70 14 Ld TSSOP

(4.4mm) M14.173

X40435V14I-C X40435 IC -40 to +85 14 Ld TSSOP

(4.4mm) M14.173

Ordering Information (Continued)

PART NUMBER* PART

MARKING MONITORED

VCC RANGE VTRIP1

RANGE VTRIP2

RANGE VTRIP3

RANGE TEMP.

RANGE (°C) PACKAGE PKG.

DWG. #

X40430, X40431, X40434, X40435

5FN8251.1

May 24, 2006

X40435S14-B X40435 B 1.3 to 5.5 4.6V ±50mV 1.3V ±50mV 2.9V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15

X40435S14Z-B

(Note) X40435S ZB 0 to 70 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40435S14I-B X40435 IB -40 to +85 14 Ld SOIC (150 mil) M14.15

X40435S14IZ-B

(Note) X40435S ZIB -40 to +85 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40435V14-B X40435 B 0 to 70 14 Ld TSSOP

(4.4mm) M14.173

X40435V14Z-B

(Note) X40435V ZB 0 to 70 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40435V14I-B X40435 IB -40 to +85 14 Ld TSSOP

(4.4mm) M14.173

X40435V14IZ-B

(Note) X40435V ZIB -40 to +85 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40435S14-A X40435 A 3.1V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15

X40435S14Z-A

(Note) X40435S ZA 0 to 70 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40435S14I-A X40435 IA -40 to +85 14 Ld SOIC (150 mil) M14.15

X40435S14IZ-A

(Note) X40435S ZIA -40 to +85 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40435V14-A X40435 A 0 to 70 14 Ld TSSOP

(4.4mm) M14.173

X40435V14Z-A

(Note) X40435V ZA 0 to 70 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40435V14I-A X40435 IA -40 to +85 14 Ld TSSOP

(4.4mm) M14.173

X40435V14IZ-A

(Note) X40435V ZIA -40 to +85 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40431S14-A X40431S A 1.7 to 5.5 2.9V ±50mV 1.7V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15

X40431S14Z-A

(Note) X40431S ZA 0 to 70 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40431S14I-A X40431S IA -40 to +85 14 Ld SOIC (150 mil) M14.15

X40431S14IZ-A

(Note) X40431S ZIA -40 to +85 14 Ld SOIC (150 mil)

(Pb-free) M14.15

X40431V14-A X40431V A 0 to 70 14 Ld TSSOP

(4.4mm) M14.173

X40431V14Z-A

(Note) X40431V ZA 0 to 70 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

X40431V14I-A X40431V IA -40 to +85 14 Ld TSSOP

(4.4mm) M14.173

X40431V14IZ-A

(Note) X40431V ZIA -40 to +85 14 Ld TSSOP

(4.4mm) (Pb-free) M14.173

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Ordering Information (Continued)

PART NUMBER* PART

MARKING MONITORED

VCC RANGE VTRIP1

RANGE VTRIP2

RANGE VTRIP3

RANGE TEMP.

RANGE (°C) PACKAGE PKG.

DWG. #

X40430, X40431, X40434, X40435

6FN8251.1

May 24, 2006

PIN CONFIGURATION

V3MON

VSS

VCC

SDA

SCL

LOWLINE

RESET

V2MON

MR WP

V3FAIL

WDO

V2FAIL

V3MON

VCC

SDA

SCL

V3FAIL

WDO

VSS

LOWLINE

RESET

V2MON

V2FAIL

X40430, X40434 X40431, X40435

14 Ld SOIC, TSSOP 14 Ld SOIC, TSSOP

PIN DESCRIPTION

Pin Name Function

1V2FAILV2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes

HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.

2V2MONV2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW.

This input can monitor an unregulated power supply with an external resistor divider or can monitor a

second power supply with no external components. Connect V2MON to VSS or VCC when not used. The

V2MON comparator is supplied by V2MON (X40430, X40431) or by the VCC input (X40434, X40435).

3LOWLINE

Early Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high when

VCC > VTRIP1.

4NCNo connect.

5MR

Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-

main HIGH/LOW until the pin is released and for the tPURST thereafter.

6 RESET/

RESET

RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when-

ever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-

grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and for

tPURST thereafter.

RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when-

ever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-

grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and for

tPURST thereafter.

SS Ground

8SDASerial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open

drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a

pull up resistor and the input buffer is always active (not gated).

Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and

followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the

watchdog time out period results in WDO going active.

9SCLSerial Clock. The Serial Clock controls the serial bus timing for data input and output.

10 WP Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has

an internal pull down resistor (>10MΩ typical).

11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes LOW.

This input can monitor an unregulated power supply with an external resistor divider or can monitor a

third power supply with no external components. Connect V3MON to VSS or VCC when not used. The

V3MON comparator is supplied by the V3MON input.

12 V3FAIL V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and goes

HIGH when V3MON exceeds VTRIP3. There is no power-up reset delay circuitry on this pin.

13 WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog

timer goes active.

14 VCC Supply Voltage

X40430, X40431, X40434, X40435

7FN8251.1

May 24, 2006

PRINCIPLES OF OPERATION

Power-on Reset

Applying power to the X40430, X40431, X40434,

X40435 activates a Power-on Reset Circuit that pulls

the RESET/RESET pins active. This signal provides

several benefits.

– It prevents the system microprocessor from starting

to operate with insufficient voltage.

– It prevents the processor from operating prior to sta-

bilization of the oscillator.

– It allows time for an FPGA to download its configura-

tion prior to initialization of the circuit.

– It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power-up.

When VCC exceeds the device VTRIP1 threshold value

for tPURST (selectable) the circuit releases the RESET

(X40431, X40435) and RESET (X40430, X40434) pin

allowing the system to begin operation.

Figure 1. Connecting a Manual Reset Push-Button

Manual Reset

By connecting a push-button directly from MR to ground,

the designer adds manual system reset capability. The

MR pin is LOW while the push-button is closed and

RESET/RESET pin remains HIGH/LOW until the push-

button is released and for tPURST thereafter.

Low Voltage VCC (V1 Monitoring)

During operation, the X40430, X40431, X40434,

X40435 monitors the VCC level and asserts

RESET/RESET if supply voltage falls below a preset

minimum VTRIP1. The RESET/RESET signal prevents

the microprocessor from operating in a power fail or

brownout condition. The RESET/RESET signal remains

active until the voltage drops below 1V. It also remains

active until VCC returns and exceeds VTRIP1 for tPURST.

Low Voltage V2 Monitoring

The X40430 also monitors a second voltage level and

asserts V2FAIL if the voltage falls below a preset mini-

mum VTRIP2. The V2FAIL signal is either ORed with

RESET to prevent the microprocessor from operating

in a power fail or brownout condition or used to inter-

rupt the microprocessor with notification of an impend-

ing power failure.

For the X40430 and X40431 the V2FAIL signal

remains active until the V2MON drops below 1V

(V2MON falling). It also remains active until V2MON

returns and exceeds VTRIP2. This voltage sense cir-

cuitry monitors the power supply connected to V2MON

pin. If VCC = 0, V2MON can still be monitored.

For the X40434 and X40435, the V2FAIL signal

remains active until VCC drops below 1V and remains

active until V2MON returns and exceeds VTRIP2. This

sense circuitry is powered by VCC. If VCC = 0, V2MON

cannot be monitored.

Low Voltage V3 Monitoring

The X40430, X40431, X40434, X40435 also monitors

a third voltage level and asserts V3FAIL if the voltage

falls below a preset minimum VTRIP3. The V3FAIL sig-

nal is either ORed with RESET to prevent the micro-

processor from operating in a power fail or brownout

condition or used to interrupt the microprocessor with

notification of an impending power failure. The V3FAIL

signal remains active until the V3MON drops below 1V

(V3MON falling). It also remains active until V3MON

returns and exceeds VTRIP3.

This voltage sense circuitry monitors the power supply

connected to V3MON pin. If VCC = 0, V3MON can still

be monitored.

Early Low VCC Detection (LOWLINE)

This CMOS output goes LOW earlier than

RESET/RESET whenever VCC falls below the VTRIP1

voltage and returns high when VCC exceeds the

VTRIP1 voltage. There is no power-up delay circuitry

(tPURST) on this pin.

VCC

System

Reset

Manual

Reset

X40430, X40434

RESET

X40430, X40431, X40434, X40435

8FN8251.1

May 24, 2006

Figure 2. Two Uses of Multiple Voltage Monitoring

Figure 3. VTRIPX Set/Reset Conditions

WATCHDOG TIMER

The Watchdog Timer circuit monitors the microproces-

sor activity by monitoring the SDA and SCL pins. A

standard read or write sequence to any slave address

byte restarts the watchdog timer and prevents the

WDO signal going active. A minimum sequence to

reset the watchdog timer requires four microprocessor

instructions namely, a Start, Clock Low, Clock High

and Stop. The state of two nonvolatile control bits in

the Status Register determine the watchdog timer

period. The microprocessor can change these watch-

dog bits by writing to the X40430, X40431, X40434,

X40435 control register (also refer to page 20).

Figure 4. Watchdog Restart

V1, V2 AND V3 THRESHOLD PROGRAM

PROCEDURE (OPTIONAL)

The X40430 is shipped with standard V1, V2 and V3

threshold (VTRIP1, VTRIP2, VTRIP3) voltages. These

values will not change over normal operating and stor-

age conditions. However, in applications where the

standard thresholds are not exactly right, or if higher

precision is needed in the threshold value, the X40430,

X40431, X40434, X40435 trip points may be adjusted.

The procedure is described in the following situation,

and uses the application of a high voltage control sig-

nal.

6-10V VCC

V3MON

X40431-A Unreg.

Supply VCC

X40431-B

RESET

V2FAIL

System

VCC

Reset

V2FAIL

V3FAIL

System

Reset

Notice: No external components required to monitor three voltages.

V3MON

V3FAIL

V2MON

Reg

3.0V

Reg

1.8V

Reg

3.3V

390K

V2MON

RESET

Power

Fail

Interrupt

VCC

(1.7V)

VCC/V2MON/V3MON

VTRIPX

tWC

A0h

770 70

SCL

WDO

SDA

(X = 1, 2, 3)

00h

SCL

SDA

.6µs 1.3µs

WDT Reset

Start Stop

X40430, X40431, X40434, X40435

9FN8251.1

May 24, 2006

Setting a VTRIPx Voltage (x = 1, 2, 3)

There are two procedures used to set the threshold

voltages (VTRIPx), depending if the threshold voltage

to be stored is higher or lower than the present value.

For example, if the present VTRIPx is 2.9 V and the

new VTRIPx is 3.2 V, the new voltage can be stored

directly into the VTRIPx cell. If however, the new setting

is to be lower than the present setting, then it is neces-

sary to “reset” the VTRIPx voltage before setting the

new value.

Setting a Higher VTRIPx Voltage (x = 1, 2, 3)

To set a VTRIPx threshold to a new voltage which is

higher than the present threshold, the user must apply

the desired VTRIPx threshold voltage to the corre-

sponding input pin Vcc(V1MON), V2MON or V3MON.

Then, a programming voltage (Vp) must be applied to the

WDO pin before a START condition is set up on SDA.

Next, issue on the SDA pin the Slave Address A0h, fol-

lowed by the Byte Address 01h for VTRIP1, 09h for

VTRIP2, and 0Dh for VTRIP3, and a 00h Data Byte in order

to program VTRIPx. The STOP bit following a valid write

operation initiates the programming sequence. Pin WDO

must then be brought LOW to complete the operation. To

check if the VTRIPX has been set, set VXMON to a value

slightly greater than VTRIPX (that was previously set).

Slowly ramp down VXMON and observe when the corre-

sponding outputs (LOWLINE, V2FAIL and V3FAIL)

switch. The voltage at which this occurs is the VTRIPX

(actual).

CASE A

Now if the desired VTRIPX is greater than the VTRIPX

(actual), then add the difference between VTRIPX

(desired) – VTRIPX (actual) to the original VTRIPX

desired. This is your new VTRIPX that should be

applied to VXMON and the whole sequence should be

repeated again (see Figure 5).

CASE B

Now if the VTRIPX (actual), is higher than the VTRIPX

(desired), perform the reset sequence as described in

the next section. The new VTRIPX voltage to be applied

to VXMON will now be: VTRIPX (desired) – (VTRIPX

(actual) – VTRIPX (desired)).

Note: This operation does not corrupt the memory array.

Setting a Lower VTRIPx Voltage (x = 1, 2, 3)

In order to set VTRIPx to a lower voltage than the

present value, then VTRIPx must first be “reset” accord-

ing to the procedure described below. Once VTRIPx

has been “reset”, then VTRIPx can be set to the desired

voltage using the procedure described in “Setting a

Higher VTRIPx Voltage”.

Resetting the VTRIPx Voltage

To reset a VTRIPx voltage, apply the programming volt-

age (Vp) to the WDO pin before a START condition is

set up on SDA. Next, issue on the SDA pin the Slave

Address A0h followed by the Byte Address 03h for

VTRIP1, 0Bh for VTRIP2, and 0Fh for VTRIP3, followed

by 00h for the Data Byte in order to reset VTRIPx. The

STOP bit following a valid write operation initiates the

programming sequence. Pin WDO must then be

brought LOW to complete the operation.

After being reset, the value of VTRIPx becomes a nomi-

nal value of 1.7V or lesser.

Notes: 1. This operation does not corrupt the memory array.

2. Set VCC ≅ 1.5(V2MON or V3MON), when setting

VTRIP2 or VTRIP3 respectively.

CONTROL REGISTER

The Control Register provides the user a mechanism

for changing the Block Lock and Watchdog Timer set-

tings. The Block Lock and Watchdog Timer bits are

nonvolatile and do not change when power is removed.

The Control Register is accessed with a special pream-

ble in the slave byte (1011) and is located at address

1FFh. It can only be modified by performing a byte write

operation directly to the address of the register and only

one data byte is allowed for each register write opera-

tion. Prior to writing to the Control Register, the WEL

and RWEL bits must be set using a two step process,

with the whole sequence requiring 3 steps. See "Writing

to the Control Registers" on page 11.

The user must issue a stop, after sending this byte to

the register, to initiate the nonvolatile cycle that stores

WD1, WD0, PUP1, PUP0, and BP. The X40430,

X40431, X40434, X40435 will not acknowledge any

data bytes written after the first byte is entered.

The state of the Control Register can be read at any

time by performing a random read at address 1FFh,

using the special preamble. Only one byte is read by

each register read operation. The master should

supply a stop condition to be consistent with the bus

protocol.

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit must be set to “1” prior to a write to the

Control Register.

76543210

PUP1 WD1 WD0 BP 0 RWEL WEL PUP0

X40430, X40431, X40434, X40435

10 FN8251.1

May 24, 2006

Figure 5. Sample VTRIP Reset Circuit

Figure 6. VTRIPX Set/Reset Sequence (X = 1, 2, 3)

WEL: Write Enable Latch (Volatile)

The WEL bit controls the access to the memory and to

the Register during a write operation. This bit is a vola-

tile latch that powers up in the LOW (disabled) state.

While the WEL bit is LOW, writes to any address,

including any control registers will be ignored (no

acknowledge will be issued after the Data Byte). The

WEL bit is set by writing a “1” to the WEL bit and

zeroes to the other bits of the control register.

X4043X

VTRIP1

Adj.

SDA

SCL

µC

Adjust

Run

V2FAIL

VTRIP2

Adj.

RESET

VTRIPX Programming

Apply VCC and Voltage

Decrease VX

Actual VTRIPX -

Desired VTRIPX

DONE

Set Higher VX Sequence

Error < MDE–

| Error | < | MDE |

YES

Error > MDE+

> Desired VTRIPX to VX

Desired

Present Value

VTRIPX<

Execute

YES

Execute

VTRIPX Reset Sequence

Set VX = desired VTRIPX

New VX applied =

Old VX applied + | Error |

New VX applied =

Old VX applied - | Error |

Execute Reset VTRIPX

Sequence

Output Switches?

Note: X = 1, 2, 3

Let: MDE = Maximum Desired Error

Vx = VCC, VxMON

MDE+

Desired Value

MDE–

Acceptable

Error Range

Error = Actual - Desired

X40430, X40431, X40434, X40435

11 FN8251.1

May 24, 2006

Once set, WEL remains set until either it is reset to 0

(by writing a “0” to the WEL bit and zeroes to the other

bits of the control register) or until the part powers up

again. Writes to the WEL bit do not cause a high volt-

age write cycle, so the device is ready for the next

operation immediately after the stop condition.

BP: Block Protect Bits (Nonvolatile)

The Block Protect Bit BP, determines which blocks of

the array are write protected. A write to a protected

block of memory is ignored. The block protect bit will

prevent write operations to half or none of the array.

PUP1, PUP0: Power-up Bits (Nonvolatile)

The Power-up bits, PUP1 and PUP0, determine the

tPURST time delay. The nominal power-up times are

shown in the following table.

WD1, WD0: Watchdog Timer Bits (Nonvolatile)

The bits WD1 and WD0 control the period of the

Watchdog Timer. The options are shown below.

Writing to the Control Registers

Changing any of the nonvolatile bits of the control and

trickle registers requires the following steps:

– Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation pre-

ceded by a start and ended with a stop).

– Write a 06H to the Control Register to set the

bit. This is also a volatile cycle. The zeros in the data

byte are required. (Operation proceeded by a start

and ended with a stop).

– Write one byte value to the Control Register that has

all the control bits set to the desired state. The Control

where xy are the WD bits, s is the BP bit and qr are the

power-up bits. This operation proceeded by a start and

ended with a stop bit. Since this is a nonvolatile write

cycle it will take up to 10ms (max.) to complete. The

RWEL bit is reset by this cycle and the sequence must

be repeated to change the nonvolatile bits again. If bit

2 is set to ‘1’ in this third step (qxys 011r) then the

RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and

BP bits remain unchanged. Writing a second byte to

the control register is not allowed. Doing so aborts the

write operation and returns a NACK.

– A read operation occurring between any of the previ-

ous operations will not interrupt the register write

operation.

– The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power

cycling the device or attempting a write to a write

protected block.

To illustrate, a sequence of writes to the device con-

sisting of [02H, 06H, 02H] will reset all of the nonvola-

tile bits in the Control Register to 0. A sequence of

[02H, 06H, 06H] will leave the nonvolatile bits

unchanged and the RWEL bit remains set.

Notes: 1. tPURST is set to 200ms as factory default.

2. Watch Dog Timer bits are shipped disabled.

FAULT DETECTION REGISTER

The Fault Detection Register (FDR) provides the user

the status of what causes the system reset active. The

Manual Reset Fail, Watchdog Timer Fail and Three

Low Voltage Fail bits are volatile

The FDR is accessed with a special preamble in the

slave byte (1011) and is located at address 0FFh. It

can only be modified by performing a byte write opera-

tion directly to the address of the register and only one

data byte is allowed for each register write operation.

There is no need to set the WEL or RWEL in the

control register to access this FDR.

Protected Addresses

(Size)

Memory Array

Lock

0 None None

1 100h – 1FFh (256 bytes) Upper Half of

Memory Array

PUP1 PUP0 Power-on Reset Delay (tPURST)

0 0 50ms

0 1 200ms (factory setting)

1 0 400ms

1 1 800ms

WD1 WD0 Watchdog Time Out Period

0 0 1.4 seconds

0 1 200 milliseconds

1 0 25 milliseconds

1 1 disabled (factory setting)

7 6543210

LV1F LV2F LV3F WDF MRF 0 0 0

X40430, X40431, X40434, X40435

12 FN8251.1

May 24, 2006

Figure 7. Valid Data Changes on the SDA Bus

At power-up, the FDR is defaulted to all “0”. The sys-

tem needs to initialize this register to all “1” before the

actual monitoring can take place. In the event that any

one of the monitored sources fail, the corresponding

bit in the register will change from a “1” to a “0” to indi-

cate the failure. At this moment, the system should

perform a read to the register and note the cause of

the reset. After reading the register the system should

reset the register back to all “1” again. The state of the

FDR can be read at any time by performing a random

read at address 0FFh, using the special preamble.

The FDR can be read by performing a random read at

0FFh address of the register at any time. Only one

byte of data is read by the register read operation.

MRF, Manual Reset Fail Bit (Volatile)

The MRF bit will be set to “0” when Manual Reset

input goes active.

WDF, Watchdog Timer Fail Bit (Volatile)

The WDF bit will be set to “0” when the WDO goes

active.

LV1F, Low VCC Reset Fail Bit (Volatile)

The LV1F bit will be set to “0” when VCC (V1MON)

falls below VTRIP1.

LV2F, Low V2MON Reset Fail Bit (Volatile)

The LV2F bit will be set to “0” when V2MON falls

below VTRIP2.

LV3F, Low V3MON Reset Fail Bit (Volatile)

The LV3F bit will be set to “0” when the V3MON falls

below VTRIP3.

SERIAL INTERFACE

Interface Conventions

The device supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data

onto the bus as a transmitter, and the receiving device

as the receiver. The device controlling the transfer is

called the master and the device being controlled is

called the slave. The master always initiates data

transfers, and provides the clock for both transmit and

receive operations. Therefore, the devices in this fam-

ily operate as slaves in all applications.

Serial Clock and Data

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions. See

Figure 7.

Serial Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL

is HIGH. The device continuously monitors the SDA

and SCL lines for the start condition and will not

respond to any command until this condition has been

met. See Figure 8.

Serial Stop Condition

All communications must be terminated by a stop con-

dition, which is a LOW to HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the device into the Standby power mode after a read

sequence. A stop condition can only be issued after the

transmitting device has released the bus. See Figure 8.

Figure 8. Valid Start and Stop Conditions

SCL

SDA

Data Stable Data Change Data Stable

SCL

SDA

Start Stop

X40430, X40431, X40434, X40435

13 FN8251.1

May 24, 2006

Serial Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfer. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data. See Figure 9.

The device will respond with an acknowledge after

recognition of a start condition and if the correct

Device Identifier and Select bits are contained in the

Slave Address Byte. If a write operation is selected,

the device will respond with an acknowledge after the

receipt of each subsequent eight bit word. The device

will acknowledge all incoming data and address bytes,

except for the Slave Address Byte when the Device

Identifier and/or Select bits are incorrect.

In the read mode, the device will transmit eight bits of

data, release the SDA line, then monitor the line for an

acknowledge. If an acknowledge is detected and no

stop condition is generated by the master, the device

will continue to transmit data. The device will terminate

further data transmissions if an acknowledge is not

detected. The master must then issue a stop condition

to return the device to Standby mode and place the

device into a known state.

Serial Write Operations

Byte Write

For a write operation, the device requires the Slave

Address Byte and a Word Address Byte. This gives

the master access to any one of the words in the

array. After receipt of the Word Address Byte, the

device responds with an acknowledge, and awaits the

next eight bits of data. After receiving the 8 bits of the

Data Byte, the device again responds with an

acknowledge. The master then terminates the transfer

by generating a stop condition, at which time the

device begins the internal write cycle to the nonvolatile

memory. During this internal write cycle, the device

inputs are disabled, so the device will not respond to any

requests from the master. The SDA output is at high

impedance. See Figure 10.

A write to a protected block of memory will suppress

the acknowledge bit.

Figure 9. Acknowledge Response From Receiver

Figure 10. Byte Write Sequence

Data Output from

Transmitter

Data Output

from Receiver

81 9

Start Acknowledge

SCL from

Master

Slave

Address

Byte

Address Data

SDA Bus

Signals from

the Slave

Signals from

the Master

X40430, X40431, X40434, X40435

14 FN8251.1

May 24, 2006

Page Write

The device is capable of a page write operation. It is

initiated in the same manner as the byte write opera-

tion; but instead of terminating the write cycle after the

first data byte is transferred, the master can transmit

an unlimited number of 8-bit bytes. After the receipt of

each byte, the device will respond with an acknowl-

edge, and the address is internally incremented by

one. The page address remains constant. When the

counter reaches the end of the page, it “rolls over” and

goes back to ‘0’ on the same page.

This means that the master can write 16 bytes to the

page starting at any location on that page. If the mas-

ter begins writing at location 10, and loads 12 bytes,

then the first 6 bytes are written to locations 10

through 15, and the last 6 bytes are written to locations

0 through 5. Afterwards, the address counter would

point to location 6 of the page that was just written. If

the master supplies more than 16 bytes of data, then

new data overwrites the previous data, one byte at a

time.

The master terminates the Data Byte loading by issuing

a stop condition, which causes the device to begin the

nonvolatile write cycle. As with the byte write operation,

all inputs are disabled until completion of the internal

write cycle. See Figure 11 for the address, acknowl-

edge, and data transfer sequence.

Stops and Write Modes

Stop conditions that terminate write operations must

be sent by the master after sending at least 1 full data

byte plus the subsequent ACK signal. If a stop is

issued in the middle of a data byte, or before 1 full

data byte plus its associated ACK is sent, then the

device will reset itself without performing the write. The

contents of the array will not be effected.

Acknowledge Polling

The disabling of the inputs during high voltage cycles

can be used to take advantage of the typical 5ms write

cycle time. Once the stop condition is issued to indi-

cate the end of the master’s byte load operation, the

device initiates the internal high voltage cycle.

Acknowledge polling can be initiated immediately. To

do this, the master issues a start condition followed by

the Slave Address Byte for a write or read operation. If

the device is still busy with the high voltage cycle then

no ACK will be returned. If the device has completed

the write operation, an ACK will be returned and the

host can then proceed with the read or write operation.

See Figure 13.

Serial Read Operations

Read operations are initiated in the same manner as

write operations with the exception that the R/W bit of

the Slave Address Byte is set to one. There are three

basic read operations: Current Address Reads, Ran-

dom Reads, and Sequential Reads.

Figure 11. Page Write Operation

Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.

Slave

Address

Byte

Address Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(1)

(1 ≤ n ≤ 16)

1010 00

address

5 Bytes

n-1

7 Bytes

address

= 6

address pointer

ends here

Addr = 7

X40430, X40431, X40434, X40435

15 FN8251.1

May 24, 2006

Current Address Read

Internally the device contains an address counter that

maintains the address of the last word read incre-

mented by one. Therefore, if the last read was to

address n, the next read operation would access data

from address n+1. On power-up, the address of the

address counter is undefined, requiring a read or write

operation for initialization.

Upon receipt of the Slave Address Byte with the R/W

bit set to one, the device issues an acknowledge and

then transmits the eight bits of the Data Byte. The

master terminates the read operation when it does not

respond with an acknowledge during the ninth clock

and then issues a stop condition. See figure 15 for the

address, acknowledge, and data transfer sequence.

Figure 13. Acknowledge Polling Sequence

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read

operation, the master must either issue a stop condi-

tion during the ninth cycle or hold SDA HIGH during

the ninth clock cycle and then issue a stop condition.

Random Read

Random read operation allows the master to access any

memory location in the array. Prior to issuing the Slave

Address Byte with the R/W bit set to one, the master

must first perform a “dummy” write operation. The master

issues the start condition and the Slave Address Byte,

receives an acknowledge, then issues the Word Address

Bytes. After acknowledging receipts of the Word Address

Bytes, the master immediately issues another start con-

dition and the Slave Address Byte with the R/W bit set to

one. This is followed by an acknowledge from the device

and then by the eight bit word. The master terminates the

read operation by not responding with an acknowledge

and then issuing a stop condition. See Figure 16 for the

address, acknowledge, and data transfer sequence.

A similar operation called “Set Current Address” where

the device will perform this operation if a stop is issued

instead of the second start is shown in Figure 15. The

device will go into standby mode after the stop and all

bus activity will be ignored until a start is detected.

This operation loads the new address into the address

counter. The next Current Address Read operation will

read from the newly loaded address. This operation

could be useful if the master knows the next address it

needs to read, but is not ready for the data.

Sequential Read

Sequential reads can be initiated as either a current

address read or random address read. The first Data

Byte is transmitted as with the other modes; however,

the master now responds with an acknowledge, indicat-

ing it requires additional data. The device continues to

output data for each acknowledge received. The master

terminates the read operation by not responding with an

acknowledge and then issuing a stop condition.

The data output is sequential, with the data from

address n followed by the data from address n + 1. The

address counter for read operations increments through

all page and column addresses, allowing the entire

memory contents to be serially read during one opera-

tion. At the end of the address space the counter “rolls

over” to address 0000h and the device continues to out-

put data for each acknowledge received. See Figure 17

for the acknowledge and data transfer sequence.

ACK

Returned?

Issue Slave Address

Byte (Read or Write)

Byte Load Completed

by Issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

YES

High Voltage Cycle

Complete. Continue

Command Sequence?

Issue STOP

Continue Normal

Read or Write

Command Sequence

PROCEED

YES

X40430, X40431, X40434, X40435

16 FN8251.1

May 24, 2006

SERIAL DEVICE ADDRESSING

Memory Address Map

CR, Control Register, CR7: CR0

Address: 1FFhex

FDR, Fault DetectionRegister, FDR7: FDR0

Address: 0FFhex

General Purpose Memory Organization, A8:A0

Address: 000h to 1FFh

General Purpose Memory Array Configuration

Slave Address Byte

Following a start condition, the master must output a

Slave Address Byte. This byte consists of several parts:

– a device type identifier that is always ‘101x’. Where

x = 0 is for Array, x = 1 is for Control Register or

Fault Detection Register.

– next two bits are ‘0’.

– next bit that becomes the MSB of the address.

Figure 14. X40430, X40431, X40434, X40435

Addressing

– last bit of the slave command byte is a R/W bit. The

R/W bit of the Slave Address Byte defines the oper-

ation to be performed. When the R/W bit is a one,

then a read operation is selected. A zero selects a

write operation.

Word Address

The word address is either supplied by the master or

obtained from an internal counter. The internal counter

is undefined on a power-up condition.

Operational Notes

The device powers-up in the following state:

– The device is in the low power standby state.

– The WEL bit is set to ‘0’. In this state it is not possi-

ble to write to the device.

– SDA pin is the input mode.

– RESET/RESET Signal is active for tPURST.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

– The WEL bit must be set to allow write operations.

– The proper clock count and bit sequence is required

prior to the stop bit in order to start a nonvolatile

write cycle.

– A three step sequence is required before writing into

the Control Register to change Watchdog Timer or

Block Lock settings.

– The WP pin, when held HIGH, prevents all writes to

the array and all the Register.

Figure 15. Current Address Read Sequence

Memory Address

A8:A0

000h

0FFh

100h

1FFh

Lower 256 bytes

Upper 256 bytes Block Protect Option

General Purpose Memory

Control Register

Fault Detection Register

A8 R/W

Word Address

Slave Byte

1011

R/W

General Purpose Memory

Control Register

Fault Detection Register

A6 A5 A4 A1 A0

A3 A2

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

1010 00

X40430, X40431, X40434, X40435

17 FN8251.1

May 24, 2006

Figure 16. Random Address Read Sequence

Figure 17. Sequential Read Sequence

Slave

Address

Byte

Address

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

101 00

Data

(2)

Slave

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(n-1)

(n is any integer greater than 1)

Data

(1)

X40430, X40431, X40434, X40435

18 FN8251.1

May 24, 2006

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on any pin with

respect to VSS ...................................... -1.0V to +7V

D.C. output current ............................................... 5mA

Lead temperature (soldering, 10s) .................... 300°C

COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device (at these or any other conditions above those

listed in the operational sections of this specification) is

not implied. Exposure to absolute maximum rating con-

ditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

*See Ordering Info

Temperature Min. Max.

Commercial 0°C 70°C

Industrial -40°C +85°C

Version

Chip Supply

Voltage

Monitored*

Voltages

X40430, X40431 2.7V to 5.5V 1.7V to 5.5V

X40434, X40435 2.7V to 5.5V 1.0V to 5.5V

D.C. OPERATING CHARACTERISTICS

(Over the recommended operating conditions unless otherwise specified)

Symbol Parameter Min Typ (4) Max Unit Test Conditions

ICC1(1) Active Supply Current (VCC) Read 1.5 mA VIL = VCC x 0.1

VIH = VCC x 0.9,

fSCL = 400kHz

ICC2(1) Active Supply Current (VCC) Write 3.0 mA

ISB1(1)(6) Standby Current (VCC) AC (WDT off) 6 10 µA VIL = VCC x 0.1

VIH = VCC x 0.9

fSCL, fSDA = 400kHz

ISB2(2)(6) Standby Current (VCC) DC (WDT on) 25 30 µA VSDA = VSCL = VCC

Others = GND or VCC

ILI Input Leakage Current (SCL, MR,

WP)

10 µA VIL = GND to VCC

ILO Output Leakage Current (SDA,

V2FAIL, V3FAIL, WDO, RESET)

10 µA VSDA = GND to VCC

Device is in Standby(2)

VIL(3) Input LOW Voltage (SDA, SCL, MR,

WP)

-0.5 VCC x 0.3 V

VIH(3) Input HIGH Voltage (SDA, SCL, MR,

WP)

VCC x 0.7 VCC + 0.5 V

VHYS(6) Schmitt Trigger Input Hysteresis

• Fixed input level

• VCC related level

0.2

.05 x VCC

VOL Output LOW Voltage (SDA, RE-

SET/RESET, LOWLINE, V2FAIL,

V3FAIL, WDO)

0.4 V IOL = 3.0mA (2.7-5.5V)

IOL = 1.8mA (2.7-3.6V)

VOH Output (RESET, LOWLINE) HIGH

Voltage

VCC – 0.8

VCC – 0.4

OH = -1.0mA (2.7-5.5V)

IOH = -0.4mA (2.7-3.6V)

X40430, X40431, X40434, X40435

19 FN8251.1

May 24, 2006

Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave

Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.

(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high

voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.

(3) VIL Min. and VIH Max. are for reference only and are not tested.

(4) At 25°C, VCC = 3V

(5) See ordering information for standard programming levels. For custom programmed levels, contact factory.

(6) Based on characterization data.

EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2, 3)

CAPACITANCE

VCC Supply

VTRIP1(5) VCC Trip Point Voltage Range 2.0 4.75 V

4.55 4.6 4.65 V X40430, X40431-A, X40434,

X40435

4.35 4.4 4.45 V X40430, X40431-B

2.85 2.9 2.95 V X40430, X40431-C

Second Supply Monitor

IV2 V2MON Current 15 µA

VTRIP2(5) V2MON Trip Point Voltage Range 1.7

0.9

4.75

3.5

x40430, X40431

x40434, X40435

2.85 2.9 2.95 V X40430, X40431-A

2.55 2.6 2.65 V X40430, X40431-B

2.15 2.2 2.25 V X40430, X40431-C

1.25 1.3 1.35 V X40434, X40435-A&B

0.95 1.0 1.05 V X40434, X40435-C

tRPD2(6) VTRIP2 to V2FAIL 5µs

Third Supply Monitor

IV3 V3MON Current 15 µA

VTRIP3(5) V3MON Trip Point Voltage Range 1.7 4.75 V

1.65 1.7 1.75 V X40430, X40431

3.05 3.1 3.15 V X40434, X40435-A

2.85 2.9 2.95 V X40434, X40435-B&C

tRPD3(6) VTRIP3 to V3FAIL 5µs

D.C. OPERATING CHARACTERISTICS (Continued)

(Over the recommended operating conditions unless otherwise specified)

Symbol Parameter Min Typ (4) Max Unit Test Conditions

–

VREF

tRPDX = 5µs worst case

Output Pin

VxMON

∆V = 100mV

∆VVref

Symbol Parameter Max Unit Test Conditions

COUT(1) Output Capacitance (SDA, RESET/RESET, LOWLINE,

V2FAIL,V3FAIL, WDO)

8pF V

OUT = 0V

CIN(1) Input Capacitance (SCL, WP, MR) 6 pF VIN = 0V

Note: (1) This parameter is not 100% tested.

X40430, X40431, X40434, X40435

20 FN8251.1

May 24, 2006

EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR

VCC = 5V

A.C. TEST CONDITIONS

SYMBOL TABLE

A.C. CHARACTERISTICS

Note: (1) Cb = total capacitance of one bus line in pF.

Input pulse levels VCC x 0.1 to VCC x 0.9

Input rise and fall times 10ns

Input and output timing levels VCC x 0.5

Output load Standard output load

SDA

30pF

V2MON, V3MON

4.6kΩ

RESET

30pF

2.06kΩ

V2FAIL,

VCC

4.6kΩ

30pF

WDO V3FAIL

Must be

steady

Will be

steady

May change

from LOW

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A Center Line

is High

Impedance

WAVEFORM INPUTS OUTPUTS

to HIGH

Symbol Parameter Min Max Unit

fSCL SCL Clock Frequency 400 kHz

tIN Pulse width Suppression Time at inputs 50 ns

tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs

tBUF Time the bus free before start of new transmission 1.3 µs

tLOW Clock LOW Time 1.3 µs

tHIGH Clock HIGH Time 0.6 µs

tSU:STA Start Condition Setup Time 0.6 µs

tHD:STA Start Condition Hold Time 0.6 µs

tSU:DAT Data In Setup Time 100 ns

tHD:DAT Data In Hold Time 0 µs

tSU:STO Stop Condition Setup Time 0.6 µs

tDH Data Output Hold Time 50 ns

tRSDA and SCL Rise Time 20 +.1Cb(1) 300 ns

tFSDA and SCL Fall Time 20 +.1Cb(1) 300 ns

tSU:WP WP Setup Time 0.6 µs

tHD:WP WP Hold Time 0 µs

Cb Capacitive load for each bus line 400 pF

X40430, X40431, X40434, X40435

21 FN8251.1

May 24, 2006

TIMING DIAGRAMS

Bus Timing

WP Pin Timing

Write Cycle Timing

Nonvolatile Write Cycle Timing

Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is

the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

tSU:STO

tHIGH

tSU:STA tHD:STA

tHD:DAT

tSU:DAT

SCL

SDA IN

SDA OUT

tFtLOW

tBUF

tDH

tAA

tHD:WP

SCL

SDA IN

tSU:WP

Clk 1 Clk 9

Slave Address Byte

START

SCL

SDA

tWC

8th Bit of Last Byte ACK

Stop

Condition

Start

Condition

Symbol Parameter Min Typ Max Unit

tWC(1) Write Cycle Time 5 10 ms

X40430, X40431, X40434, X40435

22 FN8251.1

May 24, 2006

Power Fail Timings

RESET/RESET/MR Timings

V2MON or

V2FAIL or

tRPDX

VRVALID

V3MON

V3FAIL

LOWLINE or

VCC

VTRIPX

tRPDX

tRPDL tRPDL

tRPDL

X = 2, 3

[]

LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V)

Symbol Parameters Min Typ (1) Max Unit

tRPD1(2)

tRPDL

VTRIP1 to RESET/RESET (Power-down only)

VTRIP1 to LOWLINE

5µs

t LR LOWLINE to RESET/RESET delay (Power-down only) [= tRPD1-tRPDL] 500 ns

tRPDX(2) VTRIP2 to V2FAIL, or VTRIP3 to V3FAIL (x = 2, 3) 5 µs

tPURST Power-on Reset delay:

PUP1 = 0, PUP0 = 0

PUP1 = 0, PUP0 = 1 (factory setting)

PUP1 = 1, PUP0 = 0

PUP1 = 1, PUP0 = 1

50(2)

200

400(2)

800(2)

tFVCC, V2MON, V3MON, Fall Time 20 mV/µs

tRVCC, V2MON, V3MON, Rise Time 20 mV/µs

VRVALID Reset Valid VCC 1V

tMD(2) MR to RESET/ RESET delay (activation only) 500 ns

VCC

VTRIP1

RESET

tPURST tPURST

tRPD1

VRVALID

MR tMD

tIN1

X40430, X40431, X40434, X40435

23 FN8251.1

May 24, 2006

Notes: (1) VCC = 5V at 25°C.

(2) Values based on characterization data only.

Watchdog Time Out For 2-Wire Interface

tin1 Pulse width for MR 5µs

tWDO Watchdog Timer Period:

WD1 = 0, WD0 = 0

WD1 = 0, WD0 = 1

WD1 = 1, WD0 = 0

WD1 = 1, WD0 = 1 (factory setting)

1.4(2)

200(2)

OFF

tRST1 Watchdog Reset Time Out Delay

WD1 = 0, WD0 = 0

WD1 = 0, WD0 = 1

100 200 300 ms

tRST2 Watchdog Reset Time Out Delay WD1 = 1, WD0 = 0 12.5 25 37.5 ms

tRSP Watchdog timer restart pulse width 1 µs

LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V) (CONTINUED)

Symbol Parameters Min Typ (1) Max Unit

< tWDO

tRST

WDO

SDA

Start

tWDO tRST

SCL

Start

tRSP

WDT

Restart

Start

SDA

SCL

Minimum Sequence to Reset WDT

Clockin (0 or 1)

X40430, X40431, X40434, X40435

24 FN8251.1

May 24, 2006

VTRIPX Set/Reset Conditions

VTRIP1, VTRIP2, VTRIP3 Programming Specifications: VCC = 2.0 - 5.5V; Temperature = 25°C

Parameter Description Min. Max. Unit

tVPS WDO Program Voltage Setup time 10 µs

tVPH WDO Program Voltage Hold time 10 µs

tTSU VTRIPX Level Setup time 10 µs

tTHD VTRIPX Level Hold (stable) time 10 µs

tWC VTRIPX Program Cycle 10 ms

tVPO Program Voltage Off time before next cycle 1 ms

VPProgramming Voltage 15 18 V

VTRAN1 VTRIP1 Set Voltage Range 2.0 4.75 V

VTRAN2 VTRIP2 Set Voltage Range – X40430, X40431 1.7 4.75 V

VTRAN2A VTRIP2 Set to Voltage Range – X40434, X40435 0.9 3.5 V

VTRAN3 VTRIP3 Set Voltage Range 1.7 4.75 V

Vtv VTRIPX Set Voltage variation after programming (-40 to +85°C). -25 +25 mV

tVPS WDO Program Voltage Setup time 10 µs

SCL

SDA

VCC/V2MON/V3MON

(VTRIPX)

WDO

tTSU

tTHD

tVPH

tVPS

tWC

tVPO

A0h

770 7

*0Dh

sets VTRIP1

sets VTRIP2

sets VTRIP3

*01h

*09h

*03h

*0Bh

*0Fh resets VTRIP3

resets VTRIP2

resets VTRIP1

Start

* all others reserved

00h

X40430, X40431, X40434, X40435

25 FN8251.1

May 24, 2006

X40430, X40431, X40434, X40435

Small Outline Package Family (SO)

GAUGE

PLANE

A1 L

DETAIL X 4° ±4°

SEATING

PLANE

0.010 BMCA

0.004 C

0.010 BMCA

(N/2)

NN (N/2)+1

PIN #1

I.D. MARK

h X 45°

SEE DETAIL “X”

0.010

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL SO-8 SO-14

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28) TOLERANCE NOTES

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

Rev. L 2/01

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8251.1

May 24, 2006

X40430, X40431, X40434, X40435

Thin Shrink Small Outline Plastic Packages (TSSOP)

INDEX

AREA E1

123

-B-

0.10(0.004) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

E0.25(0.010) BM M

0.25

0.010

GAUGE

PLANE

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar

protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-

sion at maximum material condition. Minimum space between protru-

sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact. (Angles in degrees)

0.05(0.002)

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.041 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.195 0.199 4.95 5.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N14 147

α0o8o0o8o-

Rev. 2 4/06