KVR667D2S8F5/1GI - KINGSTON TECHNOLOGY

Memory Module Specications

KVR667D2S8F5/1GI

1GB 128M x 72-Bit PC2-5300

CL5 ECC 240-Pin FBDIMM

Kingston.com

DESCRIPTION

This document describes ValueRAM’s 1GB (128M x 72-bit)

PC2-5300 CL5 SDRAM (Synchronous DRAM) “fully buffered”

ECC “single rank”, Intel® Compatibility Tested, memory

module. This module is based on nine 128M x 8-bit 667MHz

DDR2 FBGA components. The module also includes an

AMB device (Advanced Memory Buffer). The electrical and

mechanical specications are as follows:

SPECIFICATIONS

FBDIMM Module 240-pin

JEDEC Standard R/C A

Memory Organization 1 rank of x8 devices

DDR2 DRAM Interface SSTL_18

DDR2 Speed Grade 667 Mbps

CAS Latency 5-5-5

Module Bandwidth 5.3 GB/s

DRAM VDD = VDDQ = 1.8V

AMB VCC = VCCFBD = 1.5V

EEPROM VDDSPD = 3.3V (typical)

Heat Spreader Full DIMM Heat Spreader (FDHS)

PCB Height 30.35mm, double-side

RoHS Compliant

Continued >>

Document No. VALUERAM0852-001.A00 09/18/09 Page 1

continued ValueRAM

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DDR2 240-pin FBDIMM Pinout:

Front

Side

Back

Side

Front

Side

Back

Side

Front

Side

Back

Side

Front

Side

Back

Side

1VDD 121VDD 31 PN3151 SN361PN9 181SN9 91 PS9211SS9

2VDD 122VDD 32 PN3152SN3 62 VSS 182VSS 92 VSS 212VSS

3VDD 123VDD 33 VSS 153VSS 63 PN10183SN10 93 PS5213 SS5

4VSS 124VSS 34 PN4154 SN464PN10184SN1094 PS5214SS5

5VDD 125VDD 35 PN4155SN4 65 VSS 185VSS 95 VSS 215VSS

6VDD 126VDD 36 VSS 156VSS 66 PN11 186SN1196PS6 216SS6

7VDD 127VDD 37 PN5157 SN567PN11187SN1197 PS6217SS6

8VSS 128VSS 38 PN5158SN5 68 VSS 188VSS 98 VSS 218VSS

9VCC 129VCC 39 VSS 159VSS KEY 99 PS7219 SS7

10 VCC 130VCC 40 PN13160 SN13 69 VSS 189VSS 100PS7 220SS7

11 VSS 131VSS 41 PN13161SN1370 PS0190 SS0101 VSS 221VSS

12 VCC 132VCC 42 VSS 162VSS 71 PS0191 SS0 102PS8 222SS8

13 VCC 133VCC 43 VSS 163VSS 72 VSS 192VSS 103PS8 223SS8

14 VSS 134VSS 44 RFU* 164RFU*73PS1 193SS1 104VSS 224VSS

15 VTT 135VTT 45 RFU*165 RFU* 74 PS1194 SS1 105RFU** 225RFU**

16 VID1 136VID046VSS 166VSS 75 VSS 195VSS 106RFU** 226RFU**

17 RESET 137 DNU/M_Test 47 VSS 167VSS 76 PS2196 SS2107 VSS 227VSS

18 VSS 138VSS 48 PN12168 SN12 77 PS2197 SS2 108VDD 228SCK

19 RFU** 139RFU** 49 PN12169SN1278 VSS 198VSS 109VDD 229SCK

20 RFU** 140RFU** 50 VSS 170VSS 79 PS3199 SS3110 VSS 230VSS

21 VSS 141VSS 51 PN6171 SN680PS3 200 SS3 111VDD 231VDD

22 PN0142 SN052PN6 172SN6 81 VSS 201VSS 112VDD 232VDD

23 PN0143SN0 53 VSS 173VSS 82 PS4202 SS4113 VDD 233VDD

24 VSS 144VSS 54 PN7174 SN783PS4 203 SS4 114VSS 234VSS

25 PN1145 SN155PN7 175SN7 84 VSS 204VSS 115VDD 235VDD

26 PN1146SN1 56 VSS 176VSS 85 VSS 205VSS 116VDD 236VDD

27 VSS 147VSS 57 PN8177 SN886RFU*206 RFU*117 VTT 237VTT

28 PN2148 SN258PN8 178SN8 87 RFU*207 RFU* 118SA2 238 VDDSPD

29 PN2149SN2 59 VSS 179VSS 88 VSS 208VSS 119SDA 239SA0

30 VSS 150VSS 60 PN9180 SN989VSS 209VSS 120SCL 240SA1

90 PS9210 SS9

RFU = Reserved Future Use.

* These pin positions are reserved for forwarded clocks to be used in future module implementations

** These pin positions are reserved for future architecture flexibility

1) The following signals are CRC bits and thus appear out of the normal sequence: PN12/PN12, SN12/SN12, PN13/PN13, SN13/SN13,

PS9/PS9, SS9/SS9

continued ValueRAM

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DIMM Connector Pin Description:

Pin Name Pin Description Count

SCK System Clock Input, positive line11

SCK System Clock Input, negative line11

41senil evitisop ,ataD dnuobhtroN yramirP]0:31[NP

PN 41senil evitagen ,ataD dnuobhtroN yramirP]0:31[

01senil evitisop ,ataD dnuobhtuoS yramirP]0:9[SP

PS 01senil evitagen ,ataD dnuobhtuoS yramirP]0:9[

41senil evitisop ,ataD dnuobhtroN yradnoceS]0:31[NS

SN 41senil evitagen ,ataD dnuobhtroN yradnoceS]0:31[

01senil evitisop ,ataD dnuobhtuoS yradnoceS]0:9[SS

SS 01senil evitagen ,ataD dnuobhtuoS yradnoceS]0:9[

1tupnI kcolC )DPS( tceteD ecneserP laireSLCS

SDA SPD Data Input / Output 1

3BMA eht ni rebmun MMID eht tceles ot desu osla ,stupnI sserddA DPS]0:2[AS

VID[1:0] Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs

VID[0] is VDD value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is VCC value: OPEN = 1.5 V, GND = 1.2 V 2

RESETAMB reset signal 1

RFU Reserved for Future Use216

VCC 8)tloV 5.1( rewoP ecafretnI lennahC BMA dna rewoP eroC BMA

VDD 42)tloV 8.1( rewoP O/I MARD BMA dna rewoP MARD

VTT DRAM Address/Command/Clock Termination Power (V DD/2) 4

VDDSPDSPD Power 1

VSS Ground 80

DNU/M_Test

The DNU/M_Test pin provides an exter nal connection on R/Cs A-D for testing

the margin of Vref which is produced by a voltage divider on the module. It

is not intended to be used in normal system operation and must not be

connected (DNU) in a system. This test pin may have other features on future card designs

and if it does, will be included in this specification at that time.

Total 240

1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency

2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility

Absolute Maximum Ratings

5°

AMB device operating temperature (Ambient) 0110 °C

Symbol Parameter MIN MAX Units

IN, VOUT

Voltage on any pin relative to V

-0.31.75 V

Voltage on V

pin relative to V

-0.31.75 V

Voltage V

pin relative to Vss -0.5 2.3 V

Voltage on V

pin relative to V

-0.5 2.3 V

STG

Storage temperature-55100 °C

CASE

DDR2 SDRAM device operat ing temperature (Ambient)

Note: (1) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.

(1)

continued ValueRAM

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DQS0

VSS

D0-D8, AMB

D0-D8,SPD,AMB

D0-D8

VREF

SPD, AMB

Serial PD

A1 A2

SA0SA1 SA2

SDA

SCL

DQS0

DQS1

DQS2

DQS3

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

DQS4

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

DQS5

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

DQS6

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

DQS7

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

DM/

DQS8

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

DQS8

RDQS

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

DM/

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

RDQS

DQ12

DQ13

DQ14

DQ15

DQ8

DQ9

DQ10

DQ11

DM/

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

RDQS

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DM/

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

RDQS

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

DM/

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

RDQS

DM/

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

RDQS

DM/

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

RDQS

DM/

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

RDQS

DM/

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

RDQS

VDD

VDDSPD

AMB

VCC

VTT

Notes:

1. DQ-to-I/O wiring may be changed within a byte.

2. There are two physical copies of each address/command/con-

trol/clock

VTT Terminators

DQS9

DQS10

DQS13

DQS14

DQS11

DQS12

DQS15

DQS16

DQS17

PN0-PN13

PS0-PS9

SS0-SS9

WE (all SDRAMs)

CK/CK (all SDRAMs)

BA0-BA2 (all SDRAMs)

A0-A15 (all SDRAMs)

RAS (all SDRAMs)

CAS (all SDRAMs)

ODT -> ODT (all SDRAMs)

SN0-SN13

CKE0 -> CKE (all SDRAMs)

S0 -> CS (all SDRAMs)

DQ0-DQ63

CB0-CB7

DQS0-DQS17

DQS0-DQS8

All address/command/control/clock

SCL

SDA

SA1-SA2

RESET

SCK/SCK

SA0

Functional Block Diagram:

825

continued ValueRAM

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Architecture:

Advanced Memory Buffer Pin Description:

Pin Name Pin Description Count

FB-DIMM Channel Signals 99

1enil evitisop ,tupnI kcolC metsySKCS

SCK 1enil evitagen ,tupnI kcolC metsyS

41senil evitisop ,ataD dnuobhtroN yramirP]0:31[NP

PN 41senil evitagen ,ataD dnuobhtroN yramirP]0:31[

01senil evitisop ,ataD dnuobhtuoS yramirP]0:9[SP

PS 01senil evitagen ,ataD dnuobhtuoS yramirP]0:9[

41senil evitisop ,ataD dnuobhtroN yradnoceS]0:31[NS

SN 41senil evitagen ,ataD dnuobhtroN yradnoceS]0:31[

01senil evitisop ,ataD dnuobhtuoS yradnoceS]0:9[SS

SS 01senil evitagen ,ataD dnuobhtuoS yradnoceS]0:9[

FBDRESTo an external precision cali 1ccV ot detcennoc rotsiser noitarb

DDR2 Interface Signals 175

DQS[8:0] Data Strobes, positive lines 9

DQS[8:0] Data Strobes, negative lines 9

DQS[17:9]/DM[8:0]Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes

DQS 9senil evitagen ,)ylno MARD 4x( sebortS ataD]9:71[

DQ[63:0]Data 64

CB[7:0]Checkbits 8

23dnammoc egrahc-erp eht fo trap si 01A .sesserddAB]0:51[A ,A]0:51[A

BA[2:0]A, BA[2:0]BBank Addresses 6

RASA, RASBPart of command, with CAS, WE, and CS 2.]0:1[

CASA, CASBPart of command, with RAS, WE, and CS 2.]0:1[

WEA, WEBPart of command, with RAS, CAS, and CS 2.]0:1[

ODTA, ODTB On-die Termination Enable 2

CKE[1:0]A, CKE[1:0]BClock Enable (one per rank) 4

CS[1:0]A, CS[1:0]BChip Select (one per rank) 4

CLK[3:0] CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:2] should be out-

put disabled when not in use. 4

CLK[3:0] Negative lines for CLK[3:0] 4

1.81C_CRDD dna 81B_CRDD rof nip nruter nommoC :noitasnepmoC RDD41C_CRDD

141C_CRDD nip nruter nommoc ot detcennoc rotsiseR :noitasnepmoC RDD81B_CRDD

141C_CRDD nip nruter nommoc ot detcennoc rotsiseR :noitasnepmoC RDD81C_CRDD

DDRC_B12 DDR Compensation: Resistor connected to VSS 1

DDRC_C12 DDR Compensation: Resistor connected to VDD 1

continued ValueRAM

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SPD Bus Interface Signals 5

1tupnI kcolC )DPS( tceteD ecneserP laireSLCS

SDA SPD Data Input / Output 1

3BMA eht ni rebmun MMID eht tceles ot desu osla ,stupnI sserddA DPS]0:2[AS

Miscellaneous Signals 163

PLLTSTOP LL Clock Observability Output 1

1.CCV ot retlif ssap wol htiw deiT .LLP eht rof CCV golanALLPACCV

VSSAPLLA nalog VSS for the PLL. Tied to ground on the AMB die. Do not tie to ground on the DIMM.1

TEST_pin# Leave floating on the DIMM 6

TESTLO_pin# Tie to ground on the DIMM25

1”.MMID no reffub“ sa ytilanoitcnuf tes ot dnuorg ot eiTCNUFB

RESETAMB reset signal 1

NC No connect. Many NC are connected to VDD on the DIMM, to lower the impedance of the VDD power

islands. 129

RFUR eserved for Future Use 18

Power/Ground Signals 213

VCC AMB Core Power (1.5 Volt) 24

VCCFBD 8)tloV 5.1( rewoP O/I lennahC BMA

VDD 42)tloV 8.1( rewoP O/I MARD BMA

VDDSPD SPD Power (3.3 Volt) 1

VSS Ground 156

556 latoT

1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency.

2. TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on prototype DIMMs: each pin should have a zero

ohm resistor pulldown to ground, and an unpopulated resistor pullup to VCC. These resistors can be replaced on production

DIMMs with a direct connection to ground.

Advanced Memory Buffer Pin Description:

continued ValueRAM

Kingston.com Document No. VALUERAM0852-001.A00 09/18/09 Page 7

TECHNOLOGY

AMB

Advanced Memory Buffer

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

Package Dimensions:

(Units = millimeters)

Units: inches (millimeters)

0.054 (1.37)

0.046 (1.17)

0.346 (8.8)

MAX with heat sink

Detail A

0.047 (1.19)

0.042 (1.06)

45°x 0.0071(0.18)