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LMK01801BEVAL Evaluation Board Operating Instructions
1
LMK01801
Dual Clock Divider Buffer
Evaluation Board Operating Instructions
7 December 2011
LMK01801 EVAL
Texas Instruments, Inc.
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Table of Contents
TABLE OF CONTENTS ....................................................................................................................... 2
TABLE OF FIGURES........................................................................................................................... 3
GENERAL DESCRIPTION ................................................................................................................... 4
Block Diagram ........................................................................................................................................................... 4
Evaluation Board Kit Contents ................................................................................................................................... 5
Quick Start – Code Loader Mode ............................................................................................................................... 6
Quick Start – Pin Control Mode ................................................................................................................................. 7
Pin Control Modes ...................................................................................................................................................... 8
Using CodeLoader to Program the LMK01801 ......................................................................................................... 9
Evaluation Board Inputs/Out puts ............................................................................................................................. 12
RECOMMENDED TEST EQUIPMENT ................................................................................................. 14
APPENDIX A: CODELOADER USAGE .............................................................................................. 15
APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS ......................................................... 19
LMK01801 Sample Output Wavef orms ................................................................................................................... 25
LMK01801 Analog Delay Sample Data................................................................................................................... 26
APPENDIX C: SCHEMATICS ............................................................................................................ 28
Power ........................................................................................................................................................................ 28
Main ......................................................................................................................................................................... 29
Inputs ........................................................................................................................................................................ 30
Inputs Page 2 ............................................................................................................................................................ 31
Clock Outputs Page 1 ............................................................................................................................................... 32
Clock Outputs Page 2 ............................................................................................................................................... 33
Clock Outputs Page 3 ............................................................................................................................................... 34
APPENDIX D: BILL OF MATERIALS ................................................................................................ 35
Common Bill of Materials for Evaluation Boards .................................................................................................... 35
APPENDIX E: BALUN INFORMATION .............................................................................................. 38
Typical Balun Frequency Response ......................................................................................................................... 38
APPENDIX F: PROPERLY CONFIGURING LPT PORT ........................................................................ 39
LPT Driver Loading ................................................................................................................................................. 39
Correct LPT Port/Address ........................................................................................................................................ 39
Correct LPT Mode .................................................................................................................................................... 40
APPENDIX G: DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY ....................................... 41
APPENDIXHI: TROUBLESHOOTING INFORMATION .......................................................................... 42
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Table of Figures
Figure 1 - LMK01801 Block Diagram ........................................................................................... 4
Figure 2 - Quick Start Diagram ...................................................................................................... 6
Figure 3 - Pin Control Mode Quick Start Diagram......................................................................... 7
Figure 4 – Selecting the LMK01801 .............................................................................................. 9
Figure 6 – Setting the 122.88 MHz VCXO Default mode ........................................................... 10
Figure 5 - Loading the Device ...................................................................................................... 10
Figure 7 - Setting Divide, CLKout_TYPE, Enabled for CLKout1 on "Clock Outputs" tab. ....... 11
Figure 8 - Setting LVCMOS modes. ............................................................................................ 11
Figure 9 - Port Setup tab ............................................................................................................... 15
Figure 10 - Clock Outputs tab ....................................................................................................... 16
Figure 11 - Bits/Pins tab. .............................................................................................................. 17
Figure 12 - LMK01801 Phase Noise @ 100 MHz with Output Divider = 1 ................................ 20
Figure 13 - LMK01801 Phase Noise @ 100 MHz with Output Divider = 4 ................................ 21
Figure 14 - LMK01801 Phase Noise @ 983.04 MHz with Output Divider = 1 ........................... 22
Figure 15 - LMK01801 Phase Noise @ 983.04 MHz with Output Divider = 4 ........................... 23
Figure 16 - Phase Noise Measurement Set-Up ............................................................................. 24
Figure 17 - Noisy vs. Clean Phase Noise ...................................................................................... 24
Figure 18 - LMK01801 Sample Clock Output Waveforms .......................................................... 25
Figure 19 - CLKout12 and CLKout13 No Analog Delay............................................................. 26
Figure 20 - CLKout12 with 100 pSec of delay relative to CLKout13.......................................... 27
Figure 21 - Typical Balun Frequency Response ........................................................................... 38
Figure 22 - Successfully Opened LPT Driver ............................................................................... 39
Figure 23 - Selecting the LPT Port ............................................................................................... 40
Figure 24 - Two Different Definitions .......................................................................................... 41
Figure 25 - Two Different Definitions .......................................................................................... 41
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General Description
The LMK01801 Evaluation Board simplifies evaluation of the LMK01801 Dual Clock Buffer
Divider. Configuring and controlling the board is accomplished using Texas Instrument’s
CodeLoader software, which can be downloaded from: http://www.ti.com/tool/codeloader. The
LMK01801 can also be configured to operate in a pin control mode via headers on the PCB.
Block Diagram
The block diagram in Figure 1 illustrates the functional architecture of the LMK01801 clock
divider buffer. The LMK01801 is a very low noise solution for clocking systems that require
distribution and frequency division of precision clocks. The LMK01801 features extremely low
residual noise, frequency division, digital and analog delay adjustments, and fourteen (14)
programmable differential outputs: LVPECL, LVDS and LVCMOS (2 outputs per differential
output). The LMK01801 features two independent inputs that can be driven differentially or in
single-ended mode. The first input drives output Bank A consisting of eight (8) outputs. The
second input drives output Bank B consisting of six (6) outputs.
Figure 1 - LMK01801 Block Diagram
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Evaluation Board Kit Contents
The evaluation board kit contains…
An LMK01801 Evaluation board.
LMK01801 Family quick start guide.
o Evaluation board instructions are downloadable from the product folder on Texas
Instument’s website, www.ti.com/.
CodeLoader uWire cable (LPT --> uWire).
A USB interface board can be purchased separately under NSID USB2UWIRE_IFACE.
The CodeLoader software will run on a Windows 2000 or Windows XP PC. The CodeLoader
software is used to program the internal registers of the LMK01801 device through a
MICROWIRETM interface.
Clock output configuration:
Clock Output Type Output Connector Installed
0 LVPECL Yes
1 LVPECL No
2 LVPECL Yes
3 LVPECL No
4 LVPECL Yes
5 LVPECL No
6 LVPECL Yes
7 LVPECL No
8 LVPECL Yes
9 LVPECL Yes
10 LVPECL Yes
11 LVPECL Yes
12 LVPECL Yes
13 LVPECL Yes
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Quick Start – Code Loader Mode
1. Connect a voltage of 3.3 volts to either the Vcc SMA connector or the alternate terminal
block.
2. Connect a reference clock from a signal generator or other source. Exact frequency
depends on programming.
3. Connect the uWire header to a computer parallel port with the CodeLoader cable. A
USB communication option is available, search at www.ti.com/ for: USB2UWIRE-
IFACE.
4. Install jumpers on TYPE0, TYPE1, TYPE2, DivVal0, DivVal1, DivVal2 in the middle
‘uWire’ (pins 3,5) position but NOT on EN_PIN_CTRL.
5. Program the device with CodeLoader. Ctrl-L m ust be pressed at least once to load all
registers once after CodeLoader is started or after restoring a Mode. CodeLoader is
available for download at www.ti.com/tool/codeloader.
6. Measurements may be made at any clock output if enabled by programming.
Figure 2 - Quick Start Dia gr am
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Quick Start – Pin Control Mode
1. Connect a voltage of 3.3 volts to either the Vcc SMA connector or the alternate connector.
2. Connect a reference clock from a signal generator or other source. Exact frequency
depends on programming.
3. Install a jumper on EN_PIN_CTRL header in either the High or Low position.
4. Install other jumpers on Type0, Type1, Type2, DivVal0, DivVal1, and DivVal2 headers
based on the configurations shown in Table 1 and Table 2.
Figure 3 - Pin Control Mo de Quick Start Diagram
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Pin Control Modes
For the following tables, Low is defined as installing a jumper between pins 5 and 6 on the
desired header. A HIGH is defined as installing a jumper between pins 1 and 2 on the desired
header.
If EN_PIN_CTRL = LOW (jumper installed between header positions 5 and 6) then the
following table describes possible output configurations:
Header Output Groups Header = Low Header = Middle Header = High
Type0 CLKout0 – CLKout3 LVDS Powerdown LVPECL
Type1 CLKout4 – CLKout7 LVDS LVCMOS (Norm/Inv) LVPECL
Type2 CLKout8 – CLKout13 LVDS LVCMOS (Norm/Inv) LVPECL
DivVal0 CLKout0-3 Divider ÷1 ÷4 ÷2
DivVal1 CLKout4-7 Divider ÷1 ÷4 ÷2
DivVal2 CLKout8-11 Divider ÷1 ÷4 ÷2
CLKout12-13 Divider ÷8 ÷512 ÷16
Table 1 - EN_PIN_CTRL = LOW Configuration
If EN_PIN_CTRL = HIGH (jumper installed between header positions 1 and 2) then the
following table describes possible output configurations:
Header Output Groups Header = Low Header = Middle Header = High
Type0
CLKout0 – CLKout3 LVDS
LVPECL LVPECL
CLKout4 – CLKout7 LVCMOS (Norm/Inv)
Type1 CLKout8 – CLKout11 LVDS LVCMOS (Norm/Inv) LVPECL
Type2 CLKout12-13 LVDS LVCMOS (Norm/Inv) LVPECL
DivVal0 CLKout0-7 Divider ÷1 ÷4 ÷2
DivVal1 CLKout8-11 Divider ÷1 ÷4 ÷2
DivVal2 CLKout12-13 Divider ÷4 ÷512 ÷16
Table 2 - EN_PIN_CTRL = HIGH Configuration
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Using CodeLoader to Program the LMK01801
The purpose of this section is to walk the user through using CodeLoader to make some
measurements with the LMK01801 device. For more information on CodeLoader refer to
Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.ti.com/tool/codeloader/.
Before proceeding, be sure to follow the Quick Start section above to ensure proper connections.
1. Start CodeLoader 4 Application
Click “Start” “Programs” “CodeLoader 4” “CodeLoader 4”
The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.
2. Select Device
Click “Select Device” “Clock Conditioners” “LMK01801A1”
Once started CodeLoader 4 will load the last used device. To load a new device click “Select
Device” from the menu bar, then select the subgroup and finally device to load. For this
example, the LMK01800A1 is chosen.
Selecting the device does cause the device to
be programmed. However, it is advisable to
do CTRL-L to ensure programming.
Fi
g
ure 4 – Selectin
g
the LMK01801
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3. Program/Load Device
Press “Ctrl – L”
Assuming the Port Settings are correct, it is now
possible to click “Keyboard Controls” “Load
Device” from the menu to program the device to the
current state of the newly loaded LMK01801 file. Ctrl-
L is the accelerator assigned to the Load Device option
and is very convenient.
Once the device has been loaded, by default
CodeLoader will automatically program changed
registers, so it is not necessary to load the device
again completely. It is possible to disable this functionality by ensuring there is no checkmark
by the “Options” “AutoReload with Changes.”
Since a default mode will be restored in the next step, th is step isn’t really needed but included to
emphasize the importance of pressing “Ctrl-L” to load the device at least once after starting
CodeLoader, restoring a mode, or restoring a saved setup using the File menu.
See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.ti.com/tool/codeloader for more information on port setup. Appendix H:
Troubleshooting Information contains information on troubleshooting communications.
4. Restoring a Defa ult Mode
Click “Mode” “122.88 MHz VCXO Default”; then
Press “Ctrl – L”
Figure 6 – Setting the 122.88 MHz VCXO Default mode
For the purposes of this walkthrough a default mode will be loaded to ensure a common starting
point. This is important because when CodeLoader is closed, it remembers the last settings used
for a particular device. By loading the default mode a common starting point is ensured.
Loading a mode does not automatically program the device so it is necessary to press
“Ctrl – L” again to program the device.
Figure 5 - Loading the Devi ce
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5. Enable Clock Outputs
To measure phase noise at the clock outputs,
1. Click on the “Bank A” tab,
2. Enable an output,
3. Then set the
a. CLKout Type,
b. divide value
Figure 7 - Setting Divide, CLKout_TYPE , Ena bl e d for CL Kout1 on "Clock Outp u ts" t ab.
4. Connect the clock output SMAs to a spectrum analyzer or signal source analyzer.
a. For LVDS, a balun is recommended such as the ADT2-1T (for frequency range of
0.4 MHz to 450 MHz).
b. For LVPECL,
i. A balun can be used, or
ii. One side of the LVPECL signal can be terminated with a 50 ohm load and
the other side can be run to the test equipment
single ended.
c. For LVCMOS,
i. One side of the LVCMOS signal can be
terminated with a 50 ohm load and the other
side can be run to the test equipment single
ended.
5. The phase noise may be measured with a spectrum analyzer
or signal source analyzer.
See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock
outputs.
Figure 8 - Setting
LVCMOS modes.
This CLKoutX frequency value is only valid if
the correct clock in value is specified. It may
not necessarily represent the actual frequency
unless manually entered. This is a
mathematical calculation only, not a measured
value.
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Evaluation Board Inputs/Outputs
The following table contains descriptions of the various inputs and outputs for the evaluation
board.
Table 3. LMK01801 Evaluation Board I/O
Connector Name Input/Output Description
CLKout0 /
CLKout0*,
CLKout2 /
CLKout2*,
CLKout4 /
CLKout4*,
CLKout6 /
CLKout6*,
CLKout8 /
CLKout8*,
CLKout9/
CLKout9*,
CLKout10 /
CLKout10*,
CLKout11/
CLKout11*,
CLKout12 /
CLKout12*,
CLKout13 /
CLKout13*
Output
Populated connectors.
Differential clock output pairs. All outputs are configured
in LVPECL mode.
On the evaluation board, all clock outputs are AC-coupled
to allow safe testing with RF test equipment.
All LVPECL/2VPECL clock outputs are
terminated to GND with a 240 ohm resistor, one on
each output pin of the pair.
Vcc Input
Populated connector.
DC power supply for the PCB. Removing R1, R2, or R3
allow for splitting the power to various devices on the
board.
Note: The LMK01801 Family contains internal voltage
regulators for the VCO, PLL and related circuitry. The
clock outputs do not have an internal regulator. A clean
power supply is required for best performance.
Vcc2 Input
Unpopulated connector.
Vcc input to power the output planes separately from the
Aux Plane. Refer to schematics for more information.
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Connector Name Input/Output Description
CLKin0/CLKin0*,
CLKin1/CLKin1* Input
Populated connectors.
The default board configuration is setup for a single-ended
reference source at CLKin0* (CLKin0 pin is AC-coupled
to ground).
If a DC-coupled clock is used to drive either of the inputs,
the high voltage level must be at least 2 volts and the low
voltage no greater than 0.4 volts.
uWire Input/Output
Populated connector.
10-pin header programming interface for the board. Of
Most important are the CLKuWi re, DATAuWire, and
LEuWire programming lines from this header. Each of
these signals, TEST, and SYNC0, and SYNC1 can be
monitored through test points on the board.
SYNC0,
SYNC1 Input Unpopulated connector.
Access to SYNC0 or SYNC1 of device.
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Recommended Test Equipment
Power Supply
The Power Supply should be a low noise power supply.
Phase Noise / Spectrum Analyzer
For measuring phase noise an Agilent E5052A Signal Source Analyzer is recommended. An
Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the
architecture of the E5052A is superior for phase noise measurements. At frequencies less than
100 MHz the local oscillator noise of the E4445A is too high and measurements will reflect the
E4445A’s internal local oscillator performance, not the device under test.
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Appendix A: CodeLoader Usage
CodeLoader is used to program the evaluation board with either an LPT port using the included
CodeLoader cable or with a USB port using the optional USB <--> uWire cable available from
http://www.ti.com/. The part number is USB2UWIRE-IFACE.
Port Setup Tab
Figure 9 - Port Setup tab
On the Port Setup tab, the user may select the type of communication port (USB or Parallel) that
will be used to program the device on the evaluation board. If parallel port is selected, the user
should ensure that the correct port address is entered.
The Pin Configuration field is hardware dependent and normally SHOULD NOT be changed by
the user. Figure 9 shows the default settings.
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Clock Outputs Tab
Figure 10 - Clock Outputs tab
The clock outputs tab allows the user to Enable/Disable individual clock outputs, select the clock
mode (Bypass/Divided/Delayed/Divided & Delayed – for outputs 12 and 13), set the clock
output delay value (if delay is enabled for outputs 12 and 13 only), and the clock output divider
value (2, 4, 6, …, 510 for clock outputs 12 and 13 or 1-8 for clock outputs 0 - 11).
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Bits/Pins Tab
Figure 11 - Bits/Pins tab.
The Bits/Pins tab allows the user to program bits directly. Many of which are not available on
other tabs. Refer to the datasheet for more detailed information. The bits available are:
Common Box
o RESET - Set the reset bit. This will reset the device. In a normal application it is
not necessary to program this bit clear since it is auto-clearing. However in the
CodeLoader software, RESET must be clicked again (cleared) to not cause a reset
every time R7 is programmed.
o POWERDOWN - Place the device in powerdown mode.
Program Pins Box – These pins only have effect if the PWB headers are in the uWire
position (3-5). See Figure 2 - Quick Start Diagram for the correct configuration.
o EN_PIN_CTRL – Sets the control of the output via uWire or pins
o SYNC0 – Set high or low voltage on SYNC0 pin. Checked is high voltage.
o TRIGGER – Set high or low voltage on pin 10 of uWire header.
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Registers Tab
The registers tab shows the value of each register. This is convenient for programming the
device to the desired settings, then recording the hex values for programming in your own
application. The “Export register values in hex to text file” button will allow these register
values to be saved to a text file.
By clicking in the “bit field” it is possible to manually change the value of registers by typing ‘1’
and ‘0.’
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Appendix B: Typical Phase Noise Performance Plots
Clock Outputs
The LMK01801 Family features LVDS, LVPECL, 2VPECL, and LVCMOS types of outputs.
Include are the phase noise plots for the following outputs.
Device CLKoutX Output Divide Output Type
LMK01801A1 8 1 LVPECL
LMK01801A1 8 4 LVPECL
LMK01801A1 8 1 2VPECL
LMK01801A1 8 4 2VPECL
LMK01801A1 4 1 LVDS
LMK01801A1 4 4 LVDS
LMK01801A1 4 1 LVCMOS(Norm/Inv)
LMK01801A1 4 4 LVCMOS(Norm/Inv)
Table 4 - Phase Noise Output Test Co nfiguration
Clock Output Measurement Technique
The measurement technique for each output type varies.
LVPECL/2VPECL – Measured by using an Minicircuits ADT2-1T balun on the input and on the
output.
LVCMOS and LVDS – Measured by using an Minicircuits ADT2-1T balun on the output and
single ended input.
Parameter Test Case 1 Test Case 2 Test Case 3 Test Case 4
Input Source Wenzel XTAL Wenzel XTAL SMHU Rohde&Schwarz
SMHU
Input Frequency 100 MHz 100 MHz 983.04 MHz 983.04 MHz
Input Power 0 dBm 0 dBm 0 dBm 0 dBm
Output Divider 1 4 1 4
Figure Figure 12 Figure 13 Figure 14 Figure 15
Table 5 - LMK01801 test conditions
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LMK01801 Phase Noise, CLKin = 100 MHz, Output Divider = 1
Figure 12 - LMK01801 Phase Noise @ 100 MH z with Output Divider = 1
‐180
‐170
‐160
‐150
‐140
‐130
‐120
‐110
‐100
‐90
‐80
10.0E+0 1.0E+3 100.0E+3 10.0E+6
PhaseNoisewithOutputDivider=1
Wenzel100MHzXTAL
CLKout8_2VPECL
CLKout8_LVPECL
CLKout4_LVDS
CLKout4_LVCMOS(NORM/INV)
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LMK01801 Phase Noise, CLKin = 100 MHz, Output Divider = 4
Figure 13 - LMK01801 Phase Noise @ 100 MH z with Output Divider = 4
‐180
‐170
‐160
‐150
‐140
‐130
‐120
‐110
‐100
‐90
‐80
10.0E+0 100.0E+0 1.0E+3 10.0E+3 100.0E+3 1.0E+6
PhaseNoisewithOutputDivider=4
Wenzel100MHzXTAL
CLKout8_2VPECL
CLKout8_LVPECL
CLKout4_LVDS
CLKout4_LVCMOS(NORM/INV)
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LMK01801 Phase Noise, CLKin = 983.04 MHz, Output Divider = 1
Figure 14 - LMK01801 Phase Noise @ 983.04 MHz with Output Divider = 1
‐180
‐160
‐140
‐120
‐100
‐80
‐60
10.0E+0 100.0E+0 1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6
PhaseNoisewithDivider=1
LVDS/1
LVCMOS/1
2VPECL/1
LVPECL/1
SMHU
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LMK01801 Phase Noise, CLKin = 983.04 MHz, Output Divider = 4
Figure 15 - LMK01801 Phase Noise @ 983.04 MHz with Output Divider = 4
‐180
‐160
‐140
‐120
‐100
‐80
‐60
10.0E+0 100.0E+0 1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6
PhaseNoisewithDivider=4
LVDS/4
LVCMOS/4
2VPECL/4
LVPECL/4
SMHU
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Phase Noise Measurement
Si gnal
Source LMK01801 Agilent
5052A
RF Output @
1 GHz, 0dBm CL Kin0 or
CLKin1 CLKoutX /
CLKoutX*
!
Power
Supply
Figure 16 - Phase Noise Measurement Set-Up
The phase noise of the signal source will impact the measured phase noise of the LMK01801.
Figure 17 - Noisy vs. Clean Phase Noise
Noisy Signal
Source!
Clean Signal
Source!
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LMK01801 Sample Output W aveforms
Figure 18 - LMK01801 Sample Clock Output Waveforms
The output waveforms shown in Figure 18 were taken at a clock in frequency of 122.88 MHz,
AC coupled. These measurements follow the VID voltage convention – See Appendix G:
Differential Voltage Measurement Terminology for more information.
The output modes are as follows:
Trace Clock Output Output Type
A CLKout0 2VPECL
B CLKout1 PECL (Low Power)
C CLKout4 LVDS
D CLKout5 LVCMOS (Normal/Invert)
A
B
C
D
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LMK01801 Analog Delay Sample Data
The sample analog delay data was taken at a clock in frequency of 122.88 MHz, output format of 2VPECL. Notice in Figure 19 that
with analog delay enabled there is approximately 460 ps of delay. Then in Figure 20 we added 100 ps of delay and the resulting delay
is approximately 550 ps.
Figure 19 - CLKout12 and CLKout13 No Analog Delay
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Figure 20 - CLKout12 with 100 pSec of delay relative to CLKout13
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Appendix C: Schematics
Power
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
39Power Supplies
10/25/2011
Power.SchDoc
Sheet Title:
Size: Schematic:
Mod. Date:
File:
Rev:
Sheet: of
B
National Semiconductor and/or its licensors do not warrant the accuracy or completeness of
this specification or any information contained therein. National and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit
for any particular purpose, or will operate in an implementation. National and/or its licensors
do not warrant that the design is production worthy. You should completely validate and test
your desi g n implementation to confirm the system functionality for your application.
© Copyright, National Semiconductor, 2009
http://www.national.com
Contact: http://www.national.com/support
LMK01801 SVBProject:
Designed for: Evaluation Customer
870xxxxxx 1.0
Assembly Variant: Version1
1000
R179
VccCLKoutPlaneA
1000
R329
LDO Power Options
Vcc
VccAuxPlane
VccCLKoutPlaneA
Direct Power
IN
4
ADJ 6
GND 3
NC
7
SD
8
DAP
9
OUT 5
BYP 1
NC
2
U301
LP3878SD-ADJ
LP3878-ADJ 3.3 V component values:
C350 = 4.7 uF
R349= 51 k
C354 = 0.01 uF R351= 866
C352 = 10 uF
R350= 2.00 k
C351 = 2.2 nF
0
R340
DNP
11
22
J1
TERMBLOCK_2
IN
6OUT 1
GND 3
EN
4NC 5
DAP
7NC 2
U302
LP5900SD-3.3
GND
V_LM3878-ADJB
V_LM5900
C367 = 0.47 uF
C368 = 0.47 uF
R359 = 51 k
Designators greater than and equal to 300 are placed on bottom of PCB
LP3878SD-ADJ
LP5900SD-3.3
LP5900 Component values
0
R335
1000
R334
0.1µF
C314
1µF
C313
10µF
C312
0.01µF
C327
DNP
0.1µF
C326
1µF
C325
Populate R215 and Open R227
to use low-noise LP5900
regulator option to power CG1
and CG2 supply planes.
LDO_OutB
TESTPOINT
VccTP
TESTPOINT
51k
R353
0.01µF
C350
2.00k
R354
866
R355
51k
R357
0.47µF
C351 0.47µF
C352
2200pF
C346
0
R337
0.01µF
C330
DNP
0.1µF
C329
1µF
C328
1000
R336 Vcc3_CLKout_CG1
CG1
CG0
Vcc1_CLKout_CG0
VccCLKoutPlaneB
4.7µF
C349
1000
R341
DNPIN
4
ADJ 6
GND 3
NC
7
SD
8
DAP
9
OUT 5
BYP 1
NC
2
U300
LP3878SD-ADJ LDO_OutA
TESTPOINT
51k
R342
0.01µF
C337
2.00k
R343
866
R345
2200pF
C333 1µF
C332
DNP
4.7µF
C335
DNP
VccCLKoutPlaneAV_LM3878-ADJA
VccCLKoutPlaneB
1000
R332
0.1µF
C321
1µF
C320
10µF
C319
Vcc
SMA
0
R339
DNP
0.1µF
C56
1µF
C55
10µF
C54
0
R331 Vcc2_CLKin0
CLKin0
0.1µF
C318
0.01µF
C340
DNP
0.1µF
C339
1µF
C338
0
R350
1000
R346
0
R347
0.01µF
C344
DNP
0.1µF
C343
1µF
C342
1000
R349
Vcc10_CG3_p47
Vcc13_CG0_p64
CG3
CG2
Vcc7_CLKout_CG3
Vcc5_CLKout_CG2
1000
R344 Vcc6_CLKin1
CLKin1
0.1µF
C336
DNP
1000
R348
DNP
VccAuxPlane
1000
R351
DNP
VccCLKoutPlaneB
1µF
C345
10µF
C334
DNP
10µF
C347
0
R356 LDO_LP5900
TESTPOINT
VccAuxPlane
1µF
C341
Vcc2
SMA
DNP
VccCLKoutPlaneB
0.1µF
C324
DNP
1µF
C323
DNP
10µF
C322
DNP
1000
R333
DNP
VccCLKoutPlaneA
0.1µF
C317
DNP
1µF
C316
DNP
10µF
C315
DNP
1000
R330
DNP
0
R352 Vcc4_Bias
Bias
0.1µF
C348
0
R338 Vcc8_Digital
Digital
0.1µF
C331
DNP
100pF
C357
DNP
GND
100pF
C361
DNP
GND
100pF
C362
DNP
GND
100pF
C360
DNP
GND
100pF
C356
DNP
GND
100pF
C355
GND
100pF
C354
DNP
GND
0.1µF
C353
GND
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
29
Main
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
49Main Sheet / IC
10/25/2011
LMK01800_Core.SchDoc
Sheet Title:
Size: Schematic:
Mod. Date:
File:
Rev:
Sheet: of
B
Nati onal Se mi conductor and/or it s licensors do not warrant the accuracy or comple te ne s s of
this speci ficati o n or any information cont a ined the r ein. Nat ional a n d/ or its licensors d o no t
warrant that this design will meet the specif ications, will be suitable for your application or fi t
for any particular purpose, or will operate in an implementation. National and/or its licensors
do not warrant that the des i gn i s production worthy. You should complet e l y validat e a nd test
yo ur des ign implementat ion to confirm the system f un ctionality for your applica tion.
© Copyright, National Semiconductor, 2009
http://www.national.com
Contact: http://www.national.com/support
LMK01801 SVBProject:
Designed for: Evaluati on Customer
870xxxxxx 1.0
Assembly Variant: Version1
Designators greater than and equal to 200 are placed on bottom of PCB
CLKin0_P
CLKin0_N DATAuWire/CLKoutDIV0 47
CLKuWire/CLKoutDIV1 48
LEuWire/CLKoutDIV2
1
CLKout0
2
CLKout0*
3
CLKout1*
4
CLKout1
5
Vcc1_CLKout0_1_2_3
6
CLKout2
7
CLKout2*
8
CLKout3*
9
CLKout3
10
Test/CLKoutTYPE0
11
SYNC0/CLKoutTYPE1
12
CLKin0
13
CLKin0*
14
Vcc2_CLKin0
15
CLKout4
16
CLKout4*
17
CLKout5*
18
CLKout5
19
Vcc3_CLKout4_5_6_7
20
CLKout6*
22 CLKout6
21
CLKout7*
23
CLKout7
24
Vcc4_Bias 25
Bias 26
EN_PIN_CTRL 27
CLKout8 28
CLKout8* 29
CLKout9* 30
CLKout9 31
Vcc5_CLKout8_9_10_11 32
CLKout10 33
CLKout10* 34
CLKout11 36
CLKout11* 35
Vcc6_CLKin1 37
CLKin1 38
CLKin1* 39
SYNC1/CLKoutTYPE2 40
Vcc7_CLKout13/12 41
CLKout12 42
CLKout12* 43
CLKout13* 44
CLKout13 45
Vcc8_DIG 46
LMK01801
DAP PAD
0
U1
LMK01801
CLKout0_P
CLKout0_N
CLKout1_P
CLKout1_N
CLKout2_P
CLKout2_N
CLKout3_P
CLKout3_N
CLKout4_P
CLKout4_N
CLKout5_P
CLKout5_N
CLKout6_P
CLKout6_N
CLKout7_N
CLKout7_P
CLKin1_N
CLKin1_P
CLKout13_N
CLKout13_P
CLKout12_N
CLKout12_P
CLKout11_N
CLKout11_P
CLKout10_N
CLKout10_P
CLKout9_N
CLKout9_P
CLKout8_N
CLKout8_P
Vcc1_CLKout_CG0
Vcc3_CLKout_CG1
Vcc5_CLKout_CG2
IC_uWireLE
IC_uWireCLK
IC_uWireDATA
Vcc8_Digital
IC_SYNC0
IC_SYNC1 Vcc7_CLKout_CG3
Vcc2_CLKin0
Vcc6_CLKin1
1µF
C359
Vcc4_Bias
1µF
C358
DNP
GND
IC_TEST
IC_EN_PIN_CTRL
51.0
R310
GND
51.0
R318
GND
LMK01801BEVAL schematic.
Refer to BOM for differences.
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
30
Inputs
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
69Clock I nputs
6/10/2011
InClks.SchDoc
Sheet Title:
Size: Schematic:
Mod. Date:
File:
Rev:
Sheet: of
B
Nati ona l Semiconductor and/or it s licensors do not war rant the accuracy or completene ss of
this s pecification or any information contained therein. National and/or its lice nsors do not
warrant that this design will me e t the specifications, will be s ui table for your a pplication or fit
for any particular purpose, or will operate in an impleme ntation. Na tional and/or its licensors
do not warrant that the des ign is production worthy . You should completely validate and test
your design implementation to confirm the system functionality for your application.
© Copyright, National Semiconductor, 2009
http://www.national.com
Contact: http://www.national.com/support
LMK01801 SVBProject:
Designed for: Evaluation Customer
870xxxxxx 1.0
Assembly Variant: Version1
0
R3
0
R5
270
R6
DNP
270
R15
DNP
0
R12
DNP
270
R14
DNP
0
R10
CLKin0
0.1µF
C2
DNP
CLKin1
0.1µF
C1
CLKin1_P
CLKin1_N
CLKin0_P
CLKin0_N
CLKin1*
SMA
CLKin1
SMA
CLKin0*
SMA
CLKin0
SMA
DNP
100
R8
DNP
CLKin0_2_N
CLKin0_2_P
0
R16
0
R21
CLKin1_2_N
CLKin1_2_P
270
R18
DNP
270
R23
DNP
0
R17
0
R22
51.0
R19
DNP
270
R24
DNP
51.0
R7
100
R20
0.1µF
C6
DNP
0.1µF
C10
0.1µF
C8
0.1µF
C7
0.1µF
C9
DNP
0.1µF
C11
DNP
Vtune
1
NC
2
GND
3OUT 4
NC 5
Vcc 6
122.88 MHz VCXO
U2
CVHD-950-122.88
DNP
VCXO_GND
VCXO_GND
GND
VccCLKoutPlaneA
1000
R303
1000
R2
0.1µF
C302 1µF
C5 10µF
C303
Vtune
SMA
VtuneTP
TESTPOINT
100pF
C4
P
1NC
2PD
3S4
SCT 5
SD 6
B1
BALUN - ADT2-1T
DNP
0
R11
0
R4
CLKin0_3_N
CLKin0_3_P
0
R300
DNP
V_LM5900
33
R9
DNP
0.1µF
C3
DNP
CLKin0_4_N
CLKin0_4_P
0.1µF
C304
0.68µF
C300
DNP
39k
R302
GNDVCXO_GND
0
R305
0
R304
DNP
0.1µF
C301
0
R301
0
R1
DNP
0
R13
DNP
GND
GND
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
31
Inputs Page 2
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
59Interface
10/25/2011
LogicIO.SchDoc
Sheet Title:
Size: Schematic:
Mod. Da te:
File:
Rev:
Sheet: of
B
National Semiconductor and/or its licensors do not warrant the accuracy or completeness of
this specification or any information contained therein. National and/or its licensors do not
warrant that thi s design wil l me e t the s pe ci fi ca ti ons , wi l l be sui ta bl e for y our a pplication or fit
for any part icular purpose, or will operate in an implementation. National and/or its licensors
do not warrant that the design is production worthy. You should completely validate and test
your desi gn i mple me nt ation to confirm the syst em functi onal i t y for your application.
© Copyright, National Semiconductor, 2009
http://www.national.com
Contact: http://www.national.com/support
LMK01801 SV BProject:
Designed for: Evaluation Customer
870xxxxxx 1.0
Assembly Variant: Version1
27k
R325
uWire Header and Level Translation
Test or OutType0
Enable Pin Control
SYNC1 or OutTy pe2
12 34 56 78 910
uWire
HEADER_2X5
15k
R321
27k
R322
27k
R315
15k
R314
27k
R311
15k
R308
TEST_TP
TESTPOINT
27k
R328
uWire_SYNC1
uWire_EN_PIN_CTRL
uWire_TEST
IC_uWireDATA
uWire_SYNC1
27k
R326
DNP
SYNC0 or OutTy pe1
33pF
C309
DNP
33pF
C305
DNP
33pF
C307
DNP
33pF
C308
DNP
27k
R320
SYNC1
SMA
DNP
27k
R319
DNP
VccCLKoutPlaneA
27k
R313
DNP
VccCLKoutPlaneA
27k
R306
DNP
VccCLKoutPlaneA
uWire_LE or DivValue2
uWire_CLK or DivValue1
uWire_DATA or DivValue0
uWire_SYNC0
IC_SYNC1
SYNC0
SMA
DNP
15k
R317
27k
R316
DNP
33pF
C306
DNP
27k
R312
27k
R307
DNP
VccCLKoutPlaneB
VccCLKoutPlaneA
15k
R309
IC_SYNC0
uWire_TEST
27k
R323
DNP
VccCLKoutPlaneA
15k
R324
33pF
C310
DNP
uWire_EN_PIN_CTRL 15k
R327
33pF
C311
DNP
VccCLKoutPlaneB
IC_TEST
IC_EN_PIN_CTRL
VccCLKoutPlaneB
VccCLKoutPlaneB
1 2
3 4
5 6
DivVal2
HEADER_2X3
1 2
3 4
5 6
DivVal1
HEADER_2X3
1 2
3 4
5 6
DivVal0
HEADER_2X3
IC_uWireCLK
IC_uWireLE
VccCLKoutPlaneA
VccCLKoutPlaneA
VccCLKoutPlaneA
12 34 56
EN_PIN_CONTROL
HEADER_2X3
12 34 56
TYPE2
HEADER_2X3
LEuWire_TP
TESTPOINT
CLKuWire_TP
TESTPOINT
DATAuWire_TP
TESTPOINT
SYNC1_TP
TESTPOINT
EN_PIN_CTRL_TP
TESTPOINT
uWire_SYNC0
uWire_DATA
uWire_CLK
uWire_LE
12 34 56
TYPE1
HEADER_2X3
12 34 56
TYPE0
HEADER_2X3
VccCLKoutPlaneA
VccCLKoutPlaneA
SYNC0_TP
TESTPOINT
Placehold for 50 ohm resistor
cose to IC on Core Schematic
page.
For use with hi gh fre quency
SYNC signal s.
Placehold for 50 ohm resistor
cose to IC on Core Schematic
page.
For use with hi gh fre quency
SYNC signal s.
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
32
Clock Outputs Page 1
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
79Clock Outputs 1/ 3
6/10/2011
OutClks0.SchDoc
Sheet Title:
Size: Schematic:
Mod. Date:
File:
Rev:
Sheet: of
B
National Sem iconductor and/or its licensors do not warrant the accuracy or completenes s of
this specificati on or any information contained therei n. National and/or its licensors do not
warrant that thi s design wil l meet the s pecifica t ions, will be suitable for your application or f it
for any particular purpose, or will operate in an implementation. National and/ or its licens or s
do not warrant tha t the de s i gn i s pr oducti on worthy. You should comple t el y vali da te and te s t
your design imple m entation to confi r m t he sy stem functionality for your application.
© Copyright, National Semiconductor, 2009
http://www.national.com
Contact: http://www.national.com/support
LMK01801 SVBProject:
Desi gned for: Eval uation Customer
870xxxxxx 1.0
Assembl y Va riant: Version1
CLKout0
CLKout3
CLKout2_N
CLKout2_P
CLKout2
VccCLKoutPlaneA
VccCLKoutPlaneA
VccCLKoutPlaneA
VccCLKoutPlaneA
VccCLKoutPlaneA
VccCLKoutPlaneA
CLKout2_1_P
CLKout2_1_N
Notes:
1. Designators great er than and equal to 300 are plac ed on bottom of PCB
CLKout1
VccCLKoutPlaneA
VccCLKoutPlaneA
CLKout0
SMA
CLKout0*
SMA
CLKout2
SMA
CLKout2*
SMA
CLKout3*
SMA
DNP
CLKout3
SMA
DNP
CLKout1*
SMA
DNP
CLKout1
SMA
DNP
Default: LVPECL, AC coupled Default: LVPECL, AC coupled
Default: LVPECL, AC coupledDefaul t: LVPECL , AC couple d
CLKout0_1_P
CLKout0_1_N CLKout1_1_P
CLKout1_1_N
CLKout3_1_P
CLKout3_1_N
GND
GND
GND
GND GND
GND
GND
GND
240
R39
240
R31
120
R25
DNP 82.0
R26
DNP
120
R41
DNP 82.0
R42
DNP
68
R35
0.1µF
C14
DNP
51.0
R27
DNP
51.0
R43
DNP
0.1µF
C12
0.1µF
C16
240
R40
240
R33
120
R28
DNP
120
R44
DNP
82.0
R29
DNP
82.0
R45
DNP
0.1µF
C13
0.1µF
C17
51.0
R30
51.0
R46
0.1µF
C15
DNP
68
R36
240
R55
240
R62
120
R50
DNP 82.0
R51
DNP
120
R66
DNP 82.0
R67
DNP
68
R58
0.1µF
C21
DNP
0.1µF
C19
0.1µF
C23
51.0
R52
51.0
R68
240
R53
240
R61
120
R47
DNP 82.0
R48
DNP
120
R63
DNP 82.0
R64
DNP
0.1µF
C18
0.1µF
C22
68
R57
0.1µF
C20
DNP
51.0
R49
DNP
51.0
R65
DNP
CLKout0_N
CLKout0_P
CLKout3_P
CLKout3_N
CLKout1_P
CLKout1_N
62
R32
DNP
62
R37
DNP
62
R54
DNP
62
R59
DNP
62
R34
DNP
62
R38
DNP
62
R56
DNP
62
R60
DNP
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
33
Clock Outputs Page 2
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
89Clock Outputs 2/3
6/10/2011
OutClks1.SchDoc
Sheet Title:
Size: Schematic:
Mod. D ate:
File:
Rev:
Sheet: of
B
National Semiconductor and/or it s licensors do not warrant the accuracy o r completeness of
this specification or any i nformati on contained there in. National and/or its licensors do not
warrant that this desi gn will meet the specifications, wil l be suitable for your application or fit
for any parti cul ar purpose, or will operate in an implementation. National a nd/or i ts licensors
do not w arra nt tha t the design i s product ion worthy. Y o u shoul d compl etely validate and test
your design implementation to confirm the system functionality for your appli cation.
© Copyright, National Semiconductor, 2009
http://www.national.com
Contact: http://www.national.com/support
LMK01801 SVBProject:
Designed for: Eval ua tion Customer
870xxxxxx 1.0
Assembly Variant: Version1
CLKout4_N
CLKout4_P
CLKout4
120
R94
DNP 82.0
R95
DNP
120
R110
DNP 82.0
R111
DNP
0.1µF
C31
0.1µF
C35
CLKout7
120
R91
DNP 82.0
R92
DNP
82.0
R108
DNP
0.1µF
C30
CLKout6_N
CLKout6_P
CLKout6
VccCLKoutPlaneA
VccCLKoutPlaneA
VccCLKoutPlaneA
VccCLKoutPlaneA
VccCLKoutPlaneA
VccCLKoutPlaneA
0.1µF
C34
120
R107
DNP
CLKout5
VccCLKoutPlaneA
VccCLKoutPlaneA
Notes:
1. Designators greater than and equal to 300 are placed on bottom of PCB
CLKout5_N
CLKout5_P
CLKout7_N
CLKout7_P
68
R101
0.1µF
C32
DNP
68
R102
0.1µF
C33
DNP
CLKout4
SMA
CLKout4*
SMA
CLKout5*
SMA
DNP
CLKout5
SMA
DNP
CLKout7*
SMA
DNP
CLKout7
SMA
DNP
CLKout6
SMA
CLKout6*
SMA
Default: LVPECL, AC coupled Default: LVPECL, AC coupled
Default: LVPECL, AC coupled Default: LVPECL, AC coupled
CLKout6_1_P
CLKout6_1_N
CLKout4_1_P
CLKout4_1_N
CLKout7_1_P
CLKout7_1_N
CLKout5_1_P
CLKout5_1_N
51.0
R93
DNP
51.0
R109
DNP
51.0
R96
51.0
R112
240
R97
GND
240
R105
GND
GND
GND GND
GND
240
R98
GND
240
R106
GND
240
R75
240
R83
120
R69
DNP 82.0
R70
DNP
120
R85
DNP 82.0
R86
DNP
0.1µF
C24
0.1µF
C28
51.0
R71
DNP
51.0
R87
DNP
0.1µF
C26
DNP
68
R79
240
R84
240
R76
120
R72
DNP 82.0
R73
DNP
120
R88
DNP 82.0
R89
DNP
0.1µF
C25
0.1µF
C29
68
R80
0.1µF
C27
DNP
51.0
R74
51.0
R90
62
R78
DNP
62
R81
DNP
62
R100
DNP
62
R104
DNP
62
R77
DNP
62
R82
DNP
62
R99
DNP
62
R103
DNP
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
34
Clock Outputs Page 3
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
99Clock Outputs 3/3
6/10/2011
OutClks2.SchDoc
Sheet Title:
Size: Schematic:
Mod. Date:
File:
Rev:
Sheet: of
B
Nati ona l Semiconductor and/or its licensors do not warra nt the a ccur a cy or complete ne s s of
this spe ci f i ca t ion or any i nformation contained there i n. National and/or i ts licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit
for any particular purpose, or will operate in an implementation. National and/or its licensors
do not warrant that the design is production worthy. You should completely validate and test
your design implementation to confirm the system functionality for your application.
© Copyright, National Semiconductor, 2009
http://www.national.com
Contact: http://www.national.com/support
LMK01801 SVBProject:
Designed for: Evaluation Custom er
870xxxxxx 1.0
Assembly Variant: Version1
120
R113
DNP 82.0
R114
DNP
120
R130
DNP 82.0
R131
DNP
0.1µF
C36
0.1µF
C40
CLKout8_N
CLKout8_P
CLKout8
CLKout10
CLKout10_N
CLKout10_P
CLKout11
120
R116
DNP 82.0
R117
DNP
82.0
R133
DNP
0.1µF
C37
CLKout9
VccCLKoutPlaneB
VccCLKoutPlaneB
VccCLKoutPlaneB
VccCLKoutPlaneB
VccCLKoutPlaneB
VccCLKoutPlaneB
VccCLKoutPlaneB
VccCLKoutPlaneB
0.1µF
C41
120
R129
DNP
CLKout9_1_P
CLKout9_1_N
Notes:
1. Designa tors greater tha n a nd e qual to 300 are placed on b ot tom of PCB
CLKout9_P
CLKout9_N
CLKout11_P
CLKout11_N
68
R123
0.1µF
C38
DNP
68
R124
0.1µF
C39
DNP
CLKout8
SMA
CLKout8*
SMA
CLKout9*
SMA
DNP
CLKout9
SMA
DNP
CLKout11*
SMA
DNP
CLKout11
SMA
DNP
CLKout10
SMA
CLKout10*
SMA
Default: LVPECL, AC coupled
Default: LVPEC L, AC coupled
Default: LVPECL, AC coupled
Default: LVPECL, AC coupled
CLKout11_1_P
CLKout11_1_N
CLKout10_1_P
CLKout10_1_N
CLKout8_1_P
CLKout8_1_N
51.0
R118
51.0
R134
51.0
R115
DNP
51.0
R132
DNP
240
R119
GND
240
R127
GND
GND
GND GND
GND
240
R128
GND
240
R121
GND
CLKout12 CLKout13
VccCLKoutPlaneB
VccCLKoutPlaneB VccCLKoutPlaneB
VccCLKoutPlaneB
CLKout13_P
CLKout13_N
CLKout13*
SMA
CLKout13
SMA
CLKout12
SMA
CLKout12*
SMA
Default: LVPEC L, AC coupled Default: LVPECL, AC coupled
CLKout13_1_P
CLKout13_1_N
CLKout12_1_P
CLKout12_1_N
GND
GND GND
GND
120
R160
DNP 82.0
R161
DNP
82.0
R177
DNP
0.1µF
C53
120
R176
DNP
68
R168
0.1µF
C51
DNP
0.1µF
C49 51.0
R162
DNP
51.0
R178
DNP
240
R165
240
R172
240
R171
240
R163
120
R157
DNP 82.0
R158
DNP
120
R173
DNP 82.0
R174
DNP
68
R167
0.1µF
C50
DNP
51.0
R159
DNP
51.0
R175
DNP
0.1µF
C52
0.1µF
C48
240
R150
240
R143
120
R138
DNP 82.0
R139
DNP
120
R154
DNP 82.0
R155
DNP
0.1µF
C43
0.1µF
C47
68
R146
0.1µF
C45
DNP
51.0
R140
51.0
R156
240
R141
240
R149
120
R135
DNP 82.0
R136
DNP
120
R151
DNP 82.0
R152
DNP
68
R145
51.0
R137
DNP
51.0
R153
DNP
0.1µF
C42
0.1µF
C46 0.1µF
C44
DNP
CLKout12_N
CLKout12_P
62
R120
DNP
62
R125
DNP
62
R142
DNP
62
R147
DNP
62
R164
DNP
62
R169
DNP
62
R122
DNP
62
R126
DNP
62
R144
DNP
62
R148
DNP
62
R166
DNP
62
R170
DNP
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
35
Appendix D: Bill of Materials
Common Bill of Materials for Evaluation Boards
Item Designator Description RoHS Manufacturer PartNumber Quantity
CAPACITORS
1
C1, C7, C8, C10, C12,
C13, C16, C17, C18,
C19, C22, C23, C24,
C25, C28, C29, C30,
C31, C35, C36, C37,
C40, C41, C42, C43,
C46, C47, C48, C49,
C52, C53, C56, C301,
C302, C304, C314,
C321
CAP, CERM, 0.1uF, 25V, +/-5%, X7R, 0603 Y Kemet C0603C104J3RACTU 37
2 C4 CAP, CERM, 100pF, 50V, +/-5%, C0G/NP0,
0603 Y Kemet C0603C101J5GACTU 1
3 C5, C55, C313, C320,
C359 CAP, CERM, 1uF, 10V, +/-10%, X5R, 0603 Y Kemet C0603C105K8PACTU 5
4 C34, C326, C329,
C339, C343 CAP, CERM, 0.1uF, 25V, +/-10%, X7R, 0603 Y Kemet C0603C104K3RACTU 5
5 C54, C303, C312, C319 CAP, CERM, 10uF, 10V, +/-10%, X5R, 0805 Y Kemet C0805C106K8PACTU 4
6 C300 CAP, CERM, 0.68uF, 10V, +80/20%, Y5V, 0603 Y Kemet C0603C684Z8VACTU 1
7 C318, C331, C336,
C348 CAP, CERM, 0.1uF, 16V, +/-10%, X7R, 0603 Y TDK C1608X7R1C104K 4
8 C332, C341, C345 CAP, CERM, 1uF, 16V, +/-10%, X7R, 0603 Y TDK C1608X7R1C105K 3
9 C333, C346 CAP, CERM, 2200pF, 100V, +/-5%, X7R, 0603 Y AVX 06031C222JAT2A 2
10 C334, C347 CAP, CERM, 10uF, 10V, +/-20%, X5R, 0805 Y Kemet C0805C106M8PACTU 2
11 C335, C349 CAP, CERM, 4.7uF, 10V, +/-10%, X5R, 0603 Y Kemet C0603C475K8PACTU 2
12 C337, C350 CAP, CERM, 0.01uF, 25V, +/-5%, C0G/NP0,
0603 Y TDK C1608C0G1E103J 2
13 C340, C344 CAP, CERM, 0.01uF, 100V, +/-10%, X7R, 0603 Y Kemet C0603C103K1RACTU 2
14 C351, C352 CAP, CERM, 0.47uF, 25V, +/-10%, X7R, 0603 Y MuRata GRM188R71E474KA12D 2
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
36
Item Designator Description RoHS Manufacturer PartNumber Quantity
CONNECTORS
15
CLKin0*, CLKin1,
CLKin1*, CLKout0,
CLKout0*, CLKout2,
CLKout2*, CLKout4,
CLKout4*, CLKout6,
CLKout6*, CLKout8,
CLKout8*, CLKout10,
CLKout10*, CLKout12,
CLKout12*, Vcc, Vtune
Connector, SMT, End launch SMA 50 Ohm Y Emerson
Network Power 142-0701-851 19
18 J1 CONN TERM BLK PCB 5.08MM 2POS OR Y Weidmuller 1594540000 1
RESISTORS
19 R2, R179, R303, R329,
R332 FB, 1000 ohm, 600 mA, 0603 Y Murata BLM18HE102SN1D 5
20
R3, R5, R10, R16, R17,
R21, R22, R301, R305,
R334, R336, R346,
R349, R356
RES, 0 ohm, 5%, 0.1W, 0603 Y Vishay-Dale CRCW06030000Z0EA 14
21 R4, R11 RES, 0 ohm, 5%, 0.125W, 0805 Y Vishay-Dale CRCW08050000Z0EA 2
22
R7, R30, R46, R52,
R68, R74, R90, R96,
R112, R118, R134,
R140, R156, R159,
R175, R310, R318
RES, 51.0 ohm, 1%, 0.1W, 0603 Y Yageo America RC0603FR-0751RL 17
23 R20 RES, 100 ohm, 1%, 0.1W, 0603 Y Yageo America RC0603FR-07100RL 1
24
R31, R33, R39, R40,
R53, R55, R61, R62,
R75, R76, R83, R84,
R97, R98, R105, R106,
R119, R121, R127,
R128, R141, R143,
R149, R150, R163,
R165, R171, R172
RES, 240 ohm, 1%, 0.1W, 0603 Y Yageo America RC0603FR-07240RL 28
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
37
25
R35, R36, R57, R58,
R79, R80, R101, R102,
R123, R124, R145,
R146, R167, R168
RES, 68 ohm, 5%, 0.1W, 0603 Y Vishay-Dale CRCW060368R0JNEA 14
26 R302 RES, 39k ohm, 5%, 0.1W, 0603 Y Vishay-Dale CRCW060339K0JNEA 1
27
R306, R307, R311,
R312, R313, R315,
R316, R319, R320,
R322, R323, R325,
R326, R328
RES, 27k ohm, 5%, 0.1W, 0603 Y Vishay-Dale CRCW060327K0JNEA 14
28 R308, R309, R314,
R317, R321, R324,
R327 RES, 1.0k ohm, 5%, 0.1W, 0603 Y Vishay-Dale CRCW06031K00JNEA 7
29 R331, R335, R337,
R338, R344, R347,
R350, R352 FB, 120 ohm, 500 mA, 0603 Y Murata BLM18AG121SN1D 8
30 R342, R353, R357 RES, 51k ohm, 5%, 0.1W, 0603 Y Vishay-Dale CRCW060351K0JNEA 3
31 R343, R354 RES, 2.00k ohm, 1%, 0.1W, 0603 Y Vishay-Dale CRCW06032K00FKEA 2
32 R345, R355 RES, 866 ohm, 1%, 0.1W, 0603 Y Vishay-Dale CRCW0603866RFKEA 2
INTEGRATED CIRCUITS
34 U1 LMK01801 1
35 U300, U301 Micropower 800mA Low Noise 'Ceramic Stable'
Adjustable Voltage Regulator for 1V to 5V
Applications Y Texas
Instruments LP3878SD-ADJ 2
36 U302 Ultra Low Noise, 150mA Linear Regulator for
RF/Analog Circuits Requires No Bypass
Capacitor Y Texas
Instruments LP5900SD-3.3 1
37 uWire Low Profile Vertical Header 2x5 0.100" Y FCI 52601-G10-8LF 1
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
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Appendix E: Balun Information
Typical Balun Frequency Response
The following figure illustrates the typical frequency response of the Mini-circuit’s ADT2-1T
balun.
Figure 21 - Typical Balun Frequency Response
0
1
2
3
4
5
6
7
8
9
10
10 100 1000
Loss(dB)
Frequency(MHz)
TypicalBalunInsertionLoss
ADT2‐1T
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
39
Appendix F: Properly Configuring LPT Port
When trying to solve any communications issue, it is convenient to program the POWERDOWN
bit to confirm high/low current draw of the evaluation board or the PLL_MUX between “Logic
Low” and “Logic High” LD output to confirm successful communications.
LPT Driver Loading
The parallel port must be configured for proper operation. To confirm that the LPT port driver is
successfully loading click “LPT/USB” “Check LPT Port.” If the driver properly loads then
the following message is displayed:
Figure 22 - Successfully Opened LPT Driver
Successful loading of LPT driver does not mean LPT communications in CodeLoader are setup
properly. The proper LPT port must be selected and the LPT port must not be in an improper
mode.
The PC must be rebooted after install for LPT support to work properly.
Correct LPT Port/Address
To determine the correct LPT port in Windows, open the device manager (On Windows XP,
Start Settings Control Panel System Hardware Tab Device Manager) and check
the LPT port under the Ports (COM & LPT) node of the tree. It can be helpful to confirm that
the LPT port is mapped to the expected port address, for instance to confirm that LPT1 is really
mapped to address 0x378. This can be checked by viewing the properties of the LPT1 port and
viewing resources tab to verify that the I/O Range starts at 0x378. CodeLoader expects the a
traditional port mapping: Port Address
LPT1 0x378
LPT2 0x278
LPT3 0x3BC
If a non-standard address is used, use the “Other” port address in CodeLoader and type in the
port address in hexadecimal. It is possible to change the port address in the computer’s BIOS
settings. The port address is set in CodeLoader at the Port Setup tab as shown in Figure 23.
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
40
Figure 23 - Selecting the LPT Port
Correct LPT Mode
If communications are not working, then it is possible the LPT port mode is set improperly. It is
recommended to use the simple, Output-only mode of the LPT port. This can be set in the BIOS
of the computer. Common terms for this desired parallel port mode are “Normal,” “Output,” or
“AT.” It is possible to enter BIOS setup during the initial boot up sequence of the computer.
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
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Appendix G: Differential Voltage Measurement Terminology
The differential voltage of a differential signal can be described by two different definitions
causing confusion when reading datasheets or communicating with other engineers. This section
will address the measurement and description of a differential signal so that the reader will be
able to understand and discern between the two different definitions when used.
The first definition used to describe a diff erential signal is the absolute value of the voltage
potential between the inverting and non-inverting signal. The symbol for this first measurement
is typically VID or VOD depending on if an input or output voltage is being described.
The second definition used to describe a differential signal is to measure the potential of the non-
inverting signal with respect to the inverting signal. The symbol for this second measurement is
VSS and is a calculated parameter. Nowhere in the IC does this signal exist with respect to
ground, it only exists in reference to its differential pair. VSS can be measured directly by
oscilloscopes with floating references; otherwise this value can be calculated as twice the value
of VOD as described in the first section
Figure 24 illustrates the two different definitions side-by-side for inputs and Figure 25 illustrates
the two different definitions side-by-side for outputs. The VID and VOD definitions show VA and
VB DC levels that the non-inverting and inverting signals toggle between with respect to ground.
VSS input and output definitions show that if the inverting signal is considered the voltage
potential reference, the non-inverting signal voltage potential is now increasing and decreasing
above and below the non-inverting reference. Thus the peak-to-peak voltage of the differential
signal can be measured.
VID and VOD are often defined in volts (V) and VSS is often defined as volts peak-to-peak (VPP).
Figure 24 - Two Different Definitions
for Differential Output Signals Figure 25 - Two Different Definitions
for Differential Input Signals
SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
42
Appendix H: Troubleshooting Information
If the evaluation board is not behaving as expected, the most likely issues are…
1) Board communication issue
2) Incorrect Programming of the device
3) Setup Error
Refer to this checklist for a practical guide on identifying/exposing possible issues.
Confirm Communications
Refer to Appendix F: Properly Configuring LPT Port to trouble shoot this item.
Remember to load device with Ctrl-L!
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