MPC509 User Manual - Motorola / Freescale Semiconductor

MPC500 Fami ly

MPC509

User’s Manual

MPC509UM/AD

PowerPC Microcontrollers

TABLE OF CONTENTS

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MPC509 TABLE OF CONTENTS MOTOROLA

USER’S MANUAL Rev. 15 June 1998 iii

PREFACE

Section 1

INTRODUCTION

1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.3 Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Section 2

SIGNAL DESCRIPTIONS

2.1 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Pin Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.3 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.4 Pins with Internal Pull-Ups and Pulldowns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.5 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.5.1 Bus Arbitration and Reservation Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.5.1.1 Bus Request (B R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.5.1.2 Bus Grant (BG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.5.1.3 Bus Busy (B B ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.5.1.4 Cancel Reservation (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.5.2 Address Phase Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.5.2.1 Address Bus (ADDR[0:29]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.5.2.2 Write/Read (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.5.2.3 Burst Indicator (BURST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.5.2.4 Byte Enables (BE[0:3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.5.2.5 Transfer Start (TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.5.2.6 Address Acknowledge (AACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.5.2.7 Burst Inhibit (BI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.5.2.8 Address Retry (ARETRY). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.5.2.9 Address Type (AT[0:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.5.2.10 Cycle Types (CT[0:3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.5.3 Data Phase Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.5.3.1 Data Bus (DATA[0:31]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.5.3.2 Burst Data in Progress (BDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.5.3.3 Transfer Acknowledge (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.5.3.4 Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.5.3.5 Data Strobe (DS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.5.4 Development Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.5.4.1 Development Port Serial Data Out (DSDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.5.4.2 Development Port Serial Data In (DSDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

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2.5.4.3 Development Port Serial Clock Input (DSCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.5.4.4 Instruction Fetch Visibility Signals (VF[0:2]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.5.4.5 Instruction Flush Count (VFLS[0:1]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.5.4.6 Watchpoints (WP[0:5]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.5.5 Chip-Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.5.5.1 Chip Select for System Boot Memory (CSBOOT) . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.5.5.2 Chip Selects for External Memory (CS[0:11]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.5.6 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.5.6.1 Clock Output (CLKOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.5.6.2 Engineering Clock Output (ECROUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5.6.3 Crystal Oscillator Connections (EXTAL, XTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5.6.4 External Filter Capacitor Pins (XFCP, XFCN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5.6.5 Clock Mode (MODCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5.6.6 Phase-Locked Loop Lock Signal (PLLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5.6.7 Power-Down Wake-Up (PDWU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5.7 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.7.1 Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.7.2 Reset Output (RESETOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.8 SIU General-Purpose Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.8.1 Ports A and B (PA[0:7], PB[0:7]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.8.2 Ports I, J, K, and L (PI[0:7], PJ[0:7], PK[0:7], PL[2:7]. . . . . . . . . . . . . . . . . . . . . . . 2-21

2.5.8.3 Port M (PM[3:7]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.5.9 Interrupts and Port Q Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.5.9.1 Interrupt Requests (IRQ[0:6]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.5.9.2 Port Q (PQ[0:6]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.10 JTAG Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.10.1 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.10.2 Test Data Output (TDO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.10.3 Test Mode Select (TMS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.10.4 Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.10.5 Test Reset (TRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

Section 3

CENTRAL PROCESSING UNIT

3.1 RCPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 RCPU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.3 Instruction Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.4 Independent Execution Units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.4.1 Branch Processing Unit (BPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.4.2 Integer Unit (IU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.4.3 Load/Store Unit (LSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.4.4 Floating-Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.5 Levels of the PowerPC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

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3.6 RCPU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.7 PowerPC UISA Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.7.1 General-Purpose Registers (GPRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.7.2 Floating-Point Registers (FPRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.7.3 Floating-Point Status and Control Register (FPSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.7.4 Condition Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.7.4.1 Condition Register CR0 Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.7.4.2 Condition Register CR1 Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.7.4.3 Condition Regi st er CR

Field — Compare Instruction. . . . . . . . . . . . . . . . . . . . . . 3-15

3.7.5 Integer Exception Register (XER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.7.6 Link Register (LR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.7.7 Count Register (CTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.8 PowerPC VEA Register Set — Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.9 PowerPC OEA Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.9.1 Machine State Register (MSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.9.2 DAE/Source Instruction Service Register (DSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

3.9.3 Data Address Register (DAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.9.4 Time Base Facility (TB) — OEA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.9.5 Decrementer Register (DEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.9.6 Machine Status Save/Restore Register 0 (SRR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.9.7 Machine Status Save/Restore Register 1 (SRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

3.9.8 General SPRs (SPRG0–SPRG3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

3.9.9 Processor Version Register (PVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

3.9.10 Implementation-Specific SPRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.9.10.1 EIE, EID, and NRI Special-Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.9.10.2 Instruction-Cache Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.9.10.3 Development Support Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

3.9.10.4 Floating-Point Exception Cause Register (FPECR). . . . . . . . . . . . . . . . . . . . . . . 3-24

3.10 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

3.10.1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

3.10.2 Recommended Simplified Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

3.10.3 Calculating Effective Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

3.11 Exception Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

3.11.1 Exception Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

3.11.2 Ordered Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

3.11.3 Unordered Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

3.11.4 Precise Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

3.11.5 Exception Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

3.12 Instruction Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

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Section 4

INSTRUCTION CACHE

4.1 Instruction Cache Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 Instruction Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.3 Instruction Cache Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 3

4.4 Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.5 Cache Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Section 5

SYSTEM INTERFACE UNIT

5.1 SIU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 SIU Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3 SIU Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.3.1 SIU Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.3.2 Memory Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.3.3 Internal Module Select Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.3.3.1 Memory Block Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.3.3.2 Accesses to Unimplemented Internal Memory Locations. . . . . . . . . . . . . . . . . . . . . 5-9

5.3.3.3 Control Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5.3.3.4 Internal Memory Mapping Field (LMEMBASE). . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.3.3.5 Memory Mapping Conflicts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.3.4 Internal Cross-Bus Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.3.5 Response to Freeze Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

5.3.5.1 Effects of Freeze and Debug Mode on the Bus Monitor. . . . . . . . . . . . . . . . . . . . . 5-11

5.3.5.2 Effects of Freeze on the Programmable Interrupt Timer (PIT). . . . . . . . . . . . . . . . 5-11

5.3.5.3 Effects of Freeze on the Decrementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.3.5.4 Effects of Freeze on Register Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.4 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.4.2 External Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.4.3 Basic Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

5.4.3.1 Read Cycle Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

5.4.3.2 Write Cycle Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

5.4.4 Basic Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18

5.4.5 Bus Cycle Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

5.4.5.1 Arbitration Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

5.4.5.2 Address Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

5.4.5.3 Data Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21

5.4.6 Burst Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22

5.4.6.1 Termination of Burst Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

5.4.6.2 Burst Inhibit Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

5.4.7 Decomposed Cycles and Address Wrapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

5.4.8 Preventing Speculative Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

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5.4.9 Accesses to 16-Bit Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27

5.4.10 Address Retry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28

5.4.11 Transfer Error Acknowledge Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28

5.4.12 Cycle Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29

5.4.13 Show Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30

5.4.14 Storage Reservation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31

5.4.14.1 PowerPC Architecture Reservation Requirements. . . . . . . . . . . . . . . . . . . . . . . . 5-32

5.4.14.2 E-bus Storage Reservation Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33

5.4.14.3 Reservation Storage Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33

5.5 Chip Selects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34

5.5.1 Chip-Select Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35

5.5.2 Chip-Select Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35

5.5.3 Chip-Select Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36

5.5.4 Chip-Select Registers and Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37

5.5.4.1 Chip-Select Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39

5.5.4.2 Chip-Select Option Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40

5.5.5 Chip-Select Regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44

5.5.6 Multi-Level Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46

5.5.6.1 Main Block and Sub-Block Pairings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46

5.5.6.2 Programming the Sub-Block Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47

5.5.6.3 Multi-Level Protection for CSBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47

5.5.7 Access Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

5.5.7.1 Supervisor Space Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

5.5.7.2 Data Space Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

5.5.7.3 Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

5.5.8 Cache Inhibit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49

5.5.9 Handshaking Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49

5.5.10 Wait State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49

5.5.11 Port Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50

5.5.12 Chip-Select Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50

5.5.12.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51

5.5.12.2 Byte Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51

5.5.12.3 Region Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51

5.5.13 Interface Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52

5.5.13.1 Interface Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53

5.5.13.2 Turn-Off Times for Different Interface Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54

5.5.13.3 Interface Type and BI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55

5.5.14 Chip-Select Operation Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55

5.5.15 Pipe Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56

5.5.15.1 Pipelined Accesses to the Same Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57

5.5.15.2 Pipelined Accesses to Different Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57

5.5.16 Chip-Select Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59

5.5.16.1 Asynchronous Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59

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viii Rev. 15 June 1998 USER’S MANUAL

5.5.16.2 Asynchronous Interface with Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60

5.5.16.3 Synchronous Interface with Asynchronous OE . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60

5.5.16.4 Synchronous Interface with Early Synchronous OE. . . . . . . . . . . . . . . . . . . . . . . 5-61

5.5.16.5 Synchronous Interface with Synchronous OE, Early Overlap . . . . . . . . . . . . . . . 5-62

5.5.16.6 Synchronous Burst Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63

5.5.17 Burst Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66

5.5.18 Chip-Select Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67

5.6 Clock Submodule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67

5.6.1 Clock Submodule Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70

5.6.2 Clock Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70

5.6.3 System Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71

5.6.4 Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71

5.6.4.1 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72

5.6.4.2 Phase Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73

5.6.4.3 Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73

5.6.4.4 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74

5.6.4.5 Multiplication Factor Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74

5.6.4.6 Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74

5.6.5 CLKOUT Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74

5.6.5.1 Multiplication Factor (MF) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75

5.6.5.2 Reduced Frequency Divider (RFD[0:3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77

5.6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78

5.6.6.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78

5.6.6.2 Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78

5.6.6.3 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78

5.6.6.4 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79

5.6.6.5 Exiting Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79

5.6.7 System Clock Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79

5.6.8 Power-Down Wake Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80

5.6.9 Time Base and Decrementer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80

5.6.9.1 Time Base and Decrementer Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81

5.6.9.2 Time Base/Decrementer and Freeze Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81

5.6.9.3 Decrementer Clock Enable (DCE) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81

5.6.10 Clock Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81

5.6.10.1 Loss of PLL Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82

5.6.10.2 Loss of Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82

5.6.11 System Clock Control Register (SCCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83

5.6.12 System Clock Lock and Status Register (SCLSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84

5.7 System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-85

5.7.1 System Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-85

5.7.2 System Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86

5.7.3 Periodic Interrupt Timer (PIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86

5.7.3.1 PIT Clock Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-87

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5.7.3.2 PIT Time-Out Period Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-88

5.7.3.3 PIT Enable Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-89

5.7.3.4 PIT Interrupt Request Level and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-89

5.7.3.5 Periodic Interrupt Control and Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-89

5.7.3.6 Periodic Interrupt Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90

5.7.4 Hardware Bus Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90

5.7.4.1 Bus Monitor Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91

5.7.4.2 Bus Monitor Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91

5.7.4.3 Bus Monitor Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91

5.7.4.4 Bus Monitor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91

5.8 Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92

5.8.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92

5.8.2 Reset Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93

5.8.2.1 External Reset Request Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93

5.8.2.2 Internal Reset Request Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95

5.8.2.3 Reset Behavior for Different Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-97

5.8.3 Configuration During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98

5.8.3.1 Data Bus Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98

5.8.3.2 Internal Default Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99

5.8.3.3 Data Bus Reset Configuration Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99

5.8.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-101

5.9 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-101

5.9.1 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-102

5.9.2 Port M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103

5.9.3 Ports A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-104

5.9.4 Ports I, J, K, and L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-106

5.9.5 Port Replacement Unit (PRU) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108

Section 6

PERIPHERAL CON TROL UNIT

6.1 PCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2 PCU Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.3 Module Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.4 Software Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.4.1 Software Watchdog Service Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.4.2 Software Watchdog Control Register/Timing Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.4.3 Software Watchdog Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.5 Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.5.1 Interrupt Controller Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.5.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.5.2.1 External Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.5.2.2 Periodic Interrupt Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.5.2.3 Interrupt Request Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

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6.5.3 Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.5.3.1 Pending Interrupt Request Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

6.5.3.2 Enabled Active Interrupt Requests Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

6.5.3.3 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

6.5.3.4 PIT/Port Q Interrupt Levels Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.6 Port Q. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.6.1 Port Q Edge Detect/Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

6.6.2 Port Q Pin Assignment Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

6.6.2.1 Port Q Pin Assignment Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

6.6.2.2 Port Q Edge Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

Section 7

STATIC RAM MODULE

7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2 Placement of SRAM in Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.3 SRAM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Section 8

DEVELOPMENT SUPPORT

8.1 Program Flow Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1.1 Indirect Change-of-Flow Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.1.1.1 Marking the Indirect Change-of-Flow Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.1.1.2 Sequential Instructions with the Indirect Change-of-Flow Attribute . . . . . . . . . . . . . 8-3

8.1.2 Instruction Fetch Show Cycle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.1.3 Program Flow-Tracking Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.1.3.1 Instruction Queue Status Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.1.3.2 History Buffer Flush Status Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.1.3.3 Flow-Tracking Status Pins in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.1.3.4 Cycle Type, Write/Read, and Address Type Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.1.4 External Hardware During Program Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.1.4.1 Back Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.1.4.2 Window Trace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.1.4.3 Synchronizing the Trace Window to Internal CPU Events . . . . . . . . . . . . . . . . . . . . 8-8

8.1.4.4 Detecting the Trace Window Starting Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

8.1.4.5 Detecting the Assertion or Negation of VSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

8.1.4.6 Detecting the Trace Window Ending Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

8.1.5 Compress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11

8.2 Watchpoint and Breakpoint Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11

8.2.1 Watchpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

8.2.1.1 Restrictions on Watchpoint Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13

8.2.1.2 Byte and Half-Word Working Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13

8.2.1.3 Generating Six Compare Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15

8.2.1.4 I-Bus Support Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15

8.2.1.5 L-Bus Support Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17

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8.2.1.6 Treating Floating-Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

8.2.2 Internal Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

8.2.2.1 Breakpoint Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

8.2.2.2 Trap-Enable Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

8.2.2.3 Ignore First Match. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

8.2.3 External Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

8.2.4 Breakpoint Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

8.3 Development Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22

8.3.1 Development Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22

8.3.1.1 Development Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23

8.3.1.2 Development Serial Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23

8.3.1.3 Development Serial Data Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24

8.3.2 Development Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24

8.3.2.1 Development Port Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25

8.3.2.2 Trap Enable Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25

8.3.3 Development Port Clock Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25

8.3.4 Development Port Transmissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30

8.3.5 Trap-Enable Input Transmissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30

8.3.6 CPU Input Transmissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31

8.3.7 Serial Data Out of Development Port — Non-Debug Mode . . . . . . . . . . . . . . . . . . . . . . 8-31

8.3.8 Serial Data Out of Development Port — Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 8-32

8.3.8.1 Valid Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32

8.3.8.2 Sequencing Error Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33

8.3.8.3 CPU Exception Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33

8.3.8.4 Null Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34

8.3.9 Use of the Ready Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34

8.4 Debug Mode Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34

8.4.1 Enabling Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35

8.4.2 Entering Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35

8.4.3 Debug Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36

8.4.4 Freeze Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37

8.4.5 Exiting Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37

8.4.6 Checkstop State and Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37

8.5 Development Port Transmission Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38

8.5.1 Port Usage in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38

8.5.2 Debug Mode Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40

8.5.3 Port Usage in Normal (Non-Debug) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40

8.6 Examples of Debug Mode Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41

8.6.1 Prologue Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41

8.6.2 Epilogue Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41

8.6.3 Peek Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42

8.6.4 Poke Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42

8.7 Software Monitor Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42

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8.8 Development Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44

8.8.1 Register Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-45

8.8.2 Comparator A–D Value Registers (CMPA–CMPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46

8.8.3 Comparator E–F Value Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46

8.8.4 Comparator G–H Value Registers (CMPG–CMPH). . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-47

8.8.5 I-Bus Support Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-47

8.8.6 L-Bus Support Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-49

8.8.7 L-Bus Support Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-50

8.8.8 Breakpoint Counter A Value and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-52

8.8.9 Breakpoint Counter B Value and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-53

8.8.10 Exception Cause Register (ECR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-53

8.8.11 Debug Enable Register (DER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-55

Section 9

IEEE 1149.1-COMPLIANT INTERFACE

9.1 JTAG Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2 JTAG Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.3 Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.4 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.5 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.5.1 EXTEST (0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.5.2 BYPASS (1111) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.5.3 SAMPLE/PRELOAD (1110) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.5.4 CLAMP (0011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.5.5 HIGHZ (0010). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.5.6 EXTEST_PULLUP (0001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.5.7 IDCODE (1101) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.5.8 TMSCAN (1100). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.6 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.7 Non-IEEE 1149.1-1990 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.8 Boundary Scan Descriptor Language (BSDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

INDEX

Figure Title Page

LIST OF FIGURES

MPC509 LIST OF FIGURES MOTOROLA

USER’S MANUAL Rev. 15 June 1998 xiii

1-1 MPC509 Block Diagram .................................................................................1-2

1-2 MPC509 Pin Assignments ..............................................................................1-3

1-3 MPC509 Signals .............................................................................................1-4

1-4 MPC509 Memory Map ....................................................................................1-5

2-1 Output-Only and Three-State I/O Buffers .......................................................2-2

3-1 RCPU Block Diagram ............... .... ..... .............. ..... .............. .............. .... ..........3-2

3-2 Sequencer Data Path .....................................................................................3-4

3-3 RCPU Programming Model ............... .............. ..... .............. .............. .... ..........3-9

3-4 Basic Instruction Pipeline .............................................................................3-34

4-1 Instruc tion Cache Organizat ion .................. ..... ..... .... .............. ..... .............. .....4-2

4-2 Instruction Cache Data Path ...........................................................................4-3

5-1 SIU Block Diagram .........................................................................................5-2

5-2 Internal Module Select Scheme ......................................................................5-8

5-3 Placement of Internal Memory in Memory Map ..............................................5-9

5-4 Flow Diagram of a Single Read Cycle ..........................................................5-16

5-5 Example of a Read Cycle .............................................................................5-17

5-6 Flow Diagram of a Single Write Cycle ..........................................................5-18

5-7 Example of Pipelined Bus .............................................................................5-19

5-8 Write Followed by Two Reads on the E-Bus (Using Chip Selects) ..............5-19

5-9 External Burst Read Cycle ...........................................................................5-23

5-10 Storage Reserva tion Sign aling ................... ..... .............. .............. ..... ............5-32

5-11 Simplified Uniprocessor System with Chip-Select Logic ..............................5-34

5-12 Chip-Select Functional Block Diagram .........................................................5-36

5-13 Multi-Level Prote ction ................... ..... .............. .............. ..... .............. .... ........5-46

5-14 Chip-Select Operation Flowchart ..................................................................5-56

5-15 Overlapped Accesses to the Same Region ..................................................5-57

5-16 Pipelined Accesses to Two Different Regions ..............................................5-58

5-17 Asynchronous Read (Zero Wait States) .......................................................5-60

5-18 Asynchronous Write (Zero Wait States) .......................................................5-60

5-19 Synchron ous Read with Asynchronous OE (Zero Wait States) ...................5-61

5-20 Synchronous Write (Zero Wait States) .........................................................5-61

5-21 Synchron ous Read with Early OE (One Wait State) .............. .............. ..... ...5-62

5-22 Synchronous Read with Early Overlap (One Wait State) .............................5-63

5-23 Type 1 Synchronous Burst Read Interface ...................................................5-64

5-24 Type 1 Synchronous Burst Write Interface ...................................................5-65

5-25 Type 2 Synchronous Burst Read Interface ...................................................5-66

5-26 SIU Clock Module Block Diagram ................................................................5-69

Figure Title Page

MOTOROLA LIST OF FIGURES MPC509

xiv Rev. 15 June 1998 USER’S MANUAL

5-27 Phase-Locked Loop Block Diagram .............................................................5-72

5-28 Crystal Oscillator ..........................................................................................5-73

5-29 Charge Pump with Loop Filter Schematic ............ .... ..... ..... .............. .... ........5-73

5-30 Periodic Int errupt Timer Block Diagr am ...... ..... ..... .... .............. ..... .............. ...5-87

5-31 External Reset Request Flow .......................................................................5-94

5-32 Internal Reset Request Flow ........................................................................5-96

6-1 Peripherals Control Unit Block Diagram .........................................................6-1

6-2 Interrupt Structure Block Diagram ..................................................................6-6

6-3 Time-Multiplexing Protocol For IRQ Pins .......................................................6-8

7-1 Placement of Internal SRAM in Memory Map ................................................7-2

8-1 Watchpoint and Breakpoint Support in the RCPU ........................................8-12

8-2 Partially Supported Watchpoint/Breakpoint Example ...................................8-15

8-3 I-Bus Support General Structure ..................................................................8-16

8-4 L-Bus Support General Structure .................................................................8-18

8-5 Development Port Support Logic ..................................................................8-22

8-6 Development Port Registers and Data Paths ...............................................8-24

8-7 Enabling Clock Mode Following Reset .........................................................8-27

8-8 Asynchronous Clocked Serial Communications ...........................................8-28

8-9 Synchronous Clocked Serial Communications .............................................8-29

8-10 Synchronous Self-Clocked Serial Communications .....................................8-30

8-11 Enabling Debug Mode at Reset ....................................................................8-35

8-12 Entering Debug Mode Following Reset ........................................................8-36

8-13 General Port Usage Sequence Diagram ......................................................8-40

8-14 Debug Mode Logic .......................................................................................8-44

9-1 JTAG Pins ......................................................................................................9-1

9-2 Test Logic Block Diagram ...............................................................................9-2

9-3 Sample EXTEST Connection .........................................................................9-4

9-4 Bypass Register .............................................................................................9-5

9-5 Typical Clamp Example ..................................................................................9-6

9-6 IDREGISTER Configuration ...........................................................................9-7

Table Title Page

LIST OF TABLES

MPC509 LIST OF TABLES MOTOROLA

USER’S MANUAL Rev. 15 June 1998 xv

2-1 MPC509 Pin List ..................................................................................................2-1

2-2 EBI Pin Definitions ...............................................................................................2-2

2-3 MPC509 Power Connections.................................................................................2-3

2-4 Pins with Internal Pull-Ups/Pulldowns ...................................................................2-4

2-5 Signal Descriptions ..............................................................................................2-4

2-6 Byte Enable Encodings........................................................................................2-10

2-7 Address Type Definitions.....................................................................................2-12

3-1 RCPU Execution Units .........................................................................................3-5

3-2 FPSCR Bit Categories.........................................................................................3-11

3-3 FPSCR Bit Settings ..........................................................................................3-12

3-4 Floating-Point Result Flags in FPSCR................................................................3-13

3-5 Bit Settings for CR0 Field of CR.........................................................................3-14

3-6 Bit Settings for CR1 Field of CR .......................................................................3-15

3-7 CR

Field Bit Settings for Compare Instructions................................................3-15

3-8 Integer Exception Register Bit Definitions ..........................................................3-16

3-9 Time Base Field Definitions................................................................................3-17

3-10 Machine State Register Bit Settings ...............................................................3-18

3-11 Floating-Point Exception Mode Bits .................................................................3-19

3-12 Time Base Field Definitions..............................................................................3-20

3-13 Uses of SPRG0–SPRG3..................................................................................3-22

3-14 Processor Version Register Bit Settings .........................................................3-23

3-15 Manipulation of MSR[EE] and MSR[RI].............................................................3-23

3-16 Instruction Cache Control Registers..................................................................3-23

3-17 Development Support Registers ......................................................................3-24

3-18 Instruction Set Summary ................................................................................3-26

3-19 MPC509 Exception Classes ............................................................................3-31

3-20 Exception Vector Offset Table ........................................................................3-33

3-21 Instruction Latency and Blockage......................................................................3-35

4-1 Instruction Cache Programming Model .................................................................4-3

4-2 ICCST Bit Settings.................................................................................................4-4

4-3 I-Cache Address Register (ICADR).......................................................................4-5

4-4 I-Cache Data Register (ICDAT).............................................................................4-5

4-5 ICADR Bits Function for the Cache Read Command............................................4-8

4-6 ICDAT Layout During a Tag Read.........................................................................4-8

5-1 SIU Address Map .................................................................................................5-3

5-2 SIUMCR Bit Settings ..........................................................................................5-5

5-3 MEMMAP Bit Settings ........................................................................................5-6

5-4 Internal Memory Array Block Mapping.................................................................5-10

Table Title Page

MOTOROLA LIST OF TABLES MPC509

xvi Rev. 15 June 1998 USER’S MANUAL

5-5 EBI Signal Descriptions .....................................................................................5-13

5-6 Address Type Encodings.....................................................................................5-14

5-7 Byte Enable Encodings........................................................................................5-15

5-8 Signals Driven at Start of Address Phase............................................................5-20

5-9 Burst Access Address Wrapping.........................................................................5-25

5-10 SPECADDR Bit Settings .................................................................................5-26

5-11 SPECMASK Bit Settings .................................................................................5-26

5-12 Example Speculative Mask Values....................................................................5-27

5-13 EBI Read and Write Access to 16-Bit Ports.......... .............. ..... .............. ............5-27

5-14 Cycle Type Encodings .....................................................................................5-29

5-15 EBI Storage Reservation Interface Signals .....................................................5-34

5-16 Chip-Select Pin Functions ...............................................................................5-37

5-17 Chip-Select Module Address Map ...................................................................5-39

5-18 Chip-Select Base Address Registers Bit Settings ...... ..... ..... .............. ............5-40

5-19 Chip-Select Option Register Bit Settings .........................................................5-43

5-20 Block Size Encoding ........................................................................................5-45

5-21 Main Block and Sub-Block Pairings...................................................................5-47

5-22 TADLY and Wait State Control..........................................................................5-50

5-23 Port Size............ .............. .... .............. .............. ..... .............. ..... .............. .... ........5-50

5-24 Pin Configuration Encodings .............................................................................5-51

5-25 BYTE Field Encodings.......................................................................................5-51

5-26 REGION Field Encodings.................................................................................5-52

5-27 Interface Types ................................................................................................5-53

5-28 Pipelined Reads and Writes..............................................................................5-56

5-29 Data Bus Configuration Word Settings for Chip Selects ..................................5-67

5-30 Clocks Module Signal Descriptions ...................................................................5-70

5-31 Clock Module Power Supplies .........................................................................5-70

5-32 System Clock Sources....................... ..... .............. ..... .............. .... .............. ........5-71

5-33 CLKOUT Frequencies with a 4-MHz Crystal ...................................................5-75

5-34 Multiplication Factor Bits....................................................................................5-76

5-35 Reduced Frequency Divider Bits.......................................................................5-77

5-36 Exiting Low-Power Mode...................................................................................5-79

5-37 System Clock Lock Bits.....................................................................................5-80

5-38 SCCR Bit Settings ..........................................................................................5-83

5-39 SCLSR Bit Settings .........................................................................................5-85

5-40 System Protection Address Map .......................................................................5-86

5-41 PCFS Encodings...............................................................................................5-87

5-42 Recommended Settings for PCFS[0:2]..............................................................5-88

5-43 Example PIT Time-Out Periods.........................................................................5-88

5-44 PICSR Bit Settings ..........................................................................................5-90

5-45 BMCR Bit Settings ..........................................................................................5-92

Table Title Page

MPC509 LIST OF TABLES MOTOROLA

USER’S MANUAL Rev. 15 June 1998 xvii

5-46 Reset Status Register Bit Settings ...................................................................5-93

5-47 Reset Behavior for Different Clock Modes .......................................................5-97

5-48 Pin Configuration During Reset.........................................................................5-98

5-49 Data Bus Reset Configuration Word ..............................................................5-100

5-50 SIU Port Registers Address Map..................................................................... 5-102

5-51 Port M Pin Assignments ........... ..... .... .............. ..... .............. .............. ..... ..........5-104

5-52 Port A Pin Assignments .................................................................................5-105

5-53 Port B Pin Assignments .................................................................................5-105

5-54 Port I Pin Assignments ....................................................................................5-107

5-55 Port J Pin Assignments........ ..... .............. ..... .............. .... .............. ..... .............. .5-107

5-56 Port K Pin Assignments...................................................................................5-108

5-57 Port L Pin Assignments ...................................................................................5-108

6-1 PCU Address Map ...............................................................................................6-2

6-2 PCUMCR Bit Settings .........................................................................................6-3

6-3 SWCR/SWTC Bit Settings ..................................................................................6-5

6-4 IMB2 Interrupt Multiplexing....................................................................................6-8

6-5 Interrupt Controller Registers.................................................................................6-8

6-6 PITQIL Bit Settings ...........................................................................................6-10

6-7 Port Q Pin Assignments.......................................................................................6-12

6-8 Port Q Edge Select Field Encoding.....................................................................6-12

7-1 MPC509 SRAM Module Addresses.......................................................................7-1

7-2 SRAMMCR Bit Settings ......................................................................................7-3

8-1 Program Trace Cycle Attribute Encodings.............................................................8-3

8-2 Fetch Show Cycles Control ...................................................................................8-4

8-3 VF Pins Instruction Encodings ............................................................................8-5

8-4 VF Pins Queue Flush Encoding s.............. ..... .... .............. ..... .............. ..... ..............8-6

8-5 VFLS Pin Encodings..............................................................................................8-6

8-6 Cycle Type Encodings...........................................................................................8-7

8-7 Detecting the Trace Buffer Starting Point............................................................8-10

8-8 I-bus Watchpoint Programming Options..............................................................8-17

8-9 L-Bus Data Events .............................................................................................8-18

8-10 L-Bus Watchpoints Programming Options.........................................................8-19

8-11 Trap Enable Data Shifted Into Development Port Shift Register.......................8-31

8-12 Breakpoint Data Shifted Into Development Port Shift Register .........................8-31

8-13 CPU Instructions/Data Shifted into Shift Register..............................................8-31

8-14 Status Shifted Out of Shift Register — Non-Debug Mode................ ..... ............8-32

8-15 Status/Data Shifted Out of Shift Register.................. .............. .... .............. ..... ...8-32

8-16 Sequencing Error Activity ..................................................................................8-33

Table Title Page

MOTOROLA LIST OF TABLES MPC509

xviii Rev. 15 June 1998 USER’S MANUAL

8-17 Checkstop State and Debug Mode......... ..... .... ..... .............. ..... .............. .... ........8-38

8-18 Debug Mode Development Port Usage ...........................................................8-39

8-19 Non-Debug Mode Development Port Usage.....................................................8-41

8-20 Prologue Events................................................................................................8-41

8-21 Epilogue Events.................................................................................................8-42

8-22 Peek Instruction Sequence................................................................................8-42

8-23 Poke Instruction Sequence................................................................................8-42

8-24 Development Support Programming Model .....................................................8-45

8-25 Development Support Registers Read Access Protection ..............................8-45

8-26 Development Support Registers Write Access Protection.................................8-46

8-27 CMPA–CMPD Bit Settings ...............................................................................8-46

8-28 CMPE–CMPF Bit Settings.................................................................................8-46

8-29 CMPG–CMPH Bit Settings................................................................................8-47

8-30 ICTRL Bit Settings ...........................................................................................8-48

8-31 LCTRL1 Bit Settings..........................................................................................8-50

8-32 LCTRL2 Bit Settings ........................................................................................8-51

8-33 Breakpoint Counter A Value and Control Register (COUNTA) .......................8-52

8-34 Breakpoint Counter B Value and Control Register (COUNTB) .......................8-53

8-35 ECR Bit Settings ..............................................................................................8-54

8-36 DER Bit Settings .............................................................................................8-55

9-1 JTAG Interface Pin Descriptions............................................................................9-2

9-2 Instruction Register Encoding................................................................................9-3

MPC509 PREFACE MOTOROLA

USER’S MANUAL xix

PREFACE

This manual defines the functionality of the MPC509 for use by software and hardware

developers. The MPC509 is a member of the PowerPC-based Motorola MPC500 fam-

ily of microcontrolle rs.

Audience

This manual is intended for system software and hardware developers and applica-

tions pr og ram me rs. It is assumed that th e r ea der un de rsta nds ope rat ing systems, m i-

croprocessor and microcontroller system design, and the basic principles of RISC

processing.

Additional Reading

This section lists additional reading that provides background to or supplements the

information in this ma nual.

• John L. Hennessy and David A. Patterson,

Computer Architecture: A Quantitative

Approach

, Morgan Kaufmann Publishers, Inc., San Mateo, CA

•

PowerPC Microprocessor Family: the Programming Environments

(MPCFPE/AD)

•

RCPU Reference Manual

(RCPURM/AD)

•

SIU Reference Manual

(SIURM/AD)

• Additional Motorola MPC500-Family documentation. Refer to Motorola publica-

tion

Advanced Microcontroller Unit (AMCU) Literature

(BR1116/D) for a complete

listing of documentation.

Conventions

This document uses the following notational conventions:

ACTIVE_HIGH Names for signal s that ar e act ive high are shown in uppercase

te xt without an o verbar . Signals that are active high are ref erred

to as asserted when they are high and negated when they are

low.

ACTIVE_LOW A bar over a signal name indicates th at the signal is act iv e l o w.

Active-low signals are referred to as asserted (active) when they

are low and negated when they are high.

MOTOROLA PREFACE MPC509

xx USER’S MANUAL

mnemonics Instruction mnem onics ar e shown in lowercase bold.

italics

Italics indicate variable command parameters, for example,

bcctr

0x0F Hexadecimal numbers

0b0011 Binary numbers

rA|0 The contents of a specified GPR or the value zero.

REG[FIELD] Abbreviations or acronyms for registers are shown in uppercase

text. Specific bit fields or ranges are shown in brackets.

x In ce rtain contexts, such as a sign al encoding, this indicat es a

don’t care. F or example, if a field is binary encoded 0bx001, the

state of the first bit is a don’t care.

Nomenclature

Logic level one is the voltage that corresponds to Boolean true (1) state.

Logic level zero is the voltag e that correspon ds to Boolean false (0 ) state.

To set a bit or bits means to establish logic level one o n the bit or bits.

To clear a bit or bits means to establish logic level zero on the bit or bits.

A signal that is asserted is in its active logic state. An active low signal changes from

logic level one to logic level zero when asserted, and an active high signal changes

from logic level zero to logic level one.

A signal tha t is negated is in its inact ive logic state. An active low signa l changes from

logic level zero to logic level one when negated, and an active high signal changes

from logic level o ne to logic level zero.

LSB means le ast sign i fic an t bit o r b its. MSB mean s most signi fi cant bi t or b it s. R efe r-

ences to low and high bytes are spelled out.

MPC509 INTRODUCTION MOTOROLA

USER’S MANUAL Rev. 15 June 98 1-1

SECTION 1

INTRODUCTION

The MP C509 is a member of th e PowerP C Family of reduced in struction set computer

(RISC) microcontrollers (MCUs). The MPC509 implements the 32-bit portion of the

PowerPC™ architecture, which provides 32-bit effective addresses, integer data types

of eight, 16, and 32 bits, and floating-point data types of 32 and 64 bits.

The RISC MCU processor (RCPU) integrates four execution units: an integer unit (IU),

a load/store unit (LSU), a branch processing unit (BPU), and a floating-point unit

(FPU). The RCPU is capable of issuing one sequential (non-branch) instruction per

clock. In addition, branch instructions are evaluated ahead of time when possible,

resulting in zero-cycle execution time for many branch instructions. Instructions can

complete out of order for increased performance; however, the MPC509 makes them

appear sequential.

The MPC509 includes an on-chip, 4-Kbyte, two-way set associative, physically

addressed instruction cache, chip-select logic to reduce or eliminate external decoding

logic, four Kbytes of static RAM, and extensive processor debugging functionality.

The MPC509 has a high-bandwidth, 32-bit data bus and a 32-bit address bus. The

MCU supports 16-bit and 32-bit memories and both single-beat and burst data mem-

ory accesses.

The MP C509 is avai la bl e in a 3 V- on l y I/O conf igurat i on ( pa rt nu m be r M PC509L) an d

in a TTL-c ompatible 5 V-friendly I/O configuration (par t number MP C509L3 ).

1.1 Fe at ures

• Fully-Integrated Single-Chip Micr ocontroller

• RISC MCU Central Processing Unit (RCPU)

— 32-Bit PowerPC Architecture (Compliant with PowerPC Architecture Book 1)

— Single-Issue Processor

— Integrated Floating-Point Unit

— Branch Prediction for Prefetch

— 32 Bit x 32 Bit General-Purpo se Regist er File

— 32 Bit x 64 Bit Floating-Point Register File

— Precise Exception Model

— Internal Harvard Architecture: Load/Store Bus (L-Bus), Instruction Bus (I-Bus)

— PowerPC Time Base and Decrementer

• System Interface Unit (SIU)

— Chip-Select Logic to Reduce or Eliminate External Decoding Logic

— External Bus Interface (EBI) that Supports Synchronous, Asynchronous, Burst

Transfer, and Pipeline Transfer Memory Types

— System Protection Features Including Bus Monitor and Periodic Interrupt

Timer

MOTOROLA INTRODUCTION MPC509

1-2 Rev. 15 June 98 USER’S MANUAL

— On-Chip Phase-Locked Loop (PLL), 16 MHz to 44 MHz

— Five Dual-Purpose I/O Ports, Two Dual-Purpose Output Ports

• Peripheral Control Unit (PCU)

— Software Watchdog

— Interrupt Controller to Manage External and Internal Interrupts to the CPU

— Dual-Purpose I/O Port

— L-Bus IMB Interface (LIMB) Connecting L-Bus to Intermodule Bus 2 (IMB2)

• 4-Kbyte On-Chip Instruction Cache (I-Cache)

• 4-Kbyte On-Chip Sta tic Data RAM (SRAM)

• 3.3-V Sup ply Voltag e

• Tolerates Input Signals from 5-V Peripherals

1.2 Bl ock Diagram

Figure 1-1 MPC509 Block Diagram

Notice in Figure 1-1 that the IMB2 connects the p rocessor to any on-chip p eripher als.

No such peripherals are present on the MPC509.

INTERMODULE BUS 2 (IMB2)

DEVELOPMENT

SUPPORT

RISC MCU

PROCESSOR

4-KBYTE SR AM

PERIPHERAL

4-KBYTE

DEVELOPMENT

EXTERNAL

PORT

I-CACHE

CONTROL UNIT

INTERNAL LO AD/ ST O RE BU S (L-BUS)

INTERNAL INSTRUCTION BUS (I-BUS)

(PCU)

SYSTEM

INTERFACE

UNIT

(RCPU) BUS

(SIU)

IRQs

MPC509 INTRODUCTION MOTOROLA

USER’S MANUAL Rev. 15 June 98 1-3

1.3 Pin Connections

Figure 1-2 MPC509 Pin Assignments

VSSE9

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

DATA4

VSSE8

DATA14

DATA0

DATA1

ADDR27

ADDR26

VSSE7

VDDE7

ADDR25

ADDR21

ADDR20

VDDE8

DATA6

DATA5

DATA7

DATA3

VDDIR

DATA15

DATA2

ADDR29

ADDR28

ADDR24

ADDR23

ADDR22

VSSE6

ADDR19

ADDR18

ADDR17

ADDR16

ADDR15

VSSIR

ADDR14

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

VSSE0

DDR3/CS3

ADDR2/CS2

ADDR1/CS1

ADDR0/CS0

CSBOOT

CT3

VSSE1

VDDE1

ADDR4/CS4

VSSIL

BE0

ARETRY

CR/DS

VDDE2

ECROUT

CLKOUT

XTAL

EXTAL

BE3

CT1

CT0

CT2

BE2

ADDR5/CS5

BE1

BURST

BDIP

VSSE2

PDWU

VDDKAP1

VDDE3

VSSSN

XFCN

XFCP

VDDSN

RESETOUT

VDDIL

RESET

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

VDDE0

ADDR8/CS8

ADDR9/CS9

ADDR10/CS10

ADDR11/CS11

VSSE12

VDDE12

TEA

ADDR7/CS7

VDDIT

VSSIT

VSSE11

VDDE11

DATA27

DATA26

DATA25

DATA21

DATA20

AACK

DATA30

ADDR6/CS6

DATA29

DATA28

DATA24

DATA23

DATA22

VDDE9

VSSE10

VDDE10

DATA19

DATA18

DATA17

DATA31

DATA16

VSSE3

DSCK

DSDI

VDDKAP2

MODCLK

TRST

TMS

IRQ2

IRQ3

IRQ0

WP4

WP5

VSSIB

VDDIB

VFLS1

VF0

DSDO/PLLL

IRQ4

TDO

TDI

TCK

IRQ5

VDDE4

IRQ1

IRQ6

WP3

VFLS0

VF2

VF1

VDDE6

VSSE5

VDDE5

AT1

AT0

ADDR12

VSSE4

ADDR13

WP2

WP1

WP0

MPC509

121

MOTOROLA INTRODUCTION MPC509

1-4 Rev. 15 June 98 USER’S MANUAL

Figure 1-3 MPC509 Si gna ls

BG/PM6

BR/PM4

BR BB/PM5

CS[0:7]/ADDR[0:7]/PA[0:7]

ADDR[16:29]

PORT B

ADDR[12:15]/PB[4:7]

CS[8:11]/ADDR[8:11]/PB[0:3]

DATA[0:31]

CSBOOT

BE[2:3]/PI[6:7]

TS/PJ3

AACK/PI2

TA/PI3

TEA/PI1

PORT J

PORT M

BI/PM3

BURST/PI0

BDIP/PK0

ARETRY/PM7

PLLL/DSDO/PK2

VF[0:2]/PK[3:5]

VFLS[0:1]/PK[6:7]

WP[0:5]/PL[2:7]

CR/DS

RESETOUT

CONTROL

CHIP SELECTS

EXTERNAL BUS

INTERFACE

CLOCKS

SIU

CT[0:3]/PJ[4:7]

PORT I

PORT A

BE[0:1]/PI[4:5]

PORT KPORT L

AT1/PJ2

RESET

DSDI

DSCK

PDWU

ADDR[0:29]

BE[0:3]

CS[0:11]

AACK

TEA

BURST

BDIP

ARETRY

DSDI

VF[0:2]

VFLS[0:1]

WP[0:5]

CT[0:3]

DSCK

PLLL/DSDO

PERIPHERAL

CONTROL

PORT Q

PQ[0:6]/IRQ[0:6]IRQ[0:1]

UNIT (PCU)

XTAL

EXTAL

XFCN, XFCP

MODCLK

CLKOUT

ECROUT

AT[0:1] AT0/PJ1

WR/PK1

MPC509 INTRODUCTION MOTOROLA

USER’S MANUAL Rev. 15 June 98 1-5

1.4 Memory Map

Figure 1-4 MPC509 Memory Map

The MPC family has a unified memory map including instruction memory (I-Mem),

load/store memory (L-Mem), and all memory-mapped registers. I-Mem resides on the

instruction bus; L-Mem resides on the load/store bus. The locations of I-Mem and L-

Mem are selected in the MEMMAP register located in the SIU. In the MPC509, the

SRAM module serves as L-Mem. The MPC509 has no I-Mem module.

0x0000 0000

0x000F EFFF

0xFFF0 0000

0xFFFF EFFF

0x8007 E000

0x8007 EFFF

EXTERNAL

POSS IBLE SRAM

ONE OF FOUR POSSIBLE LOCATIONS

PERIPHERAL

EXTERNAL

CONTROL UNIT

(PCU)

CONTROL REGISTERS

0x8000 0000

EXTERNAL/RESERVED

0x8007 FFFF

0x8007 F000

VECTOR TABLE LOCATION

(IP BIT = 0)

VECTOR TABLE LOCATION

(IP BIT = 1)

LOCATION

(28 KBYTES)

POSS IBLE SRAM

LOCATION

(28 KBYTES)

POSS IBLE SRAM

LOCATION

(28 KBYTES)

POSS IBLE SRAM

LOCATION

(28 KBYTES)

0xFFFF E000

0xFFF0 6FFF

0x0000 6FFF

0x000F E000

SELECTED FOR SRAM

MOTOROLA INTRODUCTION MPC509

1-6 Rev. 15 June 98 USER’S MANUAL

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-1

SECTION 2

SIGNAL DESCRIPTIONS

This section describes the MPC509 signals and pins. For a more detailed discussion

of a particular signal, refer to the section of the manual that discusses the function

involved.

2.1 Pin List

Table 2-1 MPC509 Pin List

Primary Function(s) Port Function

Address Bus, Data Bus, Chip Selects

ADDR[0:11]/CS[0:11] PA[0:7], PB[0:3]

ADDR[12:15] PB[4:7]

ADDR[16:29] —

DATA[0:31] —

CSBOOT —

Bus Control, Clock, Development Support

BURST, TEA, AACK, TA, BE[0:1],

BE2/ADDR30, BE3 PI[0:7]

AT[0:1], TS, CT[0:3] PJ[1:7]

BDIP, WR, PLLL/DSDO, VF[0:2], VFLS[0: 1] PK[0:7]

WP[0:5] PL[2:7]

BI, BR, BB, BG, ARETRY PM[3:7]

CR/DS —

DSCK, DSDI —

XTAL, EXTAL, XFCN, XFCP, CLKOUT,

ECROUT, PDWU, MODCLK —

Reset, Interrupts

RESET, RESETOUT —

IRQ[0:6] PQ[0:6]

Test

TDI, TDO, TCK, TMS, TRST —

Power

VDDSN, VSSSN —

VDDI, VSSI —

VDDE, VSSE —

VDDKAP1, VDDKAP2 —

MOTOROLA SIGNAL DESCRIPTIONS MPC509

2-2 Rev. 15 June 98 USER’S MANUAL

2.2 Pin Characteristics

Table 2-2 shows the characteristics of the MPC509 pins. Assume the model for output

only and three-sta te I/O b uffer s shown in Figure 2-1.

Figure 2-1 Output-Only and Three-State I/O Buffers

Table 2-2 EBI Pin Definitions

Mnemonic Buffer

Type Weak

Pull-Up1When Bus is Granted When Bus Is Not

Granted During Reset

Address and Data Bus

CS[0:11]/

ADDR[0:11] Output

only No Driven Driven high Initially high, changes

five clock cycles after

reset source is negated

ADDR[12:29] 3-state No Driven unless config-

ured as input port Float unless co nfi gured

as ou tput port Float

DATA[0:31] 3-state No Driven if write, float if

read Float unles s confi gur ed

as ou tput port Float

Transfer Attributes

WR 3-state No

Output unless config-

ured as input port s Fl oat unless co nfi gured

as ou tput port Float

BURST 3-state No

BE[0:3] 3-state No

AT[0:1] 3-state No

CT[0:3] 3-state No

Transfer Handshak es

TS 3-state No Output unless config-

ured as input port Float unless co nfi gured

as ou tput port Input port; output three-

stated

AACK 3-state Yes Input u nl ess configur ed

as an output port Float unless co nfi gured

as ou tput port Input port; output three-

stated

BDIP/LAST 3-state No Output unless config-

ured as input port Float unless co nfi gured

as ou tput port Input port. After reset,

driven by CPU

BI 3-state Yes Input unless configured as output port Float

TA 3-state Yes Input u nl ess configur ed

as an output port

Float (listen only); only

driven if configured as

output port

Input port; output three-

stated

I/O

OUTPUT-ONLY BUFFER

OUTPUT

D_OUT

3-STATE BUFFER

D_OUT

D_EN

D_IN

MPC500 I/O BUFFERS

VDD

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-3

2.3 Power Connections

Table 2-3 shows the MPC509 power connections.

CAUTION

The keep-alive power pins (VDDKAP1 and VDDKAP2) must be pow-

ered up before or at the same time as VDD (V DDI, VDDE, and VDDSN).

Otherwise, an excessive draw may result.

2.4 Pins with Internal Pull-Ups and Pulldowns

Table 2-4 lists MPC509 pins with internal pull-ups or pulldowns.

TEA 3-state Yes Input u nl ess configur ed

as an output port

Float (listen only); only

driven if configured as

output port

Input port; output three-

stated

ARETRY 3-state Yes Input u nl ess configur ed

as ou tput port Input; d riven if config-

ured as output port Input port; output three-

stated

Arbitration

BR 3-state No Output unl ess configure d as input po rt. Not affect-

ed by BG.Float

BG 3-state Weak pull-

down Input u nl ess confi gured

as ou tput port Output only if config-

ured as output port Float

BB 3-state Yes Output unless config-

ured as input port

If relinquishing drive

high then float unless

configured as output

port

Float

Miscellaneous

CR/DS 3-state Yes Not affected by BG. Input unless configured for

secondary function Float

RESETOUT Output No Not affected by BG —

RESET Input No Not affected by BG —

CLKOUT Output No Not affected by BG Not affected

NOTES:

1. Weak pull-ups can maintain an internal logic level one but may not maintain a logic level one on external pins.

Table 2-3 MPC509 Power Connections

Pin Description

VDDE, VSSE External peri phe ry powe r

VDDI, VSSI Internal module power

VDDSN, VSSSN Clock syn thes iz er powe r

VDDKAP1 Keep-alive power for the internal oscillator, time base,

and decrementer

VDDKAP2 Keep-aliv e powe r for the SRAM array

Table 2-2 EBI Pin Definitions (Continued)

Mnemonic Buffer

Type Weak

Pull-Up1When Bus is Granted When Bus Is Not

Granted During Reset

MOTOROLA SIGNAL DESCRIPTIONS MPC509

2-4 Rev. 15 June 98 USER’S MANUAL

2.5 Signal Descriptions

MPC509 signals are summarized in Table 2-5 and described in the following subsec-

tions . Sin ce pins ofte n have more th an one funct ion, more tha n one descr iption may

apply to a pin.

Table 2-4 Pins with Internal Pull-Ups/Pulldowns

Pin Pull-Up/Pulldown

Pull-Up

TEA

AACK

ARETRY

IRQ[0:6]

TMS

TRST

TDI

Pulldown

DSCK

DSDI

TCK

Table 2-5 Signal Descriptions

Mnemonic Module Direction Description

ADDR[0:29] EBI Output 32-bit address bus. Driven by the bus master to index the bus slave.

Low-order bit (ADDR31) not pinned out — use byte enables instead.

BE2 functions as ADDR30 during accesses to 16-bit ports.

AACK EBI Input Address acknowledge. When asserted, indicates the slave has received

the address from the bus master.

ARETRY EBI Input When asserted, indicates the master needs to retry its address phase.

AT[0:1] EBI Output Address types. Define addressed space as user or supervisor, data or

instruction.

BB EBI Input/Output Bus busy. Asserted by current bus master to indicate the bus is currently

in use. Prospective new master should wait until the current master ne-

gates this signal.

BDIP EBI Output Burst data in progress. Asserted at the beginning of a burst cycle and

negated prior to the last beat. This signal can be negated prior to the end

of a burst to terminate the burst data phase early.

BE[0:3] EBI Output Byte enables. One byte enable per byte lane of the data bus.

BG EBI Input Bus grant. When asser ted by bus a rbiter, the b us is grant ed to the bus

master. Each master has its own bus grant signal.

BI EBI Input Burs t inhibit . When asserte d, indicat es the slave does not supp ort burst

mode.

BR EBI Output Bus request. When asserted, indicates the potential bus master is re-

questing the bus. Each master has its own bus request signal.

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-5

BURST EBI Output If asserted, indicates cycl e is a burst cycle.

CLKOUT EBI Output Continuousl y-running clock. All signal s driven on the E-bus must be syn-

chronized to the rising edge of this clock.

CR EBI Input Cancel reservation. Each RCPU has its own CR signal. When asserted,

instructs the bus master to clear its reservation.

CSBOOT Chip

Selects Output Chip select of system boot memory.

CS[0:11] Chip

Selects Output Chip-select signals for external memory devices.

CT[0:3] EBI Output Cycle type signa ls. In dicate what ty pe of b us c ycle the bus master is ini -

tiating.

DATA[0:31] EBI Input/Output 32-bit data bus.

DS EBI Output

Data stro be. Asse rted by EBI at the end of a chip-sel ec t-co ntro ll ed bu s

cycle after the chip-select unit asserts the internal TA signal or the bus

monitor timer asserts the internal TEA signal. Also asserted at the end

of a show cycle. Used primarily by development tools.

DSCK Dev.

Support Input Dev elopment serial clock. Used to clock data shi fted into or out of de vel-

opment seri al port .

DSDI Dev.

Support Input Development serial data in. Used to shift development serial data into

the development port shift register .

DSDO Dev.

Support Output Development serial data out. Used to shift development serial data out

of the development port shift register.

ECROUT Clocks Output Provides a clock reference output with a frequency equal to the crystal

oscillator frequency, taken from the PLL feedback signal.

EXTAL Clocks Input Connection for external crystal to the internal oscillator circuit, or clock

input.

IRQ[0:6] PCU Input Interrupt request inputs.

MODCLK Clocks Input

Clock mode. The state of this signal and that of VDDSN during reset de-

termine the source of the system clock (normal operation, 1:1 mode,

PLL bypass mode, or special test mode). Refer to Table 5-32 in SEC-

TION 5 SYSTEM INTERFACE UNIT for details.

PA[0:7] Ports Output Port A discrete output signals.

PB[0:7] Ports Output Port B discrete output signals.

PDWU Clocks Output Power-down wakeup to external power-on reset circuit.

PI[0:7] Ports Input/Output Port I discrete input/output signals.

PJ[0:7] Ports Input/Output Port J discrete input/output signals.

PK[0:7] Ports Input/Output Port K discrete input/output signals.

PL[2:7] Ports Input/Output Port L discrete input/output signals.

PM[3:7] Ports Input/Output Port M discrete input/output signals.

PQ[0:6] PCU Input/Output Port Q discrete input/output signals.

PLLL Clock Output Indicates whether phase-locked loop is locked.

RESET EBI Input Hard reset. When asserted, devices on the bus must reset.

RESETOUT EBI Output Reset output signal. Asserted by MCU during reset. When asserted, in-

structs all devices monitoring this signal to reset all parts within them-

selves that can be reset by software.

TA EBI Input Transfer acknowledge. When asserted, indicates the slave has received

the data during a write cycle or returned the data during a read cycle.

Table 2-5 Signal Descriptions (Continued)

Mnemonic Module Direction Description

MOTOROLA SIGNAL DESCRIPTIONS MPC509

2-6 Rev. 15 June 98 USER’S MANUAL

2.5.1 Bus Arbitration and Reservation Support Signals

The bus arbitration signals request the bus, recognize when the request is granted,

and indicate to other devices when mastership is granted. There are no separate arbi-

trati on phases for th e address and d ata buses . For a detailed description of how the se

signals interact, see 5.4.5.1 Arbitration Phase.

The cancel reservation (CR) signal is used to indicate that the processor should not

perform any stwcx. cycle to external memory. This signal is sampled at the same time

the MCU samples the arbitration pins for a qualified bus grant.

2.5.1.1 Bus Request (BR)

Output only

Module: EBI

State Meaning Asserted — Indicates the potential bus master is request-

ing the bus. Each master has its own bus request signal.

The SIU asserts BR to request bus mastership if its bus

TCK JTAG Input Test clock input with a pull-down resistor to synchronize the test logic.

TDI JTAG Input Test data input with a pull-up resistor sampled on the rising edge of

TCK.

TDO JTAG Output Three-sta table test dat a output that ch anges on the fall ing edge of TCK.

TEA EBI Input Tra ns fer error ac kn ow le dg e. Asserte d by an ex te rnal d evice to s ign al a

bus error condition.

TMS JTAG Input Test mode select input with a pull-up resistor. Sampled on the rising

edge of TCK to sequence the test controller’s state machine.

TRST JTAG Input Async hro no us a cti ve -low te st re set wi th a pu ll -up res isto r that p rovi de s

initialization of the TAP controller and other logic as required by the stan-

dard.

TS EBI Output Transfer start. When asserted, indicates the start of a bus cycle.

VDDSN Clocks Input

Power supply input to the VCO. In addition, the state of this signal and

that of MODCLK during reset determine the source of the system clock

(norma l o pera tio n, 1:1 mod e, PL L b ypa ss m ode , or s pecial tes t mo de ).

Referto Table 5-32 in SECTION 5 SYSTEM INTERFACE UNIT for de-

tails.

VF[0:2] Dev.

Support Output Denotes the last fetched instruction or how many instructions were

flushed from the instruction queue.

VFLS[0:1] Dev.

Support Output Denotes how many instructions are flushed from the history buffer dur-

ing the current clock cycle. Also indicates freeze state.

VSSSN Clocks Input Power ground input to the VCO.

WP[0:5] Dev.

Support Output Output signals for I-bus watchpoints (WP[0:3]) and L-bus watchpoints

(WP[4:5]).

XTAL Clocks Output Connection for external crystal to the internal oscillator circuit.

WR EBI Output Asserted (low): write cycle. Negated (high): read cycle.

XFCN,

XFCP Clocks Input Use d to add an exte rnal capacitor to the filter ci rcuit of the p hase-locked

loop.

Table 2-5 Signal Descriptions (Continued)

Mnemonic Module Direction Description

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-7

grant (BG) pin is not already asserted and the bus busy

(BB) has not been negated by the current bus master.

The SIU assum es ma stership of t he external bu s onl y after

receiving a qualified bus grant. This occurs when the bus

arbiter asserts BG to the SI U and the B B pin has also been

negated by the previous bus master. The SIU cannot start

a cycle on the external bus if the current master is holding

the BB pin asserted, even if the SIU has received a bus

grant (BG asserted) from the bus arbiter.

Negated — Indicates the MCU is not requesting the ad-

dress bus. Th e MCU may have no bu s ope ration pend ing,

it may be parked, or the MCU may be in the process of re-

leasing the bus in response to ARETRY.

Timing Comments Assertion — Occurs when the MCU is not parked and a bus

transaction is nee de d.

Negation — Occurs as soon as the SIU starts a bus cycle

after receiving a qualified bus grant.

2.5.1.2 Bus Grant (BG)

Input only

Module: EBI

State Meaning Asserted — (By b us arbiter) indica tes th e b us is grant ed t o

the requesting device. The signal can be kept asserted to

allow the current master to park the bus. Single-master sys-

tems can tie this signal low permanently.

Negated — Indicates the requesting device is not granted

bus mastership.

Timing Comments Assertion — May occur at any time to indicate the MCU is

free to use the address bus. After the MCU assumes bus

mastership, it does not check for a qualified bus grant again

until the cycle during which the address bus ten ure is com-

pleted (assuming it has another transaction to run). The

MCU does not accept a BG in the cycles between the as-

serti on of any TS and AACK.

Negation — May occur at any time to indicate the MCU

cannot use the bus. The MCU may still assume bus mas-

tership on the clock cycle of the negation of BG because

during the previous cycle BG indicated to the MCU that it

was free to take mastership (if qualified).

MOTOROLA SIGNAL DESCRIPTIONS MPC509

2-8 Rev. 15 June 98 USER’S MANUAL

2.5.1.3 Bus Busy (BB)

Input/Output

Module: EBI

State Meaning Asserted — The current bus master asserts this signal to

indicate the bus is currently in use. The prospective new

master must wait until the current master negates this sig-

nal.

Negate d — In di cat e s th at the b us is no t ow ne d by a no t he r

bus master and that the bus is available to the MCU when

accompanie d by a qualified bus grant.

Timing Comments Assertion — BB is asserted during the address phase of

each external bus cycle, if it was previously negated. It re-

mains asserted between internal atomic cycles (any non-

burst word accesses to an external 16-bit port).

Negation — Occurs during the clock cycle following termi-

nation of the data phase of an external bus cycle. The sig-

nal is negated for half a clock cycle and then placed in a

high-impedance state.

2.5.1.4 Cancel Reservation (CR)

Input only

Module: EBI

State Meaning Asserted — (By an external bus arbiter or reservation

snooping logic) indicates that there is no outstand ing reser-

vation on the ext ernal bus. Each RCPU has its own CR sig-

nal. Assertion indicates that the processor should not

perform any stwcx. cycle to external memory.

Negated — Indicates there is an outstanding reservation on

the external bus.

Timing Comments Assertion — Can occu r at a ny rising e dg e of the b us clock.

This signal is sam pled a t the same time the MCU sample s

the arb itr ati o n pi n s for a qu al ifi ed bus gran t pri or to starti n g

a bus cycle.

2.5.2 Address Phase Signals

The address phase is the period of time from the assertion of transfer start (TS) until

the address phase is terminated by one of the following signals: address acknowledge

(AACK), ad dress r etry (ARETRY ), or t ransf er error acknowle dge (T EA). TS is valid for

one clock cycle at the start of the address phase. The address bus and the address

attributes described below are valid for the duration of the address phase. Refer to

5.4.5.2 Address Phase for additional information on address phase signals.

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-9

2.5.2.1 Address Bus (ADDR[0:29])

Output only

Module: EBI

State Meaning Asserted/Negated — Represents the physical address of

the data to be transferred. Driven by the bus master to in-

dex the bus slave. Low-order bit (ADDR31) is not pinned

out; byte enable signals (BE[0:3]) are used instead (see Ta-

ble 2-6). During accesses to 16-bit ports, BE2 p in provid es

ADDR30 signal.

Timing Comments Assertion/Nega tion — Occurs one clock cycle aft er a qual-

ified bus gran t. Coinci des with assertion of BB and TS.

High impedance — Coincides with negation of BB, provid-

ed no qualified bus grant exists .

2.5.2.2 Writ e/Read (W R)

Output only

Module: EBI

State Meaning Asserted/Negated — This signal is driven high for a read

cycle and low for a write cycle.

Timing Comments Assertion/Negation — WR is an address attribute ; it is up-

dated at the start of the address phase and maintained until

the start of the next address phase. Note that for pipelined

accesses, it is not valid during the data phase.

High impedance — Coincides with negation of BB, provid-

ed no qualified bus grant exists .

2.5.2.3 Burst Indicator (BURST)

Output only

Module: EBI

State Meaning Asserted — indicates a burst cycle. If a burst access is

burst-inhibited by the slave, BURST is driven during each

single-beat (decompose d) cycle.

Negated — Indicates current cycle is not a burst cycle.

Timing Comments Assertion/Negation — BURST is an addres s attribu te; it is

updated at the start of the address phase and maintained

until the start of the next address phase.

High impedance — Coincides with negation of BB, provid-

ed no qualified bus grant exists .

MOTOROLA SIGNAL DESCRIPTIONS MPC509

2-10 Rev. 15 June 98 USER’S MANUAL

2.5.2.4 Byte Enables (BE[0:3])

Output only

Module: EBI

State Meaning BE[0:3] indicate which byte withi n a word is being acce ss-

ed. External memory chips can use these signals to deter-

mine which byte location is enabled. Table 2-6 explains the

encodings during accesses to 32-bit and 16-bit ports.

Timing Comments Assertion/Negation — The BE[0:3] signals are address at-

tributes; they are updated at the start of the address phase

and maintained until the start of the next address phase.

High impedance — Coincides with negation of BB, provid-

ed no qualified bus grant exists .

2.5.2 .5 Tran sfer Start ( TS)

Output only

Module: EBI

State Meaning Asserted — Indicates the start of a bus cycle.

Timing Comments Assertion — Coincides with the assertion of BB.

Negation — Occurs one clock cycle after TS is asserted.

High impedance — Coincides with negation of BB, provid-

ed no qualified bus grant exists .

2.5.2.6 Address Acknowledge (AACK)

Input only

Module: EBI

State Meaning Asserted — Indicates that the address phase of a transac-

tion is complete.

If the external access is to a chip-select region for which the

chip select is programmed to return AACK and TA, then the

external bus interface uses the logical OR of the external

AACK pin and the AACK signal returned by the chip select.

If the chip select returns AACK, it is not visibl e on the exte r-

Table 2-6 Byte Enable Encodings

Byte Enable Use During 32-Bit Port Access Use During 16-Bit Port Access

BE0 Byte enable for DATA[0:7] Byte enable for DATA[0:7]

BE1 Byte enable for DATA[8:15] Byte enable for DATA[8:15]

BE2 Byte enable for DATA[16:23] ADDR30

BE3 Byte enable for DATA[24:31] 0 = Operand size is word

1 = Operand size is byte or half-word

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-11

nal pi ns.

Negated — (While the MCU is driving BB) indicates that the

address bus and the transfer attributes must remain driven.

Timing Comments Assertion — May occur as e arly as the clock cycle afte r TS

is asserted; assertion can be delayed to allow adequate ad-

dress access time for slow devices. AACK should be as-

serted at the same time as or prior to the asser tion of TA. If

AACK is returned prior to the assertion of TA, the SIU can

initiate another cycle while the previous cycle is still in

progre ss ; th at is , ret urn ing AA CK ea rly a llo ws pip eli ni ng of

bus cycles.

Negation — Must occur one clock cycle after the assertion

of AACK.

High impedance — Coincides with negation of BB, provid-

ed no qualified bus grant exists .

2.5.2.7 Burst Inhibit (BI)

Input only

Module: EBI

State Meaning Asserted — Indicates the addressed device does not have

burst capability. When this signal is asserted, the SIU de-

composes the transfer into multiple cycles, incrementing

the address for each cycle.

For systems that do not use burst mode at all, this signal

can be tied low permanently.

Negated — Indicates the device supports burst mode, or

that the BI signal is being sent by the chip-select unit. For

systems that use SIU chip selects with all external memory,

the BI pin can remain negated; the chip-select unit can be

prog rammed t o assert BI to prevent bursts.

Timing Comments Assertion/Negation — Sampled when AACK is asserted. A

burst tr ansfer can o nly be bu rst-inhi bited befo re the fi rst TA

assertion.

Simple, asynchronous memory devices should keep AACK

negated to keep the address valid. They can assert BI at

the same time as or before AACK and at the same ti me as

the first TA assertion.

Synchronous, pipelineable memory devices that do not

support bursting should return BI with AACK as soon as

they are ready to receive the next address.

MOTOROLA SIGNAL DESCRIPTIONS MPC509

2-12 Rev. 15 June 98 USER’S MANUAL

Burstable memory devices should negate BI at the same

time as or before they assert AACK.

2.5.2.8 Address Retry (ARETRY)

Input only

Module: EBI

State Meaning Asserted — If the MCU is the bus master, ARETRY indi-

cates that the MCU must retry the preceding address

phase. The MCU will not begin a bus cycle for the clock

cycle following assertion of ARETRY. Note that the subse-

quent a ddress re tried may no t be the sam e one associ ated

with the assertion of the ARETRY signal. Assertion of ARE-

TRY overrides the assertion of AACK.

Negated/High Impedance — Indicates that the MCU does

not need to retry the last address phase.

Timing Comments Assertion — Must occur at least one clock cycle following

the assertion of TS if a retry is required. TA or TEA must not

be asserted d uring a cycle in which A RETRY is asserte d. If

TA is asserted for any part of a burst cycle, ARETRY must

not be asserted at any time during the cycle; if ARETRY is

asserted during a burst cycle, it must be asserted before

the first beat is terminated with TA.

Note that BB is not negated un til the second clock cycle af-

ter ARETRY assertion.

Negation — Must occur one clock cycle after assertion of

ARETRY.

2.5.2.9 Address Type (AT[0:1])

Output only

Module: EBI

State Meaning Asserted/Negated — AT[0:1] define the addressed space

as user o r super visor an d as data or instr uction, as shown

in Table 2-7.

Table 2-7 Address Type Definitions

AT[0:1] Address Space Definition

0b00 User, data

0b01 User, instruction

0b10 Supervisor, data

0b11 Supervisor, instruction

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-13

Timing Comments Assertion/Negation — The AT[0:1] signals are address at-

tributes; they are updated at the start of the address phase

and maintained until the start of the next address phase.

High impedance — Coincides with negation of BB, provid-

ed no qualified bus grant exists .

2.5.2.10 Cycl e Types (CT[0:3])

Output only

Module: EBI

State Meaning Asserted/Negated — Cycle type signals. Indicate what type

of bus cycle the bus master is initiating. Refer to Table 5-

14 in SECTION 5 SYSTEM INTERFACE UNIT for cycle

type encodings.

Timing Comments Assertion/Negation — The CT[0:3] signals are address at-

tributes; they are updated at the start of the address phase

and maintained until the start of the next address phase.

High impedance — Coincides with negation of BB, provid-

ed no qualified bus grant exists .

2.5.3 Data Phase Signals

Depending on the state of the pipeline, the data phase starts either one clock cycle

after the address phase sta rts, or as soon as th e previous dat a phase comp letes. The

data phase completes when it is terminated by transfer acknowledge (TA) or transfer

erro r acknow ledge (TE A ). If the cycle is a burst cycle , th en multiple TA asse rtions are

required to t ermin ate the da ta pha se. Refer to 5. 4.5.3 Da ta P ha s e fo r a dd i tiona l info r-

mation on dat a pha se sign als.

2.5.3.1 Da ta Bus (DATA[0:31])

Input/output

Module: EBI

State Meaning Asser ted/Negate d — Repres ents the sta te of data du ring a

read or write. 16-bit devices must reside on DATA[0:15].

32-bit devices reside on DATA[0:31].

Timing Comments Assertion/negation — On write cycles, the SIU drives data

one clock after driving TS. The data is available until the

slave asserts TA.

During reads, the data must be available from the slave

with TA. The data bus i s driv en on ce for n on-b urst tr ansac-

tions and four times for burst transactions.

High impedance — The pins are placed in a high-imped-

ance state during reads, or while the bus is idle, or when the

MOTOROLA SIGNAL DESCRIPTIONS MPC509

2-14 Rev. 15 June 98 USER’S MANUAL

bus is arbitrated away. For write cycles, the high-imped-

ance state occurs on the clock cycle after the final assertion

of TA.

2.5.3.2 Burst Da ta in Progress (BDIP)

Output only

Module: EBI

State Meaning Asserted — Indicates the data beat in front of the current

one is nee ded by the m aste r. This sign al is asserte d at th e

beginning of a burst data phase.

Negated — Indicates the final beat of a burst. This signal

can be negated prior to the end of a burst to terminate the

burst data phase early.

Timing Comments Assertion/Neg ation — When the L ST b it in the SIUMCR is

set, BDIP uses the timing for the LAST signal. When LS T is

cleared, BDIP uses t he timin g fo r the BDIP signal. Refer to

5.5.16.6 Synchronous Burst Interface for more information.

High impedance — Coincides with negation of BB, provid-

ed no qualified bus grant exists .

2.5.3.3 Transfer Acknowledge (TA)

Input only

Module: EBI

State Meaning Asserted — Indicates the slave has received the data dur-

ing a write cycle or returned the data during a read cycle.

Note that TA must be asse rted for each data beat i n a burst

transaction.

If the external access is to a chip-select region for which the

chip-select circuit is programmed to return AACK and TA,

the EBI uses the logical OR of the external TA pin and the

internal TA signal returned by the chip-select unit.

Negated — (While BB is asserted) indicates that, until TA

is asserted, the MCU mu st continue to drive t he data for the

current write or must wait to sample the data for reads.

Timing Comments Assertion — Must not occur before AACK is asserted for

the current transaction. TA must not be asserted on cycles

terminated by ARETRY and must not be asse r ted aft er th e

cycle has been terminated. The system can withhold asser-

tion of TA to indica te that the MC U should inser t wait states

to extend the duration of the data beat.

Negation — Must occur a fter th e clo ck cycle of t he final (or

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-15

only) data beat of the transfer. For a burst transfer that is

not under chip-select con trol, the system can assert TA for

one clock cycle and then negate it to advance the burst

transfer to the next beat and insert wait states during the

next beat.

2.5.3.4 Transfer Error Acknowledge (TEA)

Input only

Module: EBI

State Meaning Asserted — (By an external device) signals a bus error con-

dition. TEA assertion terminates the data phase of the cur-

rent bus cycle and overrides the assertion of TA. If AACK

has not be en asserted for the curren t bus cycle, TEA termi-

nates both the address phase and the data phase.

This signal is intended for the cases of a write to a read-only

address space or an access t o a non-existent address. The

signal can be output by a bus monitor timer or some system

address protection mechanism, such as the chip-select

logic.

Negated — Indicates that no external device has signaled

a bus error.

Timing Comments Assertion — May occur at any time during the address

phase or data phase of a bus cycle.

Negation — Must occur one clock cycle after assertion of

TEA.

2.5.3.5 Data Strobe (DS)

Output only

Module: EBI

State Meaning Asserted — (By EBI) indicates the termination of a cycle

from an internal source (TA or TEA asserti o n fr om the chip

select unit, TEA assertion f ro m th e b us monit or, or a show

cycle). DS can be used to latch data for a bus analyzer. It

can also aid in following the external bus p i peline.

Timing Comments Assertion — Occurs after the chip-select unit asserts the in-

ternal TA signal or the bus monitor timer asserts the inter-

nal TEA signal. DS is also asserted at the end of a show

cycle.

MOTOROLA SIGNAL DESCRIPTIONS MPC509

2-16 Rev. 15 June 98 USER’S MANUAL

2.5.4 Development Support Signals

2.5.4.1 Development Port Serial Data Out (DSDO)

Output only

Module: Development support

State Meaning Asser ted/N egate d — Indica tes the l ogic l evel o f data being

shifted out of the development port shift register.

Timing Comments Transitions are relative to CLKOUT in self-clocked mode

and relative to DSCK in clocked mode. Refer to the

RCPU

Reference Manual

(RCPURM/AD) for more information.

2.5. 4.2 Developme nt Po rt Serial Dat a In (DS DI )

Input only

Module: Development support

State Meaning Asser ted/N egate d — Indica tes the l ogic l evel o f data being

shifted into the development port shift register.

Reset Operation During reset, this pin functions as a reset configuration

mode pin. If the pin is pulled high while the MCU asserts

RESETOUT, the data bus pins are used to configure the

system whe n the reset sta te is exited. If the pin is low at the

positive edge of RESETOUT, then the system is configured

by the internal default mode. Refer to 5.8.3 Configuration

During Reset for more information on reset operation.

Timing Comments Transitions are relative to CLKOUT in self-clocked mode

and relative to DSCK in clocked mode. Refer to the

RCPU

Reference Manual

(RCPURM/AD) for more information.

2.5.4.3 Development Port Serial Clock Input (DSCK)

Input only

Module: Development support

State Meaning Asserted/Negated — Provides a clock signal for shifting

data into or out of development serial port.

Reset Operation During reset, this pin functions as a debug mode enable

pin. If the pin is pulled high while the MCU asserts RE-

SETOUT, debug mode is enabled when the reset state is

exited. For normal operation, this pin should be pulled to

ground through a resistor. Refer to 5.8.3 Configuration Dur-

ing Reset for more information.

Timing Comments Refer to the

RCPU Reference Manual

(RCPURM/AD) for

detailed timing information.

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-17

2.5.4.4 Instruction Fetch Visibility Signals (VF[0:2])

Output only

Module: Development support

State Meaning Asser ted /N eg ate d — De no te th e l ast fe tche d i nstruction or

the number of instructions that were flushed from the in-

struction queue. Refer to the

RCPU Reference Manual

(RCPURM/AD) for details.

Timing Comments Assertion/Negation — Transitions may occur every clock

cycle. This signal is not synchronous with bus cycles. Refer

to the

RCPU Reference Manual

(RCPURM/AD) for more

information on these signals.

2.5.4.5 Instruction Flush Count (VFLS[0:1])

Output only

Module: Development support

State Meaning Asserted/Negated — Denote the number of instructions

that are flushed from the history buffer during the current

clock cycle. These signals also provide the freeze indica-

tion. Refer to th e

RCPU Reference Manual

(RCPURM/AD)

for details.

Timing Comments Assertion/Negation — Transitions may occur every clock

cycle. This signal is not synchronous with bus cycles. Refer

to the

RCPU Reference Manual

(RCPURM/AD) for more

information on these signals.

2.5.4.6 Watchpoints (WP[0:5])

Output only

Module: Development support

State Meaning Assert ed — Indi cate tha t a wat chpo int e ven t has occ urred

on the I-bus (WP[0:3]) or L-bus (WP[4:5]).

Negated — Indicate that no watchpoint event has occurred.

Timing Comments Assertion/Negation — Transitions may occur every clock

cycle. This signal is not synchronous with bus cycles. Refer

to the

RCPU Reference Manual

(RCPURM/AD) for more

information on these signals.

2.5.5 Chip-Select Signals

2.5.5.1 Chip Select for System Boot Memory (CSBOOT)

Input only

Module: Chip selects

MOTOROLA SIGNAL DESCRIPTIONS MPC509

2-18 Rev. 15 June 98 USER’S MANUAL

State Meaning Asserted — Indicates the boot memory device is being se-

lected. In systems that have no external boot device, this

pin can be configured as a write enable or output enable of

an external memory device. At power up, this pin defaults

as a chip enable of the boot device.

Negated — Indicates the boot device is not b eing selected .

Timing Comments Assertion/Negation — This is an address phase signal

when used as chip enable of the boot device, or a data

phase signal when used a s output e nable or write en able of

an external memory device. When this signal is a chip en-

able, assertion may be delayed from the assertion of TS.

2.5.5.2 Chip Selects for External Memory (CS[0:11])

Output only

Module: Chip selects

State Meaning Asserted — Ind icates th at the memory region for which the

chip select is programmed is being accessed. CS[1:5] can

be programmed as chip enables, output enables, or write

enables. CS0 and CS[ 6:1 1] can be programmed as output

enables or write enables.

Negated — Indicates that the memory region for which the

chip select is programmed is not being accessed.

Timing Comments Assertion/Negation — These are address phase signals

when used as chip enables (CS[1:5] only), or data phase

signals when used as output enables or write enables.

When these signals are chip enables, assertion may be de-

layed from the assertio n of TS.

2.5.6 Clock Signals

2.5.6.1 Clock Output (CLKOUT)

Output only

Module: Clocks

State Meaning Asserted/Negated — Provides a clock which runs continu-

ously. All signals driven on the E-bus must be synchronized

to the rising edge of this clock.

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-19

2.5.6.2 Engineering Clock Output (ECROUT)

Output only

Module: Clocks

State Meaning Asserted/Negated — Provides a buffered clock reference

output with a frequency equal to the crystal oscillator fre-

quency, taken from the PLL feedback signal.

2.5.6.3 Crystal Oscillator Connections (EXTAL, XTAL)

Input, Output

Module: EBI

State Meaning Connections for the external crystal to the internal oscillator

circuit. An external oscillator should serve as input to the

EXTAL pin, when used.

2.5.6.4 External Filter Capacitor Pins (XFCP, XFCN)

Input only

Module: EBI

State Meaning Used to add an external capacitor to the filter circuit of the

phase-lock ed loop.

2.5.6.5 Clock Mode (MO DCLK)

Input only

Module: EBI

Reset Operation During reset, this sign al and VDDSN select the sou rce of the

system clock. Refer to 5.8.3 Config uration Duri ng Reset for

details.

2.5.6.6 Phase-Locked Loop Lock Signal (PLLL)

Output only

Module: Clocks

State Meaning Asserted — Indicate s that th e phase -locked loop is locked.

Negated — Indicates that the phase-locked loop is not

locked.

2.5.6.7 Power-Down Wake-Up (PDWU)

Output only

Module: EBI

State Meaning Asser ted — C an be use d as p ow er- do wn wake up to exter-

nal power-on reset circuit, or assertion can signal other

events depending on system requirements. PDWU is as-

serted when bit 0 of the decrementer register changes from

zero to one and can also be ass erted by sof twar e. See the

MOTOROLA SIGNAL DESCRIPTIONS MPC509

2-20 Rev. 15 June 98 USER’S MANUAL

RCPU Reference Manual

(RCPURM/AD) for details on

decrementer exceptions.

Negated — (By software) indicates the event causing as-

sertion of PDWU is not or is no longer occurring.

Timing Comments Negati on — Do es n ot occu r un til at le ast on e dec re me nte r

clock following assertion.

2.5.7 Reset Signals

The RESET and RESETOUT signals are used while the part is being placed into or

coming out of reset. Refer to 5.8 Reset Operation for more details on these pins.

2.5.7.1 Reset (RESET)

Input only

Module : Re set

State Meaning Asserted — Indicates that devices on the bus must reset.

Negated — Indicates normal operation.

Timing Comments For ti ming information, refe r to 5.8 Reset Operation.

2.5.7.2 Reset Output (RESETOUT)

Output only

Module : Re set

State Meaning Asserted — (During reset) instructs all devices monitoring

this signal to reset all parts within themselves that can be

reset by software. Assertion indicates that the MCU is in re-

set.

Negated — Indicates normal operation.

Timing Comments For ti ming information, refe r to 5.8 Reset Operation.

2.5.8 SIU General-Purpose Input/Output Signals

Many o f the pi ns associa ted with the SIU can be us ed for more than one fun ction. Th e

prima ry fun cti on of the se pins is to p rov ide an exter nal bu s in terfa ce. When no t us ed

for their primary function, many of these pins can be used for digital I/O. Refer to 5.9

General-Purpose I/O for more information on these signals.

2.5.8.1 Ports A and B (PA[0:7], PB[0:7])

Output only

Module: Por ts

State Meaning Asserted/Negated — Indicates the logic level of the data

being transmitt ed. Port A and po rt B shar e a data register

(PORTA/PORTB) and pin assignment register (PAPAR/

PBPAR).

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-21

Timing Comments Assertion/Negation — Accesses to these ports require

three clock cycles, the same as for external accesses to

port replacement logic if a port replacement unit (PRU) is

used.

2.5.8.2 Ports I, J, K, and L (PI[0:7], PJ[0:7], PK[0:7], PL[2:7]

Input/Output

Module: Por ts

State Meaning Asserted/Negated — Indicates the logic level of the data

being transmitt ed. Por ts I , J, K, and L sh ar e a da ta r eg ister

(PORTI, PORTJ, PORTK, PORTL), data direction register

(DDRI, DDRJ, DDRK, DDRL), and pin assignment register

(PIPAR, PJPAR, PKPAR, PLPAR).

Timing Comments Assertion/Negation — Accesses to these ports require

three clock cycles, the same as for external accesses to

port replacement logic if a port replacement unit (PRU) is

used.

2.5.8.3 Po rt M (PM[3:7])

Input/Output

Module: EBI

State Meaning Asserted/Negated — Indicates the logic level of the data

being transmitte d.

Timing Comments Assertion/Negation — Accesses to port M require two clock

cycles.

2.5.9 Interrupts and Port Q Signals

The MPC509 contains seven external interrupt pins. These pins are grouped into a

general-purpose port (port Q). When not used as interrupt inputs, any of these pins

can be u sed for d igital in put or o utput. Refe r to SECTION 6 PERIPHERAL CONTROL

UNIT for more information on these pins.

2.5.9.1 Interrupt Requests (IRQ[0:6])

Input only

Module: EBI

State Meaning Asserted — Indicates an external interrupt is being request-

ed wi th a request l evel corre sponding to t he IRQ number of

the pin.

Negated — Indicates no external interrupt when the indicat-

ed level is being requested.

MOTOROLA SIGNAL DESCRIPTIONS MPC509

2-22 Rev. 15 June 98 USER’S MANUAL

2.5.9.2 Port Q (PQ[0:6])

Input/Output

Module: PCU

State Meaning Asserted/Negated — Indicates the logic level of the data

being transmitte d.

Timing Comments Assertion/Negation — Accesses to port Q require two clock

cycles.

2.5.10 JTAG Interface Signals

Refer to SECTION 9 IEEE 114 9.1-C OMPLIA NT INTER FACE for more information on

these pins.

2.5.10.1 Test Data Input (TDI)

Input only

Module: JTAG

State Meaning Asser ted /N eg ate d — R ep res en ts th e val ue of th e test dat a

input.

Timing Comments Sampled on the rising edge of TCK.

2.5.10.2 Test Data Output (TDO)

Output only

Module: JTAG

State Meaning Asser ted /N eg ate d — R ep res en ts th e val ue of th e test dat a

output.

Timing Comments Change s on the falling edge of TCK.

2.5.10.3 Test Mode Select (TMS)

Input only

Module: JTAG

State Meaning Asserted/Negated — Sequences the test controller’s state

machine.

Timing Comments Sampled on the rising edge of TCK.

2.5.10.4 Test Clock (TCK)

Input only

Module: JTAG

State Meaning Test clock input to synchronize the test logic.

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-23

2.5.10.5 Test Reset (TRST)

Input only

Module: JTAG

State Meaning Asserted — Signals TAP controller to reset itself.

Timing Comments Asynchronous.

MOTOROLA SIGNAL DESCRIPTIONS MPC509

2-24 Rev. 15 June 98 USER’S MANUAL

MPC509 CENTRAL PROCESSING UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 3-1

SECTION 3

CENTRAL PROCESSING UNIT

The PowerPC-based RISC processor (RCPU) used in the MPC509 integrates four

execution units: an integer unit (IU), a load/store unit (LSU), a branch processing unit

(BPU), and a floating-point unit (FPU). The use of simple instructions with rapid exe-

cution times yields high efficiency and throughput for MPC509-based systems.

Most integer instructions execute in one clock cycle. The FPU includes single- and

double-precision multiply-add instructions. Instructions can complete out of order for

increased performance; however, the processor makes execution appear sequential.

This section provides an overview of the RCPU. For a more detailed description, see

the

RCPU Re fer ence Manual

(RCPURM/AD).

3.1 RC P U Fe at ure s

• High-performance microprocessor

— Single clock-cycle execution for many instructions

• Four independent execution units and two register files

— Independent LSU for load and store operations

— BPU featuring static branch prediction

— A 32-bit IU

— Fully IEEE 754-compliant FPU for both single- and double-precision opera-

tions

— Thirty-two general-purpose registers (GPRs) for integer operands

— Thirty-two floating-point registers (FPRs) for single- or double-precision oper-

ands

• Facilities for enhanced system performance

— Programmable big- and little- endian byte order ing

— Atomic memory references

• In-system testability and debugging features through boundary-scan capability

• High instruction and data throughput

— Condition register (CR) look-ahead op erations performed by BPU

— Branch-folding capability during execution (zero-cycle branch execution time)

— Programmable static branch prediction on unresolved conditional branches

— A prefetch queue that can hold up to four instructions, providing look-ahead

capability

— Interlocked pipelines with feed-forwarding that control data dependencies in

hardware

— 4-Kbyte instruction cache: two-way set-associative, LRU replacement algo-

rithm

MOTOROLA CENTRAL PROCESSING UNIT MPC509

3-2 Rev. 15 June 98 USER’S MANUAL

3.2 RC P U Bl ock Diagram

Figure 3-1 is a block diagram of the RCPU.

Figure 3-1 RCPU Block Diagram

WR ITE BA C K BUS

SOURCE BUSES

CONTROL BUS

BRANCH

I-ADDR

I-DATA

L-ADDR

L-DATA

FPR

(32 X 64)

LOAD/STORE

FLOATING

DATA

FPR

HISTORY

LOAD/STORE

INTE GER DA T A

LOAD/STORE

ADDRESS

IMUL/

IDIV ALU/GPR

HISTORY

GPR

(32 X 32)

CONTROL

REGS

(4 SLOTS/CLOCK)

INSTRUCTION

PREFETCH

PROCESSOR

NEXT ADDRESS

GENERATION

INSTRUCTION SEQUENCER

FPU

RCPU

BFU

2 SLOTS/CLOCK

QUEUE

UNIT

MPC509 CENTRAL PROCESSING UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 3-3

3.3 Instruction Sequencer

The instruction sequencer (see Figure 3-2) provides centralized control over data flow

between execution units and register files. The sequencer implements the basic

instruction pipeline, fetches instructions from the memory system, issues them to

available execution units, and maintains a state history so it can back the machine up

in the event of an exception .

The sequencer fetches the instructions from the instruction cache into the instruction

pre-fetch queue. The BPU extracts branch instructions from the pre-fetch queue and

uses st atic branch prediction on unre solved condit ional branches to allow the instruc -

tion unit to fetch instructions from a predicted target instruction stream while a

conditional branch is evaluated. The BPU folds out branch instructions for uncondi-

tional branches or conditional branches unaffected by instructions in the execution

stage.

Instructions issued beyond a predicted branch do not complete execution until the

branch is resolved, preserving the programming model of sequential execution. If

branch prediction is incorrect, the instruction unit flushes all predicted path instruc-

tions, and instructions are issued from the correct path.

MOTOROLA CENTRAL PROCESSING UNIT MPC509

3-4 Rev. 15 June 98 USER’S MANUAL

Figure 3-2 Sequencer Data Path

3.4 Independent Execution Units

The PowerPC architecture supports independent floating-point, integer, load-store,

and branch processing execution units, making it possible to implement advanced fea-

tures such as look-ahead operations. For example, since branch instructions do not

depend on GPRs or FPRs, branches can often be resolved early, eliminating stalls

caused by taken branches.

Table 3-1 summarizes the RCPU execution units.

INSTRUCTION ADDRESS GENERATOR

CC UNIT

READ/WRITE BUSES

BRANCH

INSTRUCTION BUFFER

INSTRUCTION

PREFETCH

INSTRUCTION MEMORY SYSTEM

EXECUTION UNITS AND REGISTERS FILES

CONDITION

EVALUATION

MPC509 CENTRAL PROCESSING UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 3-5

The following sections describe the execution units in greater detail.

3.4.1 Branch Processing Unit (BPU)

The BPU, located within the instruction sequencer, performs condition register look-

ahead operations on conditional branches. The BPU looks through the instruction

queue for a conditional branch instruction and attempts to resolve it early, achieving

the effect of a zero-cycle branch in many cases.

The BPU uses a bit in the instruction encoding to predict the direction of the conditional

branch . Therefore , when an unresol ved cond itiona l branch instructio n is enco untered,

the pr ocessor pref etches instr ucti on s fr om t he pr ed icted tar g et st re am u nti l th e co ndi-

tional branch is resolved.

The BPU contains an adder to compute branch target addresses and three special-

purpose, user-accessible registers: the link register (LR), the count register (CTR),

and th e con diti on re giste r (CR). The BP U calc ulates th e retu rn po inter f or su brou tine

calls and saves it into the LR. The LR also contains the branch target address for the

branch conditional to link register (bclr

) instruction. The CTR contains the branch tar-

get address for the branch conditional to count register (bcctr

) instruction. The

contents of the LR and CTR can be copied to or from any GPR. Because the BPU uses

dedicated registers rather than general-purpose or floating-point registers, execution

of branch instructions is independent from execution of integer and floating-point

instructions.

3.4.2 Integer Unit (IU)

The IU executes all integer processor instructions, except the integer storage access

instructions, which are implemented by the load/store unit. The IU contains the follow-

ing subunits:

• The IMUL- IDIV unit in cludes the impl ementation o f the integer multiply an d divide

instructions.

Table 3-1 RCPU Execution Units

Unit Description

Branch processing

unit (BPU) Includes the implementation of all branch instructions.

Load/store unit (LSU) Includes implementation of all load and store instructions, whether defined as part

of the integer processor or the floating-point processor.

Integer unit (IU )

Include s implem entation of al l integer ins tructio ns except load -store instr uction s.

This mo dule i nclud es the G PRs (inclu ding GP R histo ry a nd sc oreboa rd) and th e

following subunits:

The IMUL-IDIV includes the implementation of the integer multiply and divide in-

structions.

The ALU-BFU includes implementation of all integer logic, add and subtract in-

structions, and bit field instructions.

Floating-point unit

(FPU)

Includes the FPRs (including FPR history and scoreboard) and the implementa-

tion of all floating-point instructions except load and store floating-point instruc-

tions.

MOTOROLA CENTRAL PROCESSING UNIT MPC509

3-6 Rev. 15 June 98 USER’S MANUAL

• The ALU-BFU unit includes the implementation of all integer logic, add and sub-

tract, and bit field instructions.

The IU also includes the integer exception register (XER) and the general-purpose

IMUL-IDIV and ALU-BFU are implemented as separate execution units. The ALU-BFU

unit can execute on e instruct ion pe r clock cycle. IMUL-IDIV instructio ns requ ire multi-

ple clock cycles to execute. IMUL-IDIV is pipelined for multiply instructions, so that

consecutive multiply instructions can be issued on consecutive clock cycles. Divide

instructions are not pipelined; an integer divide instruction preceded or followed by an

integer divide or multiply instruction results in a stall in the processor pipeline. Note

that since IMUL-IDIV and ALU-BFU are implemented as separate execution units, an

integer divide instruction preceded or followed by an ALU-BFU instruction does not

cause a delay in the pipeline.

3.4.3 Load/Store Unit (LSU)

The load-store unit handles all data transfer between the general-purpose and float-

ing-point register files and the internal load/store bus (L-bus). The load/store unit is

implemented as an independent execution unit so that stalls in the memory pipeline

do not cause the master instruction pipeline to stall (unless there is a data depen-

dency). The unit is fully pipelined so that memory instructions of any size may be

issued on back-to-back cycles.

There is a 32-bit wide data path between the load/store unit and the general-purpose

point reg i ster fi le . Si ng le - wo r d acce sses to th e i nte rn al on- ch ip data RA M req ui r e on e

clock, resulting in two clocks latency. Double-word accesses require two clocks,

resulting in three clocks latency. S ince the L-bus is 32 bits wide, double-word transfers

requir e tw o bus accesses. The l oad/ store unit p erfor ms ze ro-fil l fo r byte and half- word

transfers and sign extension for half-word transfers.

Addresses are formed by adding the source one register operand specified by the

instruc tion (or ze ro) to eith er a source two reg ister oper and or t o a 16-bit, immediate

value embedded in the instruction.

3.4.4 Floating-Point Unit (FPU)

The FPU c ontai ns a d oubl e-precisi on mul tiply arra y, the f loat ing- point st atus and co n-

trol register (FPSCR), and the FPRs. The multiply-add array allows the MPC509 to

efficiently implement floating-point operations such as multiply, multiply-add, and

divide.

The MPC509 depends on a software envelope to fully implement the IEEE floating-

point specification. Overflows, underflows, NaNs, and denormalized numbers cause

floating-point assist exceptions that invoke a software routine to deliver (with hardware

assistance) the correct IEEE result.

To accelerate time-critical operations and make them more deterministic, the MPC509

provides a mode of operation that avoids invoking the software envelope and attempts

MPC509 CENTRAL PROCESSING UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 3-7

to deliver results in hardware that are adequate for most applications, if not in strict

conformance with IEEE standards. In this mode, denormalized numbers, NaNs, and

IEEE invalid operations are treated as legitimate, returning default results rather than

causing floating-point assist exceptions.

3.5 Levels of the Po werPC Architecture

The PowerPC architecture consists of three layers. Adherence to the PowerPC archi-

tectur e can be measured in terms of which of t he followin g levels o f the ar chitecture

are implemented:

• PowerPC user instruction set architecture (UISA) — Defines the base user-level

instruction set, user-level registers, data types, floating-point exception model,

memory models for a uniprocessor environment, and programming model for a

uniprocessor environment.

• PowerPC virtual environment architecture (VEA) — Describes the memory model

for a multiprocessor environment, defines cache control instructions, and de-

scribes other aspects of virtual environments. Implementations that conform to

the VEA also adhere to the UISA, but may not necessarily adhere to the OEA.

• PowerPC operating environment architecture (OEA) — Defines the memory man-

agement model, supervisor-level registers, synchronization requirements, and

the exception model. Implementations that conform to the OEA also adhere to the

UISA and the VEA.

3.6 RCPU Programming Model

The PowerPC architecture defines register-to-register operations for most computa-

tional instructions. Source operands for these instructions are accessed from the

registers or are provided as immediate values embedded in the instruction opcode.

The three-register instruction format allows specification of a target register distinct

from the two source operands. Load and store instructions transfer data between

memory and on-chip registers.

PowerPC p ro cesso r s ha ve tw o l evels o f p riv il eg e: supe r viso r mo de of oper atio n ( typ i-

cally used by the operating environment) and user mode of operation (used by the

applica tion so ftware ). The pr ogram ming mod els in corp orate 32 GP Rs, 32 FPRs, spe-

cial-purpose registers (SPRs), and several miscellaneous registers.

Supervisor-level access is provided through the processor’s exception mechanism.

That i s, when an except ion is ta ken (eith er due to an er ror or proble m that needs to be

serviced, or deliberately through the use of a trap instruction), the processor begins

operating in supervisor mode. The level of access is indicated by the privilege-level

(PR) bit in the machine state register (MSR).

Figure 3-3 shows the user-level and supervisor-level RCPU programming models and

also illustra tes the three levels of the PowerPC archi tecture. The nu mbers to the left

of the S PRs indica te the decimal n umber tha t is used in the synta x of the i nstruct ion

operands to acc ess the register.

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Note that registers such as the general-purpose registers (GPRs) and floating-point

registers (FPRs) are accessed through operands that are part of the instructions.

Access to registers can be explicit (that is, through the use of specific instructions for

that purpose such as move to special-purpose register (mtspr) and move from spe-

cial-purpose register (mfspr) instructions) or implicitly as the part o f the execution of

an instruction. Some registers are accessed both e x plicitly and implici tly.

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Figure 3-3 RCPU Programming Model

Supervisor-Level SPRs

SPR18 DAE/Source Instruction Service Register (DSISR)

SPR19 Data Address Registe r (DAR)

SPR22 Decrementer Register (DEC)

SPR26 Save and Restore Register 0 (SRR0)

SPR27 Save and Restore Register 1 (SRR1)

SPR80 External Interrupt Enable (EIE) *

SPR81 External Interrupt Disable (EID) *

SPR82 Non-Recoverable Interrupt (NRI) *

SPR272 SPR General 0 (SPRG0)

SPR273 SPR General 1 (SPRG1)

SPR274 SPR General 2 (SPRG2)

SPR275 SPR General 3 (SPRG3)

SPR284 Time Base Lower – Write (TBL)

SPR285 Time Base Upper – Write (TBU)

SPR287 Proces sor Ver sion Register (P VR)

SPR560 I-Cache Control and Status Register (ICCST) *

SPR561 I-Cache Address Register (ICADR) *

SPR562 I-Cache Data Port (ICDAT) *

SPR1022 Floating-Point Exception Cause Register (FPECR) *

Development Support SPRs

SPR144 Comparator A Value Register (CMPA) *

SPR145 Comparator B Value Register (CMPB) *

SPR146 Comparator C Value Register (CMPC) *

SPR147 Comparator D Value Register (CMPD) *

SPR148 Exception Cause Register (ECR) *

SPR149 Debug Enable Register (DER) *

SPR150 Breakp oint Counter A Value and Control (COUNTA) *

SPR151 Breakp oint Counter B Value and Control (COUNTB) *

SPR152 Comparator E Value Register (CMPE) *

SPR153 Comparator F Value Register (CMPF) *

SPR154 Comparator G Value Register (CMPG) *

SPR155 Comparator H Value Register (CMPH) *

SPR156 L-Bus Support Comparators Control (LCTRL1) *

SPR157 L-Bus Support Comparators Control (LCTRL2) *

SPR158 I-Bus Support Control Register (ICTRL) *

SPR159 Breakpoint Address Register (BAR) *

SPR630 Development Port Data Register (DPDR) *

GPR0

GPR1

GPR31

031

USER MODEL UISA

063

FPR0

FPR1

FPR31

031

Floating P oint

Status and

Control

031

FPSCR

031

Condition

User-Level SPRs

SPR1 Integer Exception Register (XER)

SPR8 Link Register (LR)

SPR9 Count Register (CTR)

Machine State

MSR

031

SUPERVISOR MODEL OEA

USER MODEL VEA

Time Ba se Fa ci lit y

(for Reading)

031

RMCU CPU REG M

* Specific to the RCPU implementation of the PowerPC Architecture

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Where not otherwise noted, reserved fields in registers are ignored when written to

and r eturn zero when read . An excepti on t o this rule is X ER[16:2 3]. These bits a re set

to the value written to them and return that value when read.

3.7 PowerPC UISA Register Set

The PowerPC UISA registers can be accessed by either user- or supervisor-level

instr uctions. The genera l-purpo se regist ers and f loating- point re gisters are acces sed

through inst ruction operands.

3.7.1 General-Purpose Registers (GPRs)

Integer data is manipulated in the integer unit’s thirty-two 32-bit GPRs, shown below.

These registers are accessed as source and destination registers through operands

in the instruction syntax.

3.7.2 Floating-Point Registers (FPRs)

The PowerPC architecture provides thirty-two 64-bit FPRs. These registers are

accessed as source and destination registers through operands in floating-point

instructions. Each FPR supports the double-precision, floating-point format. Every

instruction that interprets the contents of an FPR as a floating-point value uses the

double-precision floating-point format for this interpretation. That is, all floating-point

numbers are stored in double-precision format.

All flo ating-poin t a rith m eti c i nst ru cti on s op er ate on da ta locate d i n FPRs an d, wi th th e

exception of the compare instructions (whi ch update the CR), place the resul t into an

FPR. Information about the status of floating-point operations is placed into the float-

ing-point status and control register (FPSCR) and in some cases, into the CR, after the

completion of the operation’s writeback stage. For information on how the CR is

affected by floating-point operations, see 3.7.4 Condition Register (CR).

GPRs — G en eral - Purp ose R egi ste r s

031

GPR0

GPR1

. . .

GPR31

RESET: UNCHANGED

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3.7.3 Floating-Point Status and Control Register (FPSCR)

The FPSCR controls the handling of floating-point exceptions and records status

resulting from the floating-point operations. FPSCR[0:23] are status bits, while

FPSCR [24:31] are control bits.

FPSCR[0:12] and FPSCR[21:23] are floating-point exception condition bits. These bits

are sticky, except for the floating-point enabled exception summary (FEX) and float-

ing-point invalid operation exception summary (VX). Once set, sticky bits remain set

until they are cleared by an mcrfs, mtfs fi, mtfsf, or mtfsb0 instruction.

Table 3-2 summarizes which bits in the FPSCR are sticky status bits, which are nor-

mal status bits, and which are control bits.

FEX and VX are the lo gical ORs of other FPSCR bits. Th erefore these t wo bits are no t

listed among the FPSCR bits directly affected by the vari ous instruction s.

A listing of FPSCR b it setting s is shown in Table 3-3.

FPRs — Floating-Point Registers

063

FPR0

FPR1

. . .

FPR31

RESET: UNCHANGED

Table 3-2 FPSCR Bit Categories

Bits Type

[0], [3:12], [21:23] Status, sticky

[1:2], [13:20] Status, not sticky

[24:31] Control

FPSCR — Floating-Point Status and Control Register

012345678910 11 12 13 14 15

FX FEX VX OX UX ZX XX VXS-

NAN VXISI VXIDI VXZD

ZVXIMZ VXVC FR FI FPRF

RESET: UNCHANGED

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

FPRF[1:4] 0VX-

SOFT VX-

SQRT VXCVI VE OE UE ZE XE NI RN

RESET: UNCHANGED

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Table 3-3 FPSCR Bit Settings

Bit(s) Name Description

0FX

Floating-point exception summary. Every floating-point instruction implicitly sets FPSCR[FX] if

that instruc tion causes any of the floating -point except ion bits in the FPSC R to change from z ero

to one. The mcrfs instruction implicitly clears FPSCR[FX] if the FPSCR field containing

FPSCR[FX] is copied. The mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions can set or clear

FPSCR[FX] explicitly. This is a sticky bit.

1FEX

Floating-p oint enabl ed exceptio n summary. This bit signal s the occurre nce of any of the enabled

exceptio n con dition s. It i s the logic al O R of all the f loa ting-po int ex cepti on bit s mask ed w ith the ir

respective enable bits. The mcrfs in struction implicitl y clears F PSCR[FEX] if the result of th e log-

ic al OR described above b ecomes zero. The mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions

cannot set or clear FPSCR[FEX] explicitly. This is not a sticky bit.

2VX

Floating-point invalid operation exception summary. This bit signals the occurrence of any invalid

operation exception. It is the logical OR of all of the invalid operation exceptions. The mcrfs

instruction implicitly clears FPSCR[VX] if the result of the logical OR described above becomes

zero. The mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructi ons c annot s et or c lear FPSCR[VX] expli c-

itly. This is not a sticky bit.

3 OX Floating-point overflow exception. This is a sticky bit.

4 UX Floating-point underflow exception. This is a sticky bit.

5 ZX Floating-point zero divide exception. This is a sticky bit.

6 XX Floating-point inexact exception. This is a sticky bit.

7 VXSNAN Floating-point invalid operation exception for SNaN. This is a sticky bit.

8 VXISI Floating-point invalid operation exception for ×-×. This is a sticky bit.

9 VXIDI Floating-point invalid operation exception for ×/×. This is a sticky bit.

10 VXZDZ Floating-point invalid operation exception for 0/0. This is a sticky bit.

11 VXIMZ Floating-point invalid operation exception for ×*0. This is a sticky bit.

12 VXVC Floating-point invalid operation exception for invalid compare. This is a sticky bit.

13 FR Floating-point fraction rounded. The last floating-point instruction that potentially rounded the

intermediate result incremented the fraction. This bit is not sticky.

14 FI Floating-point fraction inexact. The last floating-point instruction that potentially rounded the

intermediate resu lt pro duc ed an inexac t frac tio n or a d isa bl ed ex ponent ov erfl ow . Th is b it is not

sticky.

15:19 FPRF

Floating-point res ult fl ags . Thi s fi eld is based on the v alue place d in to the target regist er ev en if

that value is undefined. Refer to Table 3-4 for specific bit settings.

15 Floating-point result class descriptor (C). Floating-point instructions other than the

compare i nstructio ns may se t this b it with the FPCC b its, to in dicate t he class of the

result.

16:19 Floating-point condition code (FPCC). Floating-point compare instructions always

set one of the FPCC bits to one and the other three FPCC bits to zero. Other

floating-po int inst ructions m ay set the F PCC bits with the C bit, to indi cate the c lass

of the result . Note that in this case the hi gh-orde r three bits of the FPCC retain th eir

relational significanc e indicating that the valu e is less than, grea ter than, or equal to

zero.

16 Floating-point less than or negative (FL or <)

17 Floating-point greater than or positive (FG or >)

18 Floating-point equal or zero (FE or =)

19 Floating-point unordered or NaN (FU or ?)

20 — Reserved

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Table 3-4 illustrates the floating-point result flags that correspond to FPSCR[15:19].

3.7.4 Condition Register (CR)

The condi tion regist er (CR ) is a 32 -b i t r egister tha t refl ect s the re sul t o f cer ta i n op era-

tions and provides a mechanism for testing and branching. The bits in the CR are

grou ped into eight 4-bit fields, CR0 to CR7.

21 VXSOFT

Floating-point invalid operation exception for software request. This bit can be altered only by the

mcrfs, mtfsfi, mtfsf, mtfsb0, or mtfsb1 instructions. The purpose of VXSOFT is to allow soft-

ware to cause an invalid operation condition for a condition that is not necessarily associated with

the execution of a floating-point instruction. For example, it might be set by a program that com-

putes a square root if the source operand is negative. This is a sticky bit.

22 VXSQRT Floating-point invalid operation exception for invalid square root. This is a sticky bit. This guar-

antees that software can simulate fsqrt and frsqrte, and to provide a consistent interface to

handle exceptions caused by square-root operations.

23 VXCVI Floating-point invalid operation exception for invalid integer convert. This is a sticky bit.

24 VE Floating-point invalid operation exception enable.

25 OE Floating-point overflow exception enable.

26 UE Floating-point underflow exception enable. This bit should not be used to determine whether

denormalization should be performed on floating-point stores.

27 ZE Floating-point zero divide exception enable.

28 XE Floating-point inexact exception enable.

29 NI Non-IEEE mode bit.

30:31 RN

Floating-point rounding control.

00 = Round to nearest

01 = Round toward zero

10 = Round toward +infinity

11 = Round toward –infinity

Table 3-4 Floating-Point Result Flags in FPSCR

Result Flags

(Bits 15:19)

C<>=?

Result Value Class

10001 Quiet NaN

01001 – Infinity

01000 – Normali ze d numb er

11000 – Denormalized number

10010 – Zero

00010 + Zero

10100 + Denormalized number

00100 + Norm ali ze d numb er

00101 + Infinity

Table 3-3 FPSCR Bit Settings (Continued)

Bit(s) Name Description

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The CR fields can be set in the f ollowi ng ways:

• Spe cified fi elds of the CR can be set by a mo ve instructio n (mtcrf) to the CR from

a GPR.

• Specified fields of the CR can be moved from one CR

field to another with the

mcrf instruction.

• A specified field of the CR can be set by a move instruction (mcrfs) to the CR

from the FPSCR.

• A specified field of the CR can be set by a move instruction (mcrxr) to the CR

from the XER.

• Condition register logical instructions can be used to perform logical operations

on specified bits in the condition register.

• CR0 can be the implicit result of an integer operation.

• CR1 can be the implicit result of a floating-poin t operation.

• A specified CR field can be the explicit result of either an integer or floating-point

compare instruction.

Instructions are provided to test individual CR bits.

3.7.4.1 Condition Register CR0 Field Definition

In most integer instructions, when the CR is set to reflect the result of the operation

(that is, when Rc = 1), and for addic., andi., and andis., the first three bits of CR0 are

set by an algebraic comparison of the result to zero; the fourth bit of CR0 is copied from

XER[SO]. For integer instructions, CR[0:3] are set to reflect the result as a signed

quantity. The result as an unsigned quantity or a bit string can be deduced from the

EQ bit.

The CR0 bits are interpreted as shown in Table 3-5. If any portion of the result (the 32-

bit value placed into the destination register) is undefined, the value placed in the first

three bits of CR0 is undefined.

3.7.4.2 Condition Register CR1 Field Definition

In al l floa ting -poi nt instr uctions whe n the CR i s set t o re flect the resu lt o f the oper ation

(that is , w hen Rc = 1), the CR1 fi e ld ( bit s 4 to 7 o f t he CR) i s co pi ed fr om FP SCR [0:3 ]

CR — Condition Registe r

0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31

CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7

RESET: UNCHANGED

Table 3-5 Bit Settings for CR0 Field of CR

CR0 Bit Description

0 Negative (LT) — This bit is set when the result is negative.

1 Positive (GT) — This bit is set when the result is positive (and not zero).

2 Zero (EQ) — This bit is set when the result is zero.

3 Summary overfl ow (SO) — Thi s is a copy of the fina l state of XER[SO ] at the comple tion of the instruc tion.

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to ind icate the flo ating-point e xception stat us. For more i nformation a bout the FPSC R,

see 3.7.3 Flo ating-Poin t Stat us and Control Re gister (FPSC R). The b it settings fo r the

CR1 field are shown in Table 3-6.

3.7. 4.3 Conditio n Re gist e r CR

Field — Compare Instruction

When a specified CR field is s et by a comp are instruct ion, the b its of the sp ecified fie ld

are interpreted as shown in Table 3-7. A condition re gister f ield can a lso be a ccessed

by the mfcr, mcrf, and mtcrf instructions.

3.7.5 Integer Exception Register (XER)

The integer exception register (XER) is a user-level, 32-bit register.

Table 3-6 Bit Settings for CR1 Field of CR

CR1 Bit Description

0Floating-point exception (FX) — This is a copy of the final state of FPSCR[FX] at the completion of the in-

struction.

1Floating -point enable d exception (FEX) — This is a c opy of the final state of FPSCR[FEX] at the completion

of the instruction.

2Floating -po int i nva li d exc ep tio n (VX) — This is a copy of the fina l sta te of FPSCR[VX] at t he com ple tio n of

the instruction.

3Floating-point overflow exception (OX) — This is a copy of the final state of FPSCR[OX] at the completion

of the instruction.

Table 3-7 CR

Field Bit Settings for Compare Instructions

Bit1

NOTES:

1. Here, the bit indicates the bit number in any one of the four-bit subfields, CR0–CR7

Description

Less than, floating-point less than (LT, FL).

For integer compare instructions, (rA) < SIMM, UIMM, or (rB) (algebraic com parison) or (rA) SIMM, UIMM,

or (rB) (logical comparis on ).

For floating-point compare instructions, (frA) < (frB).

Greater than, floating-point greater than (GT, FG).

For integer compare instructions, (rA) > SIMM, UIMM, or (rB) (algebraic com parison) or (rA) SIMM, UIMM,

or (rB) (logical comparis on ).

For floating-point compare instructions, (frA) > (frB).

2Equal, floating-point equal (EQ, FE).

For integer compare instructions, (rA) = SIMM, UIMM, or (rB).

For floating-point compare instructions, (frA) = (frB).

Summary overflow, floating-point unordered (SO, FU).

For integer compare instructions, this is a copy of the final state of XER[SO] at the completion of the in-

struction.

For floating-point compare instructions, one or both of (frA) and (frB) is not a number (NaN).

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The bit definitions for XER, shown in Table 3-8, are based on the operation of an

instru ction consi dered as a whole, not on interme diate resu lts. Fo r exampl e, the re sult

of th e su bt ra ct fr om c arr yi ng ( subfc

) instruction is specified as the sum of three val-

ues. This instruction sets bits in the XER based on the entire operation, not on an

interm edi a te sum .

In most cases, reserved fields in registers are ignored when written to and return zero

when read. However, XER[16:23] are set to the value written to them and return that

value when read.

3.7.6 Link Register (LR)

The 32-b it link registe r supplies th e branch tar get address for the branch cond itional

to link register (bclr

) instruction, and can be used to hold the logical address of the

instruction that follows a b ranch and link instruction.

Note tha t although the tw o least-signifi cant bits can accept any values written to them,

they are ignored when the LR is used as an address.

Both conditional and unconditional branch instructions include the option of placing the

effective address of the instruction following the branch instruction in the LR. This is

done regardless of whether the branch is taken.

XER — Integer Exception Register SPR 1

0 1 2 3 24 25 26 27 28 29 30 31

SO OV CA 0000000000000000000 BYTES

RESET: UNCHANGED

Table 3-8 Integer Exception Register Bit Definitions

Bit(s) Name Description

0SO

Summary Overflow (SO) — The summary overflow bit is set whenever an instruction sets the

overflow b it ( OV) to ind icate overflo w and re mains set until softw are clears it. It is no t alte red by

compare instructions or other instructions that cannot overflow.

1OV

Overflow (O V) — The over flow bit is set to ind icate that an overflo w has occurre d during execu -

tion of an instruction. Integer and subtract instructions having OE = 1 set OV if the carry out of

bit 0 is n ot equal to the carry out o f bit 1, and clear it o therwise . The OV bit is not altere d by com-

pare instructions or other instructions that cannot overflow.

2CA

Carry (CA) — In general, the carry bit is set to indicate that a carry out of bit 0 occurred during

execution of an instruction. Add carrying, subtract from carrying, add extended, and subtract

from extended instructions set CA to one if there is a carry out of bit 0, and clear it otherwise.

The CA bit is not alte red by co mpare i nstruc tions o r othe r instruct ions t hat cannot c arry, ex cept

that shift right algebraic instructions set the CA bit t o indicate whether any ‘1’ bits have been

shifted out of a negative quantity.

3:24 — Reserved

25:31 BYTES This field specifies the number of bytes to be transferred by a load string word indexed (lswx)

or store string word indexed (stswx) instruction.

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3.7.7 Count Register (CTR)

The count register (CTR) is a 32-bit register for holding a loop count that can be dec-

remented during execution of branch instructions that contain an appropriately coded

BO fiel d. If the value in CTR is zero be fore be ing decr emented , it is –1 afterw ard. The

count register provides the branch target address for the branch conditional to count

) instruction.

3.8 PowerPC VEA Register Set — Tim e Base

The PowerPC virtual environment architecture (VEA) defines registers in addition to

those in the UISA reg ister set . Th e P owerPC VEA registe r set can be a ccesse d b y all

software (regardless of privilege level).

The Pow erPC VEA includ es the time ba se facility (TB) , a 64-bit str ucture that conta ins

a 64-bit un si gn ed i nte ge r th at i s in cr em en ted peri od ica l ly. The fr eq uen cy at w hic h th e

counter is updated is implementation-dependent.

The TB consists of two 32-bit registers: time base upper (TBU) and time base lower

(TBL). In the context of the VEA, user-level applications are permitted read-only

access to the TB. The OEA defines supervisor-level access to the TB for writing values

to the TB. Different SPR encodings are provided for reading and writing the time base.

In 32-bit PowerPC implementations such as the RCPU, it is not possible to read the

entire 64-bit time base in a single instruction. The mftb simplified mnemonic copies

LR — Link Register SPR 8

031

Branch Address

RESET: UNCHANGED

CTR — Count Register SPR 9

031

Loop Count

RESET: UNCHANGED

TB — Time Base (Reading) TBR 268, 269

031 32 63

TBU TBL

RESET: UNCHANGED

Table 3-9 Time Base Field Definitions

Bits Name Description

0:31 TBU Time Base (Upper) — The high-order 32 bits of the time base

32:63 TBL Time Base (Lower) — The low-order 32 bits of the time base

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the low er half of the time base reg ister (TBL) to a GPR, an d the mftbu simplified mne-

monic copies the upper half of the time base (TBU) to a GPR.

3.9 PowerPC OEA Register Set

The PowerPC operating environment architecture (OEA) includes a number of SPRs

and other registers that are accessible only by supervisor-level instructions. Some

SPRs are RCPU- specific; some RCPU SPRs may no t be imple mented in other Pow -

erPC p r ocessors, or may not be implemen ted in the same way.

3.9.1 Machine State Register (MSR)

The machine state register is a 32-bit register that defines the state of the processor.

When an exception occurs, the current contents of the MSR are loaded into SRR1,

and the MSR is updated to reflect the exception-processing machine state. The MSR

can also be modified by the mtmsr, sc, and rfi instructions. It can be read by the

mfmsr instruction.

*Reset value of this bit depends on the value of the data bus reset configuration word.

Table 3-10 shows the bit definitions for the MSR.

MSR — Machine State Register

012345678910 11 12 13 14 15

RESERVED ILE

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

EE PR FP ME FE0 SE BE FE1 0IP RESERVED RI LE

RESET:

000U00000*000000

Table 3-10 Machine State Register Bit Settings

Bit(s) Name Description

0:14 — Reserved

15 ILE

Exception little endian mode. Whe n an exception occurs, this bit is copied into MSR[LE] to select

the endian mode for the context established by the exception.

0 = Processor runs in big endian mode during exception processing.

1 = Processor runs in little endian mode during exception processing.

16 EE

External int errup t enab le

0 = The processor delays recognition of external interrupts and decrementer exception condi-

tions.

1 = The processor is enabled to take an external interrupt or the decrementer exception.

Caution: Be sure the EE bit is cleare d before cha nging th e masks of any o n- or off-chip interrupt

sources or before negating any interrupt sources.

17 PR Pr ivilege level

0 = The processor can execute both user- and supervisor-level instructions.

1 = The processor can only execute user-level instructions.

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The floating-point exception mode bits are interpreted as shown in Table 3-11.

3.9.2 DAE/Source Instruction Service Register (DSISR)

The 32-bit DSISR identifies the cause of data access and alignment exceptions.

18 FP

Floating-point av ail abl e

0 = The p roc essor preven ts dis patch of flo ating-p oint in st ruction s, inclu ding fl oa ting-po int loa ds,

stores a nd mo ves. Floatin g-poin t en abled program exce ptions c an sti ll oc cur and the FPR s

can still be acc es se d.

1 = The proc essor can execute floatin g-point instructi ons, and can take floating-point ena bled ex-

ception type program exceptions.

19 ME Machine check enable

0 = Machine check exceptions are disabled.

1 = Machine check exceptions are enabled.

20 FE0 Floating-point exception mode 0 (See Table 3-11.)

21 SE

Single-step trace enable

0 = The processor executes instructions normally.

1 = The proces sor generat es a single-s tep trace ex ception upo n the succe ssful execut ion of the

next instru ction. When th is bit i s set, the proc esso r disp atches in stru ction s in st rict pro gram

order. Successful execution means the instruction caused no other exception. Single-step

tracing may not be present on all implementations.

22 BE Branch trace enable

0 = No trace exception occurs when a branch instruction is completed

1 = Tr ace except ion occurs w hen a branch instruc tion is completed

23 FE1 Floating-point exception mode 1 (See Table 3-11.)

24 — Reserved.

25 IP Exception prefix. The setting of this bit specifies the location of the exception vector table.

0 = Exception vector table starts at the physical address 0x0000 0000.

1 = Exception vector table starts at the physical address 0xFFF0 0000.

26:29 — Reserved

30 RI Recoverable exception (for machine check and non-maskable breakpoint exceptions)

0 = Machine state is not recoverable.

1 = Machine state is recoverable.

31 LE Little endian mode

0 = Processor operates in big-endian mode during normal processing.

1 = Processor operates in little-endian mode during normal processing.

Table 3-11 Floating-Point Exception Mode Bits

FE[0:1] Mode

00 Ignore exceptions mode — Floating-point exceptions do not cause the

floating-point assist error handler to be invoked.

01, 10, 11 Floating-point precise mode — The system floating-point assist error

handler is invoked precisely at the instruction that caused the enabled

exception.

Table 3-10 Machine State Register Bit Settings (Continued)

Bit(s) Name Description

MOTOROLA CENTRAL PROCESSING UNIT MPC509

3-20 Rev. 15 June 98 USER’S MANUAL

3.9.3 Data Address Register (DAR)

After a n align ment excepti on, the DAR is se t to the effective address of a load or stor e

element.

3.9.4 Time Base Facility (TB) — OEA

As described in 3.8 PowerPC VEA Register Set — Time Base, the time base (TB) pro-

vides a 64-bit incrementing counter. The VEA defines user-level, read-only access to

the TB. Writing to the TB is reserved for supervisor-level applications such as operat-

ing system s and bootstrap routines. The OEA de fines supervisor-lev el write access to

the TB.

The TB can be written at the supervisor privilege level only. The mttbl and mttbu sim-

plified mnemonics write the lower and upper halves of the TB, respectively. The

mtspr,

mttbl, and mttbu instructions treat TBL and TBU as separate 32-bit registers;

setting one leave s the other unchanged. It is not po ssible to wri te the entir e 64-bit ti me

base in a single instruction.

For information about reading the time base, refer to 3.8 PowerPC VEA Register Set

— Time Base.

3.9.5 Decrementer Register (DEC)

The decrementer (DEC, SPR 22) is a 32-bit decrementing counter defined by the Pow-

erPC architecture to provide a decrementer exception after a programmable delay.

The DEC satisfies the following requ irements:

DSISR — DAE/Source Instruction Service Register SPR 18

031

DSISR

RESET: UNCHANGED

DAR — Data Address Register SPR 19

031

Data Address

RESET: UNCHANGED

TB — Time Base (Writin g) SPR 284, 285

031 32 63

TBU TBL

RESET: UNCHANGED

Table 3-12 Time Base Field Definitions

Bits Name Description

0:31 TBU Time Base (Upper) — The high-order 32 bits of the time base

32:63 TBL Time Base (Lower) — The low-order 32 bits of the time base

MPC509 CENTRAL PROCESSING UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 3-21

• Loading a GP R from the DEC has no effect on the DEC.

• Storing a GPR to the DEC replaces the value in the DEC with the value in the

GPR.

• Whenever bit 0 of the DEC changes from zero to one, a decrementer exception

request (unless masked) is signaled. Multiple DEC exception requests may be re-

ceived before the first exception occurs; however, any additional requests are

canceled when the exception occurs for the fi rst request.

• If the DE C i s a lt er ed by sof tw are a nd the conte nt o f bi t 0 is ch an ge d fr om zero to

one, an exception request is signaled.

The decrementer frequency is based on a subdivision of the processor clock. In the

MPC509, the default frequency is 1 MHz. A bit in the system clock control register

(SCCR) in the SIU determines the clock source of both the decrementer and the time

base.

With a 1-MHz input frequency, the decrementer period is 4295 seconds (approxi-

mately 71.6 minutes):

TDEC = 232 / 1 MHz = 4295 seconds

The state of DEC after standby power is restored is indeterminate. The DEC runs con-

tinuously after power-up (unless the clock module is programmed to turn off the clock).

System software must perform any initialization. The decrementer is not affected by

reset and continues counting while reset is asserted. A decrementer exception may be

signaled to software prior to initialization.

3.9.6 Machine Status Save/Restore Register 0 (SRR0)

The machine status save/restore register 0 (SRR0) is a 32-bit register that identifies

where i nst ru cti on exe cuti o n sh ou ld resume w he n a n rfi instruction is executed follow-

ing an ex cept ion. I t also holds t he eff ecti ve add ress o f the in struct ion that foll ows t he

system call (sc) instruct ion.

When an exception occurs, SRR0 is set to point to an instruction such that all prior

instru ctions have comple ted e xecu tion an d no subs eque nt in structio n has begu n exe-

cution. The instruction addressed by SRR0 may not have completed execution,

depen ding on th e exc eptio n typ e. SRR0 addr esses eith er th e ins truc tion c ausi ng the

DEC — Decrementer Register SPR 22

031

Decrementing Counter

RESET: UNCHANGED

SRR0 — Machine Status Save/Restore Register 0 SPR 26

031

SRR0

RESET: UNDEFINED

MOTOROLA CENTRAL PROCESSING UNIT MPC509

3-22 Rev. 15 June 98 USER’S MANUAL

except ion or the im mediately following ins truction. Th e instruct ion addresse d can be

determined from the exception type and status bits.

3.9.7 Machine Status Save/Restore Register 1 (SRR1)

SRR1 is a 32-bit register used to save machine status on exceptions and to restore

machine status when an rfi instruction is executed.

In general, when an exception occurs, SRR1[0:15] are loaded with exception-specific

information, and MSR[16:31] are placed into SRR1[16:31].

3.9.8 General SPRs (SPRG0–SPRG3)

SPRG0–SPRG 3 are 32-bit registe r s provided for ge nera l opera ting system use, su ch

as performing a fast state save and for supporting multiprocessor implementations.

SPRG0–SPRG3 are s hown be low.

Uses for SPRG0–SPRG3 are shown in Table 3-13.

3.9.9 Processor Version Register (PVR)

The PVR is a 32-bit, read-only register that identifies the version and revision level of

the PowerPC processor. The contents of the PVR can be copied to a GPR by the

mfspr instruct ion. Read a ccess to the PVR is availa ble in su pervi sor mode onl y; wr ite

access is not provided.

SRR1 — Machine Status Save/Restore Register 1 SPR 27

031

SRR1

RESET: UNDEFINED

SPRG0–SPRG3 — General Special-Purpose Registers 0–3 SPR 272 – SPR 275

031

SPRG0

SPRG1

SPRG2

SPRG3

RESET: UNCHANGED

Table 3-13 Uses of SPRG0–SPRG3

SPRG0 Software may load a unique physical address in this register to identify an area of memory reserved for

use by the exception handler. This area must be unique for each processor in the system.

SPRG1 This register may be used as a scratch register by the exception handler to save the content of a GPR.

That GPR then can be loaded from SPRG0 and used as a base register to save other GPRs to memory.

SPRG2 This register may be used by the operating system as needed.

SPRG3 This register may be used by the operating system as needed.

MPC509 CENTRAL PROCESSING UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 3-23

3.9.10 Imple ment ation- Spec if ic SPRs

The RCPU inclu des seve ral i mplem entat ion-spe cific SP Rs tha t are not de fined b y the

PowerPC architecture. These registers can be accessed by supervisor-level instruc-

tions only.

3.9.10.1 EIE, EID, and NRI Special -Purpose Registers

The RCPU includes three implementation-specific SPRs to facilitate the software

manipulation of the MSR[RI] and MSR[EE] bit s. Issuing the mtspr instruction with one

of these registers as an operand causes the RI and EE bits to be set or cleared as

shown in Table 3-15.

A read (mfspr) of any of these locations is treated as an unimplemented instruction,

resulting in a software emulation exception.

3.9.10.2 Instruction-Cache Control Registers

The implementation-specific supervisor-level SPRs shown in Table 3-16 control the

oper ation of the instruction cache.

PVR — Processor Version Register SPR 287

015 16 31

VERSION REVISION

RESET: UNCHANGED

Table 3-14 Processor Version Register Bit Settings

Bit(s) Name Description

0:15 VERSION A 16-bit number that identifies the version of the processor and of the PowerPC

architecture

16:31 REVISION A 16-bit number that distinguishes between various releases of a particular version

Table 3-15 Manipulation of MSR[EE] and MSR[RI]

SPR Number

(Decimal) Mnemonic Effect on MSR Bits

MSR[EE] MSR[RI]

80 EIE 1 1

81 EID 0 1

82 NRI 0 0

Table 3-16 Instruction Cache Control Registers

SPR Number

(Decimal) Mnemonic Name

560 ICCST I-cache control and status register

561 ICADR I-cache address register

562 ICDAT I-cache data port (read only)

MOTOROLA CENTRAL PROCESSING UNIT MPC509

3-24 Rev. 15 June 98 USER’S MANUAL

Refer to 4.3 Instruction Cache Programming Model for details on these registers.

3.9.10.3 Development Support Registers

Table 3-17 lists the implementation-specific RCPU registers provided for development

support.

Refer to the

RCPU Reference Manual

(RCPURM/AD) for detailed descriptions of

these registers.

3.9.10.4 Floating-Point Exception Cause Register (FPECR)

The FPECR is a 32-bit supervisor-level internal status and control register used by the

floating-point assist software envelope. Refer to the

RCPU Reference Manual

(RCPURM/AD) for more information on this register.

3.10 I nstru ction Set

All PowerPC instructions are encoded as single words (32 bits). Instruction formats are

consistent among all instruction types, permitting e fficient decoding to occur in parallel

with operand accesses. This fixed instruction length and consistent format greatly sim-

plifies instructio n pipelining.

The PowerPC instructions are d ivided into the following categories:

• Integer instructions. These include computational and logical instructions.

— Integer arithmetic instructions

Table 3-17 Development Support Registers

SPR Number

(Decimal) Mnemonic Name

144 CMPA Comparator A Valu e Register

145 CMPB Comparator B Valu e Register

146 CMPC Comparator C Value Register

147 CMPD Comparator D Value Register

148 ECR Exception Cause Register

149 DER Debug Enable Register

150 COUNTA Breakpo int Counter A Value and Control Re gister

151 COUNTB Breakpo int Counter B Value and Control Re gister

152 CMPE Comparator E Valu e Register

153 CMPF Comparat or F Value Register

154 CMPG Comparator G Value Register

155 CMPH Comparator H Value Register

156 LCTRL1 L-Bus Support Control Register 1

157 LCTRL2 L-Bus Support Control Register 2

158 ICTRL I-Bus Support Control Register

159 BAR Breakpoint Address Register

630 DPDR Development Port Data Register

MPC509 CENTRAL PROCESSING UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 3-25

— Integer compare instructions

— Integer logical instructions

— Integer rotate and shift instructions

• Floating-point instructions. These include floating-point computational instruc-

tions, as well as instructions that affect the floating-point status and control regis-

ter (FPSCR ).

— Floating-point arithmetic instructions

— Floating-point multiply/ad d instructions

— Floating-point rounding and conversion instructions

— Floating-point compare instructions

— Floating-point status and control instructions

• Load/store instructions. These include integer and floating-point load and store

instructions.

— Integer load and store instructions

— Integer load and store multiple instructions

— Floating-point load and s tore

— Primi tiv es u sed to constr uct ato mic me mo r y op er ations (lw arx and stwcx. in-

structions)

• Flow control instructions. These include branching instruct ions, condition register

logical instructions, trap instructions, a nd other instructions that affe ct the instruc-

tion flow.

— Branch and trap instructions

— Condition register logical instructions

• Processor control instructions. These instructions are used for synchronizing

memory accesses and cache management.

— Move to/from SPR instructions

— Move to/from MSR

— Synchron ize

— Instruction synchronize

• Memory control instructions. These instructions provide control of the instruction

cache.

— Supervisor-level cache management instructions

— User-level cache instructions

Note that this grouping of the instructions does not indicate which execution unit exe-

cutes a particular instruction or group of instructions.

Integer instructions operate on byte, half-word, and word operands. Floating-point

instructions operate on single-precision (one word) and double-precision (one double

word) floating-point operands. The PowerPC architecture uses instructions that are

four bytes long and word-aligned. It provides for byte, half-word, and word operand

loads and stores between memory and a set of 32 GPRs. It also provides for word and

doubl e-word op erand lo ads and stores be tween memory a nd a set of 32 floatin g-point

registers (FPRs).

Computational instructions do not modify memory. To use a memory operand in a

computa tion an d then modi fy the sa me o r ano ther m emo ry lo catio n, the m emo ry con-

tents must be loaded into a register, modified, and then written back to the target

location with distinct instructions.

MOTOROLA CENTRAL PROCESSING UNIT MPC509

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PowerPC processors follow the program flow when they are in the normal execution

state. However, the flow of instructions can be interrupted directly by the execution of

an instruction or by an asynchronous event. Either kind of exception may cause one

of several components of the system software to be invoked.

3.10.1 Instruction Set Summary

Table 3-18 pro v ides a summary o f RCPU instructions. Refe r to the

RCPU Reference

Manual

(RCPURM/AD) for a detail ed description of the instruction set.

Table 3-18 Instruction Set Summary

Mnemoni c Operand Synta x Name

add (add. addo addo.) rD,rA,rBAdd

addc (addc. addco addco.) rD,rA,rB Add Carrying

adde (adde. addeo addeo.) rD,rA,rB Add Extended

addi rD,rA,SIMM Add Immediate

addic rD,rA,SIMM Add Immediate Carrying

addic. rD,rA,SIMM Add Immediate Carrying and Record

addis rD,rA,SIMM Add Immediate Shifted

addme (addme. addmeo addmeo.) rD,rA Add to Minus One Extended

addze (addze. addzeo addzeo.) rD,rA Add to Zero Extended

and (and.) rA,rS,rB AND

andc (andc.) rA,rS,rB AND with Comple ment

andi. rA,rS,UIMM AND Immediate

andis. rA,rS,UIMM AND Immediate Shifted

b (ba bl bla) target_addr Branch

bc (bca bcl bcla) BO,BI,target_addr Branch Conditional

bcctr (bcctrl) BO,BI Branch Conditional to Count Register

bclr (bclrl) BO,BI B ranch Conditional to Link Register

cmp crfD,L,rA,rB Compare

cmpi crfD,L,rA,SIMM Compare Immediate

cmpl crfD,L,rA,rB Compare Logical

cmpli crfD,L,rA,UIMM Compare Logical Immediate

cntlzw (cntlzw.) rA,rS Count Leading Zeros Word

crand crbD,crbA,crbB Condition Register AND

crandc crbD,crbA,crbB Condition Register AND with Complement

creqv crbD,crbA,crbB Condition Register Equivalent

crnand crbD,crbA,crbB Condition Register NAND

crnor crbD,crbA,crbB Condition Register NOR

cror crbD,crbA,crbB Condition Register OR

crorc crbD,crbA,crbB Condition Register OR with Compleme nt

crxor crbD,crbA,crbB Condition Regi ster XOR

divw (divw. divwo divwo.) rD,rA,rB Divide Word

divwu divwu. divwuo divwuo. rD,rA,rB Divide Word Unsigned

eieio — Enforce In-Order Execution of I/O

MPC509 CENTRAL PROCESSING UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 3-27

eqv (eqv.) rA,rS,rB Equivalent

extsb (extsb.) rA,rS Extend Sign Byte

extsh (extsh.) rA,rS Extend Sign Half Word

fabs (fabs.) frD,frB Floating Absolute Value

fadd (fadd.) frD,frA,frB Floating Add (Double-Precision)

fadds (fadds.) frD,frA,frB Floating A dd Single

fcmpo crfD,frA,frB Floating Compare Ordered

fcmpu crfD,frA,frB Floating Compare Unordered

fctiw (fctiw.) frD,frB Floating Convert to Integer Word

fctiwz (fctiwz.) frD,frBFloating Convert to Integer Word with Round

toward Zero

fdiv (fdiv.) frD,frA,frB Floating Divide (Double-Precision)

fdivs (fdivs.) frD,frA,frB Floating Divi de Single

fmadd (fmadd.) frD,frA,frC,frB Floating Multiply-Add (Double-Precision)

fmadds (fmadds.) frD,frA,frC,frB Floating Multiply-Add Single

fmr (fmr.) frD,frB Floating Move Regist er

fmsub (fmsub.) frD,frA,frC,frB Floating Multiply-Subtract (Double-Precision)

fmsubs (fmsubs.) frD,frA,frC,frB Floating Mult iply-Subtract Single

fmul (fmul.) frD,frA,frC Floating Mu ltiply (Double-Precision)

fmuls (fmuls.) frD,frA,frC Floating Multiply Single

fnabs (fnabs.) frD,frB Floating Negative Absolute Value

fneg (fneg.) frD,frB Floating N egate

fnmadd (fnmadd.) frD,frA,frC,frBFloating Negative Multiply-Add (Doubl e-

Precision)

fnmadds (fnmadds.) frD,frA,frC,frB Floating Negative Multiply-Add Single

fnmsub (fnmsub.) frD,frA,frC,frBFloating Negative Multiply-Subtract (Double-

Precision)

fnmsubs (fnmsubs.) frD,frA,frC,frB Floating Negative Multiply-Subtr act S ingle

frsp (frsp.) frD,frB Floating Round to Single

fsub (fsub.) frD,frA,frB Floating Subtract (Double-Precision)

fsubs (fsubs.) frD,frA,frB Floating Subtract Single

icbi rA,rB Instruction Cache Block Invalidate

isync — Instruction Synchronize

lbz rD,d(rA) Load Byte and Zero

lbzu rD,d(rA) Load Byte and Zero with Update

lbzux rD,rA,rB Load Byte and Zero with Update Indexed

lbzx rD,rA,rB Load Byte and Zero Indexed

lfd frD,d(rA) Load Floating-Point Double

lfdu frD,d(rA) Load Floating-Point Double with Update

lfdux frD,rA,rBLoad Floating-Point Double with Update

Indexed

lfdx frD,rA,rB Load Floating-Point Double Indexed

lfs frD,d(rA) Load Floating-Point Single

Table 3-18 Instruction Set Summary (Continued)

Mnemoni c Operand Synta x Name

MOTOROLA CENTRAL PROCESSING UNIT MPC509

3-28 Rev. 15 June 98 USER’S MANUAL

lfsu frD,d(rA) Load Floating-Point Single with Update

lfsux frD,rA,rB Load Float ing-Point Sing le with Updat e Indexed

lfsx frD,rA,rB Load Floating -Point Si ngle Inde xed

lha rD,d(rA) Load Half Word Algebraic

lhau rD,d(rA) Load Half Word Algebraic with Update

lhaux rD,rA,rB Load H alf Wo rd Al geb rai c wi th U p dat e In de xed

lhax rD,rA,rB Load Half Word Algebraic Indexed

lhbrx rD,rA,rB Load Half Word Byte-Reverse Indexed

lhz rD,d(rA) Load Half Word and Zero

lhzu rD,d(rA) Load Half Word and Zero with Update

lhzux rD,rA,rB Load Half Word and Zero with Update Indexed

lhzx rD,rA,rB Load Half Word and Zero Indexed

lmw rD,d(rA) Load Multiple Word

lswi rD,rA,NB Load String Word Immediate

lswx rD,rA,rB Load String Word Indexed

lwarx rD,rA,rB Load Word and Reserve Indexed

lwbrx rD,rA,rB Load Word Byte-Reverse Indexed

lwz rD,d(rA) Load Word and Zero

lwzu rD,d(rA) Load Word and Zero with Update

lwzux rD,rA,rB Load Word and Zero with Update Indexed

lwzx rD,rA,rB Load Word and Zero Indexed

mcrf crfD,crfS Move Condition Register Field

mcrfs crfD,crfS Move to Condition Register from FPSCR

mcrxr crfD Move to Condition R egister from XER

mfcr rD Move from Condition Register

mffs (mffs.) frD Move from FPSCR

mfmsr rD Move f rom Machine State Register

mfspr rD,SPR Move from Special Purpose Register

mftb rD,TBR Move from Time Base

mtcrf CRM,rS Move to Condition R egister Fields

mtfsb0 (mtfsb0.) crbD Move to FPSCR Bit 0

mtfsb1 (mtfsb1.) crbD Move to FPSCR Bit 1

mtfsf (mtfsf.) FM,frB Move to FPSCR Fields

mtfsfi (mtfsfi.) crfD,IMM Move to FPSCR Field Immediate

mtmsr rS Move to Machine State Register

mtspr SPR,rS Move to Special Purpose Reg ister

mulhw (mulhw.) rD,rA,rB Multiply Hi gh Word

mulhwu (mulhwu.) rD,rA,rB Mult ipl y Hi gh Word Unsign ed

mulli rD,rA,SIMM Multiply Lo w Immediate

mullw (mullw. mullwo mullwo.) rD,rA,rB Multiply Low

nand (nand.) rA,rS,rB NAND

neg (neg. nego nego.) rD,rA Negate

Table 3-18 Instruction Set Summary (Continued)

Mnemoni c Operand Synta x Name

MPC509 CENTRAL PROCESSING UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 3-29

nor (nor.) rA,rS,rBNOR

or (or.) rA,rS,rBOR

orc (orc.) rA,rS,rB OR with Complement

ori rA,rS,UIMM OR Immediate

oris rA,rS,UIMM OR Immediate Shifted

rfi — Return from Interrup t

rlwimi (rlwimi.) rA,rS,SH,MB,ME Rotate Left Word Immediate then Mask Insert

rlwinm (rlwinm.) rA,rS,SH,MB,ME Rotate Left Word Immediate then AND with

Mask

rlwnm (rlwnm.) rA,rS,rB,MB,ME Rotate Left Word then AND with Mask

sc — System Call

slw (slw.) rA,rS,rB Shift Left Word

sraw (sraw.) rA,rS,rB Shift Right Algebraic Word

srawi (srawi.) rA,rS,SH Shift Right Algebraic Word Immediate

srw (srw.) rA,rS,rB Shift Right Word

stb rS,d(rA) Store Byte

stbu rS,d(rA) Store Byte with Update

stbux rS,rA,rB Store Byte with Update Indexed

stbx rS,rA,rB Store Byte Indexed

stfd frS,d(rA) Store Floating-Point Double

stfdu frS,d(rA) Store Floating-Point Double with Update

stfdux frS,rB Store Floating-Point Double with Update

Indexed

stfdx frS,rB Store Floating-Point Double Indexed

stfiwx frS,rB Store Floating-Point as Integer Word Indexed

stfs frS,d(rA) Store Floating-Point Single

stfsu frS,d(rA) Store Floating-Point Single with Update

stfsux frS,rB Store Floating-Point Single with Update Indexed

stfsx frS,rB Store Floating-Point Single Indexed

sth rS,d(rA) Store Half Word

sthbrx rS,rA,rB Store Half Word Byte-Reverse Indexed

sthu rS,d(rA) Store Half Word with Update

sthux rS,rA,rB Store Half Word with Update Indexed

sthx rS,rA,rB Store Half Word Indexed

stmw rS,d(rA) Store Multiple Word

stswi rS,rA,NB Store String Word Immediate

stswx rS,rA,rB Store String Word Indexed

stw rS,d(rA) Store Word

stwbrx rS,rA,rB Store Word Byte-Reverse Indexed

stwcx. rS,rA,rB Store Word Cond itio na l Index ed

stwu rS,d(rA) Store Word with Up da te

stwux rS,rA,rB Store Word with Update Indexed

Table 3-18 Instruction Set Summary (Continued)

Mnemoni c Operand Synta x Name

MOTOROLA CENTRAL PROCESSING UNIT MPC509

3-30 Rev. 15 June 98 USER’S MANUAL

3.10.2 Recommended Simplified Mnemonics

To simplify assembly language coding, a set of alternative mnemonics is provided for

some frequently used operations (such as no-op, load immediate, load address, move

For a complete list of simplified mnemonics, see the

RCPU Reference Manual

(RCPURM/AD). Programs written to be portable across the various assemblers for the

PowerPC architecture should not assume the existence of mnemonics not described

in that manual.

3.10.3 Calculating Effective Addresses

The effective address (EA) is the 32-bit address computed by the processor when exe-

cuting a memory access or branch instruction or when fetching the next sequential

instruction.

The PowerPC architecture supports two simple memory addressing modes:

• EA = (rA|0) + 16-b it off set (i ncludi ng of fset = 0) (registe r indi rect with immedi ate

index)

• EA = (rA|0) + rB (register indirect with index)

These simple addressing modes allow efficient address generation for memory

accesses. Calculation of the effective address for aligned transfers occurs in a single

clock cycle.

For a memory access instruction, if the sum of the effective address and the operand

lengt h e xceed s th e m a xim u m effe cti ve address, t he stor a ge ope r and i s co nsi de red to

wrap around from the maximum effective address to effective address 0.

Effective address computations for both data and instruction accesses use 32-bit

unsigned binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations.

stwx rS,rA,rB Store Word Indexed

subf (subf. subfo subfo.) rD,rA,rB Subtract From

subfc (subfc. subfco subfco.) rD,rA,rB Subtract from Carrying

subfe (subfe. subfeo subfeo.) rD,rA,rB Subtract from Extended

subfic rD,rA,SIMM Subtract from Immediate Carrying

subfme (subfme. subfmeo subfmeo.) rD,rA Subtract from Minus One Extended

subfze (subfze. subfzeo subfzeo.) rD,rA Subtract from Zero Extended

sync — Synchronize

tw TO,rA,rB Trap Word

twi TO,rA,SIMM Trap Word Immediate

xor (xor.) rA,rS,rBXOR

xori rA,rS,UIMM XOR Immediate

xoris rA,rS,UIMM XOR Immediate Shifted

Table 3-18 Instruction Set Summary (Continued)

Mnemoni c Operand Synta x Name

MPC509 CENTRAL PROCESSING UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 3-31

3.11 Exception Model

The PowerPC exception mechanism allows the processor to change to supervisor

state as a r esult of exte rnal sign als, e rror s, or u nu sual co ndit ions ari sing i n the exec u-

tion of instructions. When exceptions occur, information about the state of the

processor is saved to certain registers, and the processor begins execution at an

address (exception vector) predetermined for each exception. Processing of excep-

tions occurs in supervisor mode.

Although multiple exception conditions can map to a single exception vector, a more

specific condition may be determined by examining a register associated with the

exception — for example, the DAE/source instruction service register (DSISR) and the

float ing-p oint sta tus and cont rol regis ter (F PSCR). Ad diti onall y, s ome ex cept ion con-

ditions can be explicitly enabled or disabled by so ftware .

3.11.1 Exception Classes

The MPC509 exception classes are shown in Table 3-19.

3.11.2 Ordered Exceptions

In the MPC509, all exceptions except for reset, debug port non-maskable interrupts,

and mac hine check exc eptio ns are or dere d. Or dered ex cept ions s atisfy the follow ing

criteria:

• Only on e except ion is re port ed at a tim e. If, for exa mple, a single instru ction en-

counters multiple exception conditions, those conditions are encountered

sequentially. Aft er the exceptio n handler handles an exception, inst ruction execu-

tion continues until the next exception condition is encountered.

• When the exception is taken, no program state is lost.

3.11.3 Unordered Exceptions

Unordered exceptions may be reported at any time and are not guaranteed to pre-

serve program state information. The processor can never recover from a reset

excepti on. It can r ecove r from ot he r unordered exceptions in most case s. Ho wever , i f

a debug port non-maskable interrupt or machine check exception occurs during the

servicing of a pre vious exception, the machine state inform ation in SRR0 and SRR1

(and, in some cases, the DAR and DSISR) may not be recoverable; the processor may

be in the process of saving or restoring these regi sters.

To determine whether the machine state is recoverable, the user can read the RI

(recoverable exception) bit in SRR1. During exception processing, the RI bit in the

Table 3-19 MPC509 Exception Classes

Class Exception Type

Asynchronous, unordered Machine check

System reset

Asynchronous, ordered External interrupt

Decrementer

Synchronous (ordered, precise) Instruction-caused exceptions

MOTOROLA CENTRAL PROCESSING UNIT MPC509

3-32 Rev. 15 June 98 USER’S MANUAL

MSR is copied to SRR1 and then cleared. The operating system should set the RI bit

in the MSR at the e nd of each excepti on handl er’s pr olo gue (afte r saving the pro gram

state) and clear the bit at the start of each exception handler’s epilogue (before restor-

ing the prog ram state) . Then, i f an un orde red exc ept ion o ccurs du rin g the ser vic ing of

an exception handler, the RI bit in SRR1 will contain the correct value.

3.11.4 Precise Exceptions

In the MPC509, all synchronous (instruction-caused) exceptions are precise. When a

precise exce ption occurs, the proce ssor backs the machine up to the instruction caus-

ing the exception. This ensures that the machine is in its correct architecturally-defined

state. The following conditions exist at the point a precise exception occurs:

1. Architecturally, no instruction following the faulting instruction in the code

stream has begun execution.

2. All instructions preceding the faulting instruction appear to have completed with

respect to the executing processor.

3. SRR0 addresses either the instruction causing the exception or the immediate-

ly following instruction. Which instruction is addressed can be determined from

the exception type an d the statu s bits.

4. Depending on the type of exception, the instruction causing the exception may

not have begun execution, may have partially completed, or may have complet-

ed execution.

3.11.5 Exception Vector Table

The setting of the exception prefix (IP) bit in the M SR deter m ines how exceptions are

vectored. If the bit is cleared, the exception ve ctor table begins at the physical address

0x0000 0000; if IP is set, the exception vector table begins at the physical address

0xFFF0 0000. Table 3-20 shows the exception vector offset of the first instruction of

the exception handler routine for each exception type.

MPC509 CENTRAL PROCESSING UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 3-33

3.12 Instruction Timing

The MPC509 processor is pipelined. Because the processing of an instruction is bro-

ken into a series of stages, an instruction does not require the entire resources of the

processor.

The instruction pipeline in the MPC509 has four stages:

1. Th e dispatch stag e is impl emented usi ng a distri buted mech anism. Th e central

dispa tch unit br oadcast s the instru ction to al l units. In addition, s coreboard in-

formation (regarding data dependencies) is broadcast to each execution unit.

Each ex ecution un it decodes the instruction . If the instruct ion is not implement-

ed, a program exception is taken. If the instruction is legal and no data depen-

dency is found, the instruction is accepted by the appropriate execution unit,

and the data fo und i n the destina tion r egiste r is co pied to the hi story buff er. If a

data dependency exists, the machine is stalled until the dependency is re-

solved.

2. In the execute stage, each execution unit that has an executable instruction ex-

ecutes the instruct ion. (For some instructions, this occurs over multiple cycles).

3. In the writeback stage, the execution unit writes the result to the destination reg-

ister and reports to the history buffer that the instruction is completed.

4. In the retirement stage, the history buffer retires instructions in architectural or-

Table 3-20 Exception Vector Offset Table

Vector Offset

(Hexadecimal) Exception Type

00000 Reserved

00100 System reset

00200 Machine check

00300 Data access

00400 Instruction acces s

00500 External interrupt

00600 Alignment

00700 Program

00800 Floating-point unavailable

00900 Decrementer

00A00 Reserved

00B00 Reserved

00C00 System call

00D00 Trace

00E00 Floating-poi nt ass is t

01000 Software emulation

01C00 Data breakpoint

01D00 Instruction breakpoint

01E00 Maskable external breakpoint

01F00 Non-maskable external breakpoint

MOTOROLA CENTRAL PROCESSING UNIT MPC509

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der. An instruction retires from the machine if it completes execution with no ex-

ceptions and if all instructions preceding it in the instruction stream have

finished execution with no exceptions. As many as six instructions can be re-

tired in one cl ock.

The history buffer maintains the correct architectural machine state. An exception is

taken only when the instruction is ready to be retired from the machine (i.e., after all

previ ous ly- i ssue d instr u cti ons h ave a lre ady b een re ti re d fr om th e ma chi n e). When an

exception is taken, all instructions following the excepting instruction are canceled,

i.e., the values of the affected destination registers are restored using the values saved

in the history buffer during the dispatch stage.

Figure 3-4 shows basic instruction pipeline timing.

Figure 3-4 Basic Instruction Pipeline

Table 3-21 indicates the latency and blockage for each type of instruction. Latency

refers to the interval from the time an instruction begins execution until it produces a

result th at is available for use by a subsequ ent instruction. Blockage refers to the inter-

val from the time an instruction begins execution until its execution unit is available for

a subsequent instruction. Note that when the blockage equals the latency, it is not pos-

sible to issue another instruction to the same unit in the same cycle in which the first

instruction is being written back.

I1 I2

LOAD

STORE

FETCH

DECODE

READ AND EXECUTE

WRITE BACK (TO DEST REG)

L ADDRESS DRIVE

L DATA

LOAD WRITE BACK

BRANCH DECODE

BRANCH EXECUTE

MPC509 CENTRAL PROCESSING UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 3-35

Table 3-21 Instruction Latency and Blockage

Instruction Type Precision Latency Blockage

Floating-point

multiply-add Double

Single 7

Floating-point

add or subtract Double

Single 4

Flo a ting-p oint multiply Double

Single 5

Floating-point divide Double

Single 17

10 17

Integer multiply — 2 1 or 21

NOTES:

1. Refer to Section 7, “Instruction Timing,” in the

RCPU Reference Manual

(RCPURM/AD) for details.

Integer divide — 2 to 1112 to 111

Integer load/store — See note1See note1

MOTOROLA CENTRAL PROCESSING UNIT MPC509

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MPC509 INSTRUCTION CACHE MOTOROLA

USER’S MANUAL Rev. 15 June 98 4-1

SECTION 4

INSTRUCTION CACHE

The MPC509 instruction cache (I-cache ) is a 4-K byte, two-way set associative cache.

The cache is organized into 128 sets, with two lines per set and four words per line.

Cache lines are aligned on four-word boundaries in memory.

A cache acce ss cycle begins with an instruction requ est from the CPU instruction unit.

In case of a cache hit, the instruction is delivered to the instruction unit. In case of a

cache miss, the cache initiates a burst read cycle (four beats per burst, one word per

beat) on the instru ct io n bus (I-bu s) wit h th e add ress of the re ques te d ins truc tio n. The

first word received from the bus is the requested instruction. The cache forwards this

instruction to the instruction unit as soon as it is received from the I-bus. A cache line

is then selected to receive the data which will b e coming from the bus. An LRU (least

recently use d) rep la cem en t al go ri th m is u sed to select a lin e w hen n o e m pty li n es a re

available.

Each cache line can be used as an SRAM, allowing the application to lock critical code

segments that need fast and deterministic execution time.

Cache coherency in a multi-processor environment is maintained by software and

supported by a fast hardware invalidation capability.

4.1 Instruction Cache Features

• Four Kbytes, two-way set associative, four words in a line

• LRU replacement policy

• Lockable SR AM (cache line granularity)

• Critical word first burst access

• Stream hit (allows fetch from the burst buffer and of the word currently on the I-

bus)

• Efficiently utilizes the pipeline of the I-bus by initiating a new burst cycle (if miss

is detec ted) w hile de liverin g the tail of the pr eviou s missed lin e to th e instru ction

unit

• Cache control:

— Supports PowerPC invalidate instruction

— Supports load and lock (cache line granularity)

• Supports cache inhibit:

— As a cache mode of operation (cache disable)

— On memory regions (supported by the chip select logic)

• Miss latency is reduced by

— Sending address to the cache and to the I-bus simultaneously; and

— Aborting on cache hit before cycle is mapped externally

• Minimu m operat ional power consumption

• Supports reads of tags (including all attributes) and data arrays (for debugging

MOTOROLA INSTRUCTION CACHE MPC509

4-2 Rev. 15 June 98 USER’S MANUAL

purposes)

4.2 Instruction Cache Organization

Figure 4-1 illustrates the I-cache organization.

Figure 4-1 Instruction Cache Organization

Figure 4-2 illustrates the data path of the I-cache.

WAY0

28 292721200

WORD SELEC

BIDIRECTIONAL MUX 2 ➝1

128

HIT

128

INSTRUCTION POINTER

. .

SET0

SET1

SET127

SET126

COMP

TAG0 W0 W1 W2 W3

VALID BIT

LOCK BIT

TAG1 W0 W1 W2 W3

TAG127 W0 W1 W2 W3

TAG126 W0 W1 W2 W3

. . .

. .

128

COMP

TO LINE BUFFER/

FROM BURST BUFFER

W2 TAG0 W0 W1 W2 W3

WAY1

TAG1 W0 W1 W2 W3

TAG127 W0 W1 W2 W3

TAG126 W0 W1 W2 W3

. . .

VALID BIT

LOCK BIT

MPC509 INSTRUCTION CACHE MOTOROLA

USER’S MANUAL Rev. 15 June 98 4-3

Figure 4-2 Instr u ction Cache Data Path

4.3 Instruction Cache Programming Model

Three special purpose registers (SPRs) control the I-cache:

These registers are privileged; attempting to access them when the CPU is operating

at the user privilege level results in a program exception.

Table 4-1 Instruction Cache Programming Model

Name SPR Number

(Decimal) Description

ICCST 560 I-cache control and status register

ICADR 561 I-cache address register

ICDAT 562 I-cache data port (read only)

128

INSTRUCTION I-BUS

DATA

TO CPU

4-KBYTE

ARRAY

CACHE

SET

DECODER

ADDR[21:27]

4-WORD

BUFFER

LINE

4-WORD

BURST

BUFFER

128

STREAM

HIT

MUX

2➝1

128

WORD

SELECT

MUX

4➝1

128

DATA

BYPASS

MUX

2➝132

ADDR[28:29]

MOTOROLA INSTRUCTION CACHE MPC509

4-4 Rev. 15 June 98 USER’S MANUAL

ICCST — I-Cache Control and Status Register SPR560

012345678910 11 12 13 14 15

IEN RESERVED CMD RESERVED CCER

1CCER

2CCER

3RESERVED

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED

RESET:

0000000000000000

Table 4-2 ICCST Bit Settings

Bits Mnemonic Description

0IEN

I-cache enable status bit. This bit is a read-only bit. Any attempt to write it is ignored.

0 = I- cache is dis abled

1 = I-cache is enabled

1:3 — Reserved

4:6 CMD

I-Cache Command

000 = No command

001 = Cache enable

010 = Cache disable

011 = Load & lock

100 = Unlock line

101 = Unlock all

110 = Invalidate all

111 = Reserved

7:9 — Reserved

10 CCER1 I-Cache Error Type 1 (sticky bit)

0 = No error

1 = Error

11 CCER2 I-Cache Error Type 2 (sticky bit)

0 = No error

1 = Error

12 CCER3 I-Cache Error Type 3 (sticky bit)

0 = No error

1 = Error

13:31 — Reserved

ICADR — I-Cache Address Register SPR561

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

ADR

RESET:

00000000000000000000000000000000

MPC509 INSTRUCTION CACHE MOTOROLA

USER’S MANUAL Rev. 15 June 98 4-5

4.4 Cache Operation

On an instruction fetch, bits 21:27 of the instruction’s address are used as an index

into the cache to retrieve the tags and data of one set. The tags from both accessed

lines are then compared to bits 0:20 of the instruction’s address. If a match is found

and the matc hed ent r y is valid, then the access is a cache hit.

If neither tag matches or if the matched tag is not valid, the access is a cache miss.

The I-cache includes one burst buffer that holds the last line received from the bus,

and one line buffer that holds the last line received from the cache array. If the

reque sted da ta is fo und in on e of the se b uffer s, the acce ss is cons idered a cache h it.

To minimize power consumption, the I-cache attempts to make use of data stored in

one of its int ernal buffers . Using a spec ial indic ation from the CPU, it is als o possible,

in some cases, to detect that the requested data is in one of the buffers early enough

so the cache array is not activated at all.

4.4.1 Cache Hit

On a cache hit, bits 28:29 of the instruction’s address are used to select one word from

the cache line whose tag matched. In the same clock cycle, the instruction is trans-

ferred to the instruction unit of the processor.

4.4.2 Cache Miss

On a cache miss, the address of the missed instruction is driven on the I-bus with a

four- word burst transf er read reque st. A cache line is th en selected to rece ive the data

that will be coming from the bus . The selectio n algorithm g ives first pr iority to inva lid

lines. If neither of the two candidate lines in the selected set are invalid, then the least

recently used line is selected for replacement. Locked lines are never replaced.

Table 4-3 I-Cache Addres s Register (ICADR)

Bits Mnemonic Description

0:31 ADR The address to be used in the command programmed in the control and status

ICSDAT — I-Cache Data Register SPR 562

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

DAT

RESET:

00000000000000000000000000000000

Table 4-4 I-Cache Data Register (ICDAT)

Bits Mnemonic Description

0:31 DAT The data received when reading information from the I-cache

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4-6 Rev. 15 June 98 USER’S MANUAL

The tran sfer b egins with th e w or d re qu este d b y the instr uct io n u ni t ( cr it ical wor d fi rs t),

followed by any remainin g words of t he line, then by any remaining words at t he begin-

ning of the line (wrap around). As the missed instruction is received from the bus, it is

immediately delivered to the instruction unit and also written to the burst buffer.

As subsequent instructions are received from the bus they are also written into the

burst buffer and, if needed, delivered to the instruction unit (stream hit) either directly

from the bus or from the burst buffer. When the entire line resides in the burst buffer,

it is written to the cache array if the cache array is not busy with an instruction unit

request.

If a bus error is encountered on the access to the requested instruction, a machine

check interrupt is taken. If a bus error oc curs on an y access to oth er words in the line ,

the burst bu ffer is marked invalid and the line is not written to the array. If no bus error

is encountered, the burst buffer is marked valid and eventually is written to the array.

Togethe r w i th t he missed wor d, an in di cati o n may a rri ve f ro m the I-bus that the me m-

ory device i s n on- ca che able . If su ch an i ndi ca tion is r ecei ved , the li n e is no t written to

the cache, so that subsequent references to the same line will cause the line to be

refetched.

4.5 Cache Commands

The MPC509 instru ction cache supports the PowerPC invalida te instruction together

with some additional commands that help control the cache and debug the in formation

stored in it. The additional commands are implemented using the three special pur-

pose control registers ICCST, ICADR, and ICDAT.

Most of the commands are executed immediately after the control register is written

and cannot generate any errors. When these commands are executed, there is no

need to check the error status in the ICCST.

Some commands may take longer and may generate errors. In the MPC509, only load

& lock is such a c ommand . When exe cuting this command , the user ne eds to ins ert

an isync instruction immediately after the I-cache command and check the error sta-

tus in the ICCST after the isync. The error type bits in the ICCST are sticky, allowing

the user to perform a series of I-cache commands before checking the termination sta-

tus. These bits are set by hardware and cleared by software.

All cache commands except the icbi CPU instruction require setting the appropriate

bits in the ICCST. Since the ICCST is a supervisor-level register, only the icbi instruc-

tion can be perfor med at the user privile ge level.

4.5.1 Instruction Cache Block I nvalidate

The MPC5 09 im plements t he Powe rPC instru ction ca che block i nvalidate (icbi) as if it

pertains only to the MPC509 instruction cache. This instruction does not broadcast on

the external bus and the CPU does not snoop this instruction if broadcast by other

masters.

MPC509 INSTRUCTION CACHE MOTOROLA

USER’S MANUAL Rev. 15 June 98 4-7

This command is not privileged and has no error cases that the user needs to check.

4.5.2 Invalidate All

To invalidate the whole cache, set the invalidate all command in the ICCST. This

command has no error cases that the user needs to check.

The command makes all valid lines in the cache invalid, except lines that are locked.

After this command is executed, the LRU pointer of each set points to an unlocked

way. If both lines in the set are unlocked, the LRU pointer points to way zero. This last

feature is useful in order to initialize the I-cache out of reset.

4.5.3 Load and Lock

The load & lock operation is used to lock critical code segments in the cache. The

load & lock operation is perf ormed on a single cache line. After a line is locked it oper-

ates as a regular instruction SRAM; it will not be replaced during future misses and will

not be affected by invalidate commands.

After the load & lock command is written to the ICCST, the cache checks if the line

containing the byte addressed by the ICADR is in the cache. If it is, the line is locked

and the command terminates with no exception. If the line is not in the cache a regular

miss sequence is initiated. After the whole line is placed in the cache the line is locked.

The user ne eds to check the erro r type bits in the ICCST to determ ine if the oper ation

completed properly or not. The load & lock command c an gen erate two errors:

• Type 1 — bus error in one of the cycles that fetches the line.

• Type 2 — no place to lock. It is the responsibility of the user to make sure that

there is at least one unlocked way in the appropriate set.

4.5.4 Unlock Line

The unlock line operation is used to unlock lo cked cache lines. The

unlock line oper-

ation is p erforme d on a si ngle cac he line. If the lin e is foun d in the c ache (c ache hit ),

it is unlo cked and start s to operate as a regula r valid cache li ne. If the lin e is not found

in the cache (cache miss), no operation is performed, and the command terminates

with no exception.

This command has no error cases that the user needs to check.

4.5.5 Unlock All

The unlock all operation is used to unlock the whole cache. This operation is per-

formed on all cache lines. If a line is locked, it is unlocked and starts to operate as a

regular valid cache line. If a line is not locked or if it is invalid, no operation is

performed.

This command has no error cases that the user needs to check.

MOTOROLA INSTRUCTION CACHE MPC509

4-8 Rev. 15 June 98 USER’S MANUAL

4.5.6 Cache Enable

To enable the cache, set the cache enable

command in the ICCST. This operation

can be performed only at the supervisor privilege level. The cache enable command

has no error cases that the user needs to check.

Following reset, the invalidate all and unlock all commands must be performed

before the cache enable command.

4.5.7 Cache Disable

To disable the cache, set the cache disable

comman d in the ICCST. This opera tion

can be pe rformed only at the supe rvisor privile ge level. The cach e disab le comma nd

has no error cases that the user needs to check.

4.5.8 Cache Inhibit

A memory region can be programmed in the c hip select logic to be cache inhibit. Any

reference to a cache inhibited memory region always results in cache miss.

4.5.9 Cache Read

The user ca n re ad all d ata sto re d in th e i n structio n ca che , i nclu ding th e d at a st or ed in

the tags array.

To read the data that is stored in the I-cache, follow these steps:

1. Write to the ICADR the address of the data to be read. Note that it is also pos-

sible to read this register for debugging purposes.

2. Read th e ICDAT.

So that all parts of the I-cache can be accessed, the ICADR is divided into several

fields, shown in Table 4-5.

When t he dat a arr ay is read from , the 3 2 bits of t he wo rd sele cted by the I CADR are

placed in the targe t gene ral-purpose register.

When the tag array is read, the 21 bits of the tag selected by the ICADR, along with

additional information, are placed in the target general-purpose register. Table 4-6

illustrates the bits layout of the I-cache data register when a tag is rea d.

Table 4-5 ICADR Bits Function for the Cache Read Command

0:17 18 19 20 21:27 28:29 30:31

Reserved 0 = tag

1 = data 0 = wa y 0

1 = wa y 1 Reserved Set select Word select (used

only for data array) Reserved

Table 4-6 ICDAT Layout During a Tag Read

0:20 21 22 23 24 25:31

Tag value Reserved 0 = not valid

1 = valid 0 = not locked

1 = locked LR U bit Reserved

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-1

SECTION 5

SYSTEM INTERFACE UNIT

The system interface unit (SI U) consist s of module s that control the buse s of the chip,

provide the clocks, and provide miscellaneous functions for the system, such as chip

selects, test control, reset control, and I/O ports.

The MPC509 has an internal Harvard architecture and a single external bus. The inter-

nal buses are the instruction bus (I-bus) and the load/store bus (L-bus). The external

bus interface (EBI) connects each of these internal buses with the external bus (E-

bus). The chip select block provides user-programmable chip selects to select external

memory or peripherals. The clock block controls the generation of the system clocks

and such features as programm ability of the clocks and low-power modes. The reset

control function interfaces to the reset pins and provides a reset status register. The

general-purpose I/O ports provide untimed I/O functions on pins that are not used for

their primary function.

5.1 SIU Block Diagram

A block diagram of the SIU is shown in Figure 5-1.

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-2 Rev. 15 June 98 USER’S MANUAL

Figure 5-1 SIU Block Diagram

5.2 SIU Address Map

Table 5-1 is an address map of the SIU registers. An entry of “S” in the Access column

indicates that the register is accessible in supervisor mode only. “S/U” indicates that

the re gister can b e progra mmed to th e desired privile ge level . “Test” indicates that the

SUBBUS

E-BUS

INTERFACE

E-BUS

L-BUS

I-BUS

L-BUS

BIU

I-BUS

BIU

CROSS-BUS

ARB & C N TL

ADDRESS

DECODE

ADDRESS

MUX

L-ADDR

I-ADDR

CHIP

SELECTS

DATA

MUX

I-DATA

L-DATA

CLOCKS

PORTS

BUS

PIT

RESET

POWER-PC

DEBUG

MONITOR

TIMER &

DECREMENTER

INTERFACE

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-3

Table 5-1 SIU Address Map

Access Address Register

S 0x8007 FC00 SIU Module Configuration Register (SIUMCR)

Test 0x8007 FC04 SIU Test Register 1 (SIUTEST1)

—0x8007 FC08 –

0x8007 FC1C Reserved

S 0x8007 FC20 Memory Mapping (MEMMAP)

S 0x8007 FC24 Speculative Address Register (SPECADDR)

S 0x8007 FC28 Speculative Mask Register (SPECMASK)

Test 0x8007 FC2C Termination Status Register (TERMSTAT)

—0x8007 FC30 –

0x8007 FC3C Reserved

S/U 0x8007 FC40 Periodic Interrupt Control and Status Register (PICSR)

S/U 0x8007 FC44 Periodic Interrupt Timer Register (PIT)

S 0x8007 FC48 Bus Monitor Control Register (BMCR)

S 0x8007 FC4C Reset Status Register (RS R)

S 0x8007 FC50 System Clock Control Register (SCCR)

S 0x8007 FC54 System Clock Loc k and Stat us Regi ste r (SCLSR)

—0x8007 FC58 –

0x8007 FC5C Reserved

S 0x8007FC6 0 Port M Data Direction (DDRM)

S 0x8007FC64 Port M Pin Assignment (PMPAR)

S/U 0x8007FC68 Port M Data (PORTM)

—0x8007FC6C –

0x8007FC80 Reserved

S 0x8007FC84 Port A, B Pin Assignment (PAPAR, PBPAR)

S/U 0x 8007FC88 Port A, B Data (PORTA, PORTB)

—0x8007FC8C –

0x8007FC94 Reserved

S 0x8007FC98 Port I, J, K, L Data Direction (DDRI, DDRJ, DDRK, DDRL)

S 0 x8007FC9C Port I, J, K, L Pin Assignment (PIPAR, PJPAR, PKPAR, PLPAR)

S/U 0x8007FCA0 Port I, J, K, L Data (PORTI, PORTJ, PORTK, PORTL)

—0x8007 FCA4 –

0x8007 FD 94 Reserved

S 0x8007 FD94 CS11 Option Register (CSOR11)

S 0x8007 FD98 Reserved

S 0x8007 FD9C CS10 Option Register (CSOR10)

S 0x8007 FDA0 Reserved

S 0x8007 FDA4 CS9 Option Register (CSOR9)

S 0x8007 FDA8 Reserved

S 0x8007 FDAC CS8 Option Register (CSOR8)

S 0x8007 FDB0 Reserved

S 0x8007 FDB4 CS7 Option Register (CSOR7)

S 0x8007 FDB8 Reserved

S 0x8007 FDBC CS6 Option Register (CSOR6)

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-4 Rev. 15 June 98 USER’S MANUAL

5.3 SIU Module Configuration

The SIU module configuration register (SIUMCR) configures various aspects of SIU

operation. The internal memory mapping register (MEMMAP) enables and sets the

base address of the L-bus and I-bus internal memory blocks. These registers are

accessible in supervisor mode only.

5.3.1 SIU Module Configuration Register

The SIU module configuration register (SIUMCR) configures various aspects of SIU

operation. This register is acc essible in superv isor mo de only.

S 0x8007 FDC0 CS5 Base Address Regi ster (CSBAR5)

S 0x8007 FDC4 CS5 Option Register (CSOR5)

S 0x8007 FDC8 CS4 Base Address Regi ster (CSBAR4)

S 0x8007 FDCC CS4 Option Register (CSOR4)

S 0x8007 FDD0 CS3 Base Address Regi ster (CSBAR3)

S 0x8007 FDD4 CS3 Option Register (CSOR3)

S 0x8007 FDD8 CS2 Base Address Regi ster (CSBAR2)

S 0x8007 FDDC CS2 Option Register (CSOR2)

S 0x8007 FDE0 CS1 Base Address Register (CSBAR1)

S 0x8007 FDE4 CS1 Option Register (CSOR1)

S 0x8007 FDE8 Reserved

S 0x8007 FDEC CS0 Option Register (CSOR0)

S 0x8007 FDF0 CSBOOT Sub-Block Base Address Register (CSBTSBBAR)

S 0x8007 FDF4 CSBOOT Sub-Block Option Register (CSBTSBOR)

S 0x8007 FDF8 CSBOOT Base Address Register (CSBTBAR)

S 0x8007 FDFC CSBOOT Option Register (CSBTOR)

SIUMCR — SIU Module Configuration Register 0x8007 FC00

012345678910 11 12 13 14 15

SIU-

FRZ RESERVED CSR LST 0SUP DLK LOK RESERVED LSHOW

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

PARTNUM MASKNUM

RESET:

Read-Only Fixed Value Read-Only Fixed Value

Table 5-1 SIU Address Map (Continued)

Access Address Register

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-5

Table 5-2 SIUM CR Bit Settings

Bit(s) Name Description

0 SIUFRZ

SIU freeze

0 = Decrementer and time base registers and the periodic interrupt timer continue to run while

internal freeze signal is asserted (reset value).

1 = Decr ementer and tim e b ase regi st ers and the p erio dic in terru pt ti me r sto p w hi le th e in tern al

freeze signal is asserted.

Refer to 5.3.3 Inte rnal Module Selec t Logic an d SECTION 8 DEVELOPMENT SUPPORT for

information on the freeze signal.

1:2 — Reserved

3CSR

Checkstop reset enable

0 = No acti on taken when SIU receive s the checkst op signal fro m the CPU and de bug mode not

enabled (reset value).

1 = SIU cau ses a reset upon rec eiving check stop signal from CPU and de bug mode not ena bled.

If deb ug mo de i s e nab led, the M CU e nte rs d ebug mode when the ch ec ks top si gnal is rec ei ve d,

regardless of CSR value. Refer to the

RCPU Reference Manual

(RCPURM/AD) for more infor-

mation on checkstop resets.

4LST

Burst style: BDIP or LAST

0 = BDIP pin uses BDIP timing (rese t va lue ): a ss ert BDIP during burs t, n ega te BD I P during last

beat of burst

1 = BD IP pin uses LAST timing: assert LAST during last beat of burst

Refer to 5.5.16.6 Synchronous Burst Interface for more information.

5—Reserved

6:7 SUP

Supervisor/unrestricted space. These bits control access to certain SIU registers. (Other regis-

ters are always supervisor access only.) The access restrictions for each register are shown in

Table 5-1.

00 = Unrestricted access (reset value)

01 = Supervisor mode access only

10 = Supervisor mode write access only, unrestricted read access

11 = Supervisor mode access only

8DLK

Debug register lock. This bit can be written only when internal freeze signal is asserted. DLK

allow s develo pment sof tware to conf igure s how cycle s and prev ent normal software from subse-

quently changing this configuration. This bit overrides the LOK in controlling the LSHOW field.

0 = LSH OW field in SIUMCR can be w rit ten to (reset v alue).

1 = Writes to LSHOW field are not allowed.

9LOK

Regis ter lock. O nce this bit is set, writes to the SIUMCR and ch ip-selec t registers ha ve no effe ct

and caus e a data error to be ge nerated in the inte rnal bus. In norm al operation, th is is a set-on ly

bit; once set, it cannot be cleared by software. When the internal freeze signal is asserted, the

bit can be set or cleared by software.

0 = Nor mal oper ation (reset valu e)

1 = All bit s in the SIU MCR and all of the chip-select registers are locked

10:13 — Reserved

14:15 LSHOW

L-bus show cycles

00 = Disable show cycles for all internal L-bus cycles (reset value)

01 = Show address and data of all internal L-bus write cycles

10 = Reserved

11 = Show address and data of all internal L-bus cycles

Refer to 5.4.1 3 Show Cycle s for more information.

16:23 PARTNUM Part numb er. This read-onl y field is mask p rogrammed with a cod e correspondi ng to the number

of the MCU.

24:31 MASKNUM Mask numb er. This re ad-only field is mas k progra mmed with a code co rrespon ding to th e mask

number of the MCU.

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-6 Rev. 15 June 98 USER’S MANUAL

5.3.2 Memory Mapping Register

The internal memory mapping register (MEMMAP) enables and sets the base address

of the L-bus ( SRAM) internal mem ory block. This registe r is accessible in su pervisor

mode only.

* Reset value depends on the value of the data bus configuration word during reset.

MEMM A P — Memory Mapp ing Register 0x8007 FC20

012345678910 11 12 13 14 15

LEN RESERVED LMEMBASE RESERVED

RESET:

*0000000**000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

IEN LIX RESERVED IMEMBASE RESERVED

RESET:

*1000000**000000

Table 5-3 MEMMAP Bit Settings

Bit(s) Name Description

0LEN

L-bus me mo ry ena ble

0 = L-bus memory dis ab led

1 = L-bus memory ena bled

Reset state depends on the value of the data bus configuration word.

1:7 — Reserved

8:9 LMEMBASE

Base address of the L-bus memory block

00 = Starting address is 0x0000 0000

01 = Endi ng addres s is 0x000F EFFF

10 = Starting address is 0xFFF0 0000

11 = Ending address is 0xFFFF EFFF

Reset value depends on the data bus configuration word.

10:15 — Reserved

16 IEN I-bus memory enable. This bit has no effect on the MPC509, which has no I-bus memory.

0 = I-bus memory disabled

1 = I-bus memory enabled

17 LIX L-bus to I-bus cross-bus access enable

0 = Disable data accesses to I-bus memory

1 = Enable data accesses to I-bus memory (reset value)

18:23 — Reserved

24:25 IMEMBASE

Base address of the I-bus memory bloc k

00 = Starting address is 0x0000 0000

01 = Ending address is 0x000F FFFC

10 = Starting address is 0xFFF0 0000

11 = Ending address is 0xFFFF FFFC

Reset state depends on the data bus configuration word.

26:31 — Reserved

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-7

5.3.3 Internal Module Select Logic

The SIU has a unified memory map for the L-bus and the I-bus. The I-bus has two

masters, the RCPU and the SIU. The SIU is designed so that one or more memory

modules , such as flash EEPROM or instruction RA M, may be loca ted on the I- bus. On

the MPC509, however, no memory modules are located on the I-bus.

The L- bus has at leas t two masters, the RCPU and the SIU. One or more slave mod-

ules may reside on the L-bus. These may include memory modules (RAM, flash

EEPROM) and on-chip (IMB2) peripherals, which are connected via the L-bus IMB2

interface (LIMB). On the MPC509, the SRAM module is located on the L-bus.

Each module on either bus has one or more internal control registers which control the

configuration and operation of the module. On a memory module (i.e., the SRAM on

the MPC509), these registers are not mapped with the memory array, but stay at a

fixed address in the memory map.

Capability is provided to allow masters on one bus to access slaves on the opposite

bus. L-bus masters must be able to access peripherals on the I-bus to program their

control registers or to program flash memory arrays. This is because the CPU instruc-

tion fetch unit can only run read cycles. Similarly, I-bus masters are able to execute

diagno stic pr ogra ms out o f the RAM on the L-bu s. The se cap abilitie s requ ir e that the

addresses of the memory modules on the I-bus be known to the L-bus address decode

logic and vice versa. Refer to 5.3.4 Internal Cross-Bus Accesses for details.

A block diagram of the internal module select scheme is shown in Figure 5-2.

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-8 Rev. 15 June 98 USER’S MANUAL

Figure 5-2 Internal Module Select Scheme

5.3.3.1 Memory Block Mapping

The SRAM array can be mapped to one of four locations. These locations are at the

top and bottom of the 4-Gbyte address range. They include the two alte rnatives for the

PowerPC vector map (0x0000 0100 and 0xFFFF 0100). The LMEMBASE field in the

memory mapping register (MEMMAP) determine the locations of the SRAM array.

Figure 5-3 shows the mapping of the memory blocks within the memory map.

SIU DECODE BLOCK

CONTROL REGISTERS

I-BUS

L-BUS

IMEMBASE

LMEMBASE

IMB

(READ/WRITE)

L-MEM MO DULE 2

L-MEM MODUL E 1

FIXED DECODE:

0X8000 0000 –

0X8007 EFFF

4-KBYTE BLOCK @ 0X8007 F000

I- MEM MODULE

I-BUS MAPPING SIGNALS (3)

L-BUS MA PPING SIG NA L S (3)

CPU

(IN SIU AND EACH MODULE)

INTERFACE

MPC500 MOD SEL BLOC

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-9

Figure 5-3 Placement of Internal Memory in Memory Map

5.3.3.2 Accesses to Unimplemented Internal Memory Locations

If an access is made to a location within the 2n-sized memory block that is not imple-

mented in any memory module on the chip, then the CPU takes a machine check

exception.

5.3.3.3 Contro l Register Block

The internal control registers include all of the SIU registers and all of the configura-

tion, control, an d status r egister s of each mo dule on th e I-bus or L-bus. The interna l

control registers and the IMB2 are allocated a 512-Kbyte block from 0x8000 0000 to

0x8007 FFFF. The internal control registers always occupy the highest-numbered four

Kbytes of this address range (0x8007 F000 to 0x8007 FFFF). The IMB2 modules (on

0x0000 0000

0x000F EFFC

0xFFF0 0000

0xFFFF EFFC

0x8007 E000

0x8007 EFFC

EXTERNAL

POSSIBLE SRAM

ONE OF FOUR POSSIBLE LOCATIONS

PERIPHERAL

EXTERNAL

CONTROL UNIT

(PCU)

CONTROL REGISTERS

0x8000 0000

EXTERNAL/RESERVED

0x8007 FFFC

0x8007 F000

VECTOR TABLE LOCATION

(IP BIT = 0)

VECTOR TABLE LOCATION

(IP BIT = 1)

LOCATION

(4 KBYTES)

POSSIBLE SRAM

LOCATION

(4 KBYTES)

POSSIBLE SRAM

LOCATION

(4 KBYTES)

POSSIBLE SRAM

LOCATION

(4 KBYTES)

0xFFFF E000

0xFFF0 0FFC

0x0000 0FFC

0x000F E000

SELECTED FOR SRAM

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-10 Rev. 15 June 98 USER’S MANUAL

the MP C509, this includes on ly the PCU) a re allocated the remainder of the 512-Kbyte

block.

Unlike t he memory arrays, the inte rnal control registers and IMB2 modules cannot be

disabled for development purposes. In addition, the IMB2 and control register block

are only available in data spa ce, no t in instruction space . An inst ruction access to th e

address of a control register results in a data error on the I-bus, causing the internal

TEA signal to be asserted.

5.3.3.4 Internal Me mory Mapping Field (LMEMBASE)

The LMEMBASE field in the MEMMAP register maps the L-bus memory (i.e., the

SRAM) to one of four possible locations in the memory map. The following table shows

the meaning of the field. Note that these locations include the two possible locations

for the CPU vector table. The address not given (start or end, depending upon the

block) depends on the block size.

5.3.3.5 Memory Mapping Conflicts

Any access to a memory that does not exist causes the cycle to appear on the external

bus. Because the MPC509 does not have an I-bus memory module, an access to I-

bus memo ry is sent to the exte rnal bus, e ven if the I-bus me mory enab le (IEN) bit in

the MEMBASE register is set.

5.3.4 Internal Cross-Bus Accesses

Each i nternal b us (I-b us and L -bus) has a master /slave int erface in the SIU . The slav e

interface is used for accesses by the internal master (RCPU) to the external bus, to

memory on the opposite bus (e.g., L-bus to I-bus access), or to SIU registers.

The SIU allows master s on either internal b us (I-bus or L -bus) to acc ess slaves on th e

other inte rnal b us. Accesses from o ne inte rn al b us to resources on the other bu s ta ke

at least three clocks, because of arbitration and cycle termination delays.

Instructio n fetchi ng from L-b us memo ry is int ended pri marily a s a mech anism to all ow

a customer test program to be downloaded to on-chip RAM and executed. This is not

a high-p erformance i nstruction fetchin g mechanism . Accesses from the I-bus to th e L-

bus are at least three clocks and not burstable.

Cross-bus accesses occur inside the SIU, consuming SIU resources during the

access. Internal SIU registers are not available during cross-bus accesses. Internal-

Table 5-4 Inte rnal Me mory Array Block Mapping

LMEMBASE Block Placement

00 Starting Address: 0x0000 0000

01 Ending Address: 0x000F EFFC

10 Starting Address: 0xFFF0 0000

11 Ending Address: 0xFFFF EFFC

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-11

to-external cycles are not pipe lined with cross-bus accesses, nor are two con secutive

cross-bus accesses pipelined.

Clearing the L-bus to I-bus cross-bus access (LIX) bit in the MEMMAP register dis-

ables data accesses to I-bus memory. This allows load/store data stored in a flash

memory on the I-bus to be moved off-chip for develop ment pu rpose s. When this bit is

cleared, L-bus to I-bus transactions are run externally.

5.3.5 Response to Freeze Assertion

The RCPU asserts the freeze signal to the rest of the MCU when one of the following

conditions occurs:

• Debug mode is entered; or

• A soft war e d ebu g m o nitor p ro gr am i s e nte re d as the r esu lt of an exce pti on whe n

the associated bit in the debug enable register (DER, SPR149) is set.

The following paragraphs explain how the assertion of the freeze signal affects the

SIU. See SECTION 8 DEVELOPMENT SUPPORT for additiona l details on this signal.

5.3.5.1 Effects of Freeze and Debug Mode on the Bus Monitor

When the freeze signal is asserted and debug mode is disabled, the bus monitor is

unaffect ed. This means that a software monitor must configure t he bus monitor to pr o-

vide protection from unterminated bus cycles that occur during debugging.

When the processor is in debug mode (debug mode is enabled and the freeze signal

is ass erted), the bus moni tor is e nabled. The b us monitor is also ena bled whe n debug

mode is enabled and a non-maskable breakpoint is asserted by the development port.

These enables override the bus monitor enable bit (BME) in the bus monitor control

regi ster (BMCR ) in the SIU. In bo th cases the bus monito r time-ou t period is whatever

was programmed in the BMCR. This override allows an external development tool to

retain control over the CPU in debug mode by not allowing an external bus cycle to

hang the processor in an endles s wait fo r a transfer acknow ledge.

In addition, if the processor is executing normally and runs a bus cycle that is not ter-

minated, a non-maskable breakpoint always gains control of the processor by

terminating the bus cycle with the bus monitor so the processor can enter debug

mode. In this case, the non-maskable breakpoint is not restartable. The processor

takes the breakpoint before completing the prologue of the exception handler called

as a result of the bus monitor.

5.3.5.2 Effects of Freeze on the Programmable Interrupt Timer (PIT)

When freeze is asserted and the SIU freeze bit (SIUFRZ) is set in the SIU module con-

figuration register (SIUMCR), the PIT is disabled. This disable overrides the periodic

interrupt enable bit (PIE) in the periodic interrupt control and select register (PICSR)

in the SIU. This allows the count in the PIT to be preserved when execut ion stops.

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5.3.5.3 Effects of Freeze on the Decrementer

When freeze is asserted and the SIUFRZ is set in the SIUMCR, the decrementer is

disabled. This allows the value in the decrementer to be preserved when execution

stops.

5.3. 5.4 Eff ect s of Freeze on Regi st er Loc k Bi ts

When freeze is asserted the lock bits in various registers can be set or cleared. This

allows the protected configurations to be changed and then re-locked by a develop-

ment support system.

5.4 Extern al Bus Interface

The external bus interface (EBI) interfaces the external bus (E-bus) with the two inter-

nal buses (I-bus and L-bus). The E-bus is synchronous and supports pipelined and

burst transfers. Signals drive n onto the E-bus are required to meet the set-up and hold

times relative to the rising edge of the bus clock. The bus has the ability to support mul-

tiple master s, but its pro tocol is opti mized for a sin gle-pro cessor enviro nment.

5.4.1 Features

• No external glue logic required for a simple system.

• Supports different memory (SRAM, EEPROM) types: asynchronous, synchro-

nous, pipelineable, burstable.

• Fast (one-clock) arbitration possible.

• Bus is synchronous — all signals are referenced to the rising edge of the bus

clock.

• 32-bit data bus, 32-bit address bus with byte enables.

• Compatible with PowerPC architecture.

• Protocol allows wait states to be inserted during the data phase and supports ear-

ly burst terminatio n.

• Supports both 16-bit and 32-bit port sizes.

• Bus electrical specification minimizes system power consumption.

5.4.2 External Bus Signals

Table 5-5 summarizes the E-bus sign als. The fo llowin g abbr eviat ions are use d in this

table:

M = Bus master

S = Slave device

A = Central bus arbiter

T = Bus watchdog timer

X = Any device on the system

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-13

Table 5-5 EBI Signal Descriptions

Mnemonic Direction Description

Address Phase Signals

ADDR[0:29] M → S

32-bit address bus. Least significant two bits (ADDR[30:31]) are not

pinned out; they can be determined from the BE[0: 3] pins. ADDR0 is the

most significant bit. Address bus is driven by the bus mas ter to index the

bus sl ave.

TS M → S Transfer start. This address control signal is asserted for one clock cycle

at the beginning of a bus access by the bus master.

WR M → S Write/read. When this address attribute is asserted, a write cycle is in

progress. When negat ed, a read cycle is in progress. For use of WR dur-

ing show cycles, refer to SECTION 8 DEVELOPMENT SUPPORT.

BE[0:3] M → S

Byte enables. These ad dress attribute signals indicate which byte within

a word is being accessed. External memory chips can use these signals

to determine which byte locat ion is enabled. Table 5-7 shows the enco d-

ings for these pins during accesses to 32-bit and 16-bit ports.

A device need only ob serve the byte enab les correspon ding to t he data

lanes o n which it resides. For e xample, a device on data lane DATA[0:7]

should use BE0, and a device on DATA[0:15] should use BE[0:1]. The

dev ice should not respond to the bus cycle unle ss its byte enables are

active at the start of the bus cycle.

AT[0:1] M → S Address types. These address attribute signals define addressed space

as user or supervisor, data o r inst ruct ion. Refer to Table 5-6 for encod-

ings. These signals have the same timing as ADDR[0:29].

CT[0:3] M → S Cycle type signals. These address attribute signals indicate what type of

bus cycle the bus master is initia ting. Used for development support. Re-

fer to Table 5-14 for encodings.

BURST M → SBurst cycle. This address attribute indicates that the transfer is a burst

transfer. If a burst a ccess is burst-inhi bited by the slav e, the BURST pi n

is driven during each single-beat (decomposed) cycle.

AACK S → M

Address acknowledge. When asserted, indicates the slave has received

the address from the bus master. This signal terminates the address

phase o f a bus cyc le. When the b us master re ceives this signal from th e

slave, the mast er can initia te another addres s transfer. This sig nal must

be asserted at the same time or prior to TA assertion.

ARETRY S, A → M

Address retry. This is an address phase termination signal. It is de-

signed to resolve deadlock cases on hierarchical bus structures or for

error-correcting memories. ARETRY assertion overrides AACK asse r-

tion and causes the SIU to re-arbitrate and to re-run the bus cycle.

BI S → M

Burst inhi bit. When a sserted, indi cates the slave do es not support burst

mode. Sam pl ed a t sa me tim e a s AACK. If BI is as ser ted, the SIU trans -

fers the burst data in mu ltiple cyc les and i ncrement s the addr ess fo r the

slave in order to complete the burst transfer.

Data Phase Signals

DATA[0:31] M ↔ S32-bit data bus. DATA0 is most significant bit; DATA31 is the least sig-

nificant bit. During small-port accesses, data resides on DATA[0:15].

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-14 Rev. 15 June 98 USER’S MANUAL

BDIP M → S

Burst data in progress. This signal is asserted at the beginning of a burst

data phase and is negated during the last beat of a burst. The master

uses t his signal to give t he slave advance warn ing of th e remaining data

in the b urst. Th is can also b e use d for an ea rly te rminati on of a burst cy-

cle.

When the LST bit in the SIUMCR is asserted, the BDIP pin uses LAST

timing. If the LST bit is negated, the BDIP pin uses BDIP timing. Refer

to 5.5.16.6 Synchronous Burst Interface for more information.

TA S → M

Transfer acknowledge. When asserted, indicates the slave has received

the data during a wr ite cycle or returned th e data during a r ead cycle.

During burst cycle s, the slave asserts thi s signal with every data beat re-

turned or accepted.

TEA T, S → M

Transfer error acknowledge. Assertion of TEA indicates an error co ndi -

tion has occ urred du ring th e bus cyc le, and the b us cy cle i s term inated .

This signal overrides any other cycle termination signals (e.g., TA or

ARETRY).

DS M → S

Data stro be . Asserte d by EBI at the en d of a c hip -se lec t-c ont roll ed bu s

cycle. Ass erted afte r the chip -select un it asse rts the in ternal TA or TEA

signal or the bus monitor timer asserts the internal TEA signal. Al so as -

serted at the end of a show cycle.

Arbitration

BR M → ABus request. When asserted, indicates the pote ntial bus master is re-

questing the bus. Each master has its own bus request signal.

BG A → MBus grant. When asserted by bus arbiter, the bus is granted to the bus

master. Each master has its own bus grant signal.

BB M → M, A Bus busy. Asserted by current bus master to indicate the bus is currently

in us e. Prospective new master should wait until the current mas ter ne -

gates this signal.

Miscellaneous

CR X → M

Cancel reservation. Each PowerPC CPU has its own CR signal. This

signal shows the status of any outstanding reservation on the external

bus. When asserted, CR indicates that there is no outstanding reserva-

tion. This is a level signal.

RESET Source → M This inpu t-only signal reset s the e ntire MCU. Whi le RESET is asserted,

the MCU asserts the RESETOUT signal.

RESETOUT M → S Reset outpu t. This output-on ly s ignal in dicate s tha t the MCU is in reset.

When asserted, instructs all devices monitoring this signal to reset all

parts within themselves that can be reset by software.

CLKOUT Source → M, S Continuously-runni ng clock. All signals driven on the E-bus must be syn-

chronized to the rising edge of this clock.

Table 5-6 Address Type Encodings

AT0 AT1 Address Space

0 0 User data space

0 1 User instruction space

1 0 Supervisor data space

1 1 Supe rviso r instruction sp ace

Table 5-5 EBI Signal Descriptions (Continued)

Mnemonic Direction Description

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-15

5.4.3 Basic Bus Cycle

The basic external bus cycle consists of two phases: the address phase and the data

phase. If the external bus is not available when the SIU is ready to start an external

cycle, a bus arbitration phase is also required.

External bus cycles can be single or multiple (burst) data cycles. Burst cycles normally

have four data words associated with the cycle. Refer to 5.4.6 Burst Cycles for infor-

mation on burst cycles.

5.4. 3.1 Read Cycle Flow

Figure 5-4 is a flow diagram of a single read cycle on the external bus.

Table 5-7 Byte Enable Encodings

Byte Enable Use During 32-Bit Port Access Use During 16-Bit Port Access

BE0 Byte Enable for DATA[0:7] Byte Enable for DATA[0:7]

BE1 Byte Enable for DATA[8:15] Byte Enable for DATA[8:15]

BE2 Byte Enable for DATA[16:23] ADDR30

BE3 Byte Enable for DATA[24:31] 0 = Operand size is word

1 = Operand size is byte or half word

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Figure 5-4 Flow Diagram of a Single Read Cycle

Figure 5-5 is a simplified timing diagram of a read cycle.

MASTER SLAVE

REQUEST BUS

BUS GRANT

ASSERT BUS BUSY

RECEIVED

BUS BEING

DRIVEN BY ANOTHER

ASSERT TRA NSFER

DRIVE ADDRESS

START

AND ATTRIBUTES

CAN SLAVE

PIPELINE?

ASSERT ADDRESS

ACKNOWLEDGE

RETURN DATA

ASSERT TRANSFER

ACKNOWLEDGE

ADDRESS

ACKNOWLEDGE

ALREADY ASSERT ADDRESS

ACKNOWLEDGE

RECEIVE ADDRESS

RECEIVE DATA

MASTER?

IS BUS

GRANTED?

ASSERTED?

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-17

Figure 5-5 Example of a Read Cycle

5.4.3.2 Writ e Cycle Flow

Figure 5-6 is a flow diagram of a single write cycle on the external bus.

ADDR &

DATA

AACK

PIPELINED ADDRESS

CLKOUT

ATTRIBUTES

REQUEST BUS & RECEIVE GRANT

BEGIN DRIVING AD DRES S AND ASSE RT TS

RECEIVE AACK (COULD STOP DRIVING ADDRESS HERE)

DATA RETURN FOR THE READ

WAIT ONE CLOCK

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Figure 5-6 Flow Diagram of a Single Write Cycle

5.4.4 Basic Pipeline

The EBI supports a maximum pipeline depth of two; that is, up to two addresses can

be active on a bus at the same time. Pipelining is simplified by using SIU chip selects,

since chip-select registers can have the information about the characteristics of each

external memory. 5.5 Chip Selects discusses which cycles can be pipelined.

The EBI supports pipelined accesses for read cycles only. A write bus cycle starts only

when the pipe depth is zero, or would have gone to zero if a new cycle had not started.

A read bus cycle will start when the pipe depth is either zero or one, or would have

gone to one if a new cycle had not started.

An exam ple of bus pi pe l in i ng is shown in Figure 5-7.

TRANSFER COMPLETE

MASTER SLAVE

REQUEST BUS

BUS GRANT

ASSERT BUS BUSY

RECEIVED

BUS BE ING

DRIVEN BY ANOTHER

ASSERT TRA NSFER

DRIVE ADDRESS

START

AND ATTRIBUTES

CAN SLAVE

PIPELINE?

ASSERT ADDRESS

ACKNOWLEDGE

ADDRESS

ACKNOWLEDGE

ALREADY

RECEIVE ADDRESS

DRIVE DATA

TRANSFER

ACKNOWLEDGE N

RECEIVED?

IS BUS

GRANTED?

MASTER?

ASSERTED?

LATCH DATA

ASSERT TRANSFER

ACKNOWLEDGE

ASSERT ADDRESS

ACKNOWLEDGE

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-19

Figure 5-7 Example of Pipelined Bus

Figure 5-8 illustrates a write access followed by two read accesses on the external

bus.

Figure 5-8 Write Followed by Two Reads on the E-Bus (Using Chip Selects)

ADDRESS PHASE

DATA PHASE

CLKOUT

PIPE DEPTH 01222

W1 R1

0211 1 11122

CLKOUT

R1 R2

ADDR

DATA

AACK

CE1

OE1

CE2

OE2

WE2

ADDR-PHASE

DATA-PHASE

EBI-PIPE-

DEPTH

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5.4.5 Bus Cycle Phases

The following paragraphs describe the three bus cycle phases: arbitration phase,

address phase, and data phase. Note that there is no separate arbitration for the

address a nd data buses.

5.4.5.1 Arbitration Phase

The SIU supports multiple masters but is optimized for single-master systems. Each

master m ust h ave bu s req ue st, bus grant, an d bus bu sy si g nals. Ar bi tra ti on si gn als o f

the masters feed into a central arbiter for arbitration.

Before the SIU can start a n ext ernal cycle, it must ha ve a qual ified b us grant. A qual i-

fied bus grant occurs when the external arbiter asserts BG (bus grant) and the

previous bus master negates BB (the bidirectional bus busy signal). This means that

no other master is currently running a cycle on the external bus. If the SIU is ready to

start an external cycle and it does not have a qualified bus grant, then it asserts BR

(bus request) until it receives the qualified bus grant. Once the SIU receives a qualified

bus grant, it asse rts BB and begins the address phase of the cycle.

A word-aligned access to a 16-bit port results in two bus cycles. To preserve word

coherency, the SIU does not release the bus between these two cycles.

The exter nal arbiter can park th e bus by keeping BG asserted. Single-master systems

should tie this signa l low perma nently, or config ure the pin as a port pin, which has th e

same effect. Each potential master has its own BG input signal.

5.4.5.2 Address Phase

Once the SIU has a qualified bus grant, it asserts BB and starts an address phase. The

SIU drives a new address at the start of the address phase and maintains it on the pins

throughout the address phase.

The signals shown in Table 5-8 are driven at the start of the address phase.

TS is a control signal that is valid for only one clock cycle at the start of the address

phase. The address attributes listed in Table 5-8 are updated at the start of the

address phase and are maintained until the start of the next address phase.

Table 5-8 Signals Driven at Start of Address Phase

Mnemonic Signal Name Type

ADDR[0:29] Address bus Address bus

TS Transfer start Control

WR Write/read Address attribute

BE[0:3] Byte enables Address attribute

AT[0:1] Address type Address attribute

CT[0:3] Cycle type Address attribute

BURST Burst Address attribu te

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-21

The address phase is the period of time from the assertion of TS until the address

phase is terminated by one of the following signals:

• Address a cknowledge (A ACK)

• Address retry (ARETRY)

• Transfer error acknowledge (TEA)

If the exte rnal m emory is un der chip- select con trol and th e chip select s are enab led to

return handshakes, then the chip selects normally generate AACK internally. How-

ever, if the external AACK pin is asserted bef ore the chip se lect mo dule gene rates the

signal, the chip select module accepts the external pin information and does not gen-

erat e the A ACK signal internally.

Burst inhibit (BI) is sampled when AACK is asserted. BI is asserted by the slave to indi-

cate to the SIU that the addressed device does not have burst capability. Refer to

5.4.6.2 Burst Inhibit Cycles for more information.

ARETRY an d TEA can also be used to terminate the address phase. Refer to 5.4.10

Address Re t ry and 5.4.11 Transfer Error Acknowledge Cycles for more infor mation.

5.4.5.3 Data Phase

If the pipe depth before a cycle starts is zero (or would have gone to zero if the new

cycle had not started), then the data phase always starts one clock cycle after the

addr ess phase starts. If there is a previou s data phase in progress one clock after an

address phase starts, then the data phase for that address phase starts as soon as

the prev ious da ta phas e complet es. The da ta phas e comple tes when it is term inated

by T A or TEA. If the cycle is a burst cycle, then multiple TA assertio ns ar e r eq uir ed to

terminate the data phase.

During the data phase, the following signals are used:

• DATA[0:31]

• Burst data in progress (BDIP)

The data phase can be terminated with either of the following signals:

• Transfer acknowledge (TA)

• Transfer error acknowledge (TEA)

AACK and TA are required for every cycle. If, under some error condition, the slave

asserts TA but not an AACK, the SIU do es not rec over from this error condition.

If the external memory is under chip-select control and the chip selects are pro-

grammed to return handshakes (ACKEN = 1 in the chip-select option registers), then

the chip selects return TA unless the extern al TA pin is asserted first . In that case, the

chip select module accepts the external pin information and does not generate TA

internally.

A bus timer or system address protection mechanism can assert transfer error

acknowledge (TEA) to terminate the data phase when a bus error condition is encoun-

tered. Refer to 5.4.11 Transfer Error Acknowledge Cycles for further informatio n.

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The EBI asserts the data strobe (DS) signal at the end of a chip-s elect controlled bus

cycle, provided that either

• The chip select unit asserts the internal TA signal; or

• The bus monitor timer asserts the internal TEA signal.

DS is not asse rt ed, how e ver , i f TA or TEA is asserted externally, even if TA or TEA is

simultaneously asse rted internally.

In addition to being asserted at the end of the bus cycles mentioned above, DS is

asserted at the end of a show cycle.

5.4.6 Burst Cycles

Burst cycles allow the fast transfer of instructions ove r the bus. The MPC509 supports

fixed-length burst cycles of four beats for instruction reads only. Burst cycles can be

terminated early with the BDIP signal.

Burst re ads on the exte rnal bus do not start until the intern al data bus is avail able. For

example, when the SIU starts a burst read and does not have L-bus data bus grant

because there is an L-bus cycle in progress (an IMB2 access), then the SIU holds off

the burst read until it can guarantee that it will have the internal bus grant.

At the start of a burst transfer, the master drives the address, the address attributes,

transfer start, and the BURST signal to indicate a burst transfer. If the slave can per-

form burst transfers, it negates the burst inhibit signal (BI). If the slave does not support

burst transfers, it asserts BI.

An example of a burst read on the external bus is shown in Figure 5-9.

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-23

Figure 5-9 External Burst Read Cycle

5.4.6.1 Termination of Burst Cycles

During the data phase of a burst read cycle, the master receives data from the

addressed slave. The EBI asserts the BDIP signal at the beginning of a burst data

phase and negates BDIP during the last beat of a burst. The slave device stops driving

new data after it receives the negation of BDIP at the rising edge of the clock.

The EBI can terminate a burst cycle early by asserting the BDIP pin. Early termination

is used for a word aligned (not double-word aligned) burst to a small port.

The LST bi t in t he SIU m odul e configu ration regist er (S IUMCR) deter mine s the ti ming

used for the BDIP pin. If LST is cl eared, the n the pin u ses BDIP timin g. If the bit is se t,

the pin uses LAST timing. The timing protocol of the external memory determines

whethe r this bit should be set or cl eared. Refer t o 5.5.16.6 Synchronous Burst Inter-

face for examples of both types of timing.

Burst cycles can also be terminated with th e ARETRY signal . Refer to 5.4.10 Address

Retry for more information.

5.4.6.2 Burst Inhibit Cycles

Burst inhibit (B I) is an address phase termination attribute that is sampled when AACK

is asserted. The slave asserts BI to indicate to the SIU that the addressed device does

not have burst capability. If this signal is asserted, the SIU transfers the data in multiple

cycles and increments the address for the slave in order to complete the burst transfer.

ADDR

BURST

DATA

BDIP

AACK

PIPELINED ADDRESS

LAST DATA

NEXT DATA

CLKOUT

WAIT STATE D1 D2 D3 D0

ADDR

DATA

D1 D2

PHASE

PHASE A1

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A burs t can o nly be b urst in hibit ed u ntil th e first data is a ckno wledg ed (TA asserted ).

Sinc e BI is not sampled until AACK is asserted, AACK must be a sser te d bef or e or at

the same time as TA. Otherwise, the BI pin is ne ver samp le d.

The EBI supports three types of memory. These memory types use the AACK and BI

signals as follows:

• A simple asynchro nous memory keeps AACK negat ed to keep the address va lid.

The device can assert BI along wit h AACK or before AACK and with the first TA.

• A synchro nous, pipelineable, non-burstab le memory returns AACK as soon as it

is ready to receive the next address and asserts BI.

• A burstable memory returns AACK and negates BI along with AACK or before

AACK.

CAUTION

If a memory region is under chip-select control, the chip-select unit

generates BI internally during burst accesses to interface types that

do not su ppor t burst acce sses. It i s reco mmende d that the BI pin no t

be asserted during accesses to memory regions controlled by chip

selects; instead, the chip-sele c t unit will generate the BI signal inter-

nally when appropriate.

5.4.7 Decomposed Cycles and Address Wrapping

If a burst cycle initiated by one of the internal buses is burst inhibited by the chip

selects or by the pins, the EBI decomposes this cycle into four single beat accesses.

The EBI increm en ts the a ddr e ss i nte rnal l y and sends th e re cei ve d d ata (fro m the fo ur

single external reads) back to the originating bus as a burst transaction.

The EBI breaks a burst access to a device with a 16-bit port into two or three cycles,

depending on the starting address (or eight cycles if BI is asserted) and increments the

address appropriately. Examples of burst access address wrapping are shown in

Table 5-9. If a burst access to a device with a 16-bit port is burst inhibited by the chip

selects or by external memory asserting the BI pin, th e EBI de compo ses th e tra nsfe r

into eight single-beat accesses.

Depending on the starting address for the burst access and whether the address is

word- or double-word-aligned, the EBI wraps the address to fetch the correct data from

memory (four words or ei ght hal f words).

If the EBI receives TEA for one part of a decomposed cycle, it generates TEA internally

for the remaining parts of the decomposed cycle as well.

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-25

5.4.8 Preventing Speculative Loads

The SIU can be programmed to prevent speculative loads to a selected external

region. A speculative operation is one which the hardware performs out of order and

which it otherwise m ight not perf orm, such as ex ecuting an in struction follo wing a con-

ditional branch.

Note that the MPC509 never performs speculative stores; it always waits until the

instruction is ready to be retired before writing to external memory. Refer to the

RCPU

Reference Manual

(RCPU R M/AD) for more information.

When data loaded speculatively from RAM later needs to be discarded, this does not

ordinarily present a problem. For example, a load instruction that follows a floating-

point instruction in the instruction stream could begin execution before the floating-

point in str uct io n is re ti red. If t he fl oa ti ng -p oint in st ruct ion ge n erat es an e xcep t ion, t he

result of t he lo ad ins tructi on is discarde d, the excep tion i s pro cessed, a nd the p roces-

sor autom ati ca l ly re -i ssu es the load inst ru cti on .

However, if the address of the speculat ive load repres ents a FIFO device, t he specu-

latively loaded data is lost when the exception is processed, and the re-issued load

instru ction lo ads the next da ta ite m in the q ueue. Preve nting spe culat ive loads i s nec-

essary to prevent this scenario from occurring.

Table 5-9 Burst Access Address Wrapping

Port Size Starting Address

ADDR[28:30] Burst Address Wrapping

ADDR[28:30] Half-Word/Word Boundary Address

16 bit 000

000 (Starting address)

001

010

011

100

101

110

111

Double word boundary,

Two bursts of four beats each

16 bit 010

010 (Starting address)

011

100

101

110

111

000

001

Odd word boundary,

One burst of two beats

One burst of four beats

One burst of two beats

The mas ter (the EBI) terminates the two-

beat-burst with BDIP.

32 bit 000

000 (Starting address)

010

100

110

Quad word boundary

One burst of four beats

32 bit 100

100 (Starting address)

110

000

010

Double (non-quad) word boundary

One burst of four words (word 3-4-1-2)

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As another example, a memory-mapped I/O device could have a status register that

is updated whenever its data register is read. If the data register is read speculatively,

the status register is updated, even if the result of the read is subsequently discarded

(for example, if a previously issued instruction generates an exception).

Two regi st er s an d th eir ass o ciat e d l ogi c al low a bl ock ran gin g i n si ze from 1 K byt e to

64 Kbytes, or parts of the b lock, to be pr otecte d from spe culative accesses. The most

significant 22 bits of the add ress of each L-bus cycle are bitwise compared to the non-

speculative base address register (SPECADDR), with each result bit equal to one if

the bits match. A bitwise OR is performed on the lower six bits of the resulting word

with the mask in the non-speculative mask register (SPECMASK). If all six result bits

are ones and the upper 16 result bits are all ones, then speculative accesses are pre-

vented during the current cycle.

Because the mask register can contain any six-bit value, the mask can allow for blocks

of up to 64 Kbytes, and it can provide for smaller blocks of memory that alternately

allow and prevent speculative loads. Table 5-12 provides several examples. In these

examples, the protected blocks are those that match the value in the SPECADDR

SPECADDR — Non-Speculative Base Address Register 0x8007 FC24

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

BASE ADDRESS RESERVED

RESET:

00000000000000000000000000000000

Table 5-10 SPECADDR Bit Settings

Bit(s) Name Description

0:21 BASE ADDRESS 22-bit base address of region protected from speculative loads.

22:31 — Reserved

SPECMASK — Non-Speculative Mask Register 0x8007 FC28

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED MASK RESERVED

RESET:

00000000000000000000000000000000

Table 5-11 SPECMASK Bit Settings

Bit(s) Name Description

0:15 — Reserved

16:21 MASK Six-bit mask th at s pec ifies whi ch blo ck or b loc ks wit hin reg ion sp ec ifie d i n SPECMASK reg-

ister are actually protected from speculative accesses.

22:31 — Reserved

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USER’S MANUAL Rev. 15 June 98 5-27

Protection from speculative loads can be disabled by setting the SPECADDR register

to an internal or unimplemented address range.

5.4.9 Accesses to 16-Bit Ports

The EBI supports accesses to 16-bit ports on the external bus. 16-bit port size is a

chip-select option; the access must be initiated using one of the chip selects. A 16-bit

port must connect its data lines to the upper 16 bits of the external data bus

(DATA[0:15]).

During an access to a 16-bit port, byte enable signals BE[0:1] are used to indicate

which bytes of the half-word are being accessed, and the BE2/ADDR30 pin functions

as ADDR30 (active high). BE3 is asserted (low) if the operand size is a word and

negated (high) if the operand size is a byte or half-word. This encoding is needed to

maintain coherency of word accesses on the external bus.

Table 5-13 shows how EBI decomposes the word, half word, and byte accesses to a

16-bit port. For each combination of operand size and address (placement on the inter-

nal L-data bus), the table shows the values of BE[0:3] and indicate s which bytes of th e

operand ar e accessed and where t hese b ytes are placed o n the E-bus.

All transfer errors that occur during a small port access terminate the cycle currently

in progress. If an error occurs during any part of a word access to a small port, the cur-

Table 5-12 Example Speculative Mask Values

Mask Value

(Binary) Protected Region

000000 1-Kbyte block

111111 64-Kbyte block

111110 Every second 1-Kbyte block within a 64-Kbyte block

111101 Every second 2-Kbyte block within a 64-Kbyte block

110011 Every fourth 4-Kbyte block within a 64-Kbyte block

100011 Every eighth 4-Kbyte block within a 64-Kbyte block

010000 Every sixteenth 1-Kbyte block within a 32-Kbyte block

Table 5-13 EBI Read and Write Access to 16-Bit Ports

Operand

Size Internal L-Bus

ADDR[30:31] Internal L-Bus Data

Bytes Accessed BE[0:3] Placement of L-Bus Data Bytes On E-Bus

E-Bus DATA[0:7] E-Bus DATA[8:15]

Byte 00 Byte 0 0101 Byte 0 X

Byte 01 Byte 1 1001 X Byte 1

Byte 10 Byte 2 0111 Byte 2 X

Byte 11 Byte 3 1011 X Byte 3

Half Word 00 Bytes 0 to 1 0001 Byte 0 Byte 1

Half Word 10 Bytes 2 to 3 0011 Byte 2 Byte 3

Word 00 Bytes 0 to 3 0000

0010 Byte 0

Byte 2 Byte 1

Byte 3

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rent access is terminated. Subsequent bus cycles of the small port access will

continue, but TEA will be asserted internally with each b ea t.

5.4.10 Address Retry

Address retry (ARETRY) can be used to terminate the address phase. Assertion of

ARETRY causes the master to re-arbitrate and to re-run the bus cycle. The address

retry mechanism can be used to break deadlocks between the E-bus and the user’s

on-board I/O bus (for example, a PC/AT or VME bus in a hierarchical bus system). The

address retry mechanism can also be used for error correction purposes.

After receiving TS, the external device must wait at least one clock cycle before assert-

ing ARETRY. Note t hat th is could b e an iss ue at lo w freq uencies — it is p ossi ble for

an external device to receive TS, decode the address, and assert ARETRY in the

same clock cycle. This is illegal.

The SIU does not guarantee word coherency if ARETRY is asserted for the second

half of a word cycle of a d ecomposed word transfer. The external arbiter is responsible

for maintaining the coherency by monitoring the byte enable lines and making sure

that no other master updates that location until the retried cycle is successfully

completed.

Note that BB is not negated until the second clock cycle after ARETRY assertion.

CAUTION

TA or TE A must not be asserted during a cycle in which ARETRY is

asserted. If TA is asserted for any part of a burst cycle, ARETRY

must not be asserted at any time during the cycle; if ARETRY is

asserted during a burst cycle, it must be asserted before the first beat

is terminated with TA.

5.4.11 Transfer Error Acknowledge Cycles

A bus timer or system address protection mechanism can assert transfer error

acknowledge (TEA) to terminate the data phase when one of the following types of bus

error conditions is encountered:

• Write to a read-only address space

• Access to a non-existent address

TEA assertio n override s the assert ion of TA. Assertion of TEA causes the processor

to enter the checkstop state, enter debug mode, or process a machine check excep-

tion. Refer to the

RCPU Reference Manual

(RCPURM/AD) for details.

CAUTION

TEA must not be asserted during a cycle in which ARETRY is

asserted.

If the address phase corresponding to the current data phase is still outstanding

(AACK has not yet been asserted), TEA terminates both the address and the data

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-29

phase. That is, the EBI generates AACK and TA internally and generates an internal

error signal for that cycle. If AACK has alrea dy bee n asserted ex ternal ly, the EBI ge n-

erates TA but not AACK internally and generates an internal error signal for that cycle.

All transfer errors that occur during an access to a 16-b it port terminate the cycle cur-

rently in progress. If an error occurs duri ng any part of a word acces s to a 16-bit port,

the current access is terminated. Subsequent bus cycles of the small port access will

continue, but TEA will be asserted internally with each b ea t.

All ill egal ac cesses to inter nal r egisters are te rminated with a da ta erro r, causi ng the

bus monitor to assert the internal TEA signal. Accesses to unimplemented internal

memory locations and privilege violations (user access to supervisor register or write

to read-only location or a write to register which is locked) also cause the bus monitor

to assert the internal TEA signal .

Note that the chip-select module can also assert the internal TEA signal. Refer to 5.5.7

Access Protection for more information.

5.4. 12 Cy cle Types

The cycle type pins (CT[0:3]) are address-phase signals that provide information

about the type of internal o r external b us cycle in progress. The se pins can be use d by

an external development system to construct a program trace.

Table 5-14 summarizes the cycle type encodings. Refer to the

RCPU Reference Man-

ual

(RCPURM/AD) for details on how a development system can use the information

provided by these pins.

Table 5-14 Cycle Type Encodings

CT[0:3] Cycle Type Description

0000 Normal bus cycle

This is a normal external bus cycle. Both the address and data phase

are see n on the ex ternal bus. This cycle requires an AACK and a TA sig-

nal. This cycle type is used for sequential fetches and for prefetches of

predi cte d bra nch targe ts whe re the branch c ondition ha s not b een eval-

uated before the prefetch. It is also used for all non-reservation type

load/store cycles.

0001

Reservation start if

address type is data

Instruction fetch marked

as indire ct change -of-flow if ad-

dress

type is instru ction

If the address type is data (AT1 = 0), then this is a data access to the

external bus. Both the address and the data phase are seen on the ex-

ternal bus. This cy cl e req ui r es a n AACK and a TA signa l. When this cy -

cle starts, external snooping logic should latch the address to track the

reservation.

If th e address type is instr uction (AT1 = 1), then this is an instruction

fetch cycle marked as an indirect change-of-flow cycle. Both the address

and the da ta phase are se en on the ext ernal bus. This cycle requires an

AACK and a TA signal. This cycle type is used when an external ad-

dress is the destination of a branch instruction or the destination of an

exception or VSYNC cycle.

0010 E mul ati on m em ory se le ct (no t

supported in MPC509)

This is a s pecial extern al bus cycle to emu lation memor y replacing int er-

nal I-mem or L-mem (and not resul ting in a cache hit). The MPC509

does not support this cycle type.

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5.4.13 Show Cycles

Internal bus cycles that are echoed on the external bus are referred to as show cycles.

By providing access to bus cycles that are not visible externally during normal opera-

tion, show cycles allow a developmen t supp ort system to trace the flow of a program.

The LSHOW field in the SIUMCR can be programmed to cause the EBI to echo certain

or all internal L-bu s cycles on the e xternal bu s. Likewise, the ISCTL field in the ICTRL

to cause the EBI to echo certain or all internal I-bus cycles on the external bus.

0011 PRU sele ct (not su pported in

MPC509)

This is a normal external bus cycle access to a port replacement chip

used for emulation support. Both the address and the data phase are

seen o n the e xternal bus . This c ycle requ ires an AACK and a TA signal.

It indicates that an access was made which would have gone to an in-

ternal port control register if the chip were not operating in PRU mode.

0100 I-mem (not supported in

MPC509) These are internal visibility cycles. This cycle is self-terminating and

does not require AACK and TA signals. These encodings indicate that

an access or ab orted fetc h (resultin g from eith er a cache hit or a sp ecu-

lative load that is subsequently discarded) was made to an address on

the internal I-bus or L-bus. An instruction access (AT1 = 1) with an ad-

dress which is an indirect branch target is indicated as a write on the WR

signal.

The I-Mem cycle type is not supported in the MPC509.

0101 L-mem

0110 E-Mem (external memory)

cache hit, not using a chip se-

lect

This is an internal visibility cycle. It always has an address phase and

includes a data phase for data accesses. This cycle is self-terminating

and does not req uire AACK and TA signals. It indicates that an access

was made to an address on the external bus and that a cache hit or

aborted fetc h occurred. An instru ction access with an ad dress that is an

indirect branch target is indicated as a write on the WR signal.

0111 Internal register

This is an int ernal v isibi lity c ycle . It alway s has an add ress p hase and a

data phase. This cycle is self-terminating and does not require AACK

and TA sig nals. It in dic ate s that an ac ce ss w as ma de to a c ont rol regis-

ter or internal IMB2 address. These accesses are always cache-inhibit-

ed.

1000 E-Mem cache hit

to CSBOOT re gion

These are internal visib ility cycles. Th ey always have an address phas e

and include a data phase for data accesses. These cycles are self-ter-

minatin g and do not requi re AACK an d TA sign als. Th ese en codin gs in-

dicate that an ac ce ss w as m ade to an addres s o n t he e xt ernal bus and

that a cache hit or aborted fetch occurred. An instru ction access with an

address that is an indirect branch target is indicated as a write on the

WR signal.

The region indicated is the main chip-select region, not the sub-region.

1001 E-Mem cache

hit to CS1 region

1010 E-Mem cache

hit to CS2 region

1011 E-Mem cache

hit to CS3 region

1100 E-Mem cache

hit to CS4 region

1101 E-Mem cache

hit to CS5 region

1110 Reserved —

1111 Reserved —

Table 5-14 Cycle Type Encodings (Continued)

CT[0:3] Cycle Type Description

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-31

The I-bus show cycles are always address-only cycles. They do not wait for the inter-

nal transaction to complete. L-bus show cycles have both address and data and

appear on the external bus after the internal cycle is completed.

Aborted L-bu s cycles do not result in a sh ow cycle. (The loa d/store unit of the proces-

sor may abort the cycle when the previous cycle terminates with a transfer error, or

when an exception occurs during the current cycle.)

Aborted I-bus cycles do result in a show cycle. (The processor may abort an I-bus

cycle when it encounters a branch ; it aborts the fetch just starting on a wrong path. In

addition, the processor aborts the cycle on a cache hit.)

Note that I-bus show cycles are not burst.

A show cycle involves transfer start (TS), address (ADDR), cycle type (CT), address

type (A T), burst (BUR ST) and re ad/w rite ( WR) pins. The data phase of an L-bus show

cycle looks like a write cycle going out on the external bus. The address and data

phases of a sho w cycle last one clock cycle each . No terminatio n is need ed for either

phase, as all show cycles are automatically terminated inside the SIU. For the L-bus

show cycles (I-bus show cycles are address only), the data phase always follows the

address phase by o ne clock cycle. The L-bus show cycle does not sta rt until the inter-

nal cycle completes. This allows all show cycles to complete in two clock cycles.

Show cycles require several holding registers in the SIU to hold address and data of

an L-bus cycle and addre ss of an I-bus cycle until the E-bus is availab le and the show

cycle is run. When these holding register s are full, the interna l bus (or buses) are held

up by the SIU while it waits for the show cycle to complete.

During cross-bus accesses, the show cycle is associated with the bus initiating the

transaction. For example, if I-bu s show cycles are en abled and L-bus sh ow cycles are

disabled, then an instruction fetch from L-RAM will show up as an address-only I-bus

show cycle, and an L-bus access to I-memory would not have a show cycle.

Refer to SECTION 8 DEVELOPMENT SUPPORT for more information on show

cycles.

5.4.14 Storage Reservation Support

The PowerPC lwarx (load w ord a nd re serv e index ed) and stwcx. (s tore wo rd condi -

tional indexed) instructions in combination permit the atomic update of a storage

location. Refer to the

RCPU Reference Manual

(RCPURM/AD) for details on these

instructions.

The storage reservation protocol supports a multi-level bus structure like the one

shown in Figure 5-10. In this figure, the E-bus is a PowerPC bus interfaced to a non-

local bus, such as a PC/AT or VME bus, through a non-local bus interface. For each

local bus, storage reservation is handled by the local reservation logic.

The protocol tries to optimize reservation cancellation such that a PowerPC processor

is noti fied of the l oss of a storage r eservation on a remo te bus only wh en it has issue d

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5-32 Rev. 15 June 98 USER’S MANUAL

a stwcx. instruction to that address. That is, the reservation loss indication comes as

part of the stwcx. cycle. This method eliminates the need to have very fast storage

reservation loss indication signals routed from every remote bus to every PowerPC

master.

Figure 5-10 Storage Reservation Signaling

5.4.14.1 PowerPC Architecture Reservation Requirements

The PowerPC architecture requires that the reservation protocol meets the following

requirements:

• Each PowerPC processor has at most one reservation.

• The lwarx instruction establishes a reservation.

• The lwar x instruction by the same processor clears the first reservation and es-

tablishes a new one.

• The stwcx. instruction by the same processor clears the reservation.

• A normal store by the same processor does not clear the reservation.

• A norm al store by some other pr ocessor (or othe r mechanis m, such as a DMA )

to an address with an existing reservation clears the reservation.

• If the storage reservation is lost, it is guaranteed that stwcx. instruction will not

modify storage.

• The granularity of the address compare is a multiple of the coherent block size

(which should be a multiple of four bytes).

ARETRY

CT[0:3]

E-BUS

SNOOP

LOGIC

CT[0:3]

NON-LOCAL

BUS

INTERFACE

ARETRY

MCU NON-LOCAL

BUS

SIU

BUS

MASTER

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-33

5.4.14.2 E-bus Storage Reservation Implementation

The E-bus reservation protocol requires local (external) bus reservation logic, if

needed, to:

• Snoop accesses to all local bus slaves.

• Hold one reservation for each local master capable of storage reservations.

• Set th e reserv ation when that mas ter issues a load with rese rvation .

• Clear the rese rvation when so me other master issu es a store to the reserva tion

address.

• Indicate the current status of the local bus reservation such that it may be sam-

pled prior to the address phase of the stwcx. bus cycle. (The reservation must b e

set in time to enable a store to the reservation address, and must be cleared fast

enough to disable a store to the reservation address).

The EBI samples the CR pin prior to starting an external stwcx. cycle. If the reserva-

tion is can celled (CR is asserted), no cycle starts. If the reservation is not cancelled,

the SIU begins the bus cycle.

If ARETRY is asser ted , th e SIU must re - s ampl e the CR and BG pins prior to perform-

ing the external retry.

If a reservation exists on a non-local bus, and the SIU begins a stwcx. cycle to that

address on the local bus while the non-local bus reservation is cleared, the ARETRY

signal should be asserted to the SIU, and the reservation signal should be cleared

before BG is asserted to the SIU. This means that AACK should not be returned until

successful coherent completion of the stwcx. i s ensu re d. The non - lo cal bu s inter fa c e

must no t per form th e non -local write (o r abo rt it i f the bus su ppor ts aborte d cyc les) i f it

asserts ARETRY.

NOTE

Single-master systems do not require an external reservation track-

ing logic. In these systems, the CR pin should be tied by resistor to

the reservation valid (high) state. Alternatively, the reservation pin

may be co nfig ur ed as a port. If t he r e ser vati o n p in is con fi gu red a s a

port, the SIU will always consider the reservation to be valid.

5.4.14.3 Reservation Storage Signals

Reservation storage signals used by the EBI are summarized in Table 5-15.

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5.5 Chip Sel ects

Typical microcontrollers require additional hardware to provide external chip-select

signals. In the MPC500 family, the chip-select logic controls the slaves of typical uni-

processor systems. This allows the user to implement simple systems without the

need to design any external glue logic.

Figure 5-11 is an example of a typical u niproce ssor syste m. This kind of system usu-

ally consists of a CPU, some memories, and some peripherals. In single-master

systems the CPU is the only de vice that can b e a bus maste r on the E-b us; memories

and peripherals are slaves.

Figure 5-11 Simplified Uniprocessor System with Chip-Select Logic

Table 5-15 EBI Storage Reservation Interface Signals

Name Direction Description

CR Snoop logic ⇒ SIU Can cel reservation. Eac h PowerPC CPU has its own

CR signal. This signal shows the status of any out-

standing reservation on the external bus. When as-

serted, CR indicates that there is no outstanding

reservation. This is a level signal.

ARETRY Non-local bus interface ⇒

SIU Address retry. When asse rted, indicates that the mas-

ter needs to retry its address phase.

In case of an stwcx. cycle to a non-local bus on which

the storage reservation has been lost, this signal is

used by the non-local bu s interface to ba ck off the cy-

cle.

PERIPHERAL PERIPHERAL

EPROM SRAM

EXTERNAL BUS

CPU

INTERNAL

L/I-BUS

CEs, WEs, OEs

MCU

EBI

CHIP

SIGNALS

SELECT

MODULE

CEs, WEs, OE s

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-35

The chip-select module provides the necessary control signals, such as the chip

enable (CE), write enable (WE), and output enable (OE), for the external memory and

periphe ral d evices. In ad ditio n, the chip -sel ect m odule provide s so me h andshak es for

the external bus and some limited protection mechanisms for the system.

5.5.1 Chip-Select Features

• No external glue logic required for typical systems if the chip-select module is

used.

• Modular architecture for ease of expansion.

• Twelve chip-select pins plus one CSBOOT pin.

• Pins can be programmed as CEs (six ma ximum), OEs, or WEs.

• Capable of supporting pipelineable, burstable devices.

• Returns bus handshake signals for the selected address regions.

• Provides up to seven programmable wait states for slave devices.

• Controls the clocking of data to the slaves during write cycles.

• Keeps slave sequentially consistent (data in the same order as addresses).

• Progra mmability for:

— Latching and non-latching device types.

— Burstable and non-burstable device types.

• Programmable address ra nge and block size.

• Programmable burst features:

— Interruptible burst on any burstable device.

— Pipelineable with other devices during burst cycle.

— Supports two different burst protocols.

• Supports pipe lin eabl e access es

— Up to two concurrent accesses can be outstanding to two different regions

(one access to each region).

— For two consecutive accesses to the same region, overlaps the address phase

of the second access with the data phase of the first access.

• Allows multi-level protection within a region. The CSBOOT regio n can have up to

two sub-levels of protection.

• Supports both 16-bit and 32-bit port sizes.

5.5.2 Chip-Select Block Diagram

Figure 5-12 shows the functional block diagram of the chip-select module.

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-36 Rev. 15 June 98 USER’S MANUAL

Figure 5-12 Chip-Select Functional Block Diagram

5.5.3 Chip-Select Pins

The pin configuration (PCON) field in each chip-select option register configures the

associated pin to function as a chip enable (CE), write enable (WE), output enable

(OE), or alternate-function pin. For pins configured for their alternate function, the port

A pin assignment register configures the pin as either an address bus signal

(ADDR[0:11]) or a port A or B output signal (PA[0:7] and PB[0:3]). Notice that the

CSBOOT pin has no alternate function.

Table 5-16 describes the chip-select pins.

PIN N

PIN 1

ADDRESS DECODER

CONTROL

UNIT

BASE

ADDRESS

OPTION

PIN CONFIGURATION

LOGIC CIRCUIT PIN 0

ADDRESS DECODER

CONTROL

UNIT

BASE

ADDRESS

OPTION

PIN CONFIGURATION

LOGIC CIRCUIT

ADDRESS DECODER

CONTROL

UNIT

BASE

ADDRESS

OPTION

PIN CONFIGURATION

LOGIC CIRCUIT

TIMING

BUS

DECODE

BUS

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-37

NOTE

During the first two clock cycles of power-on reset, the state of the

pins listed in Table 5-16 is unknown.

When a chip select is configur ed as a chip enable o f a memory or I/O device , the MCU

asserts the chip select when it drives the address onto the external bus. For non-pipe-

lineable devices, the CE is asserted until the access is completed. For pipelineable

devices, when CE is asserted the device should clock in the address at the rising edge

of the clock. (Note that devices that the chip-select unit regards as pipelineable are

always synchronous.)

The WE signal is used during write accesses. When a chip select is configured as a

write enable signal of a memory or I/O device, the MCU asserts the chip select as it

drives data on to the extern al bus to signa l the external device to strobe in the data. For

synchronous devices, if WE is asserted the device should clock in the data at the rising

edge of the clock.

The OE signal is used during read accesse s. When the MCU asserts a chip-select sig-

nal that is configured as an output enable of a memory or I/O device, the device can

drive its dat a onto the E-bus.

5.5.4 Chip-Select Registers and Address Map

Chip-select registers are 32 bits wide. Reads of unimplemented bits in these registers

return zero, and wr ites hav e no effect.

Table 5-16 Chip-Select Pin Functions

Chip-Select Function Alternate

Function Pin Function in Chip-Select Mode

CSBOOT —Can be the CE of the system boot memory (power-on default). In sys-

tems with no external boot device, this pin can be configured as WE or

OE of EPROMs or SRAMs.

CS0/

CSBTOE ADDR0/PA0 Can be WE or OE of EPROMs or SRAMs. When configured as a chip

select, this pin is assigned to be the OE of the CSBOOT pin following

reset.

CS1 ADDR1/PA1 Can be CE, WE, or OE of EPROMs or SRAMs.

CS2 ADDR2/PA2 Can be CE, WE, or OE of EPROMs or SRAMs.

CS3 ADDR3/PA3 Can be CE, WE, or OE of EPROMs or SRAMs.

CS4 ADDR4/PA4 Can be CE, WE, or OE of EPROMs or SRAMs.

CS5 ADDR5/PA5 Can be CE, WE, or OE of EPROMs or SRAMs.

CS6 ADDR6/PA6 Can be WE or OE of EPROMs or SRAMs.

CS7 ADDR7/PA7 Can be WE or OE of EPROMs or SRAMs.

CS8 ADDR8/PB0 Can be WE or OE of EPROMs or SRAMs.

CS9 ADDR9/PB1 Can be WE or OE of EPROMs or SRAMs.

CS10 ADDR10/PB2 Can be WE or OE of EPROMs or SRAMs.

CS11 ADDR11/PB3 Can be WE or OE of EPROMs or SRAMs.

MOTOROLA SYSTEM INTERFACE UNI T MPC509

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One base address register and one option register are associated with each chip-

selec t pi n t ha t c an fun c ti on as a chip en ab le . The CSB OO T pin has a dedicated sub-

block for multi-level protection. It has two base address registers and two option reg-

isters. One option register is associated with each pin that can function as a write

enable or output enable but not as a chip enable.

Table 5-17 is an address m ap of th e ch ip -select mo dul e . As th e en tr i es in th e A ccess

column indicate, all chip-select registers are accessible at the supervisor privilege

level only.

When set, the LOK bit in the SIU module configuration register (SIUMCR) locks all

chip-select registers to prevent software from changing the chip-select configuration

inadve rtently. B efore ch anging the chip -select configura tion, t he user n eeds to ensure

that this bit is cleared.

Note that if the processor is modifying the chip-select registers of a region and it needs

the instructions from that region (a region that it is reconfiguring), software needs to

ensure that the code is accessible elsewhere. For example, if the processor is config-

uring the CSBOOT register s and simultan eously executi ng instructions out of the boot

region, software can re-locate the necessary code to the instruction cache, internal

SRAM, or to another external region such as external SRAM, before modifying the

chip-select control registers.

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-39

5.5.4.1 Chip-Select Base Address Registers

Base add ress registe rs contain t he base ad dress of the range of m emory to wh ich the

chip select circuit responds. All base address registers contain the same fields but

have different reset values.

Table 5-17 Chip-Select Module Address Map

Access Address Register

—0x8007 FD00 –

0x8007 FD90 Reserved

S 0x8007 FD94 CS11 Option Register (CSOR11)

S 0x8007 FD98 Reserved

S 0x8007 FD9C CS10 Option Register (CSOR10)

S 0x8007 FDA0 Reserved

S 0x8007 FDA4 CS9 Option Register (CSOR9)

S 0x8007 FDA8 Reserved

S 0x8007 FDAC CS8 Option Register (CSOR8)

S 0x8007 FDB0 Reserved

S 0x8007 FDB4 C S7 Option Register (CSOR7)

S 0x8007 FDB8 Reserved

S 0x8007 FDBC CS6 Option Register (CSOR6)

S 0x8007 FDC 0 C S5 Base Address Register (CSBAR5)

S 0x8007 FDC4 CS5 Option Register (CSOR5)

S 0x8007 FDC 8 C S4 Base Address Register (CSBAR4)

S 0x8007 FDCC CS4 Option Register (CSOR4)

S 0x8007 FDD 0 C S3 Base Address Register (CSBAR3)

S 0x8007 FDD4 CS3 Option Register (CSOR3)

S 0x8007 FDD 8 C S2 Base Address Register (CSBAR2)

S 0x8007 FDDC CS2 Option Register (CSOR2)

S 0x8007 FDE0 CS1 Base Address Register (CSBAR1)

S 0x8007 FDE4 C S1 Option Register (CSOR1)

S 0x8007 FDE8 Reserved

S 0x8007 FDEC CS0 Option Register (CSOR0)

S 0x8007 FDF0 CSBOOT Sub-Block Base Address Register (CSBTSBBAR)

S 0x8007 FDF4 CSBOOT Sub-Block Option Register (CSBTSBOR)

S 0x8007 FDF8 CSBOOT Base Address Register (CSBTBAR)

S 0x8007 FDFC CSBOOT Option Register (CSBTOR)

CSBTBAR — CSBOOT Base Address Register 0x8007 FDF8

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

BA RESERVED

RESET:

IP IP IP IP IP IP IP IP IP IP IP IP 00000000000000000000

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-40 Rev. 15 June 98 USER’S MANUAL

The reset value of the BA field in the CSBTBAR equals 0x00000 if the exception prefix

(IP) bit in the MSR is zero (default), and 0xFFF00 if IP equals one.

5.5.4.2 Chip-Select Option Registers

CSBTOR, the op tion register for CSBOOT, has the same field definitions as the o ption

registers for CS[1:5 ] but has d i ffere nt reset valu es. The CS0 and CS[6:10] option re g-

isters contain a subset of the fields in the CSBTOR. The CSBOOT sub-block option

The rese t values of sever a l b i ts in th e ch ip - s elect optio n r eg i sters d epend on the dat a

bus conf igurat ion word (t he state of the interna l data bus) at reset . The TADLY fiel d in

the CSBOOT option regist er is read f rom the intern al DATA[6 :8] bits, a nd the PS f ield

is determined from DATA4. In additio n, the reset value of th e PCON fie ld in the option

registers for CS[0:11] depe nds on the val ue of i nte rn al DATA0 at r ese t. If D ATA0 = 1 ,

the CS[0:11]/ADDR[0:11] pins are configured as chip selects, and the PCON field at

reset is 0b10 (output enable) for CS0 and 0b00 (chip enable) for CS[0:11]. If internal

DATA0 = 0 at re set, t he p ins are con f igu re d as a ddr e ss pins, an d th e PC ON fiel d va l-

ues for all option registers are 0b11 (non-chip-select function). Refer to 5.8.3

Configuration During Reset for more information on the data bus configuration word.

CSBTSBBAR — CSBOOT Sub-Block Base Address Register 0x8007 FDF0

CSBAR1 — CS1 Base Address Register 0x8007 FDE0

CSBAR2 — CS2 Base Address Register 0x8007 FDD8

CSBAR3 — CS3 Base Address Register 0x8007 FDD0

CSBAR4 — CS4 Base Address Register 0x8007 FDC8

CSBAR5 — CS5 Base Address Register 0x8007 FDC0

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

BA RESERVED

RESET:

00000000000000000000000000000000

Table 5-18 Chip-Select Base Address Registers Bit Settings

Bit(s) Name Description

0:19 BA Base address. Bits 0 through 19 of the ba se address of t he block to whic h the chip select responds.

20:31 — Reserved.

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-41

*From data bus reset configuration word

*0b10 if pins are configured as chip selects at reset, otherwise 0b11

CSBTOR — CSBOOT Option Register 0x8007 FDFC

012345678910 11 12 13 14 15

BSIZE SBLK SUPV DSP WP CI RESERVED ACK-

EN TADLY

RESET:

10010101000001**

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

TAD-

LY PS PCON BYTE REGION RESERVED ITYPE

RESET:

* * * 0 0 0 0 0 0 0 0 0 * * * *

CSBTSBOR — CSBOOT Sub-Block Option Register 0x8007 FDF4

012345678910 11 12 13 14 15

BSIZE SBLK SUPV DSP WP CI RESERVED

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED

RESET:

0000000000000000

CSO R 0 — CS0 Option Register 0x800 7 FD E C

012345678910 11 12 13 14 15

RESERVED

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED PCON BYTE REGION RESERVED

RESET:

000**00000000000

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5-42 Rev. 15 June 98 USER’S MANUAL

*0b00 if pins are configured as chip selects at reset, otherwise 0b11

Table 5-19 describes the fields in the chip-select option registers.

CSO R 1 — CS1 Option Register 0x8007 FDE4

CSO R 2 — CS2 Option Register 0x8007 FDDC

CSO R 3 — CS3 Option Register 0x8007 FDD4

CSO R 4 — CS4 Option Register 0x8007 FDCC

CSO R 5 — CS5 Option Register 0x8007 FDC4

012345678910 11 12 13 14 15

BSIZE SBLK SUPV DSP WP CI RESERVED ACK-

EN TADLY

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

TAD-

LY PS PCON BYTE REGION RESERVED ITYPE

RESET:

000**00000000000

CSO R 6 — CS6 Option Register 0x8007 FDBC

CSO R 7 — CS7 Option Register 0x8007 FDB4

CSO R 8 — CS8 Option Register 0x8007 FDAC

CSO R 9 — CS9 Option Register 0x8007 FDA4

CSOR10 — CS10 Option Register 0x8007 FD9C

CSOR11 — CS11 Option Register 0x8007 FD94

012345678910 11 12 13 14 15

RESERVED

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED PCON BYTE REGION RESERVED

RESET:

000**00000000000

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-43

Table 5-19 Chip-Select Option Register Bit Settings

Bit(s) Name Description

0:3 BSIZE

Block size. This field determines the size of the block associated with the base address.

0000 = Dis ables corresponding region

0001 = 4 Kbytes

0010 = 8 Kbytes

0011 = 16 K bytes

0100 = 32 K bytes

0101 = 64 K bytes

0110 = 128 Kbytes

0111 = 256 Kbytes

1000 = 512 Kbytes

1001 = 1 Mbyte

1010 = 2 Mbytes

1011 = 4 Mbytes

1100 = 8 Mbytes

1101 = 16 Mbytes

1110 = 32 Mbytes

1111 = 64 Mbytes

Refer to 5.5.5 Chip-Select Regions for more information.

4 SBLK

Sub-block

0 = Address space is a main block

1 = A ddress spac e specifie d by the BA and BSIZE f ields of the correspo nding ba se addres s and

option registers, respectively, is a sub-block within a larger mai n block. Pairing of main

blocks and sub-blocks is as follows:

CSBOOT and CS1

CS2 and CS3

CS4 and CS5

Refer to 5.5 .6 Mul ti-Level Protect ion for more information.

5SUPV

Supervisor mode

0 = Access is permitted in supervisor or user mode

1 = Access is permitted in supervisor mode only

Refer to 5.5.7.1 Supervisor Space Protection for more informati on.

6DSP

Data spac e onl y

0 = Address block may contain both instructions and data.

1 = Address block contains data only.

Refer to 5.5 .7. 2 Data Space Protecti on for more information.

7WP

Write prot ect

0 = Block is available for both read and write operations

1 = Block is read only

Refer to 5.5.7.3 Write Protection for more information.

8CI

Cache inhibit

0 = Information in this block can be cached.

1 = Information in this block should not be cached.

Refer to 5.5.8 Cache Inhibit Control for more information.

9:12 — Reserved

13 ACKEN

Acknowledge enable.

0 = Chip-select logic will not return TA and AACK signals

1 = Chip-select logic will return TA and AACK signals

Refer to 5.5 .9 Hands hak ing Control for more information.

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5.5.5 Chip-Select Regions

The SIU supports an address space of four gigabytes (232 bytes). This space can be

divided into regions. Each region can be occupied by one or more chips, depending

on the output width of each chip.

14:16 TADLY

TA del ay. Indicates the latency o f the device fo r the first TA returned. Up to sev en wait states a re

allowed.

000 = 0 wait states

001 = 1 wait state

010 = 2 wait states

011 = 3 wait states

100 = 4 wait states

101 = 5 wait states

110 = 6 wait states

111 = 7 wait states

Refer to 5.5.10 Wait State Control for more information.

17:18 PS

Port size

00 = Reserved

01 = 16-bi t por t

10 = 32-bi t por t

11 = Reserved

Refer to 5.5.11 Port Size for more information.

19:20 PCON

Pin configuration. Note that only pins CSBOOT and CS[1:5] can be CE pins.

00 = Chip enable (CE)

01 = Write enable (WE)

10 = Output enable (OE)

11 = Alternate function (address bus or discrete output)

Refer to 5.5.12.1 Pin Configuration for more information.

21:22 BYTE

Byte enable. This field applies to pins configured as WEs only. Specifies for which of the four

bytes in a word the WE is asserted. If the region can always be written in 32-bit qu antity, this field

can be programmed to any value.

00 = Byte enable 0

01 = Byte enable 1

10 = Byte enable 2

11 = Byte enable 3

Refer to 5.5.12.2 Byte Enable Control for more information.

23:25 REGION

Memory region (only applicable when pin is configured to be a WE or OE pin). These bit s indicate

the memory region with which the pin i s associated.

000 = CSBOOT

001 = CS1

010 = CS2

011 = CS3

100 = CS4

101 = CS5

110 = Reserved

111 = Reserved

Refer to 5.5.5 Chip-Select Regions for more information.

26:27 — Reserved

28:31 ITYPE Interface type. Indicates the type of memory or peripheral device being controlled. Refer to 5.5.13

Interface Types for details.

Table 5-19 Chip-Select Option Register Bit Settings (Continued)

Bit(s) Name Description

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-45

Each chip-select pin that is programmed as a chip enable defines a separate region.

Only the CSBOOT and CS[1:5] pins can serve as chip enables. All chips within a

region have a common chip enable signal.

Each chip select that can be programmed as a chip enable has an associated base

addr ess re gis ter. In addi ti on, the CS BOOT sub-block circuit has a base address reg-

ister. The base address register specifies the base address of the memory or

peripheral controlled by the chip select.

The base address and block size together determine the range of addresses con-

trolled by a chip select. Block size is the extent of the address block above the base

address. Block size is specified in the BSIZE field of the chip-select option register.

The BA (base address) field in the chip-select base address register contains the high-

order bits (bits 0 through 19) of the address block to which the associated chip select

responds. Register bit 0 corresponds to ADDR0; register bit 19 corresponds to

ADDR19 . Th e BS IZE field d ete rm ine s ho w many of th ese bi ts a re act ual ly co mp ar ed .

For the smallest block size encoding (four Kbytes), bits 0 through 19 are compared

with ADDR[0:19 ]. For larg er blo ck sizes, not al l of th ese bits are comp ared. Table 5-

20 shows the block size and address lines compared for each BSIZE encoding.

Since the address decode logic of the chip select uses only the most significant

addre ss bits to determin e an address mat ch within its b lock size, the value o f the base

address must be a multiple of the corresponding block size.

Table 5-20 Block Size Encoding

BSIZE Field

(Binary) Block Size

(Bytes) Address Lines Compared

0000 Invalid Chip select is not asserted until BSIZE field

is assigned a non-zero value.

0001 4 K ADDR[0:19]

0010 8 K ADDR[0:18]

0011 16 K ADDR[0:17]

0100 32 K ADDR[0:16]

0101 64 K ADDR[0:15]

0110 128 K ADDR[0:14]

0111 256 K ADDR[0:13]

1000 512 K ADDR[0:12]

1001 1 M ADDR[0 :11]

1010 2 M ADDR[0 :10]

1011 4 M ADDR[0 :9]

1100 8 M ADDR[0 :8]

1101 16 M ADDR[0:7]

1110 32 M ADDR[0:6]

1111 64 M ADDR[0:5]

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Althou gh the base addr ess registers can be pr ogrammed to be any ad dress within the

address map, the user must avoid programming these registers to values that overlap

the addresses of internal modules. At power-on time, the address of the boot device

may match that of an internal module, because a system can have on-chip EPROM

for instructions. If this occurs, the internal access overrides the external access. That

is, the i nternal acce ss provides the boot instruct ions, and the chip- select unit do es not

run an external cycle.

The reset va lue of the BA fie ld in the CSB OOT base address r egister depends on the

value of the exception prefix (IP) bit in the machine state register. Refer to the

RCPU

Reference Manual

(RCPURM/AD) for a description of the machine state register.

5.5.6 Multi-Level Protection

The chip-select unit allows protection for an address space within another address

space. Figure 5-13 illustrates this concept.

Figure 5-13 Multi-Level Protection

Figure 5-13 shows a sub-block contained within a main block. The main block and the

sub-block can have different protection mechanisms programmed. For example, the

user can have a separate data space and instruction space within a single chip-select

region.

The block size of the sub-block should be less than the block size of the main block.

The protection of the smaller block overrides the protection of the main block.

5.5.6.1 Main Block and Sub-Block Pairings

Multi-level protection is accomplished using a paired set of chip-select decoding cir-

cuits. The decoding pairs are specified in Ta ble 5-21 .

SUB-BLOCK*

MAIN BLOCK

(HAS ITS OWN PROTECTION)

MAIN BLOCK HIGH ADDRESS

MAIN BLOCK LOW ADDRESS

SUB-BLOCK HIGH ADDRESS

SUB-BLOCK LOW ADDRESS

* SUB-BLOCK HAS ITS OWN PROTECTION AND

OVERRIDES THE MA IN BLOCK’S PROTE CTION.

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If the address of an access falls within a sub-block, the protection of the sub-block

overrides that of the main blo ck. (The sub-block decoding logic overrid es the decoding

logic of the main block.) If all match conditions are met, the chip-select pin of the main

block is asserted.

Notice that only CSBOOT and CS[1:5] are involved in the sub-block protection

scheme. These are the chip selects with address decoding logic (i.e., they can act as

chip enables).

5.5.6.2 Programming the Sub-Block Option Register

When the SBLK bit in CSOR1, CSOR3, or CSOR5 is set, the corresponding address

block (defined by the BA and BSIZE fields) is designated a sub-block. Table 5-21 indi-

cates the main block to which the sub-block is assigned.

When t he SBLK bit in on e of the se regi sters is set, the fol lowing fi elds in t he sub-b lock

option register must b e progra mmed to the same value s as in th e option re gister fo r

the corresponding main block: ITYPE, ACKEN, TADLY, and PS. If there is a discrep-

ancy in the encoding of any of these bits in the two option registers, the chip-select unit

uses th e bits that a re set in e ither r egist er (i.e ., it pe rform s a logi cal OR on the asso ci-

ated bits in the two registers).

When the SBLK bit in CSOR1, CSOR3, or CSOR5 is set, the corresponding chip-

select pin cannot act as a CE pin, since its decoder is used for multi-level protection.

The pin, however, can still be configured (by programming the PCON field) to function

as an OE, WE, or non -chip-select pin. If th e pin is co nfigured as a WE or OE, it can b e

assigned to any region (not just the region associated with the sub-block).

The CSBOOT, CS2, and CS4 regions cannot be sub-blocks. They can only be the

main blocks. Setting the SBLOCK bit in any of these registers has no effect.

5.5.6.3 Multi-Level Protection for CSBOOT

The CSBOOT regi on ha s a ded i cate d sub -b l ock de code r in addi tio n to i ts pai red sub-

block decoder (CS1). If both sub-block decoders are used, the CS1 decoder has

higher priority than the dedicated sub-block decoder. That is, if an address is con-

tained in both sub-blocks, the protections specified in the CS1 option register are used.

If an address is contained in the dedicated sub-block (and the CSBOOT main block)

but not the CS1 sub- b lo ck, th e p ro te cti ons specifie d i n the C SBO OT sub-block option

regist er are used.

The SBLK bit of the dedicated sub-block option register is cleared at power-on. The bit

can be modified after reset if needed. The boot region would need to contain enough

Table 5-21 Main Block and Sub-Block Pairings

Main Block Sub-Block

CSBOOT CS1

CS2 CS3

CS4 CS5

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instructions to reconfigure the chip-select registers to provide multi-level protection

shortly after power-on.

5.5.7 Access Protection

The SUPV , DSP, an d WP bits i n the op tion re gisters fo r CSB OOT, th e CSBOOT sub-

block, and CS[1:5] control access to the address block assigned to the chip select.

These bits are present in the option registers for chip selects with address decoding

logic only; they are not present in the option registers for CS0 or CS[6:11]. In addi tion,

the bits take effect on ly if the chip sele ct is program med eithe r as a CE or as a sub-

block.

If the c hip-select unit detect s a protec tion viola tion, it ass erts the int ernal TEA signal

and does not assert the external chip enable signal. Assertion of TEA causes the pr o-

cessor to enter the checkstop state, enter debug mode, or process a machine check

exception. Refer to the

RCPU Referen c e Manual

(RCPURM/AD) for details.

5.5.7.1 Supervisor Space Protection

The SUPV bit in the option registers for CSBOOT, the CSBOOT sub-block, and

CS[1:5] controls user-level access to the associated region. If the bit is set, access is

permitted at the supervisor privilege level only. If the bit is cleared, both supervisor-

and user-level acc esses are permitted.

When an access is made to the region assigned to the chip select, the chip-select logic

compares the SUPV bit with the internal AT0 signal, which indicates whether the

access is at the user (AT0 = 0) or supervisor (AT0 = 1) privile ge level. If the chip-select

logic de tects a protecti on violation ( SUPV = 1 a nd AT0 = 0), it a sserts the inter nal TEA

signal and does not assert the external chip enable signal.

This protection applies to data address space only. The chip-select logic does not

check for supervisor access protection on instruction accesses.

5.5.7.2 Data Space Protection

The DSP bit in the optio n registers fo r CSBOOT, the CSBOOT sub-block, a nd CS[1:5 ]

controls whether instruction access is allowed to the address block associated with the

chip select. If DSP is set, the address block is designated as data space; no instruction

access is allowed. This featur e can be used to prevent the system from inadv erten tly

executing instructions out of data space.

When an access is made to the region controlled by the chip select, the chip-select

logic compares the DSP bit with the internal AT1 signal, which indicates whether the

access is to instructio n or data space. If the chip-select logic det ects a protection vio -

lation (DSP = 1 and AT1 = 1), it asserts the internal TEA signal and does not assert

the external chip enable signal.

5.5.7.3 Writ e Protection

The WP bit in the option registers for CSBOOT, the CSBOOT sub-block, and CS[1:5]

controls whether the address block is write-protected. If WP is set, read accesses only

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USER’S MANUAL Rev. 15 June 98 5-49

are permitted. If WP is cleared, both read and write accesses are allowed. This feature

permit s the user to protect certain reg ions, such as R OM region s, from bei ng inadvert-

ently written.

When an access is made to the region controlled by the chip select, the chip-select

logic compares the WP bit with the internal WR signal, which indicates whether the

access is a read or a write . If t he chip- sele ct logic detects a pro tectio n viola tion (W P =

1 an d WR = 0), it asserts the inte rnal TEA sig nal and does no t assert the external chip

enable signal.

5.5.8 Cache Inhibit Control

The CI ( cache in hibit) b it in the option r egisters f or CSBOOT, th e CSBOOT sub-block,

and CS[1:5] controls wh ether the informa tion in the addre ss block can be cache d. The

chip-select logic provides the status of this bit to the cache during the data phase of

an access. If CI is set, the data in the region is not cached.

5.5.9 Handshaking Control

The acknowledge enable (ACKEN) bit in the option registers for CSBOOT and CS[1:5]

determines whether the chip-select logic returns address acknowledge (AACK) and

transfer acknowledge (TA) signals for the region. When ACKEN is set, the chip-select

logic returns these signals. (When ACKEN is set, external logic can still return these

signals. If it does, it must assert them before the chip-select logic asserts the signals

interna lly . ) When AC KEN is cle ared , the exte rn al devi ce mu st ret urn them .

When ACK EN is cl eare d, the chip -sel ec t log ic sti ll retu rn s th e BI and PS[0:1] signals.

Since the chip-select logic does not return the TA signal, the TADLY field, indicating

the number of wait states before TA assertion, is not used.

After power-o n, the CSBOOT circ uit is enabl ed to return AACK and TA. If the external

boot device returns the TA signal, however, before the chip-select logic asserts TA

internally, the ex ternal TA assertion terminates the access.

5.5.10 Wait State Control

The TADLY field in the option registers for CSBOOT and CS[1:5] indicates the number

of wait states for the chip-select logic to insert before returning TA. If this field is

encoded for zero wait states, TA is asserted one clock cycle after TS is asserted. An

encoding of one wait state means that TA is asserted two clock cycles after TS, and

so on. Up to seven wait st ates are allowed. The encodings are shown in Table 5-22.

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Note th is fiel d is use d only when the chip- sele ct logic r etur ns the hand shak ing sign als

(ACKEN = 1).

Note that the user does not program the number of wait states prior to AACK assertion.

The chip-select logic uses the following scheme to determine when to assert AACK:

• If the region is an asynchronous type, AACK is asserted at the end of access to

the region.

• If the region is pipelineable and the region is not busy with a pending access,

AACK is asse rted after the address is la tched by the region (i.e. , at the next r ising

clock edge).

• If the region is pipelineable and the region is busy with a pending access, AACK

is asserted for the next access to the region at the end of the pending access to

the region (i.e., when TA is asserted for that access).

5.5.11 Port Size

The PS fi eld i n di cate s th e po rt size of the re gion . The chi p- se lec t log i c alw ays retu r ns

PS[0:1] for regions under its control. Port size encoding is shown in Table 5-23. The

0b00 and 0b11 encodings are reserved; if one of these encodings is used, the port size

defaults to 32 bits.

5.5. 12 Chi p-S ele ct Pin C ontrol

The PCON, BYTE, and REGI ON fi elds of e ach chi p-sele ct opti on re giste r contro l how

the associated pin is used. The PCON field determines pin function (CE, OE, WE, or

alternate function). The BYTE field determines which byte enable a WE pin corre-

sponds to. The REGION field assigns a WE or OE pin to one of six chip-select regions.

Table 5-22 TADLY and Wait State Control

TADLY Wait States

0b000 0

0b001 1

0b010 2

0b011 3

0b100 4

0b101 5

0b110 6

0b111 7

Table 5-23 Port Size

PS Field Port Size

0b00 Reserved

0b01 16 bits

0b10 32 bits

0b11 Reserved

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5.5.12.1 Pin Configuration

The PCON (pin configuration) field in the chip-select option register configures the

associated pin to be a CE, WE, OE, or non-chip-select function pin. The encodings are

shown in Table 5-24.

Note that only the CSBOOT and CS[1:5] pins can be CE pins. If the pi n is a CE pin,

the REGION field does not affect it, since each CE pin ha s its own ba se ad dr ess re g-

ister and decoding logic.

The CS0 and CS [6:11] p ins cannot be C E pins. If one of these pins is configured as a

chip enable, the pin is never asserted.

A PCON encoding of 0b11 assigns the pin to its alternate function. In this case, the

value in the port A/B pin assignment register (PABPAR) determines whether the pin

operates as an address pin or discrete output pin. Refer to 5.9.3 Ports A and B for

more infor mation.

5.5.12.2 Byte Enable Control

The BYTE field is applicable only for pins configured as WE pins. This fi eld is used to

determine to which of the four E-bus byte enables the pin corresponds. That is, the WE

pin will be asse rted only when the correspond ing E-bus byte enable is asserted. The

encodi ng is shown in Table 5-25. If the regio n can al ways be w ritten in 32- bit quan tity,

this field can be programmed to any value.

If the pin is configured as an OE, this field is not used. (It is assumed the OE pin

enables the outputs of all four bytes of the region onto the 32-bit E-bus.) Thus, typically

a writable region would have multiple WEs, one OE, and one CE.

5.5.12. 3 Regi on Control

The REGION field indicates which memory region the pin is assigned to. This field is

used only when the pin is configured to be a WE or OE pin. For example, a PCON

Table 5-24 Pin Configuration Encodings

PCON Pin Assignment

0b00 Chip enable (CE)

0b01 Write enable (WE)

0b10 Output enable (OE)

0b11 Address pin or discrete output

Table 5-25 BYTE Field Encodings

BYTE Byte Enabled

0b00 Byte enab le 0

0b01 Byte enab le 1

0b10 Byte enab le 2

0b11 Byte enab le 3

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encoding of 0b10 and a REGION encoding of 0b001 configures the pin as an OE of

the memory region defined by CS1.

REGION field encodings are shown in Table 5-26.

5.5.13 Interface Types

The chip-select module supports a wide variety of devices. The interface type (ITYPE)

field in the option registers for CSBOOT and CS[1:5] identifies the characteristics of

the device interface. These characteristics include whether the external device

interface:

• Is synchronous or asynchronous

• Supports pipelined accesses

• Can hold off its internal data

• Has a synchronous OE, an asynchronous OE, or no OE

• Is b urstable or non-burs table

• Uses the LAST or BDIP protocol for ending a burst transmission

The following paragraphs define these c oncepts.

A bursta ble device can accept on e address an d drive o ut multip le data beats. A burst-

able device must be synchronous. (Note that devices with fast static column access

are not considered burstable. This class of devices is considered asynchronous.)

Two acces ses are ov erlapped if they are aligned such that the addres s of the second

access is on the external bus at the same time as the data of the first access.

Two accesses are pipelined

if they are aligned such that the address of the second

access is on the external bus before the data of the first access.

A devi ce is p ipeli neab le if it can lat ch t he ad dress pr esente d to i t and does not r equir e

the ad dress to be vali d on it s address pins fo r the duration of th e access to the de vice.

The pipe lin ea ble de vi ce sho ul d latch the ad dr ess at the risin g ed ge of the cl ock whe n

its CE is asserted. Note that only synchronous devices are treated as pipelineable by

the chip-select logic.

Table 5-26 REGION Field Encodings

REGION Memory Region Defined by

0b000 CSBOOT

0b001 CS1

0b010 CS2

0b011 CS3

0b100 CS4

0b101 CS5

0b110 Reserved

0b111 Reserved

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BDIP and LAST are the early termination control signals for burst cycles. A memory

device with a type 1 burst interface may have a BDIP signal as one of its inputs. A

memory device with a type 2 burst interface has a LAST signal as one of its inputs.

Refer to 5.5.16.6 Synchronous Burst Interface for a description of these interface

types.

A device may or may not have the ability to hold off its data output until the data bus

is available to the device. To be able to hold off its data the device needs an OE control

input, and if the device is burstable it also needs the ability to suspend its internal state

machine from advancing to the next data beat until the data bus has been granted to

it. An ex am pl e o f thi s i s a m emo ry device with burst a dd ress ad vance control such as

BDIP to control the incrementing of its internal address counter.

5.5.13.1 Interface Type Descriptions

Table 5-27 lists the characteristics of each interface type. Note that if software pro-

grams the ITYPE field to one of the reserved values, the chip- select sign al will never

be asserted.

Table 5-27 Interface Types

ITYPE

(Binary) Interface Type

0000

Generic asynchronous region with output buffer turn-off time of less than or equal

to one clock period (see 5.5.13.2 Turn-Off Times for Different Interface

Types). A device of this type c annot be pipelined . Ref er to Figure 5-17 and Fig-

ure 5-18.

0001

Generic asynchronous region with output bu ffer turn-off time of two cloc k periods

(see 5.5.13.2 Turn-Off Times for Different Interface Types). A device of this

type c annot be p ipelin ed. Th e chip-sel ect l ogic in serts a dea d cl ock betwe en two

subsequent accesses to the same region of this type in order to satisfy the high

time required by the CE and WE of some memory types.

0010

Synchron ous re gion (no burst) wi th asy nchronou s OE . Refer to Figure 5-1 9 an d

Figure 5-20. A device with this type of interface is pipelineable, can function as

an async hronous de vice, and ha s the ability to hold off its internal da ta on a read

access until OE is asser ted.

Note that with this interface type, if the MCU receives TA before asserting OE, OE

may still be asserted and may remain asserted.

0011

Synchron ous regio n (no burst) with sync hronous OE . Refer to Figure 5-21. A d e-

vice with this type of interface is pipelineable, can function as an asynchronous

device, and has the ability to hold off its internal data on a read access until OE

is asserted. The chip-select logic asserts OE for one cl ock cycle on access es to

devices with this interface type.

A devic e with s ynchronous OE must be programm ed for one or more wait states.

If the region is programmed for zero wait states with synchronous OE, the chip-

select log ic still g ene rates th e OE as if the reg ion were p rogr ammed for o ne wait

state.

0100 Reserved.

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5.5.13.2 Turn-Off Times for Different Interface Types

The turn-off time for asynchronous devices is equal to the time for OE to negate plus

the time for device’s outputs to go to a high-impedance state. For devices with an

0101

Region with fixed burst access capability (burst type 1) and asynchronous OE.

Refer to Figure 5-23 and Figure 5-24. A device of this type is pipelineable and

can hold off its internal data until OE is asserted. The interface keeps the first data

beat valid until the BDIP signal indicates that it should send out the next data.

This interface type can function as an asynchronous interface. That is, a device

with this ITYPE can be assigned to the CSBOOT region, which comes out of reset

configured as an asynchronous region with seven wait states. In this case, the

MCU doesn’t latch the data to be read until the assigned number of wait states

have elapsed and OE is asserted.

0110 Reserved.

0111

Regio n with fix ed bu rst acce ss capabil ity (burs t type 1 ) and synchron ous OE . Re-

fer to Figure 5-23 (but with a synchronous, not asynchronous, OE) and to Figure

5-24. Devic es with this type o f interf ace are p ipelineab le and c an hold o ff internal

data until OE is asserted. The interface keeps the first data beat valid until the

BDIP signal indicates that it should send out the next data.

This interface type can function as an asynchronous interface. That is, a device

with this ITYPE can be assigned to the CSBOOT region, which comes out of reset

configured as an asynchronous region with seven wait states. In this case, the

MCU doesn’t latch the data to be read until the assigned number of wait states

have elapsed and OE is asserted.

1000

Region with fixed burst access capability (burst type 2). Refer to Figure 5-25.

This interface type uses th e LAST timing protocol. Typically, this ITYPE is used

for burst accesses to DRAM.

This interface type may have an OE and may have a wait state counter, but the

chip-select logic does not expect the device to have either and will never assert

the OE signal. (OE can be provided by external logic if required, or a diffe rent

ITYPE can be selected.) The device will drive out the data after the number of wait

states it requ ires. The interf ace kee ps the first data bea t valid for onl y one clock .

Any access to a device with this type of interface must be made using chip se-

lects, and the ACKEN bit in the option register for the chip select must be set.

Because this type cannot hold off its internal data until the data bus is available,

an access to a region of this type cannot be pipelined with a previous access to

the same or a different region. (That is, the address of an access to this region

cannot ap pear on the ex ternal bu s before the data for the pr evio us access .) The

address for the second acces s can overlap the data for the first access, however.

In addition, if an access to this region is followed by an access to a pipelineable

region, the second access is pipelined.

This interface type can function as an asynchronous interface. That is, a device

with this ITYPE can be assigned to the CSBOOT region, which comes out of reset

configured as an asynchronous region with seven wait states. In this case, the

MCU doesn’t latch the data to be read until the assigned number of wait states

have elapsed and OE is asserted.

1001

Synchronous region (no burst) with synchronous OE, as with ITYPE 3, but with

early ove rlapping of accesses to th e region. Refer to Figure 5-2 1. This type of in-

terface must be able to pipeline another access to it one clock cycle before it

drives valid data out on a read or receives data on a write for the previous access.

1010–1111 Reserved.

Table 5-27 Interface Types (Continued)

ITYPE

(Binary) Interface Type

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USER’S MANUAL Rev. 15 June 98 5-55

ITYPE of zero, turn-off time is less than or equal to one clock cycle. For devices with

an ITYPE of one, turn-off time is two clock cycles.

The turn-off time of asynchrono us dev ices must be ta ken into accoun t in systems that

pipeline accesses to devices controlled by chip selects with accesses to devices that

are n ot under chip select control. Otherwise, external bus c ontention can result.

The turn off time for synchronous devices is equal to the time from the rising edge of

the device’s clock to the time the de vice’s outpu ts are in a hig h-impedance sta te. This

turn off time must be less than or equal to one clock period.

5.5.13.3 Interface Type and BI Generation

During a burst access to a re gion under chip -select control that does not sup port burst

accesses, the chip-select unit asserts the BI signal internally. Only regions with an

ITYPE of five, seven, and eight support burst accesses.

CAUTION

It is recommended that the BI pin not be a sserted during accesses to

memory regions controlled by chip selects; instead, the chip-select

unit will generate the BI signal internally when appropriate.

5.5.14 Chip-Select Operation Flowchart

Figure 5-14 illustrates the operation of the chip-select logic for external accesses.

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Figure 5-14 Chip-Select Operation Flowchart

5.5.15 Pipe Trac king

The chip-select module supports pipelined accesses to external devices. Up to two

cycles can be pending in the chip-select module.

The chip-select unit supports pipelined reads for certain types of interfaces. Pipelined

writes are not supported. Table 5-28 summarizes the chip-select pipelining of read

and write accesses.

Table 5-28 Pipelined Reads and Writes

First Access Second Access Pipelining

Supported

Read Read Yes

Write Read Yes

Read Write No

Write Write No

IDLE

DECODES ADDRESS

ASSERTS CE

ASSERTS OE

WAITS UNTIL DELAY TIME

ASSERTS TA IF ENABLED

ASSERTS WE

WAITS UNTIL TURN IN THE PIPE

(IF READ)

(IF WRITE)

(NO MORE)

(IF NEW CYCLE)

ASSERTS AACK IF ENABLED

(IF MATCH & DOES NOT VIOLATE PROTECTION)

RETURNS BI, PS[0:1]

(LAST DATA &

OVERLAP ACCESS)

(IF BURST)

MPC500 CS FLOW

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The following subsections explain which types of interfaces permit pipelining of read

accesses. Pipelining of consecutive accesses to the same region is discussed first, fol-

lowed by pipelining of consecutive accesses to different regions.

5.5.15.1 Pipelined Accesses to the Same Region

The chip-select unit overlaps consecutive accesses to the same region, provided the

following cond itions are met:

• The second access is a read

• The region is pipelineable (as determined by its ITYPE)

• The TA signal is generated by the chip-select logic (ACKEN = 1).

When t hese condit ions are met, the address (and CE assertion) for the second access

can overlap t he dat a phase of the f irst acc ess.

Figure 5-15 illu str ate s th e co ncept of ove r la pp ed acce sses to th e sa me regio n. ( Note

that the diagram cannot be assumed to be accurate in timing.)

Figure 5-15 Overlapped Accesses to the Same Region

NOTE

If the region is programmed to return its own handshaking signals

(ACKEN = 0), the chip-select logic does not know whether the device

has an address latch (hence, whether the device is programmable).

The chip-select control logic takes this into account and asserts the

CE of the second access o nly afte r AACK has been asserted for the

first access.

5.5.15.2 Pipelined Accesses to Different Regions

The chip-select unit supports pipelined accesses to different memory regions, depend-

ing on the properties of the two regions. The chip-select module tracks the incoming

cycles and uses the information in the option registers to control the assertion of the

CE, WE, and O E signals.

ADDR

CLKOUT

2ND ADDRESS OVERLAP WITH 1ST DATA

DATA

1ST ADDRESS LATCHED

A2, OVERLAPA1, READ

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For the chip-select module to pipeline accesses to two different regions, the first region

must be pipelineable; otherwise, the chip-select unit waits for th e first access to com -

plet e (TA asserted) before beginning the second access.

Figure 5-16 uses two synchronous devices (ITYPE = 2) to illustrate this pipelining

case. In this example, the first access is to a four-wait-state region, and the second

access is to a region with zero wait states. (For a second region with wait states, the

pipelining is similar except the data of the second region takes more time to be avail-

able on the bus if the second region cannot hold off its internal data.) The example is

intended to show when the CE (or address phase) and the data phase of the second

access can be given to the region. It assumes the device(s) in the first region is pipe-

lineable, and both accesses ar e initiated by the same bus master.

Figure 5-16 Pipelined Accesses to Two Different Regions

1. If both regions are under chip-select control, the delays of both regions are

known to the chip-sele ct logic, and the interface type of the first re gion supports

pipe lining, then t he seco nd access (if a read) can be pip elined with the firs t.

2. For a ny tw o co nsecu tive acce sses, if the la ten cy of eith er re gion is no t kn own

to the chip-select logic, the two accesses are pipelined only if the second ac-

cess is a read access to a region with an interface type that can hold off the data

until the data bu s is available (See Table 5-27).

For example, suppose the first access is to a region that supplies its own TA

signal, the second access is to another region with ITYPE = 8, and TA is re-

turned by t he chip-sele ct log ic for the seco nd acce ss. In this ca se, t he chip-se-

lect logic must hold off the second access until the first access is completed

because the second region may not be able to hold off its data without an OE.

On the oth er ha nd , sup po se th e fi rs t acce ss is to a re gi on tha t su ppli es its o w n

TA signal, the se cond access is to another region with ITYPE = 3 (synchronous

OE) and TA i s returned by the chip-select logic for the second access. In this

ADDR

CE1

CLKOUT

DATA

OE1

1ST ADDRESS LATCHED

CE2

OE2

2ND CE ASSE RTS

A1, READ A2, READ

D1 D2

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USER’S MANUAL Rev. 15 June 98 5-59

case, the second region can hold off its data until its OE is asserted. The chip-

select module can pipeline the second access (if a read) with the first access

after it has received the AACK signal for the first access. The chip-select logic

asserts the CE of the second access while the data phase of the first access is

still in pr ogress, if the se cond access is issued before the first access is com -

pleted.

3. If the first access is to a region that is not under chip-select control (external

glue logic ge nerates a ll contr ol and handsha ke sign als for the regi on, as for a

DRAM con troller, fo r exampl e), and the second acces s is to a reg ion tha t is un-

der chip-select cont rol, the chip-select module does

not

pipeline the second ac-

cess with the first.

4. If the first access is to a region under chip-select control and the second access

is a read access to a region that is not under chip-select control, the external

glue logic desig ner must decide whether to pipeline the se cond access with the

first. The decision depends on system requirements and on the interface type

of the region that is not under chip-select control.

5. If the firs t access is a burst read access to a bur stable re gion a nd the se cond is

a read access to ano ther regio n, the c hip-select module pip elines th e second

read if the second access is to a region with an interface type that is pipeline-

able and can hold off its data. If ITYPE = 8 for the second region, the chip-select

module does not pipeline the second access with the first.

6. If the first access is to a synchronous region, and the second access is to an

asynchronous region, the chip-select module does

not

pipeline the accesses.

7. If the first access is to an asynchronous region, the chip-select module does

not

pipe line the sec ond access wi th the fi rst, since both th e externa l address a nd

data bus must be available for the first access until it is completed. If the first

region requires an extra clock to turn off its buffer, the chip-select logic allows

an extra clock for the region.

5.5.16 Chip-Select Timing Diagra ms

The diagrams in this section show the different device interfaces that the chip-select

module supports. Where applicable, the diagrams indicate how the various signals

(address, data, and chip-select signals) are correlated.

CAUTION

The user must not assume that CE is always asserted simulta-

neously with TS. Depending on the state of the pipeline (which

depends on the interface types of the devices being accessed), the

chip-select unit may delay asserting CE until one or more clock

cycles after TS is asserted.

5.5.16.1 Asynchronous Interface

An external device with an asynchronous interface requires the address and the chip

select signals (CE, OE, and WE) to be valid until the end of the access. The next

access to the same de vice mu st wa it fo r the p revious access to co mplete . No ove rlap

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of accesses is allowed. Figure 5-17 and Figure 5-18 illustrate the asynchronous inter-

face for read and write accesses. For the asynchronous write, the external memory

latches the data when WE is asserted.

Figure 5-17 Asynchronous Read (Zero Wait States)

Figure 5-18 Asynchronous Write (Zero Wait States)

5.5.16.2 Asynchronous Interface with Latch Enable

Devices with an address latch enable signal, such as the Motorola MCM62995A mem-

ory chip, also support unlatched asynchronous read and write interfaces as shown in

Figure 5-17 and Figure 5-18. The chip-select module supports this type of device in

the unlatched asynchronous mode only.

5.5.16.3 Synchronous Interface with Asynchronous OE

Devices with ITYPE = 2 have a synchronous interface with an asynchronous output

enabl e. Devices of this type clock the addr ess and the data on the rising ed ge of CLK-

OUT. On a read access, these devices drive the data out as soon as the OE is

asserted. In addition, the interface has the ability to latch the address so the next

access to the same device can be overlapped with the previous access.

ADDR

DATA

CLKOUT

POSSIBLE A2

ADDR

DATA

CLKOUT

STROBE IN DATA

POSSIBLE A2

OUTPUT BUFFERS CORRELATION

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USER’S MANUAL Rev. 15 June 98 5-61

Figure 5-19 and Figure 5-20 illustrate reads and writes for devices with this type of

interface.

Figure 5-19 Synchronous Read with Asynchronous OE (Zero Wait States)

Figure 5-20 Synchronous Write (Zero Wait States)

5.5.16.4 Synchronous Interface with Early Synchronous OE

Devices with ITYPE = 3 have a synchronous interface with a synchronous output

enable. OE is asserted, at th e earliest, one clock cycle after CE. Th e synchronous OE

should be sampled by the external device using the rising edge of its clock signal.

For read accesses, the early OE signal allows the responding device to prepare for the

next data cycle. If OE is a ssert e d, th e de vice can prepar e to dr i ve th e ne xt da ta or re-

ADDR

DATA

CLKOUT

(ASYNCHRONOUS)

AACK

OVERLAP ACCESS

CLOCK IN ADDRESS FO R REA D

ENAB LE DATA OUTPUT

= UNDEFINED

= DON’T CARE

ADDR

DATA

CLKOUT

CLOCK IN ADDRESS FOR WRITE

CLOCK IN DATA FOR WRITE

OVERLAP ACCESS

AACK

OE = DON’T CAREOR = UNDEFINED

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fill its internal data queue. If OE is not asserted, the device can place the data lines in

a high -impedance s tate for fast relinqu ishing of the data bus.

Figure 5-21 Synchronous Read with Early OE (One Wait State)

5.5.16.5 Synchronous Interface with Synchronous OE, Early Overlap

Devices with ITYPE = 9 are synchronous wi th a synchronous ou tput enable. They are

different from devices with ITYPE = 3 in that they support early overlapping of

accesses. That is, the region is capable of accepting a second address one clock cycle

before the data phase of the first access terminates. Notice in Figure 5-22 that CE is

asserted one clock cycle earlier than in the previous example (Figure 5-21).

ADDR

DATA

CLKOUT

(SYNCHRONOUS)

AACK

OVERLAP ACCESS

CLOCK IN ADDRESS FOR READ

ENABLE DATA OUTPUT

DE VICE CAN 3-STATE ITS

DRIVERS FROM CLOCK

ONE WAIT STATE

= UNDEFINED

= DON’T CARE

EDGE

NEXT POSSIBLE CE

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USER’S MANUAL Rev. 15 June 98 5-63

Figure 5-22 Synchronous Read with Early Overlap (One Wait State)

5.5.16.6 Synchronous Burst Interface

The chip-select module supports two types of burst interfaces. The type 1 burst inter-

face uses the output enable and the write enable to control the data being driven out

or recei ved. The type 1 b urst interf ace also re quires a BDIP signal to co ntrol whe n the

region should output the next beat of t he burst.

For t he re ad case, the typ e 2 burst in terfa ce d oes not re qui re an outpu t enab le si gnal .

Instead, it uses a LAST signal. When this signal is asserted at the rising edge of the

clock, the type 2 burst device places its output buffers in a high-impedance state fol-

lowin g t he cl ock ed ge. The C E of the type 2 bu rs t m ust be valid fo r th e dur a ti on of th e

device’s access latency or wait states. This type of device also requires a signal with

timing similar to that of the TS signal. The interface may or may not contain an OE

signal.

Any access to a device with type 2 burst interface must be made using chip selects,

and the ACKEN bit in the option register for the chip select must be set.

NOTE

The LAST and BD IP signals share the same pin. The LST bit in the

SIU module configuration register (SIUMCR) specifies whether the

pin uses timing for the LAST signal (LST = 1) or the BDIP signal (LST

= 0).

Type 1 and type 2 burst interfaces both have address latches, so the address of the

next access to the device can be overlapped with the previous access. That is, the

ADDR

DATA

CLKOUT

= UNDEFINED

= DON’T CARE

(SYNCHRONOUS)

AACK

OVERLAP ACCESS

CLOCK IN ADDRESS FOR READ

ENAB LE DATA OUTPUT

DE VICE CAN 3-STATE ITS

DRIVERS FROM CLOCK

ONE WAIT STATE

EARLY OVERLAP ACCESS

DATA PHASE TERMINATES

EDGE

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addre ss of an acce ss d oe s no t n eed to be valid after th e add r ess h as b ee n la tched at

the rising edge of the clock.

For type 1 burst interface s with an asynchronous OE, the ITYPE field in the appropri-

ate chip-select option register should be programmed to 0b0101. For type 1 burst

interfaces with a synchronous OE, this field should be programmed to 0b0111. For

type 2 burst interfaces, ITYPE should be programmed to 0b 1000.

Figure 5- 23 and Figure 5-24 show a read and wri te access, respectively, to a type 1

burst interface. Note in Figure 5-23 that the OE is asynchrono us (I TY PE = 5) .

Figure 5-23 Type 1 Synchronous Burst Read Interface

ADDR

DATA

LKOUT

= UNDEFINED

= DON’T CARE

D1 D2

LAST DATA

WAIT STATE

AACK

ENABLE DATA OUT

OE TURN OFF

(ASYNCHRONOUS)

POSSIBLE A2

BDIP

NEXT DATA

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USER’S MANUAL Rev. 15 June 98 5-65

Figure 5-24 Type 1 Synchronous Burst Write Interface

Figure 5-25 shows a rea d access to a type 2 burst in terfac e (ITYPE = 8). No te that a n

output enable signal is not required for this type of interface. Instead, the interface

uses the LAST signal.

ADDR

DATA

CLOCK

CLOCK = E-BUS CLOCK = UNDEFINED

= DON’T CARE

CLOCK IN DATA

AACK

D0 D1 D2 D3

POSSIB LE A2

BDIP LAST DATA

NEXT DATA AT NEXT CLOCK

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Figure 5-25 Type 2 Synchronous Burst Read Interface

5.5.17 Burst Handling

The chip-select module supports burst accesses, with four data beats per burst. The

following pa r agraphs describe how the chip-select module handles some of the more

complex cases.

• For a single-word access to a burstable region, the chip-select module asserts

OE (on a read) or WE (on a write) for only one word. The burstable region may

requir e an early termi nation sign al such as LAST. The EB I is expected to provid e

the early termination indication to the region.

• For fixed burst access to a burstable region, since all burstable types supported

by the chip-select module allow fixed burst accesses, the chip-select module

keeps the OE or WE asserted for the leng th o f fo ur words u nless the cycle is te r-

minat ed ea rl y.

• For a burst access to a non-burstable region, the chip-select module asserts the

burst inhibit indication to the EBI and treats the access as a single-word access.

• For a f ixe d- bu rst acc e ss t o a burs tab le sm all p ort (16 -bi t) de v ice , t he c hip -s el ect

module keeps the OE or WE valid until the EBI terminates the burst. Depending

on the starting address of the burst, the EBI breaks the access into two or more

cycles and increments the address appropriately. The small port device is expect-

ed to wrap as spe c ified in 5.4 External Bus Interface.

• For a si ngle- word a ccess to a device wit h a smal l port , th e chip- select modu le al-

ways performs a single access to the small port device and indicates to the EBI

that the device has a 16-bit port. If more data is needed, the EB I requests the chip

selects to perform another access to the device to complete the transfer.

ADDR

DATA

LAST

CLKOUT

= UNDEFINED

= DON’T CARE

AACK

D0 D1 D2 D3

2 WAIT STATE S

ADDRES S LAT CHED

LAST DATA

POSSIBLE A2 POSSIBLE OVERLAP

ACCESS

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5.5.18 Chip-Select Reset Operation

The dat a bus conf igurat ion word specifies how the MCU is configured at reset. Table

5-29 summarizes the data bus configuration bits that affect chip selects.

The boot region can be a ROM or flas h EPROM. At power-o n, it is assumed that no

writing to the region is needed until the chip-select logic has been configured. Thus,

no WE is ne ede d at powe r-on time. The boot de vice can be in ternal o r exte rn al m e m-

ory. If internal memory, the boot device is not under chip-select control. If the boot

devic e is located externall y, the ch ip-select lo gic decod es the addr ess of the acces s

and enables the CE and OE of the boot device appropriately. If the external boot

device has a type 2 burst interface, the LAST signal must be supplied by the EBI.

Note tha t a t power-on , th e bo ot re gi on m ay be l oca ted a t th e upper most or lo w ermo st

1 Mbyte of the address range. The CSBOOT base ad dress (sp ecified in the B A field

of CSBTBAR) can be reset to 0xFFF0 0000 or 0x0000 0000 accordingly. The chip-

select logic asserts th e CSBOOT signal for th e entire 1-Mbyte range if th e access is to

external boot memory.

While RESET is asserted, the MCU drives the chip-select pins high (negated) to avoid

a possible data bus conflict.

5.6 Clock Submodule

The system clock provides timing signals for the IMB2 and for an external peripheral

bus. The MCU drives the system clock onto t he external bus on t he CLKOUT pin. The

main timing reference for the MPC500 family is a 4-MHz crystal. The system operating

frequ ency is ge nerate d throug h a program mable ph ase-loc ked loop . The PLL is pro-

gram mable in inte ger multipl es of 4 MHz to genera te operat ing frequenci es of 16 MHz

Table 5-29 Data Bus Configuration Word Settings for Chip Selects

Bit(s) Configuration Function

Affected Description

0Addres s bus/chip selects 0 = CS[0:11]/ADDR[0:11] configured as address pins

1 = CS[0:11]/ADDR[0:11] configured as chip-select pins (default value)

1Exception prefix

(vector table location) 0 = Vector table begins at 0x0000 0000

1 = Vector table begins at 0xFFF0 0000 (default value)

2Burst m ode type 0 = Type 1 bur st mode — uses BDIP timing ( default v alue)

0 = Ty pe 2 burst mode — uses LAST timi ng

3ITYPE of boot device 0 = Boot device ITYPE = 0x08 (Synchronous burst)

1 = Boot device ITYPE = 0x01 (Asynchronous — default value)

4Port size of boot device 0 = Boot device has 16-bit port (default value)

1 = Boot device has 32-bit port

6:8

TA delay for CSBOOT 000 = 0 wait states

001 = 1 wait state

010 = 2 wait states

011 = 3 wait states

100 = 4 wait states

101 = 5 wait states

110 = 6 wait states

111 = 7 wait states (default value)

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to 44 MHz. These frequencies can be divided by powers of two to generate other

frequencies.

If the crystal cease s to function, the loss of oscillator (LOO) b it is set and the PLL is

forced to o perate in the se lf-clocked mode (SCM). This mod e provides a system clock

frequency of approximately 4 MHz. The exact frequency depends on the voltage and

temperature of the CPU, but is optimized for nominal operating conditions.

The PLL can be bypassed by grounding the VDDSN pin. Note that in this case, the input

frequency needs to be twice the desired operating system frequency. With VDDSN

grounded, the multiplication factor (MF) bits in the system clock control register

(SCCR) no longer have any effect on the system frequency, but the reduced frequency

(RFD) bits and the low-power mode (LPM) bits do have an effect.

Three different low-power modes are available to minimize standby power usage. Nor-

mal operation or one of the three low-power modes is selected by programming the

LPM bits in the SCCR.

The clock submodule also provides a clock source for the PowerPC time base and

decrementer. The oscillator, time base, and decrementer are powered from the keep

alive power supply (VDDKAP1). This allows the time base to continue incrementing

even when the ma in po wer to the MCU is off. Wh ile the po wer is off, th e d ecremen ter

also continues to count. The power-down wakeup pin (PDWU) can be programmed to

signal an external power-on reset circuit to en able power to th e system wheneve r the

MSB of the decrementer changes from a zero to a one.

Figure 5-26 is a block diagram of the SIU clock module.

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USER’S MANUAL Rev. 15 June 98 5-69

Figure 5-26 SIU Clock Module Block Diagram

OSC

TB, DEC

SPLL

ECR

RFD

SYSTEM

VDDSN

ECROUT

OSCCLK

VCOOUT

CLKOUT

2:1 MUX

SI_S_FREEZE

XTAL

EXTAL

MODCLK

XFCN

LPM3

(÷4)

LPM2

LPM1

LPM3

MF[0:3]

RFD[0:3]

VDDSN

XTAL

EXTAL

MODCLK

LOO

LOCK

LPM1

VDDSN

MODCLK

XFCP

SIU CLOCK BLOCK

CLOCKS

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5.6.1 Clock Submodule Signal Descriptions

Table 5-30 describes the signals used by the clock module.

5.6.2 Clock Power Supplies

The power supply for each block of the clock submodule is shown in Table 5- 31.

To improve noise immunity, the PLL has its own set of power supply pins, VDDSYN and

GNDSYN. Only the charge pump and the VCO are powered by these pins.

The oscillator, system clock control register, and system clock control and status reg-

ister a re powe red fro m the keep a live pow er supply ( VDDKA P1) and VSSI. In addition ,

VDDKAP1 powers the PowerPC time base and decrementer. This allows the time

Table 5-30 Clocks Module Signal Descriptions

Mnemonic Name Direction Description

CLKOUT System clock out Output System clock. Used as the bus timing reference by

external devices.

EXTAL, XTAL Crystal oscillator Input, Output Connecti ons for externa l crystal to the internal osc illa-

tor circuit. An external oscillator should serve as input

to the EXTAL pin, when used.

XFCN, XFCP External filter

capacitor Input These pins are used to add an external capacitor to

the filter circuit of the phase-locked loop.

MODCLK Clock mode select Input The state of this input signal during reset selects the

source of the system clock. Refer to 5.6.3 System

Clock Sources.

VDDSN, VSSSN Synthesizer power Input These pins supply a quiet power source to the VCO.

ECROUT Engineering clock

reference output Output Buffered output of the crystal oscillator. The ECROUT

output frequency is equal to the crystal oscillator fre-

quency.

PLLL/DSDO PLL lock status or

debug output Output Phase-locked loop status output or debug output.

PDWU Power-down wake-

up Output

Asserted or negated, respectively, by software setting

or clearin g the WUR bi t in the SCLSR. Als o asser ted

when decrementer counts down to zero. Can be used

as power-down wakeup to external power-on reset

circuit.

Table 5-31 Clock Module Power Supplies

Power Supply Blocks

VDDI

CLKOUT

ECR

PIT Clock

RFD

PLL (Digital)

VDDKAP1

Decrementer/Time Base Clock

Oscillator

SCCR

SCCSR

VDDSN PLL (Analog)

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base to continue incrementing at 1 MHz even when the main power to the MCU is off.

While the power is off, the decrementer also continues to count and may be used to

signal the external power supply to enable power to the system at specific intervals.

This is the power-down wakeup feature.

5.6.3 System Clock Sources

The VDDSN and MODCLK pins are used to configure the clock source for the MCU.

The configuration modes are shown in Table 5-32.

When both pins are hig h, the CPU clocks are config ured for normal operatio n and th e

PLL i s fully programmable.

If MODCLK = 0 and VDDSN = 1, then the PLL enters 1:1 frequency mode. In this mode,

CLKOUT frequency is equal to the oscillator frequency and is not affected by the RFD

bits. The oscillator can be driven by either an external crystal or an external clock

source.

If VDDSN = 0 and MODCLK = 1, then the PLL is disabled and bypassed. In this case,

CLKOUT frequency is equal to one half the oscillator frequency. In this mode, the

oscillator source must have a 50% duty cycle.

In each clock mode except bypass mo de, CLKOUT frequen cy can be reduce d by pro-

gramming the RFD field to a non-zero value. Refer to 5.6.5 CLKOUT Frequency

Control for details.

If VDDSN = 0 and MODCLK = 0, then the CPU clocks are configured in special test

mode. In this mode, the PLL and most of the clock generation circuitry are bypassed.

This mode is intended for factory test only.

CAUTION

When the clock is in PLL bypass mode or special test mode, setting

the LOLRE bit in the SCCR generates a loss-of-lock reset request

(since the PL L is off). The L OLRE bit must n ot be set whe n the clock

is in PLL bypass or special test mode.

5.6.4 Phase-Locked Loop

The pha s e-l ocke d lo op ( PL L) i s a f re qu ency synthesis PL L that can mul tipl y the r efe r-

ence clock frequency by a factor from 4 to 11, provided the system clock (CLKOUT)

Table 5-32 System Clock Sources

VDDSN MODCLK PLL Options

1 1 Normal Operation

1 0 1:1 mode (C LKOUT fre quenc y is equal to osc illator freque ncy)

PLL bypa ss mode (CLKO UT frequenc y is equal to one half th e

oscillator frequency)

0 0 Special t est mo de

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frequency (when RFD = 0b000) remains within the specified limits. With a reference

frequency of 4 MHz, the PLL can synthesize frequencies from 16 MHz to 44 MHz.

The output of the PLL can be divided down to reduce the system frequency with the

reduced frequency divider (RFD). The RFD is not contained in the feedback loop of

the PLL, so changing the RFD bits does not affect PLL operation.

Note that the system frequency programmed should not exceed the operating fre-

quency of any of the parts in the target system.

Figure 5-27 shows the overall block diagram for the PLL. Each of the major blocks

shown is discussed briefly below.

Figure 5-27 Phase-Locked Loop Block Diagram

5.6.4.1 Crystal Oscillator

The crystal oscillator has one 10-M¾ resistor and two external 36-pf capacitors con-

nected to the EXTAL and XTA L pins, as shown in Figur e 5-28. The internal oscillator

is designed to work best with a 4-MHz crystal. Crystal start-up times depend on the

value of the resistor. The start-up time can be reduced by reducing the value of the

resistor.

VSSSN

PHASE

DETECTOR CHARGE

PUMP

DIVIDER

XFCN

VCO

OSCILLATOR

CIRCUITRY

XFCPXTAL

EXTAL

VSSSN VSSSN

C2XFCP C1XFCP = 15.0 nF CXFCN = .1µF

Rxfc = 1k

MPC509

CIRCUIT BOARD

(OPTIONAL)

VDDSN / VDDSN

MUX

CLKOUT1:1 MODE

(NPO)

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Figure 5-28 Crystal Oscillator

5.6.4.2 Phase Detector

The phase detector compares both the phase and frequency of the reference clock

(

oscclk

in Figure 5-27) and the feedback clock. The reference clock comes from either

the crystal oscillator or an external clock source. The feedback clock comes from

either CLKOUT (th e system clock) in 1:1 mode or the VCO output d ivided down b y the

MF divider in normal mo de.

The phase detector pulses either the UP or DOWN signal, depending on the relative

phase of the two clocks. If the falling edge of the feedback clock lags the falling edge

of the reference clock, then the UP signal is pulsed. If the falling edge of the feedback

clock leads the falling edge of the reference clock, then the DOWN signal is pulsed.

The width of these pulses relative to the reference clock is dependent on how much

the two clocks lead or lag each other.

5.6.4.3 Charge Pump and Loop Filter

The UP and DOWN signals fr om the pha se detector contro l wheth er the char ge pump

applies or removes charge, respectively, from the loop filter. The loop filter is shown in

Figure 5-29. The filter network is external to the chip and can be replaced if necessary.

Figure 5-29 Charge Pump with Loop Filter Schematic

36 pF

4 MHz

10 MΩ

EXTAL

XTAL

CHARGE

PUMP

XFCP

MCU

–15.0 nfd

1 KΩ

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5.6.4.4 VCO

The VCO uses a single-ended design with an external capacitor to increase noise

immunity. The voltage on XFCP controls the VCO output frequency. The frequency-

to-voltage relationship (VCO gain) is positive, and the output frequency is twice the

maximum target system frequency.

5.6.4.5 Multiplication Factor Divider

The multiplication factor divider (MFD) divides down the output of the VCO and feeds

it back to the phase detector (when the PLL is not operating in 1:1 mode). The phase

detector controls the VCO frequency (via the charge pump and loop filter) such that

the reference and feedback clocks have the same frequency and phase.

Thus, the in put to the MFD, wh ich is also the outpu t of the VCO, is a t a frequ ency that

is the reference freq uency multiplied by t he same amount that the MFD divides by. For

example, if the MFD divides the VCO frequency by six, then the PLL will be frequency

locked when the VCO frequency is six times the reference frequency.

The presence of the MFD in the loop allows the PLL to perform frequency multiplica-

tion, or synthesis. When the PLL is operating in 1:1 mode, the MFD is bypassed and

the effective multiplication factor is one. Refer to 5.6.5 CLKOUT Freque ncy Control for

details on setting system clock frequency with the MF and RFD bits.

5.6.4.6 Clock De lay

Besides frequency synthesis, the PLL must also align the phase of (i.e., phase lock)

the re ference and system clocks to ensur e proper system timing. Since the p urpose of

the RFD is to allow the user to change the system frequency without forcing the PLL

to re-lock, the feedback clock must originate before the RFD (i.e., the output of the

VCO).

The clock delay is a chain of gates that approximates the delay through the RFD, clock

generation circuits, metal routing and the CLKOUT driver. This approach does not

allow for precise phase alignment. System applications must not rely on precise phase

alignment bet ween the reference and system clocks when the PLL is op erating in nor-

mal (frequency synthesis) mode. In 1:1 mode, however, the RFD is disabled. The

feedba ck clock comes directly from the CLKOUT pin, and true ph ase lock is achieved .

5.6.5 CLKOUT Frequency Control

The multiplication factor (MF) and reduced frequency divide (RFD) fields in the SCCR

determine the system clock (CLKOUT) frequency. Table 5-33 summarizes the avail-

able CLKOUT frequencies with a 4-MHz crystal.

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-75

Whenever clo ck r eset is asser ted , th e MF bits ar e se t to 0 x2 ( multi ply by si x) , an d th e

RFD bits are set to 0x3 (divide by eight). These values program the PLL to generate

the default system frequency of 3 MHz when a 4-MHz crystal is used.

5.6.5.1 Multiplication Factor (MF) Bits

The MF bits determine the operating frequency of the PLL. The 4-MHz crystal refer-

ence fr eq ue ncy i s m ul tip l ie d by an i n teg er f ro m 4 to 11, de pe nd in g on t he val u e of the

MF bits, resulting in a PLL frequency of 16 MHz to 44 MHz. Table 5-34 summarizes

the effect of the MF bits.

Table 5-33 CLKOUT Frequencies with a 4-MHz Crystal1

NOTES:

1. Settings resulting in CLKOUT frequencies in the shaded areas should not be used in the MPC509.

RFD[0:3] CLKOUT (Hz)

MF = X000

(x4) MF = X001

(x5) MF = X010

(x6) MF = X011

(x7) MF = X100

(x8) MF = X101

(x9) MF = X110

(x10) MF = X111

(x11)

0 = 0000 (÷ 1) 16.000 M 20.000 M 24.000M 28.000 M 32.000 M 36.000 M 40.000 M 44.000 M

1 = 0001 (÷ 2) 8.000 M 10.000 M 12.000 M 14.000 M 16.000 M 18.000 M 20.000 M 22.000 M

2 = 0010 (÷ 4) 4.000 M 5.000 M 6.000 M 7.000 M 8.000 M 9 .000 M 10.000 M 11.000 M

3 = 0011 (÷ 8) 2.000 M 2.500 M 3.000 M2

2. Default setting.

3.500 M 4.000 M 4.500 M 5.000 M 5.500 M

4 = 0100 (÷ 16) 1.000 M 1.250 M 1.500 M 1.750 M 2.000 M 2.250 M 2.500 M 2.750 M

5 = 0101 (÷ 32) 0.500 M 0.625 M 0.750 M 0.875 M 1.000 M 1.125 M 1.250 M 1.3750 M

6 = 0110 (÷ 64) 0.250 M 0.313 M 0.375 M 0.438 M 0.500 M 0.563 M 0.625 M 0.688 M

7 = 0111 (÷ 128) 0.125 M 0.156 M 0.188 M 0.219 M 0.250M 0.281 M 0.313 M 0.344 M

8 = 1000 (÷ 256) 62.500 K 78.125 K 93.750 K 0.109 M 0.125 M 0 .141 M 0.156 M 0.172 M

9 = 1001 (÷ 512) 31.250 K 39.063 K 46.875 K 54.688 K 62.500 K 70.313 K 78.125 K 85.938 K

10 = 1010 (÷ 1024) 15.625 K 19.531 K 23.438 K 27.344 K 31.250 K 35.156 K 39.063 K 42.969 K

11 = 1010 (÷ 1024) 15.625 K 19.531 K 23.438 K 27.344 K 31.250 K 35.156 K 39.063 K 42.969 K

12 = 1010 (÷ 1024) 15.625 K 19.531 K 23.438 K 27.344 K 31.250 K 35.156 K 39.063 K 42.969 K

13 = 1010 (÷ 1024) 15.625 K 19.531 K 23.438 K 27.344 K 31.250 K 35.156 K 39.063 K 42.969 K

14 = 1010 (÷ 1024) 15.625 K 19.531 K 23.438 K 27.344 K 31.250 K 35.156 K 39.063 K 42.969 K

15 = 1010 (÷ 1024) 15.625 K 19.531 K 23.438 K 27.344 K 31.250 K 35.156 K 39.063 K 42.969 K

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-76 Rev. 15 June 98 USER’S MANUAL

Note that the PLL frequency is equal to the CLKOUT frequency when the RFD bits are

programmed to 0b0000 (divide by one). Note also that the value of MF0 is ignored.

However, this bit should be written to zero in case it is used in future implementations.

CAUTION

The MF bits must not be programmed to a value that requires the

VCO to operate at greater than 180 MHz. (FVCO = 4 x MF factor x

FREF.) Specifically, if the reference crystal frequency is 5 MHz, the

MF settings of X110 (times 10) and X111 (times 11) must be avoided.

The MF bits can be read and written at any time. However, the MF bit field can be

write-protected by setting the MF lock (MPL) bit in the SCSLR.

Changing the MF bits causes the PLL to lose lock. If the loss-of-lock reset enable bit

(LOLRE) is set, the loss-of-lock condition causes the clock module to signal a reset

condition to the reset controller. The reset controller may wait for the PLL to lock before

negating reset. Thus, the PLL can still be out of lock when RESETOUT is negated.

After changing the MF bits, software should monitor the system PLL lock status

(SPLS) bit in the SCSLR to determine lock status.

The RFD bits should always be written to a value of 0x1 or greater before changing

the MF bits to ensure the system frequency does not exceed the system’s design mar-

gin, s ince t he VCO o versho ots in freque ncy as it trie s to co mpensat e for t he chan ge

in frequency. For example, to change from the default system frequency to 16 MHz,

write the RFD bits to 0x1, then write the MF bits to 0x0. After the PLL locks, write the

RFD bits to 0x0.

When the PLL is operating in one-to-one mode, the multiplication factor is set to one

and MF is ignored.

Figure 5-27 shows how the PLL uses the MF bits to multiply the input crystal fre-

quency. The output of th e VCO is divi ded down to generate the feedback signa l to the

phase comparator. The MF bits control the value of the divider in the PLL feedback

loop. The phase comparator determines the phase shift between the feedback signal

Table 5-34 Multiplication Factor Bits

MF Field (Binary) Multiplication Factor PLL Frequency

(with 4-MHz Reference)

x000 4 16 MHz

x001 5 20 MHz

x010 6 24 MHz

x011 7 28 MHz

x100 8 32 MHz

x101 9 36 MHz

x110 10 40 MHz

x111 11 44 MHz

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

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and the reference clock. This difference results in either an increase or decrease in the

VCO output frequency.

5.6.5.2 Reduced Frequency Divider (RFD[0:3])

The RFD bits control a prescaler at the output of the PLL. The reset state of the RFD

bits is 0x3, which divides the output of the VCO by eight.

These bit s can be ch anged witho ut affectin g the PLL’s VCO, i.e., no re-lo ck delay is

incurre d. All change s in frequen cy are synchroni zed to the ne xt falling edg e of the cur-

rent system clock.

Table 5-35 summarizes the possible values for the RFD bits.

These bits can be read at any time. They should be written only when the system PLL

lock status bit (SPLS) is set. Writing the RFD bits, especially to 0x0, when the PLL is

not locked can ca use the clock frequ ency to surpass the syste m operating freq uency.

Software is responsible for monitoring the SPLS bit and preventing a write to RFD[0:3]

while the PLL is out of lock.

The RFD bits should always be written to a value of 0x1 or greater before changing

the MF bits to ensure the system frequ ency does not exceed the system’s design mar-

gin since the VCO overshoots in frequency as it tries to compensate for the change in

frequency. The RFD bits should be changed to their final value only after the MF bits

have been written to their final value and PLL lock at the new frequency has been

established. For example, to change from the default system frequency to 16 MHz,

Table 5-35 Reduced Frequency Divider Bits

RFD Field

(Binary) Divider

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 512

1010 1024

1011 1024

1100 1024

1101 1024

1110 1024

1111 1024

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-78 Rev. 15 June 98 USER’S MANUAL

write the RFD bits to 0x1, then write the MF bits to 0x0. After the PLL locks, write the

RFD bits to 0x0.

The RFD bits can be protected against further writes by setting the RFD lock (RFDL)

bit in the SC SL R re gi ste r.

NOTE

The RFD bits do not a ffect clock freq uency when t he system clock is

operating in 1:1 mode.

5.6.6 Low-Power Modes

The clock module provides one normal operating mode and three low-power modes.

The low-po wer mode (LPM) bi ts in the SCCR select one of these fou r modes. When

one of the three low-power modes is selected, the EBI prevents the CPU from starting

any more bus cycles, but allows the current bus cycle to terminate. At the end of the

current b us cycle, the appropriate clocks are st opped and th e EBI continues operatio n

as defined for the low-power mode selected.

Note th at in debug mode, the crystal an d the PLL are not shut do wn, but co ntinue to

run and provide clocks to the debug module.

The LPM bits can be protected against further writes by setting the LPM lock (LPML)

bit in the SC LS R re gi ste r.

5.6.6.1 Normal Mode

The normal operating mode, state 0x0, is the state out of clock reset. This is also the

state the bits go to when the low-power mode exit signal arrives.

5.6.6.2 Single-Chip Mode

Mode 0x1 is single-chip mod e. In this mode, CLK OUT is turne d off. This mo de can b e

selected when the MCU is used by itself and does not need to provide a system clock.

Turning off CLKOUT saves power and improves electromagnetic compatibility. The

low-power mode exit signal is the logical OR of the external reset pin, the IRQ[0:1] pins

(if LPMM = 1), the decrementer interrupt, and the PIT interrupt.

Sinc e the oscilla tor and PLL are still ru nning an d locked, the low-po wer mode ex it sig-

nal must be a minimum of two system clock cycles and exiting this state does not incur

a PLL lock time.

5.6.6.3 Doze Mode

Mode 0x2 is doze mode. In this state, not only is CLKOUT turned off, but also all inter-

nal clocks are turned off. However, the oscillator and the PLL continue to operate

normally. The low-power mode exit signal is the logical OR of the external reset pin,

the IRQ[0:1] pins (if LPMM = 1), the decrementer interrupt, and the PIT interrupt. Since

the oscillator and PLL are still running and locked, the low power mode exit signal must

be a minimum of two system clock cycles and exiting this state does not incur a PLL

lock time.

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-79

5.6.6.4 Slee p Mode

Mode 0x3 is sleep m ode. In th is state,

all

clocks are turned off, including the oscillator

and the PLL. The low-power mode exit sig nal is the logical OR of the external reset pin

and the IRQ[0:1] pins (if LPMM = 1). The decrementer interrupt and the PIT interrupt

are not active in this mode. Since all clocks are stopped, this signal is asynchronous.

Exiting state 0x3 requires the normal crystal start-up time plus PLL lock time or time-

out.

5.6.6.5 Exiting Low-Power Mode

Table 5-36 summarizes the events that cause the MCU to exit from each of the three

low-power modes.

The low-power mode mask (LPMM) bit in the SCCR is used to mask the IRQ[0:1] pins

to the low-power mode exit logic. When the LPMM bit is zero, the IRQ[0:1] pins are

disabled from causing an exit from any of the low-power modes. When the LPMM bit

is a one, the IRQ[0:1] pins are enabled to cause an exit from any of the low-power

modes.

When a low level occurs at the IRQ[0:1] pins and the LPMM bi t is a o ne, the LP M bits

are cleared and the low-power mode exit sequence begins. If the LPMM bit = 1, then

the low-power mode exit sequence is started even if a low-power mode is not selected.

The time r equired to e xit the low-po wer mode s depends on whic h mode was se lected.

For modes 1 and 2, the delay from the exit sign al being asserted to the clocks starting

up is two clock cycles of the frequency that the VCO was programmed to generate.

The delay for mode 3 is the crystal start-up time plus the VCO lock time.

The LPMM bit can be read or written any time.

5.6.7 System Clock Lock Bits

The system clock lock and status register (SCLSR) contains several bits that lock the

corresponding bits or fields in the system clock control register (SCCR). Table 5-37

summarizes the lock bits and the fields that they control.

Table 5-36 Exiting Low-Power Mode

Event Causing Exit

from Low-Power Mode Mode 0x1 Mode 0x2 Mode 0x3

RESETOUT assertion Yes Yes Yes

IRQ pin assertion (if LPMM = 1) Yes Yes Yes

Decrementer in terr upt Yes Yes No

PIT interrupt Yes Yes No

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When a lock bit (MPL, LPML, or RFDL) is cleared, writes to the corresponding bit or

field in the SCCR (MF, LPM or RFD, respectively) take effect. When the lock bit is set,

however, writes to the corresponding bit or field in the SCCR have no effect. All other

bits in the SCCR are unaffected.

The MPL, LPML, and RFDL bits can be written to zero as many times as required. Only

a clock reset can clear one of these bits, however, once it is written to a one. In freeze

mode, the lock bits can be written to a one or to a zero at any time.

5.6.8 Power-Down Wake Up

PDWU (power-down wake up) is an output signal used to signal an external power

supply to enable power to the system. PDWU can be asserted by the decrementer

counting down to zero or by the CPU setting the wake-up request (WUR) bit in the

SCLSR.

The WU R bit contr ols the s tate of the PDWU pi n directl y. The WUR b it is set when the

CPU wr ites a one to it or when the MSB of th e de cre m enter cha nge s fr om a zer o to a

one. WUR is cleared when the CPU writes a zero to it. (Note that to clear the bit, it is

not

necessary to read the bit as a one before writing it as a zero, as is required to clear

most status bits.)

Note th at the WUR b it is no t affe cted by r esets a nd its va lue sh ould rem ain as l ong as

the keep-alive power is valid. At keep-alive reset, the WUR bit is in an unknown state.

5.6.9 Time Base and Decrementer Support

The time base is a timer facility defined by the PowerP C architecture. I t is a 64-bit free-

running binary counter which is incremented at a frequency determined by each imple-

mentation of the time base. There is no interrupt or other indication generated when

the count rolls over. The period of the time base depends on the driving frequency. The

time base is not affected by any resets and should be initialized by software.

The decrementer is a 32-bit decrementing counter defined by the PowerPC architec-

ture. The decrementer causes an interrupt, unless masked by MSR[EE], when it

passes through zero.

The time base and decrementer use the stand-by power supply, VDDKAP1. This

allows them to be used while normal power is off. The time base and decrementer also

continue to function in all low-power modes except sleep mode (LPM = 0b11), in which

the oscillator is turned off.

Table 5-37 System Clock Lock Bits

SCLSR Lock Bit SCCR Field Affected

MPL MF

LPML LPM

RFDL RFD

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-81

The state of the decre menter and ti me base af ter standby power is restored is indeter-

minate. The decrementer runs continuously after power-up (unless the decrementer

clock enab le bit is cleared). Syste m software is n ecessary to perform any initialization .

The decrementer is not affected by reset and continues counting while reset is

asserted.

Reads and writes of the time base and decrementer are restricted to special instruc-

tions. Refer to SECTION 3 CENTRAL PROCESSING UNIT and to the

RCPU

Reference Manual

(RCPURM/AD) for instructions on reading and writing the time

base and decrementer.

5.6.9.1 Time Base and Decrementer Clock Source

The frequency source is the crystal oscillator divided by four

The clock source for the time base and decrementer is the crystal oscillator divided by

four. With a 4-MHz oscillator frequency, the period for the time base is:

TTB = 264 / 1MHz = 1.8 x 1013 seconds

which is approximately 585,000 years.

With the same clock source, the period for the decrementer is:

TDEC = 232 / 1MHz = 4295 seconds

which is approximately 71.6 minutes.

5.6.9.2 Time Base/Decrementer and Freeze Assertion

The assertion of the global freeze signal can stop the clock to the time base and dec-

rement er if th e SIUFRZ bi t in the SIUMC R (0x80 07 FC00) is set. Th e actual free zing

of the clock source occurs at the falling edge of the clock.

5.6.9.3 Decrementer Cl ock Enable (DCE) Bit

The decrementer clock enable (DCE) bit in the SCCR enables or disables the clock

source to the decrementer. The default state is to have the clock enabled. The actual

clock source is determined by the TBS bit. The DCE bit does not affect the decre-

menter until after the next increment time, as determined by the clock source.

5.6. 10 Clock Resets

The following reset conditions cause the internal clock reset signal to be asserted:

external reset, loss-of-oscillator (when LOORE is set), and loss-of-lock (when LOLRE

is set). Clock reset causes the clock circuitry, including the PLL, oscillator, SCCR, and

SCLSR to be reset.

Note that all reset sources cause normal reset processing to occur, as described in 5.8

Reset O peratio n. However, only the reset sources mentioned above (external reset,

loss-of-oscillator, and loss-of-lock) result in clock reset.

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5.6.10.1 Loss of PLL Lock

The system PLL lock status (SPLS) in the SCLSR indicates the current lock status of

the PLL. When the SP LS bit is clea r , the PLL is n ot l ocke d. Whe n th e SP LS b it is se t,

the PLL is locked. The SPLS bit can be read anytime. It can be writte n only during spe-

cial test mode.

In PLL bypass mode and special test mode, this bit is forced high to indicate a lock

condition.

The loss-of-lock reset enable (LOLRE) bit in the SCCR indicates how the clocks

should handle a loss of lock indication (SPLS asserted). When LOLRE is clear, clock

reset is not asserted if a loss of lock indication occurs. When LOLRE is set, clock reset

is asserted when a loss of lock indication occurs. The reset module may wait for the

PLL to lock before negating reset (see 5.8 Reset Operation). The LOLRE bit is cleared

whenever clock reset is asserted and may be re-initialized by software.

CAUTION

When the clock is in PLL bypass mode or special test mode, setting

the LOLRE bit in the SCCR generates a loss-of-lock reset request

(since the PL L is off). The L OLRE bit must n ot be set whe n the clock

is in PLL bypass or special test mode.

The system PLL lock status sticky bit (SPLSS) in the SCLSR must be initialized by

software. After the bit is set by software, any out-of-lock indication clears the SPLSS

bit, even if the out-of-lock indication is active while the setting takes place. The bit

remains clear until software again sets it. At clock reset, the state of the SPLSS bit is

zero, since the PLL has not achieved lock.

5.6.10.2 Loss of Oscillator

The loss-of-oscillator (LOO) status bit in the SCLSR indicates the absence of an input

freque ncy on the EX TAL pin. A fr equency be low 125 kH z causes the l oss-of-osci llator

circuitry to assert the LOO bit and force the PLL into self-clocked mode. A frequency

above 500 kHz causes the loss-of-oscillator circuitry to negate the LOO bit, and the

PLL operates normally. The LOO bit can be read any time. It can be written only in spe-

cial test mode.

The loss-of-o scillator reset enable (LOORE) bi t in the SCCR indicates how the clock

module should handle a loss-of-oscillator condition (LOO asserted). When LOORE is

clear, clock reset is not asserted if a loss-of-oscillator indication occurs. When LOORE

is set, clock reset is asserted when a loss-of-oscillator indication occurs. The reset

module may wait fo r th e P LL to lock b ef ore ne ga ting re set (se e 5.8 Reset Op er ati o n).

The LOORE bit is cleared when clock reset is asserted and may be re-initialized by

software.

Note that a loss of oscillator forces the PLL to go out of lock and into the self-clocked

mode (SCM), regardless of the state of the LOORE bit.

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5.6.11 System Clock Control Register (SCCR)

The SCCR con trols the operation of the PLL. It is powered b y VDDKAP1. The SCCR

is not affected by reset conditions that do not cause clock reset. Clock reset (caused

by loss-of-o scillator, loss- of-lock, or e xternal re set) cau ses the reg ister to be reset a s

indicated in the diagram.

SCCR — System Clock Control Reg ister 0x8007 FC50

012345678910 11 12 13 14 15

RESERVED LPMM 0 DCE LOL-

RE LOOR

E0MF RESERVED

CLOCK RESET:

0000010000010000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED LPM RESERVED RFD

CLOCK RESET:

0000000000000011

Table 5-38 SCCR Bit Settings

Bit(s) Name Description

0:2 — Reserved

3 LPMM Low-power mode mask

0 = IRQ[0:1] pins cannot be used to wake up from LPM

1 = IRQ[0:1] pins can be us ed to w ake up from LPM

4—Reserved

5DCE

Decrementer clock enable

0 = Clock to decrementer is disabled

1 = Clock to decrementer is enabled

6LOLRE

Loss-of -loc k res et enable

0 = Loss of lock does not cause reset

1 = Loss of lock causes re set

7LOORE

Loss-of-oscillator reset enable

0 = Loss of oscillator does not cause reset

1 = Loss of oscillator causes reset

8—Reserved

9:12 MF

Multipl ication fac tor. In norma l mode, the output o f the VCO is divided down to gen erate the feed-

back signal to the phase comparator. The MF fi eld controls the value of the divider in the PLL

feedback loop.

The MF and RFD fields determine the CLKOUT frequency. Refer to Table 5-33.

X000 = x 4

X001 = x 5

X010 = x 6

X011 = x 7

X100 = x 8

X101 = x 9

X110 = x 10

X111 = x 11

Caution: The MF bits must not be programmed to a value that requires the VCO to operate at

greater than 180 MHz. (FVCO = 4 x MF factor x FREF.) Specifically, if the reference crystal fre-

quency is 5 MHz, the MF settings of X110 (times 10) and X111 (times 11) must be avoided.

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5.6.12 System Clock Lock and Status Register (SCLSR)

The system clock lock and status register (SCLSR) contains lock and status bits for

the PLL. It is powered by VDDKAP1. The SCLSR is not affected by reset conditions

that do not cause clock reset. Clock reset (caused by loss-o f-oscillator, loss-of-lock, or

external reset) causes the register to be reset as indicated in the diagram.

U = Unaffected by clock reset

13:21 — Reserved

22:23 LPM

Low-power mode select bits. Refer to Table 5-35 and Table 5-36.

00 = Normal operating mode

01 = Low-power mode 1 (single chip)

10 = Low-power mode 2 (doze)

11 = Low-power mode 3 (sleep)

Since all clocks are stopped in sleep mode, exiting this mode requires the normal crystal start-

up time plus the PLL lock time. Minimum length of the exit signal is two clocks in single-chip

mode, three clocks in doze mode, and until the PLL is stable in sleep mode.

24:27 — Reserved

28:31 RFD

Reduced-frequency divider. The RFD field controls a prescaler at the output of the PLL. In normal

mode, the MF and RFD fields determine the CLKOUT frequency. (In bypass mode, only this field,

and not the MF field, affects CLKOUT frequency. In one-to-one mode, this field has no effect.)

Refer to Ta ble 5-33.

0000 = ÷ 1

0001 = ÷ 2

0010 = ÷ 4

0011 = ÷ 8

0100 = ÷ 16

0101 = ÷ 32

0110 = ÷ 64

0111 = ÷ 128

1000 = ÷ 256

1001 = ÷ 512

1010 = ÷ 1024

1011 = ÷ 1024

1100 = ÷ 1024

1101 = ÷ 1024

1110 = ÷ 1024

1111 = ÷ 1024

SCLSR — System Clock Lock and Status Register 0x8007 FC54

012345678910 11 12 13 14 15

RESERVED STME MPL LPML RFDL RESERVED STMS

CLOCK RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED WUR RESERVED SPLS

SSPLS LOO

CLOCK RESET:

0000000U00000UUU

Table 5-38 SCCR Bit Settings (Continued)

Bit(s) Name Description

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

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5.7 System Protec tion

SIU system protection features include a periodic interrupt timer and a bus monitor.

Additional MPC509 system protection features include the PowerPC decrementer and

time base, described in SECTION 3 CENTRAL PROCESSING UNIT, and a software

watchdog, described in 6.4 Sof tw ar e Wat c hd og.

5.7.1 System Protection Features

• The bus monito r monitors any interna l-to-extern al bus accesses. Four selectab le

response time period s are available, ranging from 16 to 2 56 system c lock cycles.

An internal bus error signal is generated if a bus time-out occurs.

• The periodic interrupt timer generates an interrupt after a period specified by the

user.

Table 5-39 SCLSR Bit Settings

Bit(s) Name Description

0:3 — Reserved

4STME

System PLL test mode enable

0 = Test mode disabled

1 = Test mode enabled

5MPL

MF lock

0 = Writes to MF field (in SCCR) allowed

1 = Writes to MF field have no effect

6 LPML Low-power mode lock

0 = Writes to LPM bits allowed

1 = Writes to LPM bits have no effect

7RFDL

Reduced-frequency divide lock

0 = Writes to RF bits allowed

1 = Writes to RF bits have no effect

8:13 — Reserved

14:15 STMS System PLL test mode select

00 = Normal operation

00, 01, 11 = Special test modes (for factory test only)

16:22 — Reserved

23 WUR Wake-up request

0 = PDWU p in for ced low (request power off)

1 = PDWU pin forced high (request power on)

24:28 — Reserved

29 SPLSS System PLL lock status sticky bit

0 = PLL has gone out of lock since software last set this bit

1 = PLL has remained in lock since software last set this bit

30 SPLS System PLL lock status

0 = PLL has not locked

1 = PLL has locked

31 LOO Loss-of-oscillator status

0 = Clock detected

1 = Crystal not detected

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5.7.2 System Protection Registers

Table 5-40 shows the SIU system protection registers.

5.7.3 Periodic Interrupt Timer (PIT)

The periodic interru pt time r consists of a 16-bit counter clocked by the input os cillator

signal divided by four. A 4 -MHz system oscillator freque ncy results in a one-microsec-

ond c ount inte rv al . The in p ut c lo ck s ig n al is su pp lied by th e cl ock mod u le. In o rde r to

ensure adequate range for the PIT, the input clock signal to the PIT must not exceed

4 MHz.

The 16-bit counter counts down to zero when loaded with a value from the PIT count

(PITC) field in the PICSR. After the timer reaches zero, the PIT status (PS) bit is set

and an interrupt is generated if the PIT interrupt enable (PIE) bit is set to one.

At the next input clock edge, the value in the PITC is loaded into the counter, and the

process st arts over. W hen a new val ue is loaded into the P ITC field, the periodic tim er

is updated (i.e., the new value is loaded into the modulus counter), and the counter

begins co unti ng.

The software service routine should read the PS bit and then write it to zero to termi-

nate the interrupt request. The interrupt request remains pending until the PS bit is

cleared. If the counter reaches zero again before the interrupt service routine clears

the PS bit, the interrupt request remains pending until PS is cleared.

Any write to the PITC stops the current countdown, and the count resumes with the

new value in PITC. If the PITC is loaded with the value 0, the PIT counts for the max-

imum period.

If the PIT enable (PTE) bit is not set, the PIT is unable to count and retains the old

count value. Reads of the PIT register have no effect on the value in the PIT.

Figure 5-30 is a block diagram of the PIT.

Table 5-40 System Protection Address Map

Access Address Register

S/U 0x8007 FC40 Periodic Interrupt Control and Select Register (PICSR)

S/U 0x8007 FC44 Periodic Interrupt Timer Register (PIT)

S 0x8007 FC48 Bus Monitor Control Register (BMCR)

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-87

Figure 5-30 Periodic Interrupt Timer Block Diagram

5.7.3.1 PIT Clock Frequency Selection

The PIT clock freq uen cy sele ct (PCFS) field in the PICS R selects t he app ropriat e fre-

quency for the PIT clock source over a range of external clock or crystal frequencies.

The bit encod ings ar e shown in Table 5-41.

To ach ieve a PI T settin g of appr oximate ly 1 MHz , program the PCF S field as shown

in Table 5-42.

Table 5-41 PCFS Encodings

PCFS Encoding Divide Input

Frequency by:

0b000 4

0b001 8

0b010 16

0b011 32

0b100 64

0b101 Reserved

0b110 Reserved

0b111 Reserved

EXTAL

DISABLE

CLOCK

FREEZE

16-BIT

PITC

COUNTER PS

PIE

PIT INTERRUPT

PTE

MODULUS

PIT

PCFS[2:0]

CLOCKS

PCFS

DIVIDE

BY 4

LOGIC

FREEZE

LOGIC

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-88 Rev. 15 June 98 USER’S MANUAL

5.7.3.2 PIT Time-Out Period Selection

The PIT time-out period is determined by the input clock frequency, the divider speci-

fied in the PCFS field, and the timing count specified in the PITC field of the PICSR.

The time-out pe riod is calculated as follows:

PIT period = PITC/(PIT frequency)

where t he PIT fre qu ency i s e qual to the P IT i np ut clo ck fr e que ncy divided by a divi sor

determined by the PCFS bits , as sp ecified in 5.7.3.1 PIT Clock Fre que ncy Sel e ction .

With a 4-MHz clock frequency and a PCFS value of 0b000 (divide by 4, reset value),

this gives a range from 1 µs (PITC = 0x0001) to 65.5 ms (PITC = 0x0000).

Table 5-42 Recommended Settings for PCFS[0:2]

Input Frequency Range PCFS[0:2]

1 MHz < FREQ ≤ 4 MHz 0b000

4 MHz < FREQ ≤ 8 MHz 0b001

8 MHz < FREQ ≤ 16 MHz 0b010

16 MHz < FREQ ≤ 32 MHz 0b011

32 MHz < FREQ ≤ 64 MHz 0b100

Reserved 0b101

Reserved 0b110

Reserved 0b111

Table 5-43 Example PIT Time-Out Periods

PITC Value Time-Out Period1

NOTES:

1. After a time-o ut is s ignaled, s ome add itional tim e may

elapse prior to any obse rved act ion.

1 (decimal) 1 µs

5 (decimal) 5 µs

10 (decimal) 10 µs

100 (decimal) 100 µs

1000 (decimal) 1.00 ms

10000 (decimal) 10.00 ms

50000 (decim al ) 5 0.0 ms

FFFF (hex) 65.5 ms

0000 (hex)2

2. The count value associated with the maximum time-

out is 0b0000.

65.5 ms

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-89

5.7.3.3 PIT Enable Bits

The PIT enable (PTE) bit in the PICSR enables or disables the timer. When the timer

is disabled, it retains its current va lue. When the timer is en abled, it resu mes counting

starting with the current value.

The periodic inte rrupt enable (PIE) bit in the PICSR enables or disables PIT interrupts.

When this bit is cleared, the PIT does not generate any interrupts. The PIT continues

to count even when interrupts are disabled.

5.7.3.4 PIT Interrupt Request Level and Status

The PIT inte rrupt request leve l (PITIRQL) field in the PIT/po rt Q interru pt level register

(PITQIL) determines the level of PIT interrupt requests. Refer to 6.5.3.4 PIT/Port Q

Interrupt Levels Register for a description of this register.

The PIT status (PS) bit is set when the PIT issues an interrupt request. This occurs

when the modulus counter counts to zero. The PS bit is cleared by writing it to zero

after reading it as a one. Attempting to write this bit to one has no effect.

5.7.3.5 Periodic Interrupt Control and Select Register

The periodic interrupt control and select register (PICSR) contains the interrupt status

bit as well as the controls for the 16 bits to be loaded into a modulus counter. Reserved

bits in this register return zero when read. This register can be read or written at any

time.

PICSR — Periodic Interrupt Control and Select Register 0x8007 FC40

012345678910 11 12 13 14 15

0PTE PIE RESERVED PCFS RESERVED PS

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

PITC

RESET:

0000000000000000

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-90 Rev. 15 June 98 USER’S MANUAL

5.7.3.6 Periodic Interrupt Timer Register

The periodic interrupt timer (PIT) register is a read-only register that shows the current

value in the periodic interrupt down counter. Writes to this register have no effect.

Reads of the register do not affect the counter.

5.7.4 Hardware Bus Monitor

Typical bus systems require a bus monitor to detect excessively long data and address

acknowledge response times. The MPC509 provides a bus monitor to monitor inter-

nal-to -external bus acce sses on t he E-bus . If the external bus pipeline depth is zero

(all previous external bus cycles are complete), the monitor counts from transfer start

to tran sfe r ackno w ledg e. Other wise , t he mo ni to r cou nts fr om transfer a ckno wle dge to

transfer ackn owl edg e.

If the monitor times out, transfer error acknowledge (TEA) is asserted internally.

The bus monitor is always enabled (regardless of the value of the BME bit in the

BMCR) while the internal freeze signal is asserted and debug mode is enabled, or

while debug mode is enabled and the debug non-maskable breakpoint is asserted.

Table 5-44 PICSR Bit Settings

Bit(s) Name Description

0—Reserved

1PTE

Periodic timer enable

0 = Disable decrementer counter

1 = Enable decrementer counter

2PIE

Periodic interrupt enable

0 = Disable peri odi c int errup t

1 = Enable periodic interrupt

Caution: Be sure the EE (external interrupts enable) bit in the MSR is cleared before changing

the value of this bit.

3:4 — Reserved

5:7 PCFS PIT clock frequency select. To achieve PIT setting of approximately 1 MHz, program the PCFS

field as shown in Table 5-42.

8:14 — Reserved

15 PS PIT status

0 = No PIT interrupt asserted

1 = Periodic interrupt asserted

16:31 PITC Periodic interrupt timing count. Number of counts to load into the PIT.

PIT — Periodic Interrupt Timer Register 0x8007 FC44

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED PIT

RESET: UNDEFINED

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-91

5.7.4.1 Bus Monitor Timing

The bus monitor timing (BMT) field in the BMCR allows the user to select one of four

selectable response time periods. Periods range from 16 to 256 system clock cycles.

The programmability of the time-out allows for a variation in system peripheral

respon se time. The timi ng mechanism is derived fr om taps off a divid er chain which is

clocked by the system clock.

The time-out period should be set for the maximum to tal cycle time (including all bea ts

of a burst, i.e., until TA is asserted for the final beat of a burst cycle), not for just the

address phase or data phase of the cycle.

5.7.4.2 Bus Monitor Lock

The bus mo ni to r lo ck (B ML K) bi t in th e B MCR is use d to preven t i na dve rt ent wri tes to

the BMCR. Once BMLK is set, subsequent writes to the BMCR have no effect and

result in a data error on the internal bus.

Writing a zero to BMLK after it ha s been set has no e ffect. A write to the BMCR b efore

the lock bit is set can configure protected bits and set the BMLK in the same access.

The BMLK bit is cleared by reset. It can also be cleared by software while the internal

FREEZE signal is asserted. Software can write BMLK to zero any number of times

before writing it to one.

5.7.4.3 Bus Monitor Enable

The bus monitor enable (BME) bit in the BMCR enables or disables the operation of

the bus monitor during internal-to-external bus cycles. Note that the bus monitor is

always enabled while freeze is asserted and debug mode is enabled, or when debug

mode i s enabled and the de bu g non-ma skab l e br ea kpo in t is a sser t ed , even if BME is

cleared.

5.7.4.4 Bus Monitor Control Register

A diagram and description of the BMCR are provided below.

BMCR — Bus Monitor Control Reg i ster 0x8007 FC48

012345678910 11 12 13 14 15

RESERVED BMLK BME BMT RESERVED

RESET:

0000010000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED

RESET:

0000000000000000

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-92 Rev. 15 June 98 USER’S MANUAL

5.8 Re se t Opera ti o n

Reset procedures handle system initialization and recovery from catastrophic failure.

The MPC509 performs reset with a combination of hardware and software. The SIU

determines whether a reset is valid, asserts control signals, performs basic system

configu ration based on hardware m ode-s elect inp uts, and t hen pas ses cont rol to the

CPU.

Reset i s the highest- prio rity CPU exception . Any proce ssing in prog ress is ab orte d by

the reset exception and cannot be restarted. Only essential tasks are performed during

reset exception processing. Other initialization tasks must be accomplished by the

except ion handle r ro utine.

5.8.1 Reset Sources

The following sources can cause reset:

• External reset pin (RESET)

• Loss of oscillator

• Loss of PLL lock

• Software watchdog reset

• Checkstop reset

• JTAG reset (external TRST pin)

All of these reset sources are fed into the reset controller. The reset status register

(RSR) reflects the most recent source, or sources, of reset. (Simultaneous reset

reques ts ca n cau se more th an o ne bi t to be se t at t he sa me t ime.) This re giste r c on-

tains one bit for each reset source. A bit set t o logic one indicat es the type of reset that

last occurred.

Individual bits in the RSR can be cleared by writing them as zeros after reading them

as ones . (Writin g indivi dual bi ts as ones ha s no effect.) The r egister can be read at al l

times. Assertion of the RESET pin clears all bits except the RESET bit.

Table 5-45 BMCR Bit Settings

Bit(s) Name Description

0:3 — Reserved

4BMLK

Bus monitor lock

0 = Enable changes to BMLK, BME, BMT

1 = Ignore writes to BMLK, BME, BMT

5BME

Bus monit or enab le

0 = Disable bus monitor

1 = Enable bus monitor

6:7 BMT

Bus monitor timing. These bits select the time-out period, in system clocks, for the bus monitor.

00 = 256 system clocks

01 = 64 system clocks

10 = 32 system clocks

11 = 16 system clocks

8:31 — Reserved

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-93

5.8.2 Reset Flow

The reset fl ow can be divided into two flow s: exter nal reset re quest fl ow and th e inte r-

nal reset request flow .

5.8. 2.1 Exte rnal Reset Re ques t Flow

Figure 5-31 is a flow diagram for external resets.

RSR — Reset Status Register 0x8007 FC4C

012345678910 11 12 13 14 15

RE-

SET LOO LOL SW CR JTAG RESERVED

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED

Table 5-46 Reset Status Register Bit Settings

Bit(s) Name Description

0 RESET If set, sou rce of reset is the external RESET input pin. This pin should be asserted whenever VDD

is be low VDDmin.

1LOO

If set, source of reset is a loss of oscill ator. The clock module asserts loss-of -oscillator reset when

the MC U is in lo w-power mo de 3 or no cloc k signal is pr esent on the EXT AL pin. If the clo ck mod-

ule detects a loss-of-oscillator condition, erroneous external bus operation will occur if synchro-

nous external devices use the MCU input clock. Erroneous operation can also occur if devices

with a PLL use the MCU CLKOUT signa l. This sou rce of reset i s masked by the loss -of-oscil lator

reset enable (LOORE) bit in the system clock control register (SCCR).

2LOL

If se t, the cause of re set is the lo ss of PLL loc k. The cloc k module a sserts loss-of-l ock reset w hen

the PLL det ects a loss of lock and the loss-of-l ock reset ena ble bit is set in the sy stem cloc k con-

trol register (SCCR). I f the PLL detects a loss of lo ck condition, erroneous external bus operatio n

will occur if synchronous external devices use the MCU input clock. Erroneous operation can

als o occur if d evices with a P LL use th e MCU CLK OUT sign al. Thi s sour ce of res et is mask ed

by the loss-of-lock reset enable (LOLRE) bit in the system clock control register.

3SW

If se t, sou rce of res et is a software watchdog ti me -out. This oc cu rs w hen th e s oftware watc hdo g

counter reaches zero.

4CR

If set, the source of reset is a checkstop. This occurs when the processor enters the checkstop

state and the checkstop reset is enabled.

5 JTAG If set, the source of reset is the JTAG module. This reset occurs only during production testing.

6:31 — Reserved

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-94 Rev. 15 June 98 USER’S MANUAL

Figure 5-31 External Reset Request Flow

The external reset flow begins when the RESET pin is asserted (low). The external

reset request has a synchronization phase during which it takes one of the two paths

IDLE

IS CNT

= 17?

ASSERT RES ET O UT

AND INTERNAL RESET.

REQUEST INTERNAL BUSES

RESET = 1

START THE COUNTER

WAIT FOR CNT = 17

WAIT FOR PLL TO LOCK

THIS STAT E DEPENDS ON PLL

MODE AND RESET CONFIG

WORD

IS CNT = 17

OR PLL LOCKED?

CONTINUE REQUESTING BUSES

RELEASE RES ETOUT AND INTERNAL

IF RE SET = 0

IF RESET = 0

RESETS AND START THE COUNTER

YES

RELEASE BU S

AND GO TO IDLE

RESET = 0

YES

FROM INTERNAL

RESET FLOW

REQUESTS

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-95

(synchronous or asynchronous) before getting to the reset control logic. The external

reset request follows the asynchronous path in the case of power-on reset or in case

of loss of oscillator.

Under all remaining conditions the reset request goes through the synchronous path,

in which the reset request is synchronized with the system clock. RESET must be

asserted for at least two clock cycles to be recognized by the reset control block.

Once the reset request passes through the synchronization phase, the chip enters

reset. The RESETOUT pin and the internal reset signal are driven while the chip is in

reset. (No te t ha t th is inte rn al re set sig nal is an ou tp ut fro m th e rese t co nt ro l block tha t

is sent to the internal MCU modules. This signal is different from internal reset request,

which are inputs to the reset control block.) Six clock cycles after RESET is negated,

all mode select pins are sampled except for the VDDSN and MODCLK pins. These

two pins are sampled at the rising edge of RESETOUT.

After the RESE T pin i s negated, R ESETOUT is held fo r a minimum of 17 clock cycles.

After the 17 clock cycles, the state of data bus configuration bit 19 and the phase-

locked loop (PLL) mode determine when RESETOUT is released.

• If the PLL is o pera ting in 1 :1 mo de or the dat a bus config urat io n bit 1 9 is cle ared ,

RESETOUT is release d wh en the PLL is locked.

• If data bus configuration bit 19 is set and the PLL is not operating in 1:1 mode,

RESETOUT is released as soon as the 17 clock cycles have finished.

When the PLL is operating in 1:1 mod e, the MCU waits until the PLL is locke d before

releasing RESETOUT, since the clo ck which is an input to the MCU may also be used

as an input to other bus devices. In addition, if other bus devices use the MCU

CLKOUT signal to feed a PLL, the user must ensure that the PLL is locked before

RESETOUT is rele a sed . This i s ach ie ved by cl ea rin g data b us c onf ig u ratio n bit 1 9 at

reset.

While RESETOUT is bei ng asse rte d, the SIU req ue sts control of the I- bus and L-bu s.

The IMB2 interface requests control of the IMB2 bus. Internal reset is released when

RESETOUT is released; however, the internal buses are not released until 16 clock

cycles after RESETOUT is negated.

If an external reset is asserted any time during this process, this process begins again.

5.8.2.2 Internal Reset Request Flow

Figure 5-32 is a flow diagram for internal reset requests.

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-96 Rev. 15 June 98 USER’S MANUAL

Figure 5-32 Internal Reset Request Flow

IDLE

IS CNT

= 17?

START THE COUNTER

WAIT FOR CNT = 17 AND

WAIT FOR PLL TO LOCK

THIS STATE DEPE NDS ON PL L

MODE AND RESET CONFIG

WORD

IS CNT = 17

OR PLL LOCKED ?

CONTINUE REQUESTING BUSES.

INTERNAL RESET.

IF RESET = 0

START THE COUNTER

INT_RST = 1

YES

LOO/LOL RST

IS RESET CLOCKS

AND PLL

YES

REQUEST THE INTERNAL BUSES.

WAIT FOR 32 CLOCKS OR EBI

IDLE INDICATION

IS CNT = 32

OR EBI IDLE?

YES

ASSERT RESETO UT

AND INTERNAL RESETS.

ANO

YES

IF RESET = 0

TO EXTERNAL RESET FLOW

INT_RS T IS EITHE R

LOO OR LOL OR JTAG OR

SWDOG TIMER OR CH E C KS T OP

RESET REQUEST

NOTE:

RELEASE RESETOUT AND

RELEASE BUS

AND GO TO IDLE

REQUESTS

YES

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-97

The SIU en ters in te rnal re set flo w whe n an inter nal reset r equest i s is sued due to one

of the following causes: loss of clock, loss of PLL lock, software watchdog time-out,

entry into checkst op sta te, or a ssertion of a JTAG re set requ est. If the sou rce o f rese t

is either loss of oscillator or loss of clock, the SI U resets the clocks and the PLL imme-

diately. For other reset sources, the SIU does not reset the clocks or the PLL.

When the internal reset request signal is asserted, the SIU atte mpts to complete the

current transaction on the external bus before placing the chip (except clocks and PLL)

in reset. The SIU requests the L-bus and I-bus and removes the qualified bus grant

from the EBI to make sure that no new transaction is started.

The SIU waits for 32 clock cycles (after internal reset request is asserted) or for the

EBI to indicate that the SIU is idle, whichever occurs first. Then the SIU asserts

RESETOUT and in ternal reset. RESETOUT and internal reset will be driven out to put

the chip into reset. Four clock cycles after the assertion of RESETOUT, all mode select

pins w ill be sampl ed except V DDSN, DS CK and M ODCLK p ins whic h are sampled at

the rising edge of RESETOUT.

RESETOUT is held for a minimum of 17 clock cycles. After the 17 clock cycles, the

state of data bus configuration bit 19 determines when RES ETOUT is released.

• If the PLL is o pera ting in 1 :1 mo de or the dat a bus config urat io n bit 1 9 is cle ared ,

RESETOUT is released when the phase-locked loop (PLL) is locked.

• If data bus configuration bit 19 is set and the PLL is not operating in 1:1 mode,

RESETOUT is released as soon as the 17 clock cycles have finished.

Internal reset is released when RESETOUT is released; however, the internal buses

are not released until 17 clocks after RESETOUT is negated.

If an external reset is asserted any time during this process, the external reset flow

begins.

5.8.2.3 Reset Behavior for Different Clock Modes

Table 5-47 summarizes the conditions under which internal reset is released for each

clock mode.

Table 5-47 Reset Behavior for Different Clock Modes

Clock Mode VDDSN MODCLK Internal DATA19 = 1 at Reset Internal DATA19 = 0 at Reset

Normal

operation 11

Release internal reset 17 clocks

after RESET is negated

Release in ternal reset when PLL

is locked and 17 clocks after

RESET is negate d OR when

time-out value in the time base

occurs first)

1:1 mode 1 0 Release internal reset when PLL is locked and 17 clocks after

RESET is ne gated

SPLL bypass mode 0 1 Release internal reset 17 clocks after RESET is negated

Special test mode 0 0 Release internal reset 17 clocks afte r RESET is negated

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-98 Rev. 15 June 98 USER’S MANUAL

5.8.3 Configuration During Reset

Many SIU pins can have more than one function. The logic state of certain mode-

select pins during reset determines which functions are assigned to pins with multiple

functio ns. These mod e-select pi ns determine ot her aspects of operating configuratio n

as well.

Basic operating configuration is determined by the DSDI and DSCK pins, as shown in

Table 5-48.

The state of the DSDI pin is latched internally five clock cycles after RESETOUT is

asserted. The stat e o f the DSCK pin is latche d e very clock cycle while RESETOUT is

asserted. The MCU is configured based on the values latched from these two pins.

The user is responsible for ensuring a valid level on these pins five clock cycles after

RESETOUT is asserted. If DSDI is asserted (causing data bus configuration mode to

be entered), the user must also drive DATA[0:5], at a mini mum.

For any reset source other than external reset, the external data pins are latched five

clock cycles after internal reset control logic asserts RESETOUT . For external resets,

the data pins are latched five clock cycles after RESET is neg ated. The def ault re set

configuration word is driven onto the internal buses until the external word is latched.

If no external reset configuration word is latched, the default word continues to be

driven on the internal bu ses.

This s cheme allow s users of th e inte rnal def ault mode to limi t their requir ed exter nal

configuration hardware to two pull-down resistors (DSDI and DSCK). It also allows

many options to be configured with a single three-state octal buffer.

5.8.3.1 Data Bus Configuration Mode

If data bus configuration mode is selected (DSDI asserted), then the MCU is config-

ured according to the valu es latched from the data bus pins.

NOTE

BG must be asserted in order for the reset configuration word latch

to access the data bus.

The external data bus is divided into four groups:

• DSDI, DATA[0:5]

• DATA[6:13]

• DATA[14:21]

Table 5-48 Pin Configuration During Reset

Pin During Reset Function Affected

DSCK asserted (1) Debug mode enabled

DSCK negated (0) Debug mode disabled

DSDI asserted (1) Data bus configuration mode

DSDI negated (0) Internal default mode

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-99

• DATA[22:31]

This g rouping a llows th e user to use th ree-stat e octa l buffers t o only drive v alid data

on the pins for those reset configuration options that the user would want to change.

The state of the last pin in each group (pins 5, 13, and 21) determines whether the next

set of configuration options use the internal default values or are configured from the

externa l data b us. The user i s requir ed to dri ve to a val id level al l the pin s in any of th e

groups that are to be changed. The functions selected by these pins are shown in

Table 5-49.

5.8.3.2 Inter nal Defa ult Mode

If DSDI is he ld low duri ng re set, in tern al def ault mod e is select ed . The i nter nal defa ult

mode allows MCUs with on-board non-volatile memory modules (such as flash

EEPROM) to provide a pin configuration word on the instruction or load/store data bus

during reset. For MCUs with out such a memory module, such a s the MPC509, the SIU

provides a mask-programmed default value.

5.8.3.3 Data Bus Reset Config uration Word

In either reset configuration mode (data bus configuration mode or internal default

mode), the configuration is accomplished within the MCU by driving a configuration

word on the internal data bus before the internal RESET signal is negated. At the

negation of internal RESET, those functions that are configured at reset latch their

configuration values from the assigned bits of the internal data bus. The format of the

data bu s reset confi guratio n word is the sa me rega rdless of w hich config uration m ode

is select ed, except that da ta bus bits 5, 13, and 21 have no mean ing in interna l default

mode. Table 5-49 describes the conf iguration options.

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-100 Rev. 15 June 98 USER’S MANUAL

Table 5-49 Data Bus Reset Configuratio n Word

Data

Bus

Bit

Configuration Function

Affected Effect of Mode Select = 1

During Reset Effect of Mode Select = 0

During Reset

Internal Default

Mode

3 V I/O1TTL I/O2

0Address Bus M ini mum Bus Mode

ADDR[0:11]/CS[0:11]

conf igu red as chip selec ts

Maximum Bus M ode

ADDR[0:11]/CS[0:11] configured

as address pins 11

1Vector Table Lo cation (IP

Bit) Vector Ta ble

0xFFF0 0000 Vector Table

0x0000 000 0 01

2Burst Type/Indication Type 2 (LAST Timing) Type 1 (BDIP Timing) 0 0

3Interface Type

for CSBOOT

ITYPE = 001

Asynchronous

(Time to Hi-Z = 2 Clk)

ITYPE = 1000

Synchronous Burst 11

4CSBOOT Port Size 32-Bit 16-Bit 1 0

5Reset Configuration

Source For DATA[6:13] Latch configuration from

external pins Latc h configu ration fr om internal

defaults 00

6:8 TA Delay For CSBOOT

TA Dela y En co ding

000

001

010

011

100

101

110

111

Number of Wait States

010 111

9:10 IMEMBASE[0:1]

IMEMBASE

I-Mem Block Placement

Start Addr: 0x0000 0000

End Addr: 0x000F FFFF

Start Addr: 0xFFF0 0000

End Addr: 0xFFFF FFFF

Note: M PC 509 doe s no t c onta in

I-Mem

01 10

11:12

LMEMBASE[0:1] LMEMBASE

L-Mem (SRAM) Block Place-

ment

Start address: 0x0000 0000

End address: 0x000F FFFF

Start address: 0xFFF0 0000

End address: 0xFFFF FFFF

11 11

13 Reset configuration

source for DATA[14:21] Latch configuration from

external pins Latc h configu ration fr om internal

defaults 00

14 CT[0:3], AT[0:1], TS CT[0:3], AT[0:1], TS PJ[1:7] 1 1

15 WR, BDIP WR, BDIP PK[0:1] 1 1

16 PLLL/DSDO, VF[0:2],

VFLS[0:1], WP[1:5] DSDO, Pipe Tracking,

Watchpoints PK[2:7], PL[2:7] 1 1

17 BURST, TEA, A ACK, TA,

BE[0:3] Handshake Pins PORTI[0:7] 1 1

18 CR, BI, BR, BB, BG,

ARETRY Bus Arbitration Pins PM[2:7] 1 1

19 Release reset when PLL

locked Refer to Table 5-47 Refer to Table 5-47 01

20 Reserved 0 0

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-101

5.8.4 Power-On Reset

Power-on reset occurs when the VDDKAP1 pin is high and VDD makes a transition

from zero to one. The SIU does not have a power-on reset circuit. This function must

be pr ovided externally.

NOTE

The ADDR[0:11]/CS[0:11] pins contain unknown values during the

first two clocks of power-on reset. The user must ensure that external

EEPROM and st andby mem ory i nterfa ce log ic do n ot all ow ina dvert-

ent writes during this time.

5.9 General-Purpose I/O

Many o f the pi ns associa ted with the SIU can be us ed for more than one fun ction. Th e

prima ry fun cti on of the se pins is to p rov ide an exter nal bu s in terfa ce. When no t us ed

for their primary function, many of these pins can be used as digital I/O pins.

SIU digital I/O pins are grouped into eight-bit ports. The following registers are asso-

ciated with each I/O port. (Output-only ports do not have a data direction register.)

• Pin assig nmen t re gi ste r — all ows the user to co nfi gur e a pi n fo r its pr i mar y func-

tion or digital I/O.

• Data direction register — configures individual pins as input or output pins.

• Data register — monitors or controls the state of its pins, depending on the state

21 Reset configuration

source For DATA[22:31] Latch configuration from

external pins Latc h configu ration fr om internal

defaults 00

22 Reserved 0 0

23 Reserved 0 0

24 LEN L-bus memory modules

are enabled. L-bus memory modules are dis-

abled and emulated externally 11

25 PRUMODE Forces acce sses to ports

A, B, I, J, K, and L to go

external

No effect 00

26 ADDR[12:15] ADDR[12:15] PB[4:7] 1 1

27 Reserved 0 0

28 Reserved 0 0

29 Reserved 0 0

30 Test Slave Mode Enable Test Slave Mode Disabled Test Slave Mode Enabled 1 1

31 Test Transparent

Mode Enable Te st Tran spa ren t

Mode Disabled Test Transparen t

Mode Enabled 11

NOTES:

1. 3 V only I/O structure. The part number is MPC509L (CFT33).

2. TTL compatible (5 V friendly input) I/O structure. The part number is MPC509L3 (CFT33).

Table 5-49 Data Bus Reset Configuration Word (Continued)

Data

Bus

Bit

Configuration Function

Affected Effect of Mode Select = 1

During Reset Effect of Mode Select = 0

During Reset

Internal Default

Mode

3 V I/O1TTL I/O2

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-102 Rev. 15 June 98 USER’S MANUAL

of the data direction register for that pin.

If a pin is not configured as an I/O port pin in the pin assignment register, the data

direction and data registers have no effect on the pin.

Ports A through L can be used with a port replacement unit (PRU). These ports provide

three-clock-cycle access. If PRU mode is enabled at reset, access to these registers

is disabled, an d an ext ernal bu s cycle is init iated . Othe r (no n-PRU) po rts p rovide two-

clock-cycle access.

In addition to the SIU ports described in this section, port Q in the peripherals controller

unit provides edge- or level-sensitive I/O. Refer to 6.5 Port Q for information on port Q.

Table 5-50 is an address map of the SIU port registers.

5.9.1 Port Timing

Ports A through L can be used with a port replacement unit (PRU). These ports provide

three-clock-cycle access. If PRU mode is enabled at reset, access to these registers

is disabled, an d an ext ernal bu s cycle is init iated . Othe r (no n-PRU) po rts p rovide two-

clock-cycle access. Input port pins are sampled synchronously.

After a pin assignment or data direction register is modified, the change may require

an additional clock cycle to take effect at the pin.

Note th at the timing of o utput port pin s does not match the timing of t he correspondi ng

bus control pins.

Table 5-50 SIU Port Registers Address Map

Access Address Register

S 0x8007 FC60 Port M Data Direction (DDRM)

S 0x8007 FC64 Port M Pin Assignment (PMPAR)

S/U 0x8007 FC68 Port M Data (PORTM)

—0x8007 FC6C –

0x8007 FC80 Reserved

S 0x8007 FC84 Port A, B Pin Assignment

(PAPAR, PBPAR)

S/U 0x8007 FC88 Port A, B Data (PORTA, PORTB)

—0x8007 FC8C –

0x8007 FC94 Reserved

S 0x8007 FC98 Port I, J, K, L Data Direction

(DDRI, DDRJ, DDRK, DDRL)

S 0x8007 FC9C Port I, J, K, L Pin Assignment

(PIPAR, PJPAR, PKPAR, PLPAR)

S/U 0x80 07 FCA0 Port I, J, K, L Data

(PORTI, PORTJ, PORTK, PORTL)

—0x8007 FCA4 –

0x8007 FCFF Reserved

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-103

5.9.2 Port M

U = Unaffected by reset

Writ es to PORTM ar e stored in intern al data la tches. If any b it of the por t is confi gured

as an output, the value latched for that bit is driven onto the pin. A read of PORTM

retur ns t he val ue a t th e p i n o nly if t he pi n is con f igur e d a s a discrete i np ut. Oth er wise ,

the value read will be the value stored in the internal data latch. PORTM can be read

or written at any time. This register is unaffected by reset.

The bit s in this re gister control the directio n of the p ort M p in drivers w hen the pins are

configured as I/O pins. Setting a bit in this register to one configures the corresponding

pin as an output; clearing the bit configures the pin as an input.

PORTM — Port M Data Register 0x8007 FC68

012345678910 11 12 13 14 15

000PM3 PM4 PM5 PM6 PM7 RESERVED

RESET:

0 0 0 U U U U U 0 0 0 0 0 0 0 0

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED

RESET:

0000000000000000

DDRM — Port M Data Direction Register 0x8007 FC60

012345678910 11 12 13 14 15

000DDM3 DDM4 DDM5 DDM6 DDM7 RESERVED

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED

RESET:

0000000000000000

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-104 Rev. 15 June 98 USER’S MANUAL

* Reset setting depends on the value of the configuration word at reset.

The bits in this register control the function of the associated pins. Setting a bit in this

configures the pin as an I/O pin (or as the DS signal, in the case of PMPA2).

5.9.3 Ports A and B

Ports A and B are 8-bit output ports. Associated with each port is a data register and

a pin a ssignment register; data direction re gisters are no t needed.

U = Unaffected by reset

PMPAR — Port M Pin Assignment Register 0x8007 FC64

012345678910 11 12 13 14 15

0 0 PMPA

2PMPA

3PMPA

4PMPA

5PMPA

6PMPA

7RESERVED

RESET:

0 0 * * * * * * 0 0 0 0 0 0 0 0

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED

RESET:

0000000000000000

Table 5-51 Port M Pin Assignments

PMPAR Bit Port M Signal Bus Control Signal

PMPA2 DS CR

PMPA3 PM3 BI

PMPA4 PM4 BR

PMPA5 PM5 BB

PMPA6 PM6 BG

PMPA7 PM7 ARETRY

PORTA, PORTB — Port A, B Data Registers 0x8007 FC88

012345678910 11 12 13 14 15

PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

RESET:

UUUUUUUUUUUUUUUU

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED

RESET:

0000000000000000

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-105

When a port A o r port B pin is configur ed as a gen eral-purp ose outpu t, the value in the

port A or port B data register is driven onto the pin. PORTA and PORTB are unaffected

by res et.

* Reset setting depends on the value of the configuration word at reset.

Each bit in this register controls the function of the asso ciated pin, provided the pin is

config ur ed fo r no n- chi p-s e lec t f un cti on i n t he cor r esp on ding chi p -se l ect op ti on s r eg is-

ter. Setting a bit in the PAPAR or PBPAR configures the corresponding pin as an

address bus pin; clearing the bit configures the pin as an I/O pin.

PAPAR, PBPAR — Port A, B Pin Assignment Register 0x8007 FC84

012345678910 11 12 13 14 15

PAPA

0PAPA

1PAPA

2PAPA

3PAPA

4PAPA

5PAPA

6PAPA

7PBPA

0PBPA

1PBPA

2PBPA

3PBPA

4PBPA

5PBPA

6PBPA

RESET:

111111111111****

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED

RESET:

0000000000000000

Table 5-52 Port A Pin Assignments

PMPAR Bit Port A Signal Bus Control Signal

PAPA0 PA0 ADDR0

PAPA1 PA1 ADDR1

PAPA2 PA2 ADDR2

PAPA3 PA3 ADDR3

PAPA4 PA4 ADDR4

PAPA5 PA5 ADDR5

PAPA6 PA6 ADDR6

PAPA7 PA7 ADDR7

Table 5-53 Port B Pin Assignments

PMPAR Bit Port B Signal Bus Control Signal

PBPA0 PB0 ADDR8

PBPA1 PB1 ADDR9

PBPA2 PB2 ADDR10

PBPA3 PB3 ADDR11

PBPA4 PB4 ADDR12

PBPA5 PB5 ADDR13

PBPA6 PB6 ADDR14

PBPA7 PB7 ADDR15

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-106 Rev. 15 June 98 USER’S MANUAL

5.9.4 Ports I, J, K, and L

U = Unaffected by reset

Writ es to po rt I, J, K , and L data r egister s are sto red in in tern al data l atche s. If any p in

in one of th ese po rt s is co nfig ur ed as an ou tpu t, th e va lu e l at che d fo r th e co rr e spon d-

ing data register bit is driven onto the pin. A read of one of these data registers returns

the value at the pin only if the pin is configured as a discrete input. Otherwise, the value

read is the value stored in the internal data latch. Port I, J, K, and L data registers can

be read at any time. These registers are unaffected by reset.

The bi ts in these register s cont rol the direction of the asso ciated pin drivers when the

pins are configured as I/O pins. Setting a bit in these registers configures the corre-

sponding pin as an output; clearing the bit configures the pin as an input.

PORTI, PORTJ, PORTK, PORTL — Port I, J, K, L Data Registers 0x8007 FCA0

012345678910 11 12 13 14 15

PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7

RESET:

UUUUUUUU0UUUUUUU

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 0 0 PL2 PL3 PL4 PL5 PL6 PL7

RESET:

UUUUUUUU00UUUUUU

DDRI, DDRJ, DDRK, DDRL — Port I, J, K, L Data Direction Registers 0x8007 FC98

012345678910 11 12 13 14 15

DDI0 DDI1 DDI2 DDI3 DDI4 DDI5 DDI6 DDI7 0DDJ1 DDJ2 DDJ3 DDJ4 DDJ5 DDJ6 DDJ7

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

DDK0 DDK1 DDK2 DDK3 DDK4 DDK5 DDK6 DDK7 0 0 DDL2 DDL3 DDL4 DDL5 DDL6 DDL7

RESET:

0000000000000000

MPC509 SYSTEM INTERFACE UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 5-107

* Reset setting depends on the value of the configuration word at reset.

The bits in these registers control the function of the associated pins. Setting a bit con-

figures the corresponding pin as a bus control signal; clearing the bit configures the

pin as an I/ O pin.

PIPAR, PJPAR,

PKPAR, PLPAR — Port I, J, K, L Pin Assignment Registers 0x8007 FC9C

012345678910 11 12 13 14 15

PIPA0 PIPA1 PIPA2 PIPA3 PIPA4 PIPA5 PIPA6 PIPA7 0 PJPA1 PJPA2 PJPA3 PJPA4 PJPA5 PJPA6 PJPA7

RESET:

********0*******

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

PKPA

0PKPA

1PKPA

2PKPA

3PKPA

4PKPA

5PKPA

6PKPA

70 0 PLPA2 PLPA3 PLPA4 PLPA5 PLPA6 PLPA7

RESET:

********00******

Table 5-54 Port I Pin Assignments

PIPAR Bit Port I Signal Bus Control Signal

PIPA0 PI0 BURST

PIPA1 PI1 TEA

PIPA2 PI2 AACK

PIPA3 PI3 TA

PIPA4 PI4 BE0

PIPA5 PI5 BE1

PIPA6 PI6 BE2

PIPA7 PI7 BE3

Table 5-55 Port J Pin Assignments

PJPAR Bit Port J Signal Bus Control Signal

PJPA1 PJ1 AT0

PJPA2 PJ2 AT1

PJPA3 PJ3 TS

PJPA4 PJ4 CT0

PJPA5 PJ5 CT1

PJPA6 PJ6 CT2

PJPA7 PJ7 CT3

MOTOROLA SYSTEM INTERFACE UNI T MPC509

5-108 Rev. 15 June 98 USER’S MANUAL

5.9. 5 Port Replac eme n t Uni t (P RU) Mode

The entire external bus interface must be supported in order to build an emulator for

an MCU. The SIU contains support for external port replacement logic which can be

used to faithfully replicate on-chip ports externally. This PRU mode allows system

development of a single-chip application in expanded mode. Access (including access

time) to the port replacement logic can be made transparent to the application

software.

In PRU m ode, all da ta, data d irection, and pin assi gnment registers fo r ports A, B, I , J,

K, and L are mapp ed externally . The SIU does not respond to these accesses, allow-

ing external logic, such as a PRU, to respond.

PRU mod e is invoked by pulling D ATA25 high d uring re set. Other pins should be con-

figured as bus control pins.

Table 5-56 Port K Pin Assignments

PKPAR Bit Port K Signal Bus Control Signal

PKPA0 PK0 BDIP

PKPA1 PK1 WR

PKPA2 PK2 PLLL/DSDO

PKPA3 PK3 VF0

PKPA4 PK4 VF1

PKPA5 PK5 VF2

PKPA6 PK6 VFLS0

PKPA7 PK7 VFLS1

Table 5-57 Port L Pin Assignments

PLPAR Bit Port L Signal Bus Control Signal

PLPA2 PL2 WP0

PLPA3 PL3 WP1

PLPA4 PL4 WP2

PLPA5 PL5 WP3

PLPA6 PL6 WP4

PLPA7 PL7 WP5

MPC509 PERIPHERAL CONTROL UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 6-1

SECTION 6

PERIPHERAL CONTROL UNIT

The peripheral control unit (PCU) consists of the follo wing submod ules:

• Software watchdog — provides system protection.

• Interr upt controller — controls the interr upts that external peripheral s and internal

modules send to the CPU.

• Port Q — provides for digital I/O on pins that are not being used as interrupt in-

puts.

• Test submodule — allows factory testing of the MCU.

• L-bu s/IMB2 interf ace ( LIMB) — provi des a n inte rface betw een t he l oad/sto re b us

and the second generation intermodule bus (IMB2). The IMB2 connects on-chip

peri pherals to the processor v ia the LI MB.

6.1 PCU Block Diagram

Figure 6-1 shows a block diagram of the PCU.

Figure 6-1 Peripherals Control Unit Block Diagram

ADDRESS

DATA

INTERRUPT

TEST

L BUS

IMB2

IRQ[0:7]

SOFTWARE

PORTQ

L-BUS

IMB2

ADDR[0:31]

DATA[0:31]

ADDR[0:31]

INTERFACE

DECODE

MUX

WATCHDOG

CONTROLLER

MOTOROLA PERIPHERAL CONTROL UNIT MPC509

6-2 Rev. 15 June 98 USER’S MANUAL

6.2 PCU Address Map

Table 6-1 shows the address map for the PCU. An entry of “S” in the Access column

indicates that the register is accessible in supervisor mode only. “S/U” indicates that

the re gister can b e progra mmed to th e desired privile ge level . “Test” indicates that the

CAUTION

Avoid wr i ti ng to te st location 0 x8007 EF98 . S etti n g t he hi gh - orde r bi t

in this reserved register causes the MCU to enter test mode.

6.3 Module Configuration

The peripheral control unit module configuration register (PCUMCR) contains fields for

stopping th e system clock to IMB2 modules, assigning certain PCU registers to either

supervisor or unrestricted memory space, and assigning the number of interrupt

request levels available to IMB2 peripherals.

Table 6-1 PCU Address Map

Access Address Register

S 0x8007 EF80 Peripheral Control Unit Module Configuration Register (PCUMCR)

—0x8007 EF84 –

0x8007 EF8C Reserved

Test 0x8007 EF90 Test Control Register (TSTMSRA) Test Control Register (TSTMSRB)

Test 0x8007 EF94 Test Control Register (TSTCNTRAB) Test Control Register (TSTREPS)

Test 0x8007 EF98 Test Control Register (TSTCREG1) Test Control Register (TSTCREG2)

Test 0x8007 EF9C Test Control Register (TSTDREG) Reserved

S 0x8007 EFA0 Pending Interrupt Request Register (IRQPEND)

S 0x8007 EFA4 Enabled Active Interrupt Request Register (IRQAND)

S 0x8007 EFA8 Interrupt Enable Register (IRQENABLE)

S 0x8007 EFAC PIT/Port Q Interrupt Level Register (PITQIL)

—0x8007 EFB0 –

0x8007 EFBC Reserved

S 0x8007 EFC0 Software Service Register (SWSR) Reserved

S 0x8007 EFC4 Sof tw are Watchd og Control Fiel d/T im ing Count (SWC R/S WTC)

S/U 0x8007 EFC8 Software Watchdog Register

— 0x8007 EFCC Reserved

S/U 0x8007 EFD0 Port Q Edge Detect/Data (PQEDGDAT) Reserved

S 0x8007 EFD4 Port Q Pin Assignment Register (PQPAR)

—0x8007 EFD8 –

0x8007 EFFC Reserved

MPC509 PERIPHERAL CONTROL UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 6-3

6.4 Software Watchdog

The software watchdog monitors the system so ftware interfaces and requires the soft-

ware to ta ke p er i od ic a c ti on in or de r to e nsure tha t the pro gr am is exe c uting prop er ly .

To prot ect ag ainst softwa re e rror, th e foll owing servic e mu st be e xecuted on a reg ular

basis:

1. Write 0x556C to the SWSR

2. Write 0xAA39 to the SWSR

This seq ue nce cl ea rs the watchd og timer , an d the tim i ng pr oc ess b eg i ns a ga i n. If thi s

periodic servicing does not occur, the software watchdog issues a reset.

Any number of instructions may occur between the two writes to the SWSR. If any

value other than 0x556C or 0xAA39 is written to the SWSR, however, the entire

sequence must start over.

PCUMCR — Peripheral Control Unit Module Configuration Register 0x8007 EF80

012345678910 11 12 13 14 15

STOP IRQMUX RESERVED SUPV RESERVED

RESET:

0110000010000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED

RESET:

0000000000000000

Table 6-2 PCUMCR Bit Settings

Bit(s) Name Description

0STOP

Stop system clock to peripherals controller

0 = Enable system clock to IMB2 modules

1 = Disable system clo ck to I M B2 mo dules

1:2 IRQMUX

Interrupt request multiplexer control

00 = Disable multiplexing scheme (eight possible interrupt sources)

01 = 2-to-1 multiplexing (16 possible interrupt sources)

10 = 3-to-1 multiplexing (24 possible interrupt sources)

11 = 4-to-1 multiplexing (32 possible interrupt sources)

Refer to 6.5.2.3 Interrupt Request Multiplexing for details.

3:7 — Reserved

8:9 SUPV

Supervisor access for PCU registers

00 = Supervisor/unrestricted registers respond to accesses in supervisor or user data space.

01 = Supervisor/unrestricted registers respond to accesses in supervisor space only.

10 = Supervisor/unrestricted registers respond to read accesses in either data space, but write

accesses can only be performed in supervisor data space.

11 = Undefined

10:31 — Reserved

MOTOROLA PERIPHERAL CONTROL UNIT MPC509

6-4 Rev. 15 June 98 USER’S MANUAL

6.4.1 Software Watchdog Service Register

A write of 0x556C followed by a write of 0xAA39 to the software watchdog service reg-

ister (SWSR) causes the software watchdog register to be reloaded with the value in

the software watchdog timing count (SWTC) field of the SWCR.

This reg ister can be wri tten at any time within the tim e-out period . A write of any val ue

other t han those sh own abo ve resets the se rvicing sequence, re quiri ng both val ues to

be wri tten to the SWSR befor e the value i n the SWTC f ield is re loaded int o the SWSR.

Reads of the SWSR return zero.

6.4.2 Software Watchdog Control Register/Timing Count

The software watchdog control register/timing count consists of the software watchdog

enable (SWE) and software watchdog lock (SWLK) bits and the timing count field for

the software watchdog. The software watchdog timing count (SWTC) field contains the

24-bit value that is loaded into the SWSR upon completion of the software watchdog

service sequence.

When th e SWLK bit is cleared, this register can be written. Once the lock bit i s set, fur-

ther writes to this register have no effect. (In debug mode, however, the lock bit can

be cleared by software.) The reg ister can be read at an y time.

SWSR — Software Watchdog Service Register 0x8007 EFC0

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SWSR RESERVED

RESET:

00000000000000000000000000000000

SWCR/SWTC — Software Watchdog Control Field/Timing Count 0x8007 EFC4

012345678910 11 12 13 14 15

000000SWE SWLK SWTC

RESET:

0000001011111111

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SWTC

RESET:

1111111111111111

MPC509 PERIPHERAL CONTROL UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 6-5

6.4.3 Software Watchdog Register

The software watchdog register (SWR) is a read-only register that shows the current

value of the software watchdog down counter. Writes to this register have no effect.

6.5 Interrupt Controller

Interrupts provide a mechanism for asynchronous, real-time communication between

I/O devices and the CPU. The MPC509 interrupt controller joins the simple interrupt

structure of the CPU with the complex structure of interrupt sources in the system. The

CPU has a single maskable external interrupt. A complete MPC509-based system can

have multiple interrupting modules, each with multiple interrupt sou rces.

The interrupt controller consolidates all the interrupt sources into a single interrupt sig-

nal to the processor. Interrupt sources include the periodic interrupt timer, external

interrupt pins, and any IMB2 peripherals.

External interrupt input pins are grouped into a general-purpose port (port Q). When

not us ed as interru pt inpu ts, a ny of these pins can b e used for di gita l input or outp ut.

Port Q operation is described in 6.6 Port Q.

6.5.1 Interrupt Controller Operation

The fo llowing control and s tatus registe rs associate d with the in terrupt controller indi-

cate which of 32 possible interrupt levels are pending and control which interrupt

sources are passed on to the CPU:

• The pending interrupt request register (IRQPEND) contains a status bit for each

of the 32 interrupt levels.

• The in terrupt enab le register (IRQENABLE ) contains an e nable bit fo r each of the

Table 6-3 SWCR/SWTC Bit Settings

Bit(s) Name Description

0:5 — Reserved

6SWE

Software watchdog enable

0 = Disable watchdog counter

1 = Enable watchdog counter

7SWLK

Software watchdog lock

0 = Enable changes to SWLK, SWE, SWTC

1 = Ignore writes to SWLK, SWE, SWTC

8:31 SWTC Software watchdog timing count. This 24-bit register contains the count for the software watch-

dog timer, which counts at system clock frequency. If this register is loaded with zero, the

maximum time-out is programmed.

SWR — Software Watchdog Register 0x8007 EFC8

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED SWR

RESET:

XXXXXXXX111111111111111111111111

MOTOROLA PERIPHERAL CONTROL UNIT MPC509

6-6 Rev. 15 June 98 USER’S MANUAL

32 interrupt levels.

• The interrupt request levels register (PITQIL) determines the interrupt request

level assigned to each interrupt source.

If a bit in the IRQPEND register is asserted (indicating that an interrupt request at the

associated level is pending) and the corresponding bit in the IRQENABLE register is

asserted, then the interru pt request li ne to the CPU will be asserted. These registers

are described in greater detail in 6.5.3 Interrupt Controller Registers.

Figure 6-2 provides an overview of MPC509 interrupt management.

Figure 6-2 Interrupt Structure Block Diagram

The interrupt controller does not enforce a priority scheme. All interrupt priority is

determine d by the so ftware . In additio n, the interrup t contro ller doe s not a utomatically

update the interrupt mask upon entering or leaving interrupt processing. Any updates

to the interrupt mask are the responsibility of software. In this way, the system is not

limited to a particular interrupt priority updating scheme.

In addition to the interrupt controller on the MCU, external peripheral chips in an

MPC509-based system may contain their own interrupt controllers. Each interrupt

input from an external peripheral chip to the MCU can be routed through the PCU inter-

rupt controller or can be routed directly to the CPU IRQ input. This allows the system

interrupts to be structured in a cascade, where an interrupt controller on an external

chip is read only if a certain interrupt on the MCU is serviced, or in parallel, where all

PROGRAMMABLE

INTERRUPT TIMER

PORT Q

PICSR

PIT

PITQIL[27:31]

PQPAR

PQEDGDAT

PITQIL[0:26]

INTERRUPT

CONTROLLER

IRQPEND

IRQENABLE

IRQAND

RCPU

EIE

EID

NRI

MPC509

IRQ[0:6]

MPC509 PERIPHERAL CONTROL UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 6-7

interrupt controllers in the system are read and combined before it is determined which

interrupt in the system needs servicing.

6.5.2 Interrupt Sources

Sources of interrupt requests to the interrupt controller include the periodic interrupt

timer (PIT), two L-bus interrupt request sources, and the IRQ[0:6] interrupt request

pins. The re quest levels of PIT interrupts, IMB2 interru pts, and external IRQ[0:2] inter-

rupts are assigned by programming the PITQIL register. The request levels of IRQ[3:6]

external interrupts are assigned fixed values, as explained below.

CAUTION

Be sure the EE (external interrupt enable) bit in the MSR is cleared

before chang ing the masks o f any on- or off-chip inte rrupt sources or

before negating any interrupt sources. (On-chip interrupt masks are

the IRQENABLE register and the PIE bit in the PICSR.)

6.5.2.1 External Interrupt Requests

The levels of the IRQ[0:2] interrupt request pins are assigned by programming the PIT-

QIL. The remainin g inter rupt requ est pi ns have fi xed valu es. IRQ 3 always generates

a level 6 interrupt request; IRQ4 generates a level 8 interrupt request; IRQ5 generates

a level 10 interrupt request; and IRQ6 always generates a level 12 interrupt request.

6.5.2.2 Periodic Interrupt Timer Interrupts

The periodic interrupt timer (PIT) is a 16-bit counter that generates an interrupt when-

ever it counts down to zero, provided PIT interrupts are enabled. The PITIRQL (PIT

interrupt request level) field in the PITQIL register assigns the interrupt request level

for PIT interrupts. Refer to 5.7.3 Periodic Interrupt Timer (PIT) for details of PIT

operation.

6.5.2.3 Interrupt Request Multiplexing

The IMB2 has ten lines for interrupt support: eight interrupt request lines (IRQ[0:7])

from the interrupting modules and two multiplexer control inputs (ILBS[0:1]). This

scheme enables the peripheral control unit to transfer up to 32 levels of interrupt

requests to the interrupt controller.

When the four-to-one multiplexing scheme is used, the IMB2 IRQ lines update eight of

the 32 bits of the IRQPEND register during each clock cycle. A maximum latency of

four clock cycles and an average latency of two clock cycles result before the interrup t

request can reach the interrupt cont roller.

Figure 6-3 illustrates the timing for the four-to-one multiplexing scheme.

MOTOROLA PERIPHERAL CONTROL UNIT MPC509

6-8 Rev. 15 June 98 USER’S MANUAL

Figure 6-3 Time-Multiplexing Protocol For IRQ Pins

The IRQMUX field in the PCU module configuration register (PCUMCR) selects the

type of multiple xing the interru pt controller pe rforms. Refer to Table 6-4.

Time multiplexing is disabled during reset, but the reset default value enables time

multiplexing as soon as reset is released.

6.5.3 Interrupt Controller Registers

Contro l and status registers associated with the interrupt controller in dicate whi ch of

32 possible interrupt levels are pending and control which interrupt sources are

passed on to the CPU. Table 6-5 lists these registers.

Table 6-4 IMB2 Interrupt Multiplexing

IRQMUX[0:1] Available

IRQ Levels Type of

Multiplexing Maximum Latency

00 IRQ[0:7] None One clock cycle

01 IRQ[0:15] Two to one Two clock cycles

10 IRQ[0:23] Three to one Three clock cycles

11 IRQ[0:31] Four to one Four clock cycles

Table 6-5 Inte rrupt Controll er Re gisters

Pen ding Interrupt

Request Register (IRQPEND)

Contains a status bit for each of the 32 interrupt levels. Each bit of

IRQPEND is a read-only status bit that reflects the current state of the

corresponding interrupt signal.

Interrupt Enable

Enabled Active Interrupt

Requests Register (IRQAND)

Logica l AND of the IR QPEND and IR QENABLE regi sters. Th is regis ter

reflects which levels are actually causing the IRQ input to t he CPU to b e

asserted.

Interrupt Request

Levels Register (PITQIL) Contains four 5-bit fields that determine the interrupt request levels of

the PIT and the IRQ[0:2] pins.

IMB2 CLOCK

IMB2 IRQ[0:7] IRQ

[0:7] IRQ

[8:15] IRQ

[16:23] IRQ

[24:31] IRQ

[0:7]

MPC509 PERIPHERAL CONTROL UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 6-9

6.5.3.1 Pending Interrupt Request Register

The pending interrupt request register (IRQPEND) is a read-only status register that

reflects the state of the 32 interrupt levels.

6.5.3.2 Enab led Active Interr upt Requests Register

The en abled active inter rupt re quests regi ster ( IRQAND) is a rea d-only st atus r egister

that is defined by the following equation:

IRQAND = IRQPEND & IRQENABLE

where & is a bitwise operat ion.

6.5.3.3 Inter rupt Enable Register

The interrupt enable register (IRQENABLE) is a read/write register. The bits in this reg-

ister are affected only by writes from the CPU (or other bus master) and by reset.

CAUTION

Be sure the EE (external interrupt enable) bit in the MSR is cleared

before changing any masks in this register.

IRQPEND — Pending Interrupt Request Register 0x8007 EFA0

012345678910 11 12 13 14 15

L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31

RESET:

0000000000000000

IRQAND — Enabled Active Interrupt Requests Register 0x8007 EFA4

012345678910 11 12 13 14 15

L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31

RESET:

0000000000000000

MOTOROLA PERIPHERAL CONTROL UNIT MPC509

6-10 Rev. 15 June 98 USER’S MANUAL

6.5.3.4 PIT/Port Q Interrupt Levels Register

The PIT/ po rt Q inte rrup t level s registe r (PI TQIL) co ntains fo ur 5-bi t fiel ds for p rogra m-

ming the interrupt request level of the periodic interrupt timer (PIT) and the IRQ[0:2]

interrupt request pins. Refer to 6.5.2 Interrupt Sources for more information.

6.6 Po rt Q

When not used as interrupt inputs, the IRQ[0:6]/PQ[0:6] pins can be used for general-

purpose I/O. The following registers control port Q operation:

• Port Q Pin Assignment Register (PQPAR) — allows the user to configure each

pin as a digital input, digital output, edge- or level-sensitive interrupt request to the

IRQENABLE — Interrupt Ena ble Registe r 0x8007 EFA8

012345678910 11 12 13 14 15

L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31

RESET:

0000000000000000

PITQIL — PIT/Port Q Interrupt Levels Register 0x8007 EFA C

012345678910 11 12 13 14 15

0IRQ0L IRQ1L IRQ2L

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED PITIRQL

RESET:

0000000000000000

Table 6-6 PITQIL Bit Settings

Bit(s) Name Description

0—Reserved

1:5 IRQ0L Interrupt request level for the IRQ0 pin

6:10 IRQ1L Interrupt request level for the IRQ1 pin

11:15 IRQ2L Interrupt request level for the IRQ2 pin

16:26 — Reserved

27:31 PITIRQL Interrupt request level for PIT interrupts

MPC509 PERIPHERAL CONTROL UNIT MOTOROLA

USER’S MANUAL Rev. 15 June 98 6-11

CPU, or edge- or level-sensitive inte rrupt reque s t to the interrupt contr olle r.

• Port Q Edge Detect/Data Register (PQEDGDAT) — contains the following fields:

— The port Q data field (PQ[0:6]) monitors or controls the state of port Q pins,

depending on the encoding for each pin in the PQPAR.

— The por t Q edge-d etect statu s field (PQ E[0:6]) m onitors whe n the pr oper tran-

sition occurs on a port Q or interrupt request pin.

6.6.1 Port Q Edge Detect/Data Register

The port Q edge detect/d ata register ( PQEDGDAT) con sists of the por t Q edge-dete ct

status field (PQE[0:6]) and the port Q data field (PQ[0:6]).

Port Q edge status (PQE) bits indicate when the proper transition has occurred on a

port Q pin. Each pin can be configured as an interrupt input or as digital I/O. If the pin

is configured in the PQPAR as an edge-sensitive interrupt request pin, then the PQE

bit act s as a st atus b it that indicat es whet her th e corres pond ing i nterru pt requ est li ne

is asserted. The bit als o acts as a status bit if the pins are configur ed as general-pur-

pose inputs or outputs. Wh en the pin is configure d in edge-de tect mode, the stat us bit

is cleared by reading the bit as a one and then writing it to zero. In level-sensitive

mode, the bit remains cleared.

A write to the por t Q da ta reg ister i s stor ed in the in terna l dat a l atch , an d i f any P Q bi t

is configured as an output, the value latched for that bit is driven onto the pin. A read

of this port returns the value at the pin only if the pin is configured as a discrete input.

Otherwise, the va lue read is the valu e stored in the internal data latch. The port Q data

U = Unaffected by reset

6.6.2 Port Q Pin Assignment Register

The port Q pin assignment register (PQPAR) contains the port Q pin assignment fields

(PQPA[0:6]) and the port Q edge fields (PQEDGE[0:6]).

PQEDGDAT — Port Q Edge Detect/Data Register 0x8007 EFD0

012345678910 11 12 13 14 15

PQE0 PQE1 PQE2 PQE3 PQE4 PQE5 PQE6 0PQ0 PQ1 PQ2 PQ3 PQ4 PQ5 PQ6 0

RESET:

U U 0 0 0 0 0 0 U U 0 0 0 0 0 0

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED

RESET:

0000000000000000

MOTOROLA PERIPHERAL CONTROL UNIT MPC509

6-12 Rev. 15 June 98 USER’S MANUAL

6.6.2.1 Port Q Pin Assignment Fields

The por t Q pi n assignment fiel ds ( PQ PA[0 :6 ] ) se lect the basic fu ncti o n o f ea ch port Q

pin, as shown in Table 6-7.

6.6.2.2 Port Q Edge Fields

The port Q edge (PQEDGE[0:6]) fields select whether the port/interrupt pin is edge

sensitiv e or leve l sensitiv e. When th e selecte d transition occurs on a port Q pin, a cor-

responding status bit is set in the PQEDGDAT register.

Table 6-8 explains the encodings for PQEDGE fields.

PQPAR — Port Q Pin Assignment Register 0x8007 EFD4

012345678910 11 12 13 14 15

PQPA0 PQEDGE0 PQPA1 PQEDGE1 PQPA2 PQEDGE2 PQPA3 PQEDGE3

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

PQPA4 PQEDGE4 PQPA5 PQEDGE5 PQPA6 PQEDGE6 PQPA7 PQEDGE7

RESET:

0000000000000000

Table 6-7 Port Q Pin Assignments

PQPA Val ue Pin Function PORTQ (Port Q Data Field) Interrupt Request Source

0b00 General-Purpose Input A read returns the state of the pin.

A write has no effect. None

0b01 General-Purpose Output A read returns the value in the

latch. A write drives the value in the

latch onto the pin. None

0b10 IRQ to CPU A read returns the state of the pin.

A write has no effect.

From pin if PQEDG field is set to

“Level”, othe rw ise fr om port Q

edge detect logic

0b11 IRQ to Interrupt Controller A re ad return s the state of th e pin.

A write has no effect.

From pin if PQEDG field is set to

“Level”, othe rw ise fr om port Q

edge detect logic

Table 6-8 Port Q Edge Select Field Encoding

PQEDGE

Value Edge Select PORTQE (Port Q

Edge Detect Field)

00 Level sensitive Returns zero when read

01 Falling-edge sensitive Set on rising edge

10 Rising-edge sensitiv e Set on falling edge

11 Either-edge sensitive Set on either edge

MPC509 STATIC RAM MODULE MOTOROLA

USER’S MANUAL Rev. 15 June 98 7-1

SECTION 7

STATIC RAM MODULE

The static RAM (SRAM) module consists of a 4-Kbyte block of static RAM. The pri-

mary function of this module is to serve as fast (one-cycle access), general-purpose

RAM for the MCU. The SRAM can be read or written as either bytes, half-words or

words.

The bus inter face and contr ol logic for the SR AM module are powe red by VDD. A sep-

arate pin, VDDKAP2, s upplies power to the memory arrays. If main power is shut off,

VDDKAP2 can b e ma inta ined i n or der to reta in t he data in the SR AM ar ray. When the

main power is off, access to the SRAM array is blocked.

7.1 Fe at ures

• Fast, One-Cycle Access

• Low-Pow er Mode

— Two-Cycle Access

— Pipelined for Back-to-Back Accesses

• Programmable Attributes (Supervisor Only, Data Only, Read Only)

7.2 Placement of SRAM in Memory Map

The SRAM module consists of two separately addressable sections. The first is the

array itself. The second section is a set of registers used for configuration and testing

of the SRAM array.

The SRAM array is assign ed to one o f four l ocation s in the MCU add ress map by pro-

gramming the LMEMBASE field in the SIU internal memory mapping register

(MEMMAP).

Note that the user must reserve the entire 32-Kbyte block containing the selected 4-

Kbyte block of SRAM. Table 7-1 indicates the location of the SRAM array and the

associated reserved locations for each value of LMEMBASE.

Refer to 5.2 SIU Module Configuration for a diagram of the ME MMAP register.

Table 7-1 MPC509 SRAM Module Addresses

LMEMBASE SRAM Location Re served Location

00 0x0000 0000 – 0x0000 6FFF 0x0000 7FFF – 0x0000 7FFF

01 0x000F 8000 – 0x000F EFFF 0x000F F000 – 0x000F FFFF

10 0xFFF0 0000 – 0xFFF0 6FFF 0xFFF0 7FFC – 0xFFF0 7FFF

11 0xFFFF 8000 – 0xFFFF EFFF 0xFFFF F000 – 0xFFFF FFFF

MOTOROLA STATIC RAM MODULE MPC509

7-2 Rev. 15 June 98 USER’S MANUAL

Figure 7-1, a memory map of the MPC509, shows the po ssible locations of the SRAM

array.

Figure 7-1 Placement of Internal SRAM in Memory Map

7.3 SRAM Registers

The control block for the SRAM module contains one control register for configuring

the array and one control register for use in testing.

0x0000 0000

0x000F EFFF

0xFFF0 0000

0xFFFF EFFF

0x8007 E000

0x8007 EFFC

EXTERNAL

POSS IBLE SRAM

ONE OF FOUR POSSIBLE LOCATIONS

PERIPHERAL

EXTERNAL

CONTROL UNIT

(PCU)

CONTROL REGISTERS

0x8000 0000

EXTERNAL/RESERVED

0x8007 FFFC

0x8007 F000

VECTOR TABLE LOCATION

(IP BIT = 0)

VECTOR TABLE LOCATION

(IP BIT = 1)

LOCATION

(28 KBYTES)

POSS IBLE SRAM

LOCATION

(28 KBYTES)

POSS IBLE SRAM

LOCATION

(28 KBYTES)

POSS IBLE SRAM

LOCATION

(28 KBYTES)

0xFFFF 8000

0xFFF0 6FFF

0x0000 6FFF

0x000F 8000

SELECTED FOR SRAM

MPC509 STATIC RAM MODULE MOTOROLA

USER’S MANUAL Rev. 15 June 98 7-3

Each SRAM mo dule configuration regis ter contains bits for set ting access rights to th e

array. Table 7-2 provides definitions for the bits.

SRAMTST — SRAM Test Register 0x8007 F004

The SRAM test register is used for factory testing only.

SRAMMCR — SRAM Module Configuration Register 0x8007 F000

012345678910 11 12 13 14 15

LCK DIS 2CY RESERVED

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED R0 D0 S0 RESERVED

RESET:

0000000000000000

Table 7-2 SRAMMCR Bit Settings

Bit(s) Name Description

0LCK

Loc k bit

0 = Writes to the SRAMMCR are accepted.

1 = Writes to the SRAMMCR are ignored.

1DIS

Module disable

0 = SRAM module is enabled.

1 = SR AM m odu le is d is abl ed . M od ule c an be s ubs eq uen tly re-enabled by s oftware se t-

ting this bit or by reset. Attempts to read SRAM array when it is disabled result in

internal TEA assertion.

22CY

Two-cycle mode

0 = SRAM module is in singl e-c yc le mo de (normal operati on).

1 = SRAM m odule is in two-cycle mode. In this mode, the first c ycle is us ed for dec oding

the address, and the second cycle is used for accepting or providing data. This

mode provides some power savings while keeping the memory active.

3:19 — Reserved

20 R0

Read onl y

0 = 4-Kbyte block is readable and writable.

1 = 4-Kbyte block is read only. Attempts to write to this space result in internal TEA as-

sertion.

21 D0

Data only

0 = 4-Kbyte block can contain data or instructions.

1 = 4-Kbyt e block contain s data only. Attemp ts to load instruc tions from this spac e result

in internal TEA assertion.

22 S0

Supervisor only

0 = 4-Kbyte block is placed in unrestricted space.

1 = 4-Kbyte bloc k is pla ced in superv isor sp ace. Attem pts to ac cess this space from the

user privilege level result in internal TEA asse rtion.

23:31 — Reserved

MOTOROLA STATIC RAM MODULE MPC509

7-4 Rev. 15 June 98 USER’S MANUAL

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-1

SECTION 8

DEVELOPMENT SUPPORT

Development tools are used by a microcomputer system developer to debug the hard-

ware and software of a target system. These tools are used to give the developer

some control over the execution of the target program. In-circuit emulators and bus

state anal yze rs a re the m ost freq ue ntl y used debug gin g too l s. In or de r fo r th ese tool s

to function properly, they must have full visibility of the microprocessor’s buses.

Visibility extends beyond the address and data portions of the buses and includes

attribut e and handshake signals. In some cases it may also in clude bus arbitrat ion sig-

nals and signals wh ich cause processo r exceptions such as interrupt s and resets. Th e

visibility requirements of emulators and bus analyzers are in opposition to the trend of

modern microcomputers and microprocessors where the CPU bus may be hidden

behind a memory management unit or cache or where bus cycles to internal resources

are n ot visible externally.

The development tool visibility requirements may be reduced if some of the develop-

ment support functions are included in the silicon. For example, if the bus comparator

part of a bus analyzer or breakpoint generator is included on the chip, it is not neces-

sary for the entire bus to be visible at all times. In many cases the visibility

requirements may be reduced to instruction fetch cycles for tracking program execu-

tion. If some additional status information is also available to assist in execution

tracking and the development tool has access to the source code, then the only need

for bus visibility is oft en th e de stina tion a dd ress o f indirect ch an ge-o f-flow instructio ns

(return from subro utine, return from interr upt, and inde xed br anches and jumps).

Since full bus visibility reduces available bus bandwidth and processor performance,

certain development support functions have been included in the MCU. These func-

tions include the following:

• Controls to limit which inte rnal bus cycles are reflecte d on the externa l bus (show

cycles)

• CPU status signals to allow instruction execution tracking with minimal visibility of

the instructions being fetched

• Watchp oi nt com p ar ato r s th at can gene ra te br ea kpo in ts o r sign al a n e x tern al b us

analyzer

• A serial development port for general emulation control

8.1 Program Flow Tracking

The exact program flow is visible on the external bus only when the processor is pro-

grammed to show all fetch cycles on the external bus. This mode is selected by

programming the IS CTL (instruction fetch show cycle control) field in the I-bus support

control register (ICTRL), as shown in Table 8-2. In this mode, the processor is fetch

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-2 Rev. 15 June 98 USER’S MANUAL

serialized, and all internal fetch cycles appear on the external bus. Processor perfor-

mance is therefore much lower than when working in regular mode.

The me chanism d escr i be d be lo w a llo w s tracking of t he pro gram in str uctions flow w it h

almost n o per forma nce de grad ation. The inform ation provi ded exter nally may b e cap-

tured and compressed and then parsed by a post-processing program using the

microarchitecture defined below.

The RCPU implements a prefetch queue combined with parallel, out of order, pipe-

lined execution. Instructions progress inside the processor from fetch to retire. An

instruction retire s from the machine only after it, and all precedin g instructions, finish

execution with no exception. Therefore only retired instructions can be considered

architecturally executed.

These features, together with the fact that most fetch cycles are performed internally

(e.g. from the I-cache), increase performance but make it very difficult to provide the

user with the real program trace.

In orde r to recons truct a progr am trace, the program cod e and the foll owing ad ditional

information from the MCU are needed:

• A description of the last fetched instruction (stall, sequential, branch not taken,

branch direct taken, branch indirect taken, exception taken).

• The ad dr ess es o f the ta r get s o f a ll indir ect flo w cha ng e. In dire ct flow ch an ge s i n-

clude a ll bran ches using the link and count regi sters as th e target ad dress, all ex-

cept ions, and rfi and mtmsr because they may cause a context switch.

• The number of instructions canceled each clock.

Reporting on program trace during retirement would significantly complicate the visi-

bility support and increase the die size. (Complications arise because more than one

instruction can retire in a clock cycle, and because it is harder to report on indirect

bran ches du ring retirement.) Th erefore, pr ogram tr ace is reported during fetch. Since

not all fetched instructions eventually retire, an indication on canceled instructions is

reported.

Instructions are fetched sequentially until branches (direct or indirect) or exceptions

appear in th e pr ogra m flow or some stall in exec ution cause s th e ma chine n ot to fetc h

the next address. Instructions may be architecturally executed, or they may be can-

celed in some stage of the machine pipeline.

The following sections define how this information is generated and how it should be

used to reconstruct the program trace. The issue of data compression that could

reduce the amount of memory needed by the debug system is also mentioned.

8.1.1 Indirect Change-of-Flow Cycles

indirect change-of-flo w

attribute is attached to all fetch cycles that result from indi-

rect flow changes. Indirect flow changes include the following types of instructions or

events:

• Assertion or negation of VSYNC.

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-3

• Exception taken.

• Indirect branch taken.

• Execution of the following sequential instructions: rfi, isync, mtmsr, and mtspr

to CMPA–CMPF, ICTRL, ECR, and DER.

When a program trace recording is needed, the user can ensure that cycles which

result fr om a n indi rect ch ange-o f-fl ow are visib le on t he exte rnal bus. Th e user can d o

this in on e of tw o ways: by sett ing th e VSYNC bi t, or by progra mming the ISCTL bits

in the I -bus sup port cont rol registe r. Refer to 8.1.2 Instruction Fetch Show Cycle Con-

trol for more information.

When the processor is programmed to generate show cycles on the external bus

resulting from indirect change-of-flow, these cycles can generate regular bus cycles

(address phase and data phase) when the instructions reside in one of the external

devices, or they can generate address-only show cycles for instructions that reside in

an internal device such as I-cache or internal ROM.

8.1.1.1 Marking the Indirect Change-of-Flow Attribute

When an instruction fetch cycle that resu lts from an in direct change-of-flow is an inter-

nal access (e.g., access to an internal memory location, or a cache hit during an

access to an external memory address), the indirect change-of-flow attribute is indi-

cated by the assertion (low) of the WR pin during the external bus show cycle.

When an instruction fetch cycle that results from an indirect change-of-flow is an

access to external memory not resulting in a cache hit, the indirect change-of-flow

attribute is indicated by the value 0001 on the CT[0:3] pins.

Table 8-1 summarizes the encodings that represent the indirect change-of-flow

attribute. In all cases the AT1 pin is asserted (high), indicating the cycle is an instruc-

tion fetch cycle.

Refer to 8.1 .3 Pro gram Flow-Tra cking Pins for more information on the use of these

pins for program flow tracking.

8.1.1.2 Sequential Instructions with the Indirect Change-of-Flow Attribute

Because certain sequential instructions (rfi, isync, mtmsr, and mtspr to CMPA–

CMPF, ICTRL, ECR, and DER) affect the machine in a manner similar to indirect

branch instructions, th e processor marks these instructions as indirect branch instruc-

tions (VF = 101, see Table 8-3) and marks the subsequent instruction address with

the indirect change-of-flow attribute, as if it were an indirect branch target. Therefore,

when the processor detects one of these instructions, the address of the following

Table 8-1 Program Trace Cycle Attribute Encodings

CT[0:3] AT1 WR Type of Bus Cycle

0001 1 1 External bus cycle

01xx,

10xx,

110x 10

Show cycle on the external bus reflecting

an access to internal register or memory or

a cache hit

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-4 Rev. 15 June 98 USER’S MANUAL

instruction is visible externally. This enables the reconstructing software to correctly

evaluate the effect of these instructions.

8.1.2 Instruction Fetch Show Cycle Control

Instruction fetch show cycles are controlled by the bits in the ICTRL and the state of

VSYNC, as illustrated in Table 8-2.

Note that when the value of the ISCTL field is changed (with the mtspr instruction),

the new value does not take effect until two instructions after the mtspr instruction.

The instruction immediately following mtspr is u nder control of th e old ISC TL value.

In order to keep the pin count of the chip as low as possible, VSYNC is not imple-

mente d as an externa l pin; rath er, it is asse rted and neg ated using th e developme nt

port serial interface. Fo r more information on this interface refer to 8.3.5 Trap-Enable

Input Transmissions.

The assertion and negation of VSYNC forces the machine to synchronize and the first

fetch after this synchronization to be marked as an indirect change-of-flow cycle and

to be visible on the external bus. This enables the external hardware to synchronize

with the internal activity of the processor.

When eith er VSYN C is asserted o r the ISCTL bi ts in the I-b us control regi ster are pr o-

grammed to a value of 0b10, cycles resulting from an indirect change-of-flow are

shown on the external bus. By programming the ISCTL bits to show all indirect flow

changes, the user can thus ensure that the processor maintains exactly the same

behavi or when VSYNC i s asserted as when i t is negated. The loss of per formance the

user can expect from the additional external bus cycles is minimal.

For add itional information o n the ISCTL bits and t he ICTRL register, refer to 8.8 Devel-

opment Support Registers. For more information on the use of VSYNC during program

trace, refer to 8.1.4 External Hardware During Program Trace.

8.1.3 Program Flow-Tracking Pins

The following sets of pins are used in program flow tracking:

• Instru ction qu eue statu s pins (VF[0 :2]) den ote the type of th e last fe tched instr uc-

tion or how many instructions were flushed from the instruction queue.

• History buffer flushes status pins (VFLS [0:1]) denote how many instructions were

Table 8-2 Fetch Show Cycles Control

VSYNC ISCTL (Instruction Fetch

Show Cycle Control Bits) Show Cycles Generated

X 00 All fetch cycles

X 01 All change-of-flow (direct & indirect)

X 10 All indirect change-of-flow

0 11 No show cycles are performed

1 11 All indirect change-of-flow

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-5

flushed from the history buffer during the current clock cycle.

• Address type p in 1 (A T1) indicates whether the cycle is tran sferring an instruction

or data.

• The write/read pin (WR), when asserted during an instruction fetch show cycle,

indicates the current cycle results from an indirect change-of-flow.

• Cycle type pins (CT[0:3]) indicate the type of bus cycle and are used to determine

the address of an internal memory or register that is being accessed.

8.1.3.1 Instruction Queue Status Pins

Instructio n queue status pi ns VF[0:2] indicate the type of the last fetched instruct ion or

how ma ny in structi ons were f lushe d fr om t he i nstructi on qu eue. These s tatu s pi ns are

used fo r both functions because queue flushe s occur only during clock cycles in which

there is no fetch type information to be reported.

Table 8-3 shows the possible instruction types.

Table 8-4 shows VF[0:2] encodings for instruction queue flush information.

Table 8-3 VF Pins Instruction Encodings

VF[0:2] Instruction Type VF Next Clock Will Hold

000 None More instruction t ype information

001 Sequential More instruction t ype information

010 Branch (direct or indirect) not taken More instruc tion type infor mation

011 VSYNC wa s asserted/negated and therefore the

next instruction will be marked with the indirect

change-of-flow attribute

More instruction t ype information

100 Exception taken — the target will be marked with the

program trace cycle attribute Queue flush inform atio n1

NOTES:

1. Unless next clock VF = 111. See below.

101

Branch indirect taken, rfi, mtmsr, isync and in some

cases mtspr to CMPA-F, ICTRL, ECR, or DER —

the target w ill b e marked wit h the in direct c hange -of-

flow attribute2

2. The sequential instructions listed here affect the machine in a manner similar to indirect branch instructions.

Refer to 8.1.1.2 Sequential Instructions with the Indirect Change-of-Flow Attribute.

Queue flu sh inf ormation1

110 Branch direct taken Queue flush information1

111 Branch (direct or indirect) not taken Queue flush information1

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There is one special case in which although queue flush information is expected on

the VF[0 :2] pin s (accord ing to th e immed iately pr eceding va lue on th ese pin s), reg ular

instruction type in formatio n is reporte d. The on ly instructio n type inform ation th at can

appear in this case is VF[0:2] = 111, indicating branch (direct or indirect) not taken.

Since the maximum queue flushes possible is five, identifying this special case is not

a problem.

8.1.3.2 History Buffer Flush Status Pins

History buffer flush status pins VFLS[0:1] indicate how many instructions are flushed

from the history buffer this clock. Table 8-4 shows VFLS encodings.

8.1.3.3 Flow-Tracking Status Pins in Debug Mode

When the processor is in debug mode, the VF[0:2] signals are low (000) and the

VFLS[0:1] sig nals are high (11).

If VSYNC is asserted or negated while the processor is in debug mode, this informa-

tion is repor ted as th e firs t VF pin s report when t he pro cessor re turns to r egula r mode.

If VSYNC is not changed while the processor is in deb ug mode, the first VF pins report

is of an indirect branch taken (VF[0:2] = 101), appropriate for the rfi instruction that is

being issued . In both cases, the first instruction fe tch after debug mode is marked with

the program trace cycle attribute and therefore is visible externally.

Table 8-4 VF Pins Queue Flush Encodings

VF[0:2] Queue Flush Information

000 0 instructions flushed from instruction queue

001 1 instruction flushed from instruction queue

010 2 instructions flushed from instruction queue

011 3 instructions flushed from instruction queue

100 4 instructions flushed from instruction queue

101 5 instructions flushed from instruction queue

110 Reserved

111 Instruction type information1

NOTES:

1. Refer to Table 8-3.

Table 8-5 VFLS Pin Encodings

VFLS[0:1] History Buffer Flush Information

00 0 instructions flushed from history queue

01 1 instruction flushed from history queue

10 2 instructions flushed from history queue

11 Used for debug mode indication (FREEZE). Program trace

external hardware should ignore this setting.

MPC509 DEVELOPMENT SUPPORT MOTOROLA

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8.1.3.4 Cycle Type, Write/Read, and Address Type Pins

Cycle type pin s (CT[0:3]) indi cate the t ype of bus cycle being p erformed. During sh ow

cycles, these pins are used to determine the internal address being accessed. Table

8-6 summarizes cycle type encodings.

Notice in Table 8-6 that during an instruction fetch (AT1 = 1) to internal memory or to

external memory resulting in a cache hit, a logic level of zero on the WR pin indicates

that the cycle is the result of an indirect change-of-flow. The indirect change-of-flow

attribute is also indicated by a cycle type encoding of 0001 when AT1 = 1. Refer to

8.1.1.1 Marking the Indirect Change-of-Flow Attribute for addi tiona l in fo rm ation.

8.1.4 External Hardware During Program Trace

When program trace is needed, external hardware needs to record the status pins

(VF[0:2] and VFLS[0:1]) of each clock and record the address of all cycles marked with

the indirect change-of-flow attribute.

Table 8-6 Cycle Type Encodings

CT[0:3] Description

0000 Normal external bus cycle

0001

If address type is data (AT1 = 0), this is a data access to the external bus

and the start of a reservation.

If address type is instruction (AT1 = 1), this cycle type indicates that an

external address is the destination of an indirect change-of-flow.

0010

External bus cycle to emulation memory replacing internal I-bus or L-bus

memory. An in struction acces s (AT1 = 1) with an ad dress that is the targ et

of an indirect change-of-flow is indicated as a logic level zero on the WR

output.

0011 Normal external bus cycle access to a port replacement chip used for

emulation support.

0100 Access to internal I-bus memory. An instruction access (AT1 = 1) with an

address that is the target of an indirect change-of-flow is indicated as a logic

level zero on the WR outp ut.

0101 Access to internal L-bus memory. An instruction access (AT1 = 1) with an

address that is the target of an indirect change-of-flow is indicated as a logic

level zero on the WR output .

0110 Cache hit on external memory address not controlled by chip selects. An

instruc tion access (AT1 = 1) with an add ress that is the target of an indirect

change-of-flow is indicated as a logic level zero on the WR output.

0111 Access to an internal register.

1000

1001

1010

1011

1100

1101

Cache hit on external memory address controlled by CSBOOT.

Cache hit on external memory address controlled by CS1.

Cache hit on external memory address controlled by CS2.

Cache hit on external memory address controlled by CS3.

Cache hit on external memory address controlled by CS4.

Cache hit on external memory address controlled by CS5.

An instruction access (AT1 = 1) with an address that is the target of an

indirect change-of-flow is indicated as a logic level zero on the WR output.

1110 Reserved

1111

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Program trace can be used in various ways. Two types of traces that can be imple-

mented are the back trace and the windo w trace.

8.1.4.1 Back Trace

A back trace provides a record of the program trace

before

some event occurred. An

example of such an event is some system failure.

When a back trace is needed, the external hardware should start sampling the status

pins and the address of all cycles marked with the indirect change-of-flow attribute

immediately after reset is negated. Since the ISCTL field in the ICTRL has a value of

is 0b00 (show all cycles) out of reset, all cycles marked with the indirect change-of-flow

attribute are visible on the external bus. VSYNC should be asserted sometime after

reset and negated when the programmed event occurs. VSYNC must be asserted

before the ISCTL encoding is changed to 0b11 (no show cycles), if such an encoding

is selected.

Note t hat i n case the ti ming of the pro gramm ed eve nt is unknown , it i s poss ibl e to u se

cyclic buffers.

After VSYNC is neg ated, the trace buffer will contain the program flow trace of the pro-

gram e xecut ed bef ore the programmed event occurred.

8.1.4.2 Window Trace

Window trace provides a record of the program trace

between

two events. VSYNC

should be asserted between these two events.

After VSYNC is negated, the trace buffer will contain information describing the pro-

gram trace of the program executed between the two events.

8.1.4.3 Synchronizing the Trace Window to Internal CPU Events

In order to synchr onize the asser tion or negat ion of VSYN C to an event interna l to the

processor, internal breakpoints can be used together with debug mode. This method

is avai labl e onl y whe n debu g mod e is en able d. (Refe r to 8.4 D eb ug M o de Fu ncti o ns .)

The following steps enable the user to synchronize the trace window to events internal

to the processor:

1. E nter debug mode, eith er immedi ately out of reset or using the debu g mode re-

quest.

2. Program the hardware to break on the event that marks the start of the trace

window using the control registers defined in 8.8 Development Support Regis-

ters.

3. Enable debug mode entry for the programmed breakpoint in the debug enable

4. Return to the regular code run.

5. The hardware gene rates a br eakpoint when the programmed event is detected,

and the machine enters debug mode.

6. Program the hardware to break on the event that marks the end of the trace

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USER’S MANUAL Rev. 15 June 98 8-9

window.

7. Assert VSYNC.

8. Return to the regular code run. The first report on the VF pins is a VSYNC

(VF[0:2] = 011).

9. Th e exte r nal ha rdware sta rt s sam pli ng the program tr ace information upon th e

report on the VF pins of VSY NC.

10. The ha rdware generates a b reakpoint when t he programmed event is detected,

and the machine enters debug mode.

11. Negate VSYNC.

12. Return to the regular code run. The first report on the VF pins is a VSYNC

(VF[0:2] = 011).

13. The external hardware stops sampling the program trace information upon the

report on the VF pins of VSY NC.

A second method allows the trace window to be synchronized to internal processor

events without stopping execution and entering debug mode at the two events.

1. E nter debug mode, eith er immedi ately out of reset or using the debu g mode re-

quest.

2. Program a watchpoint for the event that marks the start of the trace window us-

ing the control registers defined in 8.8 Development Support Registers.

3. Program a second watchpoint for the event that marks the end of the trace win-

dow.

4. Retu rn to re gular co de execution by exiting debug mo de.

5. The watchpoint logic signals the starting event by asserting the appropriate

watc hp oi nt pin.

6. Upo n dete cting t he first w atchp oint, assert V SYNC using the dev elop ment p ort

seri a l in terfac e.

7. The exte rnal prog ram trace hardware sta rts sampling t he progra m trace infor -

mation upon the report on the VF pins of VSYNC.

8. The watchpoint logic signals the ending event by asserting the appropriate

watc hp oi nt pin.

9. Upo n de tect in g the se cond wa tchp oi nt , n eg ate VS YN C u s in g the d eve lo pmen t

port serial interface.

10. The external program trace hardware stops sampling the program trace infor-

mation upon the report on VF[0:1] of VSYNC.

The second method is not as precise as the first method because of the delay between

the asser tion of the w atchpoint pins and the a ssertion or n egation of VS YNC using th e

development port serial interface. It has the advantage, however, of allowing the pro-

gram to run in quasi-real time (slowed only by show cycles on the external bus),

instead of stopping execution a t the starting and ending events.

8.1.4.4 Detecting the Trace Window Starting Address

For a b ack trace, t he value of the sta tus pins (VF[ 0:2] and V FLS[0:1 ]) and t he address

of the cycles marked with the indirect change-of-flow attrib ute should be latche d start-

ing imm ediate ly afte r the ne gation of reset . Th e start ing addr ess is the fi rst add ress in

the program trace cycle buffer.

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For a windo w trace, th e value of th e status p ins and th e address of the cycles marke d

with the indirect change-of-flow attribute should be latched beginning immediately

after th e first VSYNC is r eported on the VF pins. The starting addr ess of the trace win-

dow should be calculated according to the first two VF pin reports.

Assume VF1 and VF2 are the two first VF pin reports and T1 and T2 are the addresses

of the first two cycles marked with the indirect change-of-flow attribute that were

latched in the trace buffer. Use Table 8-7 to calculate the trace window starting

address.

8.1.4.5 Detecting the Assertion or Negation of VSYNC

Since the VF pi ns are u sed for re porting b oth inst ruction t ype info rmation and queue

flush information, special care must be taken when trying to detect the assertion or

negat io n of VS Y NC. A V F[0 : 2] en cod in g o f 011 indi cat es the as se rtio n o r ne ga tion of

VSYNC only if the previous VF[0:2] pin values were 000, 001, or 010.

8.1.4.6 Detecting the Trace Window Ending Address

The information on the VF and VFLS status pins changes every clock. Cycles marked

with th e indir ect cha nge-of- flow are gene rated on th e ex tern al bus onl y whe n po ssible

(when the SIU wins the arbitration over the external bus). Therefore, there is some

delay between the time it is reported on the status pins that a cycle marked as program

trace cycle will be performed on the external bus and the actual time that this cycle can

be detected on the external bus.

When the user negates VSYNC, the processor delays the report of the assertion or

negation of VSYNC on the VF pins until all addresses marked with the indirect change-

of-flow attribute have been made visible externally. Therefore, the external hardware

should stop sampling the value of the status pins (VF and VFLS) and the address of

the cycles marke d with the program trace cycle attribute immediately aft er the VSYNC

report on the VF pins.

CAUTION

The last two instructions reported on the VF pins are not always valid.

Therefore, at the last stage of the reconstruction software, the last

two instructions should be ignored.

Table 8-7 Detecting the Trace Buffer Starting Point

VF1 VF2 Starting Point Description

011

VSYNC 001

Sequential T1 VSYNC asserted followed by a sequential instruction.

The starting address is T1.

011

VSYNC 110

Branch direct

taken

T1 – 4 + offset

(T1 – 4) VSYNC asserted followed by a taken direct branch.

The start ing addres s is the ta rget of the direct branch.

011

VSYNC 101

Branch indirect

taken

T2 VSYNC asserte d followed by a taken in direct bra nch.

The starting address is the target of the indirect

branch.

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-11

8.1.5 Compress

In orde r to stor e all t he inf ormati on gen erat ed on the pins du rin g prog ram trace (5 bits

per clock + 30 bits per show cycle) a large memory buffer may be needed. However,

since this information includes events that were canceled, compression can be very

effective. External hardware can be added to eliminate all canceled instructions and

report only on branches (taken and not taken), indirect flow change, and the number

of sequential instructions after the last flow change.

8.2 Watchpoint and Breakpoint Support

The RCPU provides the ability to detect specific bus cycles, as defined by a user

(watchpoints). It also provides the ability to conditionally respond to these watchpoints

by taking an exception (internal breakpoints). Breakpoints can also be caused by an

event or state in a peripheral or through the development port (external breakpoints,

i.e., breakpoints external to the processor).

When a watchpoint is detected, it is reported to external hardware on dedicated pins.

Watchpoints d o not change the timing or flow of the processor. Because bus cycles on

the internal MCU buses are not necessarily visible on the external bus, the watch-

points are a convenient way to signal an external instrument (such as a bus state

analyzer or oscilloscope) that the internal bus cycle occurred.

An internal breakpoint occurs when a particular watchpoint is enabled to generate a

breakpoint. A watchpoint may be enabled to generate a breakpoint from a software

monitor or by using the development port serial interface. A watchpoint output may

also be counte d. When the cou nter reache s zero, an inte rnal breakpo int is gene rated.

An external breakpoint occurs when a development system or external peripheral

requests a breakpoint through the development port serial interface. In addition, if an

on-chip peripheral requests a breakpoint, an external breakpoint is generated.

All in ternal breakpoint s are m asked by t he MSR[ RI] bit u nless the non-masked control

bit (BRKNOMSK) in LCTRL2 is set. The development port maskable breakpoint and

breakpoints from internal peripherals are masked by the MSR[RI] bit. The develop-

ment port non-maskable b reakp oint is not masked by this bit.

Figure 8-1 is a diagram of watchpoint and breakpoint support in the RCPU.

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8-12 Rev. 15 June 98 USER’S MANUAL

Figure 8-1 Watchpoint and Breakpoint Support in the RCPU

8.2.1 Watchpoints

Watchpoints are based on eight comparators on the I-bus and L-bus, two counters,

and two AND-OR logic structures. There are four comparators on the instruction

address bu s ( I- addr ess), two comp ar at or s on th e load/store ad dr ess bus (L-ad dr ess),

and two comparators on the load/store data bus (L-data).

The comparators are able to detect the following conditions: equal, not equal, greater

than, and less than. Greater than or equal and less than or equal are easily obtained

from these four conditions. (For more informat ion refer to 8.2.1 .3 Genera ting Si x Com-

pare Types.) Using the AND-OR logic structures, in range and out of range detection

(on ad dr ess a nd on d ata ) are su pported . Us ing the coun ter s, i t is p ossibl e to p ro gr am

a breakpoint to be generated after an event is detected a predefined number of times.

DEVELOPMENT

SYSTEM OR

EXTERNAL

PERIPHERALS

INTERNAL

PERIPHERALS

MASKABLE BREAKPOIN T

NON-MASKABLE BREAKPOINT

DEVELOPMENT PORT TRAP ENABLE BITS

DEVELOPMENT

PORT

SOFTWARE TRAP ENA BLE BITS

(NON-MASKED CONTROL BIT)

MSRRI

LCTRL2

MSR

INTERNAL

WATCHPOINTS

LOGIC

WATCHPOINTS

BITWISE AND

BITWISE OR

COUNTERS

BREAKP0INT

TO CPU

TO WATCHPOINTS

PINS

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-13

The L-data comparators can operate on integer data, floating-point single-precision

data, and the integer value stored using the stfiwx instruction. Integer comparisons

can be performed on bytes, half words, and words. The operands can be treated as

signed or unsigned values.

The comparators generate match events. The I-bus match events enter the I-bus

AND-OR logic, where the I-bus watchpoints and breakpoint are generated. When

asserted, the I-bus watchpoints may generate the I-bus breakpoint. Two of them may

decrement one of the counters. When a counter that is counting one of the I-bus

watchpoints expires, the I-bus breakpoint is asserted.

The I-b us watchpoin ts and the L-bus match events (add ress and data ) enter t he L-bus

AND-OR logic where the L-bus watchpoints and breakpoint are generated. When

asserted , the L-bus watchpoi nts may generate the L-bus brea kpoint, or they may dec-

rement one of the counters. When a counter that is counting one of the L-bus

watchpoints expires, the L-bus breakpoint is asserted.

L-bus watchpoints can be qualified by I-bus watchpoints. If qualified, the L-bus watch-

point occurs only if the L-bus cycle was the result of executing an instruction that

caus ed the qualifying I-bus wat chpo int.

A watch point progr esses in the m achine along with the in struction that ca used it (fetch

or load/store cycle). Watchpoints are reported on the external pins when the associ-

ated instruction is retired.

8.2.1.1 Restrictions on Watchpoint Detection

There are cases when the same watchpoint can be detected more than once during

the exec ution of a sin gle instruc tion. For example , the proc essor may det ect an L-b us

watchpoint on more than one transfer when executing a load/store multiple or string

instru ction or may de tect an L- bus watchp oint on more than one byte when wo rking i n

byte mode. In these cases only one watchpoint of the same type is reported for a single

instruction. Similarly, only one watchpoint of the same type can be counted in the

counters for a single instruction.

Since watchpoint events are reported upon the retirement of the instruction that

caused the event, and more than one instruction can retire from the machine in one

clock, separate watchpoint events may be reported in the same clock. Moreover, the

same event, if detected on more than one instruction (e.g. tight loops, range detec-

tion), in some cases is reported only once. However, the internal counters still count

correctly.

8.2.1.2 Byte and Half-Word Working Modes

Watchpoint and breakpoint support enables the user to detect matches on bytes and

half words even when accessed using a load/store instruction of larger data widths,

e.g. when loading a table of bytes using a series of lo ad word in structions.

To use this feature the user needs to program the byte mask for each of the L-data

comparators and to write the needed match value to the correct half word of the data

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-14 Rev. 15 June 98 USER’S MANUAL

compar ator w hen work ing in ha lf-wo rd mode and to the correc t bytes of the data co m-

parator when working in byte mode.

Since byte s and ha lf w or ds can b e a ccesse d using a large r da ta w idth i nstr uc ti on, th e

user cann ot pr edict th e exact valu e of the L-add ress lin es whe n the re queste d byte or

half word is accessed. For example, if the matched byte is byte two of the word and it

is accessed using a load word instruction, the L-address value will be of the word (byte

zero). Therefore the processor masks the two least significant bits of the L-address

compar ator s wheneve r a wor d access is perfor med and th e least si gni fican t bit whe n-

ever a h alf wo rd a cc ess is pe rfor me d. Addr es s ra ng e is su pp or te d only wh en ali gn ed

according to the access size.

The followin g examples illustrate how to detect ma tches on bytes and half words.

1. A fully suppo r ted sc enario:

• Looking for:

— Data size: Byte

— Address: 0x0000 0003

— Data value: greater than 0x07 and less than 0x0C

• Programmi ng option:

— One L-address comparator = 0x0000 0003 and program for equal

— One L-data comparator = 0xXXXX XXX7 and program for greater than

— One L-data comparator = 0xXXXX XXXC and program for less than

— Both byte masks = 0b0001

— Both L-data comparators program to byte mode

• Result: The event will be detected regardless of the instruction the compiler

chooses for this access.

2. A fully suppo r ted sc enario:

• Looking for:

— Data size: Half word

— Address: greater than 0x0000 0000 and less than 0x0000 000C

— Data value: greater than 0x4E20 and less than 0x9C4 0

• Programmi ng option:

— One L-address comparator = 0x0000 0000 and program for greater than

— One L-address comparator = 0x0000 000C and program for less than

— One L-data comparator = 0x4E20 4E20 and program for greater than

— One L-data comparator = 0x9C40 9C40 and program for less than

— Both byte masks = 0b1111

— Both L-data comparators program to half word mode

• Result: The event will be detected correctly provided that the compiler does

not use a load/store instruction with data size of byte.

3. A partially supported scenario:

• Looking for:

— Data size: Half word

— Address: greater than 0x0000 0002 and less than 0x0000 000E

— Data value: greater than 0x4E20 and less than 0x9C4 0

• Programmi ng option:

— One L-address comparator = 0x0000 0002 and program for greater than

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USER’S MANUAL Rev. 15 June 98 8-15

— One L-address comparator = 0x0000 000E and program for less than

— One L-data comparator = 0x4E20 4E20 and program for greater than

— One L-data comparator = 0x9C40 9C40 and program for less than

— Both byte masks = 0b1111

— Both L-data comparators program to half-word mode or to word mode

4. Result: The event will be detected correctly if the compiler choose s a load/store

instruction with data size of half word. If the compiler chooses load/store in-

structi ons with data si ze gr ea ter than ha lf wo rd ( w or d, m ul ti p le ), ther e m i ght b e

some f alse detect io ns. The se can be i gno red only by th e softwa re th at h andl es

the breakpoints. Figure 8-2 illustrates this partially supported scenario.

Figure 8-2 Partially Supported Watchpoint/Breakpoint Example

8.2.1.3 Generating Six Compare Types

Using the four basic compare types (equal, not equal, greater than, less than), it is pos-

sible to generate two additional compare types: “greater than or equal” and “less than

or equal ” .

The “greater than or equal” compare type can be generated using the greater than

compare type and programming the comparator to the needed value minus one.

The “less tha n or eq ual” compar e type can be gene rate d using the less tha n compar e

type and programming the comparator to the needed value plus one.

This method does not work for the following boundary cases:

• Less than or equal of the largest unsigned number (1111...1)

• Greater than or equal of the smallest unsigned number (0000...0)

• Less than or equal of the maximum positive number when in signed mode

(0111...1)

• Greater than or equal of the maximum negative number when in signed mode

(1000...)

These boundary cases need no special support because they all mean “always true”

and can be programmed using the ignore option of the L-bu s watchpoint programming

(refer to 8.8 Development Support Registers).

8.2.1.4 I-Bus Support Detailed Description

There are four I-bus address comparators (comparators A,B,C,D). Each is 30 bits long

and generates two o utput signals: equal and less than. These signals are used to gen-

0x0000_0000

0x0000_0004

0x0000_0008

0x0000_000c

0x0000_0010

POSSIBLE FALSE DETECT ON THESE

HALF WORDS WHEN USING WORD/MULTIPLE

MOTOROLA DEVELOPMENT SUPPORT MPC509

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erate o ne of the following four events: equa l, not equal, greater than, less than. Figure

8-3 shows the general structure of I-bus support.

Figure 8-3 I-Bus Support General Structure

The I-bus watchpoints and breakpoint are generated using these events and accord-

ing to the user’s programming of the CMPA, CMPB, CMPC, CMPD, and ICTRL

registers. Table 8-8 shows how watchpoints are determined from the programming

options. Note that using the OR option enables “out of range” detection.

COMPARATOR

COMPARE TYPE

COMPARATOR

EVENTS GENERATOR

AND-OR

LOGIC

CONTROL BITS

(A&B)

(A | B)

(C&D)

(C | D)

I-WATCHPOINT 0

I-WATCHPOINT 1

I-BREAKPOINT

I-WATCHPOINT 2

I-WATCHPOINT 3

COMPARE

TYPE

LOGIC

COMPARE

TYPE

LOGIC

COMPARE

TYPE

LOGIC

COMPARE

TYPE

LOGIC

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8.2.1.5 L-Bus Support Detailed Description

There are two L-bus address comparators (comparators E and F). Each compares the

32 address bits and the cycle’s read/write attribute. The two least significant bits are

masked (ignored) whenever a word is accessed, and the least significant bit is masked

whenever a half word is accessed. (For more information refer to 8.2.1.2 Byte and

Half-Word Working Modes). Each comparator generates two output signals: equal and

less than. These signals are used to generate one of the following four events (one

from each comparator): equal, not equal, greater than, less than.

There are two L-bus data comparators (comparators G and H). Each is 32 bits wide

and can be programmed to treat numbers either as signed values or as unsigned val-

ues. Each data comparator operates as four independent byte comparators. Each

byte comparator has a mask bit and generates two output signals, equal and less than,

if the mask bit is not set. Therefore, each 32-bit comparator has eight output signals.

These sig nals are used to ge nera te the “ equa l and less th an” sig nals acc ording to the

compare size programmed by the user (byte, half word, word). In byte mode all signals

are significant. In half-word mode only four signals from each 32-bit comparator are

signifi cant. In word mode only two sig nals from each 32-bit comparator ar e significan t.

From the new “equal and less than” signals, depending on the compare type pro-

grammed by the user, one of the following four match events is generated: equal, not

equal , greater than , less than. Theref ore from the two 32-bit compara tors, eight mat ch

indications are generated: Gmatch[0:3], Hmatch[0:3].

According to the lo wer bits of the address a nd the size of the cycle , only ma tch indica-

tions that were detected on b ytes that have valid info rmation are validated; the rest are

negated. Note that if the cycle executed has a smaller size than the compare size (e.g.,

a byte access when the compare size is word or half word) no match indication is

asserted.

Figure 8-4 shows the general structure of L-bus support.

Table 8-8 I-bus Watchpoint Programming Options

Name Description Programming Options

IW0 First I-bus watchpoint Comparator A

Comparators (A&B)

IW1 Second I-bus watchpoint Comparator B

Comparator (A | B)

IW2 Third I-bus watchpoint Comparator C

Comparators (C&D)

IW3 Fourth I-bus watchpoint Comparator D

Comparat or (C | D)

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-18 Rev. 15 June 98 USER’S MANUAL

Figure 8-4 L-Bus Support General Structure

Using th e m atch ind i cati on sig na ls, fo ur L -b us da ta eve nts are ge ne ra ted a s sh own in

Table 8-9.

Table 8-9 L-Bus Data Events

Event Name Event Function1

NOTES:

1. ‘&’ denotes a logical AND, ‘|’ denotes a logical OR

G (Gmatch0 | Gmatch1 | Gmatch2 | Gmatc h3)

H (Hmatch0 | Hmatch1 | Hmatch2 | Hmatch3)

(G&H) ((Gmatch0 & Hmatch0) | (Gmatch1 & Hmatch1) | (Gmatch2 & Hmatch2) | (Gmatch3 & Hmatch3))

COMPARATOR G

BYTE 0 EQ

COMPARE SIZECOMPARE TYPE

BYTE 1 EQ

BYTE 2 EQ

BYTE 3 EQ

COMPARATOR H

BYTE 0 EQ

BYTE 1 EQ

BYTE 2 EQ

BYTE 3 EQ

ADDR(30:31)

L-BUS CYCLE SIZE

COMPARE SIZE

VALID 0

VALID 1

VALID 2

VALID 3

(G&H)

(G | H)

I-BUS WATCHPOINTS

L-WATCHPOINT 0

L-WATCHPOINT 1

L-BREAKPOINT

SIZE

LOGIC

COMPARE BYTE

QUALIFIER

LOGIC

EVENTS GENERATOR

AND-OR LOGIC

SIZE

LOGIC

BYTE

QUALIFIER

LOGIC

CONTROL BITS

(E&F)

(E | F)

EVENTS

GENERATOR

LT EQ LT EQ

COMPARE TYPE

TYPE

LOGIC

COMPARE

TYPE

LOGIC

BYTE MASK

COMPARATOR E

TYPE LOGIC

COMPARATOR F

TYPE LOGIC

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-19

The four L-bus data even ts toget her wit h the match events of th e L-b us address co m-

parators and the I-bus watchpoints are used to generate the L-bus watchpoints and

breakp oint accord ing to t he user’s programm ing of the CMPE, CM PF, CMPG , CMPH,

LCTRL1, and LCTRL2 registers. Table 8-10 shows how the watchpoints are deter-

mined from the programming options.

8.2.1.6 Treating Floating-Point Numbers

The data comparators can detect match events on floating-point single precision val-

ues in floa ti ng po in t l oa d/ s tore instructi o ns. Wh en floa ting poi n t va lues are compar ed ,

the comparators must be programmed to operate in signed word mode.

During th e execut io n of a load /store instr uctio n of a float in g-po int d ouble o pe rand, the

L-data comparators never generate a match. If L-data events are programmed for

don’t care (i.e., LCTRL2[LWOLADC] = 0), L-bus watchpoint and breakpoint events can

be generated from the L-address events, even if the instruction is a load/store double

instruction.

8.2.2 Internal Breakpoints

Internal breakpoints are generated from the watchpoints. The user may enable a

watchp oint t o crea te a breakp oin t by setting the associ ated softwa re trap enabl e bit i n

the ICTRL o r LC TRL2 r e gi ster . Th is can b e d one by a software m oni t or program exe-

cuted by the MCU. An external development tool can also enable internal breakpoints

from watch points by settin g the associated de velopmen t port trap enab le bit usi ng the

development port serial inter face.

Internal breakpoints can also be generated by assigning a breakpoint count er to a par-

ticular watchpoint. The counter counts down for each watchpoint, and a breakpoint is

generated when the counter rea ches zero.

An internal breakpoint progresses in the machine along with the instruction that

caused it (fet ch or loa d/st ore cycle ). Wh en a brea kpo i nt rea che s the top of the history

buffer, the machine processes the breakpoint exception.

An instruction tha t causes an I-bus breakpoint is not retired. The processor branche s

to the breakpoint exception routine

before

it executes the instruction. An instruction

Table 8-10 L-Bus Watchpoints Programming Options

Name Description I-Bus Events

Programming Options L-Address Events

Programming Options L-Data Events

Programming Options

LW0 First

L-bus watc hpo int IW0, IW1, IW2, IW3

or don’t care

Comparator E

Comparat or F

Comparators (E&F)

Comparators (E | F)

or don’t care

Comparator G

Comparator H

Comparators (G&H)

Comparators (G | H)

or don’t care

LW1 Second

L-bus watc hpo int IW0, IW1, IW2, IW3

or don’t care

Comparator E

Comparat or F

Comparators (E&F)

Comparators (E | F)

or don’t care

Comparator G

Comparator H

Comparators (G&H)

Comparators (G | H)

or don’t care

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-20 Rev. 15 June 98 USER’S MANUAL

that causes an L-bus breakpoint is executed. The processor branches to the break-

point ex ce ptio n routin e

after

it executes the instruction. The address of the load/store

cycle that gene rate d the L-bus b reakp oint is stored in the breakp oint a ddre ss register

(BAR).

8.2.2.1 Breakpoint Counters

There are two 16-bit down counters. Each counter is able to count one of the I-bus

watchp oints or o ne of t he L-bu s watc hpoi nts. Bot h gen erate th e cor respo nding b reak-

point when they reach zero. If the instruction associated with the watchpoint is not

retired, the counter is adjusted back so that it reflects actual execution.

In the masked mo de, the coun ters do not count w atchp oints detec ted wh en MSR[RI ]

= 0. See 8.2. 4 Breakp oi nt Ma ski ng.

When counting watchpoints programmed on the actual instructions that alter the

counters, the counters will have unpredictable values. A sync instruction should be

inserted before a read of an active counter.

8.2.2.2 Trap-Enable Programming

The trap enable bits can be programmed by regular, supervisor-level software (by writ-

ing to the ICTRL or LCTRL2 with the mtspr instruction) or “on the fly” using the

development port interface. For more information on the latter method, refer to 8.3.5

Trap-Enable Input Transmissions.

The value used by the breakpoints generation logic is the bit-wise OR of the software

trap enable bits (the bits written using the mtspr) and the development port trap

enable bits (the bits serially shifted using the development port).

All bits, the software trap-enable bits and the development port trap enable bits, can

be read from ICTRL and the LCTRL2 using mfspr. For th e e x act b it s pl ace m ent re fer

to Table 8-30 and Table 8-32.

8.2.2.3 Ignore First Match

In order to facilitate the debugger utilities of “continu e” and “go from x”, the option to

ignore t he first match is supported for the I-bus breakpoints. When an I-bus breakpoint

is firs t enab led (a s a resu lt of the first write to t he I-b us supp ort contr ol reg ister or as a

result of the assertion of the MSR[RI] bit in masked mode), the first instruction will not

cause an I-bus breakpoin t if th e IFM ( ignore first mat ch) bit in the I-bus sup port con trol

at a breakpoint and then later to “continue” from that point without the breakpoint

immediately stopping the processor again before executing the first instruction.

When the IFM bit is cleared, every ma tched instruct ion can cause an I-bus br eakpoint

(used for “go from x,” where x is an address that would not cause a breakpoint).

The IFM bit is set by the software and cleared by the hardware after the first I-bus

breakpoint match is ignored.

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-21

Since L-bus breakpoints are treated after the instruction is executed, L-bus break-

points and counter-generated I-bus breakpoints are not affected by this mode.

8.2.3 External Breakpoints

Breakpoints external to the processor can come from either an on-chip peripheral or

from the development port. For additional information on breakpoints from on-chip

peripherals, consult the user’s manual for the microcontroller of interest or the refer-

ence manual for the peripheral of interest.

The deve lopme nt port ser ial in terface ca n be use d to assert either a maskabl e or non-

maskable breakpoint. Refer to 8.3.5 Trap-Enable Input Transmissions for more infor-

mation about generating breakpoints from the development port. The development

port breakpoint bits remain asserted until they are cleared; however, they cause a

breakpoint only when they change from cleared to set. If they remain set, they do not

cause an additional breakpoint until they are cleared and set again.

External breakpoints are not referenced to any particular instruction; they are refer-

enced to the current or following L-bus cycle. The breakpoint is taken as soon as the

processor completes an instruc tion that uses the L-bus.

8.2.4 Breakpoint Masking

The processor responds to two different types of breakpoints. The maskable break-

point is taken only if the processor is in a recoverable state. This means that taking the

breakpoint will not destroy any of the internal machine context. The processor is

define d to be in a recov erable st ate when the MSR[RI ] (recov erable exception) bit is

set. Maskab le brea kpoi nts are gene rate d by the inte rnal breakpo int l ogic, mod ules on

the IMB2, and the development port.

Non-m askable breakpoints cause the pro cesso r to stop without regard to the state of

the MSR[RI] bit. If the processor is in a non-recoverable state when the breakpoint

occurs, the state of the SRR0, SRR1, and the DAR may have been overwritten by the

breakpoint. It will not be possible to restart the processor, since the restart address and

MSR context may not be available in SRR0 and SRR1.

Only th e de velop ment port a nd th e i ntern al br eakpo int logic are capabl e o f gen eratin g

a non- maskable bre akpoint. This al lows the user to stop the proce ssor in cases whe re

it would otherwise not stop, but with the penalty that it may not be restartable. The

value of the MSR[RI] bit as saved in the SRR1 register indicates whether the proces-

sor stopped in a recoverable state or not.

Internal breakpoints are made maskable or non-maskable by clearing or setting the

BRKNOMSK bit of the LCTRL2 register. Refer to 8.8.7 L-Bus Support Control Register

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-22 Rev. 15 June 98 USER’S MANUAL

8.3 Development Port

The development port provides a full duplex serial interface for communications

betwe en the inter nal deve lopm ent supp ort l ogic, i nclu ding d ebug m ode , and a n exte r-

nal development tool.

The relationship of the development support logic to the rest of the MCU is shown in

Figure 8-5. Although the development p ort is implemented as part of t he system inter-

face unit (SIU), it is used in conjunction with RCPU development support features and

is therefore described in this section.

Figure 8-5 Development Port Support Logic

8.3.1 De velopment Port Signals

The following development port signals are provided:

• Development serial clock (DSCK)

• Development serial data in (DSDI)

• Development serial data out (DSDO)

The development port signal DSDO shares a pin with the PLLL signal.

DEVEL OPME NT PO RT

DEVELOPMENT PORT

RCPU

TECR

CONTROL LOGIC

SHIFT REGISTER

DSDI

DSCK

BKPT, TE,

VSYNC

PLLL/

DSDO

VFLS

(FRZ)

EXT

BUS

I-CACHE

L-BUS

I-BUS

32 SIU/

EBI

DEV SU P PO RT SPRs

BREAKPOINT LOGIC

SIU BUS

DEV

PORT

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-23

8.3.1.1 Development Serial Clock

In clocked mode (see 8.3.3 Development Port Clock Mode Selection), the develop-

ment serial clock (DSCK) is used to shift data into and out of the development port shift

thereby minimizing the chance of propagating metastable states into the serial state

machine. The values of the pins are sampled during the low phase of the system clock.

At the rising edge of the system clo ck, the samp le d value s a re latched in terna lly. On e

quarte r cl ock l at er , t he l at c hed va lue s a re ma de available to the de vel o pm en t su pp or t

logic.

In clocked mode, detection of the rising edge of the synchronized clock causes the

synchronized data from the DSDI pin to be loaded into the least significant bit of the

shift register. This transfer occurs one quarter clock after the next rising edge of the

system clock. A t the same t ime, the n ew most significant bit of th e shift register is pre-

sented at the PLLL/DS DO pin. Future references to the DSCK signal imply t he internal

synchronized va lue of the clock . The DSCK input must be driven eith er high o r low at

all tim es and not a llowed to float . A typical target en vironmen t would p ull this input l ow

with a resistor.

To allow the synchronizers to operate correctly, the development serial clock fre-

quency must not exceed one half of the system clock frequency. The clock may be

implemented as a free-running clock. The shifting of data is controlled by ready and

start signals so the clock does not need to be gated with the serial transmissions.

Refer to 8.3.5 Trap-Enabl e Input Trans missions and 8.3.6 CPU Input Transmissions.

The DSCK pin is also used during reset to enable debug mode and immediately fol-

lowing reset to optionally cause immediate entry into debug mode following reset. This

is described in section 8.4.1 Enabling Debug Mode and 8.4.2 Entering Debug Mode.

8.3.1.2 Development Serial Data In

Data to be transferred into the development port shift register is presented at the

development serial data in (DSDI) pin by external logic. To be sure that the correct

value i s used in ternal ly, transi tions on the DSDI pi n should occur at lea st a setu p time

ahead of the rising edge of the DSCK signal (if in clocked mode) o r a setup time ahead

of the rising edge of the system clock, whichever is greater. This will allow operation

of the development port either asynchronously or synchronously with the system

clock. The DSDI input must be driven either high or low at all times and not allowed to

float. A typical target environment would pull this input low with a resistor.

When t he processor i s not in debug mode (free ze not indi cated on VFLS [0:1] pins) th e

data received on the DSDI pin is transferred to the trap enable control regi ster. When

the processor is in debug mode, the data received on the DSDI pin is provided to the

debug mode interface. Refer to 8.3.5 Trap-Enable Input Transmissions and 8.3.6 CPU

Input Transmissions for additional information.

The DSDI pin is also used at reset to control overall chip reset configuration and imme-

diately following reset to determine the development port clock mode. See 8.3.3

Development Port Clock Mode Selection for more information.

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-24 Rev. 15 June 98 USER’S MANUAL

8.3.1.3 Development Serial Data Out

When the processor is not in reset, the development port shifts data out of the devel-

opment port shift register using the development serial data out (PLLL/DSDO) pin.

When the processor is in reset, the PLLL/DSDO pin indicates the state of lock of the

system clock phase-locked loop. This can be used to determine when a reset is

caused by a loss of lock on the system clock PLL.

8.3.2 Development Port Registers

The development port consists of two registers: the development port shift register

and the trap enable control register. These registers are described in the following

paragraphs. Figure 8-6 illustrates the development port registers and data paths.

Figure 8-6 Development Port Re gisters and Data Paths

LENGTH/STATUS0

CONTROL/STATUS1

SHIFT REGI ST ER (35 BITS)

INPUT AND OU TPUT 3-STAT E BUF FERS (32 BITS)

START/READY

DSDI (INTERNAL)

DSCK

DSDI

PLLL/DSDO

DEVELOPMENT PORT BUS

(TO SIU)

DSDO (INTERNAL)

SHIFT

32 (DATA)

(DEVELOPMENT PORT PINS)

TRA P ENA BLES, VSYNC, BREA KP OI NT S (9 BIT S )

6 2

TRAP ENABLES [0:5] BREAKPOINTS

(TO RCPU)

HANDSHAKE AND BUS INTERFACE SIGNALS

DEBUG BUS CONTROL

(OEs AND WEs)

VSYNC

SHIFT CONTROL

AND COUNTER

CLOCK

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-25

8.3.2.1 Development Port Shift Register

The development port shift register is a 35-bit shift register. Instructions and data are

shifted into it serially from DSDI. These instructions or data are then transferred in par-

allel to the processor or the trap enable control register (TECR).

When the processor enter s debug mode, it fe tches instr uctions fr om the developm ent

port shift register. These instructions are serially loaded into the shift register from

DSDI.

When the processor is in debu g mode, data i s transfe rred to the CPU by shi fting it into

the shift register. The processor then reads the data as the result of ex ecuting a “move

from special-purpose register DPDR” (development port data register) instruction.

In debug mode, data is also parallel loaded into the development port shift register

from the CPU by executing a “move to special purpose register DPDR” instruction. It

is then shifted out serially to PLLL/DSDO.

8.3.2.2 Trap Enable Control Register

The trap enable control register (TECR) is a nine-bit register that is loaded from the

development port shift register. The contents of the TECR are used to drive the six trap

enable signals, the two breakpoint signals, and the VSYNC signal to the processor.

Trap-enable transmissions to the development port cause the appropriate bits of the

development port shift register to be transferred to the control register.

8.3.3 Development Port Clock Mode Selection

All of the d evelopment port serial tran smissions are clocked transmiss ions. The trans-

mission clock can be either synchronous or asynchronous with the system clock

(CLKOUT). The development port supports three methods for clocking the serial

trans missi ons. The first me tho d allows th e trans missi on to occ ur witho ut bein g exter -

nally synchronized with CLKOUT but at more restricted data rates. The two faster

commu nication meth ods require the clock an d data to be exter nally synchronize d with

CLKOUT.

The first clock mode is called

asynchronous clocked

since the input clock (DSCK) is

asynchronous with CLKOUT. The input synchronizers on the DSCK and DSDI pins

sample the inp uts to ensure tha t th e sig nals u s ed inte rn ally ha ve n o meta sta ble o scil-

lations. To be sure that data on DSDI is sampled correctly, transitions on DSDI must

occur a setup time ahe ad of the risi ng edge of DSCK. Data o n DSDI must a lso be he ld

for one CLK OUT cycle plus one hold time after t he rising ed ge of DSCK. Th is ensures

that after the signals have passed through the input synchronizers, the data will be

valid at the rising edge of the serial clock even if DSCK and DSDI do not meet the

setup and hold time requirements of the pins.

Asynchronous clocked mode allows communications with the port from a development

tool that does not have access to the CLKOUT signal or where the CLKOUT signal has

been de layed or s kewed. Beca use of th e asynchro nous natur e of the inputs and the

setup and hold time requirements on DSDI, this clock mode must be clocked at a fre-

quency less than or equal to one third of CLKOUT.

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-26 Rev. 15 June 98 USER’S MANUAL

The second clock mode is called

synchronous clocked

because the input clock and

input data meet all setup and hold time requirements with respect to CLKOUT. Since

the input synchronizers must sample the input clock in both the high and low state,

DSCK cannot be faster than one half of CLKOUT.

The third clock mode is called

synchronous self-clocked

because it does not require

an input clock. Instead, the port is clocked by the system clock. The DSDI input is

required to meet a ll setup and hold time requir ements with respect to CLKOUT. The

data rate for this mode is always the same as the system clock rate, which is at least

twice as fast as in synchronous clocked mode. In this mode, an undelayed CLKOUT

signal must be available to the development tool, and extra care must be taken to

avoid noise and crosstalk on the serial lines.

The selection of clocked or self-clocked mode is made immediately following reset.

The state of the DSDI input is la tched e ight clocks after RESE TOUT is negated. If it is

latched low, external clocked mode is enabled. If it is latched high, then self-clocked

mode is enabled. When external clocked mode is enabled, the use of asynchronous

or synchronous mode is determined by the design of the external development tool.

Since DSDI is used during reset to configure the MCU and to select the development

port clocking scheme, it is necessary to prevent any transitions on DSDI during this

time from being recognized as the start of a serial transmission. The port does not

begin scanning for the start bit of a serial transmission until 16 clocks after the negation

of RESETOUT. If DSDI is a sserted 1 6 clocks afte r RES ETOUT n ega ti on , th e po r t w ill

wait until DSDI is negated to begin scanning for the start bit.

The selection of clocked/self-clocked mode is shown in Figure 8-7. The timing dia-

grams in Figure 8-8, Figur e 8-9, and Figure 8-10 show the se rial communications for

both trap enable mode and debug mode for all clocking schemes.

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-27

Figure 8-7 Enabling Clock Mode Following Reset

Exampl es of seri al commun ication s using the thre e clock modes ar e shown i n Figure

8-8, Figure 8-9, and Figure 8-10.

DSDI

OUT

CLK

SRESET

DSDI PRIOR TO RESETOUT DETERMINES PART CONFIGURATION MODE.

DSDI NEGATES FOLLOWING RESETOUT NEGATION TO ENABLE CLOCKED MODE.

CLKEN

INTERNAL CLOCK ENABLE SIGNAL ASSERTS EIGHT CLOCKS AFTER RESETOUT NEGATION

RESET

BECAUSE DSDI IS NEGATED. THIS ENABLES CLOCKED MODE.

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-28 Rev. 15 June 98 USER’S MANUAL

Figure 8-8 Asynchronous Clocked Serial Communications

In Figure 8-8, the frequency on the DSCK pin is equal to CLKOUT frequency divided

by th ree. This is t he maximum fr equency al lowed for the asynchrono us clocked mode .

DSCK and DSDI transitions are not required to be synchronous with CLKOUT.

DSCK

DSDI

PLLL/

LENGTH CNTRL DI<0>

S<0> S<1> DO<0>

START

READY

OUT

CLK

DSDO

SYNC

DSCK

SYNC

LENGTH

CNTRL DI<0>START

DSDI

INT S/R

CLK

DEBUG PORT DRIVES “READY” BIT ONTO PLLL/DSDO WHEN READY FOR A NEW TRANSMISSION.

DEBUG PORT DETECTS THE “START” BIT ON DSDI AND FOLLOWS

THE “READY” BIT WITH TWO STATUS BITS AND N OUTPUT DATA BITS.

DEVELOPMENT TOOL DRIVES THE “START” BIT ON DSDI (AFTER DETECTING “READY” BIT ON

PLLL/DSDO WHEN IN DEB UG MODE). THE “START” BIT IS IMMEDIATELY FOLLOWED BY

A LENGTH BIT AND A CONTROL BIT AND THEN N (7 OR 32) INPUT DA TA BITS.

DI DI DI

DI DI DI

DO DO DO

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-29

Figure 8-9 Synchronous Clocked Serial Communications

In Figure 8-9, the frequency on the DSCK pin is equal to CLKOUT frequency divided

by two. DSDI and DSCK transitions must meet setup and hold timing requirements

with respect to CLKOUT.

DEBUG PORT DRIVES “READY” BIT ONTO PLLL/DSDO WHEN READY FOR A NEW TRANSMISSION.

DSCK

DSDI

PLLL/

LENGTH CNTRL DI<0>

S<0> S<1> DO<0>

START

READY

DI DI DI

DO DO DO

DEBUG PORT DETECTS THE “START” BIT ON DSDI AND FOLLOWS

THE “READY” BIT WITH TWO STATUS BITS AND N (7 OR 32) OUTPUT DATA BITS.

OUT

CLK

DO<1>

DSDO

SYNC

DSCK

SYNC LENGTH CNTRL DI<0>START DI DI DI

DSDI

DI<1>

INT S/R

CLK

DI<1>

DI <N><N-1><N-2>

<N-3>

<-3>

DEVELOPMENT TOOL DRIVES THE “START” BIT ON DSDI (AFTER DETECTING “READY” BIT ON

PLLL/DSDO WHEN IN DEBU G MODE). THE “START” BIT IS IMMEDIATELY FOLLOWED BY

A LENGTH BIT AND A CONTROL BIT AND THEN N (7 OR 32) INPUT DATA BITS.

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-30 Rev. 15 June 98 USER’S MANUAL

Figure 8-10 Synchronous Self-Clocked Serial Communications

In Figure 8-10, the DSCK pin is not used, and the transmission is clocked by

CLKOUT. DSDI transitions must meet setup and hold timing requirements with

respect to CLKOUT.

8.3.4 De velopment Port Transmissions

The development port starts communications by setting PLLL/DSDO (the

ready

bit, or

MSB of the 35-bit development port shift register) low to indicate that all activity related

to the previo us tr ansm issi on is co mpl et e a nd th at a ne w tr an smissi o n ma y b egi n . Th e

start of a serial transmission from an external development tool to the development

port is signa l ed by a

start

bit on the DSDI pin.

The start bit also signals the development port that it can begin driving data on the

DSDO pin . While da ta is shifti ng into the LSB of the shift re giste r from the D SDI pin, it

is simultaneously shifting out of the MSB of the shift register onto the DSDO pin.

length

bit defin es the transmission as bein g to either the tra p-enable register (length

bit = 1, indicating seven data bits) or the CPU (length bit = 0, indicating 32 data bits).

Transmissi o ns of data and i n stru cti on s to the C PU are al lo w ed on l y w he n the p ro ces-

sor is in debug mode. The two types of transmissions are discussed in 8.3.5 Trap-

Enable Input Transmissions and 8.3.6 CPU Input Transmissions.

8.3.5 Trap-Enable Input Transmissions

If the length bit is set, the input transmission will only be ten bits long. These trap-

enable transmissions into the development port include a start bit, a length bit, a con-

trol bit, and seven data bits. Only the seven data bits are shifted into the 35-bit shift

OUT

CLK 1234123412341234123412341234123423 14

DEVELOPMENT TOOL DRIVES THE “START” BIT ON DSDI (AFTER DETECTING “READY” BIT ON

DEBUG PORT DRIVES “READY” BIT ONTO PLLL/DSDO WHEN CPU READY FOR A NEW TRANSMISSION.

DSDI

PLLL/ S<0> S<1> DO<0>

READY DO DO DO

DEBUG PORT DETECTS THE “START” BIT ON DSDI AND FOLLOWS

THE “READY” BIT WITH TWO STATUS BITS AND N (7 OR 32) OUTPUT DATA BITS.

DSDO

SYNC LENGTHCNTRL DI<0>START DI DI DI

DSDI DI<1>

INT S/R

CLK

LENGTH CNTRL DI<0>START DI DI DI

DI<1> DI

DO<

1234 12341234123412341234231

<N-4>

DI<

PLLL/DSDO WHEN IN DEB UG MODE). THE “START” BIT IS IMMEDIATELY FOLLOWED BY

A LENGTH BIT AND A CONTROL BIT AND THEN N (7 OR 32) INPUT DATA BITS.

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-31

whether the data is latched into the trap enable and VSYNC bits of the TECR or into

the breakpoints bits of the TECR, as shown in Table 8-11 and Table 8-12.

8.3.6 CPU Input Transmissions

If the length bit in the serial input sequence is cleared, the transmission is an input to

the CPU. This transmissio n type is legal only when the processor is in de bu g mo de.

For transmissions to the CPU, the 35 bits of the development port shift register are

interpreted as a start bit, a length bit, a control bit, and 32 bits of instructions or data.

The encoding of data shifted into the development port shift register (through the DSDI

pin) is shown in Table 8-13.

The control bit differentiates between instructions and data and allows the develop-

ment p ort to dete ct that a n instr uction w as en tered w hen th e CPU was ex pecti ng dat a

and vice versa. If this occurs, a sequence error indication is shifted out in the next

serial transmission.

8.3.7 Serial Data Out of Development Port — Non-Debug Mode

The encoding of data shifted out of the development port shift register when the pro-

cessor is not in debug mode is shown in Table 8-14.

Table 8-11 Trap Enable Data Shifted Into Development Port Shift Register

Start Length Control

1st 2nd 3rd 4th 1st 2nd

VSYNC

UsageI-bus L-bus

Watchpoint Trap Enables

1 1 0 0 = disabled; 1 = enabled Input data for trap enable

control register

Table 8-12 Breakpoint Data Shifted Into Development Port Shift Register

Start Length Control Non-

Maskable Maskable Reserved bits Usage

Breakpoints

1 1 1 0 = negate; 1 = assert 11111 Input data for trap enable

control register

Table 8-13 CPU Instructions/Data Shifted into Shift Register

Start Length Control Instruction/Data (32 Bits) Usage

1 0 0 CPU Instruction In put instruction for t he CPU

1 0 1 CPU Data Input data for the CPU

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-32 Rev. 15 June 98 USER’S MANUAL

When the processor is not in debug mode, the sequencing error encoding indicates

that the transmission from the external development tool was a transmission to the

CPU (l en gt h = 0 ). Wh en a sequ encing er r or occu rs , th e d eve l opment port i g no re s the

data being shifted in while the sequencing error is shifting out.

The null output encoding is used to indicate that the previous transmission did not

have any associated errors.

When th e processor i s not in debug mode, the ready bi t is asserted at th e end of ea ch

transmission. If debug mode is not enabled and transmission errors can be guaran-

teed not to occur, the status output is not needed, and the DSDO pin can be used for

untimed I/O.

8.3.8 Serial Data Out of Development Port — Debug Mode

The encoding of data shifted out of the development port shift register when the pro-

cessor is in debug mode is shown in Table 8-14 .

8.3.8.1 Valid Data Output

The

valid data

encoding is used when data has been transferred from the CPU to the

development port shift register. This is the result of executing an instruction in debug

mode to move the contents of a general-purp ose register to the developmen t port data

The valid data encoding has the highest priority of all status outputs and is reported

even if an exce ptio n occur s at the sa me tim e. Any exception that i s re cogni zed du rin g

the transmission of valid data is not related to the execution of an instruction. There-

fore, a status of va lid data i s output a nd the CP U exceptio n status is saved for t he next

transmission. Since it is not possible for a sequencing error to occur and for valid data

Table 8-14 Status Shifted Out of Shift Register — Non-Debug Mode

Ready Status [0:1] Data (7 or 32 Bits1)

NOTES:

1. Depending on input mode.

Indication

(0) 0 1 Ones Sequencing Error

(0) 1 1 Ones Null

Table 8-15 Status/Data Shift e d Out of Shift Registe r

Ready Status [0:1] Data (7 or 32 Bits1)

NOTES:

1. Depending on input mode.

Indication

(0) 0 0 Data Valid Data from CPU

(0) 0 1 Ones Sequencing Error

(0) 1 0 Ones CPU Exception

(0) 1 1 Ones Null

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-33

to be received on the same transmission, there is no conflict between a valid data sta-

tus and the sequencing e rror status.

8.3.8.2 Sequ encing Error Output

The

sequencing error

encoding indicates that the inputs from the external develop-

ment tool are not what the development port or the CPU was expecting. Two cases

could cause this error: 1) the processor was trying to read instructions and data was

shift ed int o the d evelo pmen t port , or 2) the p roces sor wa s try ing to read data a nd an

instruction was shifted into the development port.

When a sequen cing error occurs, the port termina tes the CPU read or fetch cycle wit h

a bus error. This bus error causes the CPU to signal the development port that an

exception occurred. Since a stat us of sequencin g error has a higher priority than a sta-

tus of exception, the por t r e ports the seq uen ci ng er ror . The de vel o pm en t po rt i gno r es

the data being shifted in while the sequencing error is shifting out. The next transmis-

sion to the port should be a new instruction or trap enable data.

Table 8-16 illustrates a typical seque nce of events wh en a seq uencing error occurs.

This e xample begins with CP U data being shifted into t he shif t registe r (con trol bi t = 1)

when the processor is expecting an instruction. During the next transmission, a

sequencing error is shifted out of the development port, and the data shifted into the

shift register is thrown away. During the third transmission, the “CPU exception” status

is output, and again the data shifted into the shift register is thrown away. During the

fourth transmission, an instruction is again shifted into the development port and

fetched by the CPU for execution. Notice in this example that the development port

throws away the first two input transmissions following the one causing the sequencing

error.

8.3.8.3 CPU Exception Output

The

CPU e xception

encodi ng is used t o indi cate th at the CP U enco unter ed an excep-

tion during the execution of the previous instruction in debug mode. Exceptions may

occur as the result of instruction execution (such as unimplemented opcode or arith-

metic error), because of a memory access fault, or from an external interrupt. The

exception is recognized only if th e associated bit in the DER is set. When an exception

occurs, the development port ignores the data being shifted in while the CPU excep-

Table 8-16 Sequencing Error Activity

Trans # Input to

Development Port Output from

Development Port Port Action CPU Action

1CPU data

(Control bit = 1) Depends on

transmissions

Cause bus error, set

sequence error latch Fetch instruction, take

exception because of bus

error

2X (Thrown away) Sequencing error Set exception latch, clear

sequencing error latch Signal exception to port,

begin new fetch from port

3X (Th rown away ) CPU exception Clear exception latch Con tinue to wait for

instruction from port

4CPU instruction Null Send instruction to CPU at

end of transmission Fetch ins truction from port

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-34 Rev. 15 June 98 USER’S MANUAL

tion status is shifting out. The port terminates the current CPU access with a bus error.

The next transmissi on to the port s hould be a new ins truction or trap enable data.

8.3.8.4 Null Output

Finally, th e

null

encoding is used to indicate that no data has been transferred from the

CPU to the development port shift register. It also indicates that the previous transmis-

sion did not have any associated errors.

8.3.9 Use of the Ready Bit

To minimize the overhead required to detect and correct errors, the external develop-

ment system should wait for the ready bit on DSDO before beginning each input

transmission. This ensures that all CPU activity (if any) relative to the previous trans-

mission has been completed and that any errors have been reported.

When th e ready b it is used to pace th e transm issions, the er ror stat us is r epor ted du r-

ing the transmission following the error. Since any transmission into the port which

occurs while shifting out an error status is ignored by the port, the error handler in the

external development tool does not need to undo the effects of an intervening

instruction.

To improve system performance, however, an external development system may

begin tr ansmissio ns bef ore t he read y bit i s asser ted. I f the next tran smissio n does not

wait until the port indicates ready, the port will not assert ready again until this next

transmission completes and all activity associated with it has finished. Transmissions

that be gin before re ady is asserted on DSDI are subject to the fo llowing limita tions and

problems.

First, if the previous transmission results in a sequence error, or the CPU reports an

exception, that status may not be reported until two transmissions after the transmis-

sion that caused the error. (When the ready bit is used, the status is reported in the

follow ing transmission .) This is because an err or condit ion which occur s after the start

of a transmis sion cannot be reported until the next transm ission.

Second, if a transmitted instruction causes the CPU to write to the DPDR and the

trans mission that follo ws does not wait for the assertion of read y, the CPU dat a may

not be latched into the development port shift register, and the valid data status is not

output. Despite this, no error is indicated in the st atus outputs. To ensure that the CPU

has had enough time to write to the DPDR, there must be at least four CLKOUT cycles

between the time the last bit of the instruction (move to SPR) is clocked into the port

and the time the start bit for the next transmission is clocked into the port.

8.4 Debug Mode Functions

In debug mode, the CPU fetches all instructions from the development port. In addi-

tion, d ata ca n be read f r om and wri tt en to t he de vel op me nt p or t . This a llow s me mo ry

and r egisters to b e read a nd modified by an exter nal develop ment tool ( emulator) co n-

nected to the development port.

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-35

8.4.1 Enabling Debug Mode

Debug mode is enabled by asserting the DSCK pin during reset. The state of this pin

is sampled immediately before the negation of RESETOUT. If the DSCK pin is sam-

pled low, debug mode is disabled until a subsequent reset when the DSCK pin is

sampled high. When debug mode is disabled, the internal watchpoint/breakpoint hard-

ware is still operational and can be used by a software monitor program for debugging

purposes.

The DSCK pin is sampled again eight clock cycles following the negation of

RESETOUT. If DSCK is negated following reset, the processor jumps to the reset vec-

tor and begins normal execution. If DSCK is asserted following reset and debug mode

is enabled, the processor enters debug mode before executing any instructions.

A timing diagram for enabling debug mode is shown in Figure 8-11.

Figure 8-11 Enabling Debug Mode at Reset

8.4.2 Entering Debug Mode

Debug mode is entered whenever debug mode is enabled, an exception occurs, and

the corresponding bit is set in the debug enable register (DER). The processor per-

forms normal exception processing, i.e., saving the next instruction address and the

curre nt state of M SR in SRR0 and SRR 1 an d modi fying th e cont en ts of th e MS R. Th e

processo r then enters de bug mo de and fetches the next instructi on from the develo p-

ment port instead of from the vector address. The exception cause register (ECR)

shows which eve nt caused ent ry into debu g mode. The fre eze indicatio n is encoded

on the VFLS pins to show that the CPU is in debug mode.

DSCK

OUT

CLK

SRESET

DSCK ASSERTED PRIOR TO RESETOUT NEGATION ENABLES DEBUG MODE.

DEBUG MODE IS ENABLED IF DSCK IS HIGH IMMEDIATELY

DSCK IS NEGATED WITHIN EIGHT CLOCKS F OLLOWING RESETOUT NEGATION TO AVOID ENTRY INTO DEBUG MODE.

DM_EN

NMBKPT

INTERNAL BREAKPOINT SIGN AL DOES NOT ASSERT BECAUSE DSCK IS NEGATED LESS THAN EIGHT CLOCKS

RESET

AFTER RESETOUT NEGATION (THEREFORE CPU DOES NOT ENTER DEBU G MODE FOLLOWING RESET).

BEFORE RESETOUT NEGATES.

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-36 Rev. 15 June 98 USER’S MANUAL

Debug mode may also be entered immediately following reset. If the DSCK pin con-

tinues to be asserted following reset (after debug mode is enabled), the processor

takes a breakpoint exception and enters debug mode directly after fetching (but not

executing) the reset vector. To avoid entering debug mode following reset, the DSCK

pin must be negated no later than seven clock cycles after RESETOUT is negated.

A timing diagram fo r entering de bug mode foll owing reset is shown in Figure 8-12.

Figure 8-12 Entering Debug Mode Following Reset

8.4.3 Debug Mode Operation

In debug mode, the CPU fetches instructions from the development port. It can also

read and write data at the development port. In debug mode the prefetch mechanism

in th e CPU is di sabled . Thi s force s al l da ta acce sses to the de velopm ent p ort to o ccur

immediately following the fetch of the associated instruction.

In debug mode, if an exception occurs during the execution of an instruction, normal

exception processing does not result. (That is, the processor does not save the MSR

and in struction add ress and does no t branch to the exception handler.) Inst ead, a fla g

is set that results in a CPU exception status indication in the data shifted out of the

devel opment port shift reg ister. The same thing happen s if the pr ocessor de tects an

external interrupt. (This can occur only when the associated DER bit is clear and

MSR[EE] is set.) When the data in the development port shift register is shifted out,

DSCK

OUT

CLK

SRESET

DSCK ASSERTED PRIOR TO RESETOUT NEGATION ENABLES DEBUG MODE.

DEBUG MODE IS ENABLED IF DSCK IS ASSERTED

DSCK STAYS ASSERTED FOR AT LEAST EIGHT CLOCK CYCLES FOLLOWING RESETOUT NEGATION

DM_EN

NMBKPT

INTERNAL BREAKPOINT SIGN AL ASSERTS BECAUSE DSCK STAYS ASSERTED FOR AT LEAST

RESET

EIGHT CLOCK CYCLES AFTER RESETOUT NEGATION (THEREFORE CPU WILL ENTER DEBUG MODE

IMMEDIATELY BEFORE RESETOUT NEGATES.

VFLS

[0:1]

DEBUG MODE ENTRY IS INDICATED BY VFLS[0:1] BOTH HIGH

TO CAUSE ENTRY INTO DEBUG MODE.

FOLLOWING RESET).

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-37

the exception status is detected by the external development tool. The cause of the

exception can be determined by reading the ECR.

8.4.4 Freeze Function

While the processor is in debug mode, the freeze indication is broadcast throughout

the MC U. This si gnal is gen erate d by the CP U when d ebug m ode is ente red, o r when

a software debug monitor program is entered as the result of an exception and the

associated bit in the DER is set. The software monitor can only assert freeze when

debug mode is not enabled. Refer to 8.7 Software Monitor Support for more

information.

Freeze is indicated by the value 11 on the VFLS[0:1] pins. This encoding is not used

for pipeline tracking and is left on the VFLS[0:1] pins when the processor is in debug

mode. Figure 8-14 shows how the internal freeze signal is generated.

8.4.5 Exiting Debug Mode

Executing the rfi instruction in debug mode causes the processor to leave debug

mode and return to normal execution. The freeze indication on the VFLS pins is

negated to indicate that the CPU has exited debug mode.

Software must read the ECR (to clear it) before executing the rfi instruction. Other-

wise, if a bit in the ECR is asserted and its corresponding enable bit in the DER is also

asserted , the processor re -enters debug m ode and re-asse rts the freeze sign al imme-

diately after executing the rfi instruction.

8.4.6 Checkstop State and Debug Mode

When debug mode is disabled, the processor enters the checkstop state if, when a

machine check exception is detected, the machine check exception is disabled

(MSR[ME] = 0). However, when debug mode is e nabled, if a machine check exception

is detected when MSR[ME] = 0 and the checkstop enable bit in the DER is set, the

processo r enters d ebug mode rat her than th e che ckstop sta te. This a llows the u ser t o

determine why the checkstop state was entered. Table 8-17 shows what happens

when a machine check exception occurs under various conditions.

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8.5 Development Port Transmission Sequence

The following sections describe the sequence of events for communication with the

develo pment port i n both debug and normal mod e and provide speci fic sequen ces for

prologues, epilogues, and poking and peeking operations.

8.5.1 Port Usage in Debug Mode

The seque nce of e ven ts for co mmunic ation w ith the de velopm ent po rt in debu g mod e

(freeze is indicated on the VFLS pins) is shown in Table 8-18. The sequence starts

with the processor trying to read an instruction in step 1. Th e sequence ends when the

processor is ready to read the next instruction. Reading an instruction is the first actio n

the pr oce ssor ta kes a fte r e ntering deb ug m od e. Th e p r ocesso r an d d eve lo pm en t p or t

activity is determined by the instruction or data shifted into the shift register. The

instr uct ion or d ata s hif te d in t o the sh if t re gi s ter al so de term ine s t h e st atu s s h ifte d out

during the next transmission. The next step column indicates which step has the

appr opriate status response.

Table 8-17 Checkstop State and Debug Mode

MSR[ME] Debug

Mode

Enable CHSTPE1

NOTES:

1. Checkstop enable bit in the DER

MCIE2

2. Machine check interrupt enable bit in the DER

Action Performed

when CPU Detects a

Machine Check Interrupt ECR Value

0 0 X X Enter the checkstop state 0x2000 0000

0 1 0 X Enter the checkstop state 0x2000 0000

0 1 1 X Enter debug mode 0x2000 0000

1 0 X X Take machine check exception 0x1000 0000

1 1 X 0 Take machine check exception 0x1000 0000

1 1 X 1 Enter debug mode 0x1000 0000

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-39

Table 8-18 Debug Mode Development Port Usage

This

Step

Serial Data Shifted In

(DSDO Indicates

“READY”)

Shifted Out

This

Transmission

Development Port Activity;

Processor Ac tivity Next

Step

CPU instruction

(non-DPDR)

Null

Port transfers instruction to CPU;

CPU executes instruction, fetches next

instruction 1

CPU instruction (DPDR

read) Port transfers instruction to CPU;

CPU executes instruction, reads DPDR 2

CPU instruction (DPDR

write) Port transfers instruction to CPU;

CPU writes DPDR, fetches next instruction 3

CPU instruction

(instruction execution

causes exception)

Port transfers instruction to CPU;

CPU signals exception to port, fetches next

instruction 4

Data for CPU Port ignores data, terminates fetch with

error, latches sequence error;

CPU signals exception to port, fetches next

instruction

Data for Trap Enable

Control R egister Port updates trap enable control register;

CPU waits (continues fetch) 1

Any CPU instruction

Null

Port ignores data, terminates DPDR read

with error;

latches sequence error;

CPU signals exception to port, fetches next

instruction

Data for CPU Port transfers data to CPU;

CPU reads data from DPDR, fetches next

instruction 1

Data for trap enable

control register Port updates TECR

CPU waits (continue data read) 2

CPU instruction (non-

DPDR)

CPU data

Port transfers instruction to CPU;

CPU executes instruction, fetches next

instruction 1

CPU instruction (DPDR

read) Port transfers instruction to CPU;

CPU executes instruction, reads DPDR 2

CPU instruction (DPDR

write) Port transfers instruction to CPU;

CPU writes DPDR, fetches next instruction 3

CPU instruction (with

exception) Port transfers instruction to CPU;

CPU signals exception to port, fetches next

instruction 4

Data for CPU Port ignores data, terminates fetch with

error, latches sequence error;

CPU signals exception to port, fetches next

instruction

Data for trap enable

control register 7 MSB of CPU

data Port updates TECR;

CPU waits (continues fetch) 1

4Any (ignored by port) Exception Port ignores data;

CPU waits (continues fetch) 1

5Any (ignored by port) Sequence Error Port ignores data;

CPU waits (continues fetch) 4

MOTOROLA DEVELOPMENT SUPPORT MPC509

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8.5.2 Debug Mode Sequence Diagram

The sequence of activity shown in Table 8-18 is summarized below in Figure 8-13.

The numbers in the large circles correspond to the steps in Table 8-18. The letters in

the large circles indicate the status that will be shifted out during the transmission. The

letter s in t he sm al l circles sho w the activi ty of the de vel op m ent p or t and the C PU as a

result of the transmission.

Figure 8-13 General Port Usage Sequence Diagram

8.5.3 Port Usage in Normal (Non-Debug) Mode

The sequence of events for communication with the development port when the CPU

is not in debug mode (freeze is not indicated on the VFLS pins) is shown below in

Table 8-18. Note that any instructions or data for the CPU result in a sequence error

status response when the processor is not in debug mode. Only data for the trap

enable control register is allowed.

235

TRAP ENABLE CPU

CPU DATA

DPDR READ

DPDR WRITE

INSTRUCTION ANY INSTRUCTION

WITH EXCEPTION

CPU

INSTR

INSTRUCTION

CPU

DATA TRAP

ENABLE

NON DPDR

INSTRUCTION

CPU

INSTR CPU

DATA

INSTRUCTION

DATA

TRAP

ENABLE

DATA

N - SHIFT OUT NULL STATUS

I - TRANSFER INSTR TO CPU

R - TRANSF ER DATA TO CPU (READ)

E - TER M INATE CPU REA D WITH ERROR

T - TRANSFER DATA TO TECR

L - LATCH SEQUENCE ERROR

D - SHIFT OUT DATA FROM CPU

X - SHIFT OUT EXCEP TION STATUS

S - SHIFT OUT SEQUENCE ERROR STATUS

NDXS

TTR

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-41

8.6 Examples of Debug Mode Sequences

The tabl es that fo llow sh ow typica l sequence s of inst ructi ons tha t are use d in a deve l-

opmen t activity. They assume that no bus errors or sequence error s occur and that n o

writes occur to the trap enable control register.

8.6.1 Prologue Instruction Sequence

The prologue sequence of instructions is used to unload the machine context when

entering debug mode. The sequence starts by unloading two general-purpose regis-

ters (R0 and R1) to be used as a data transfer register and an address pointer. Since

SRR0 and SRR1 are not changed while in debug mode except by explicitly writing to

them, there is no need to save and restore these registers. Finally, the ECR is

unloaded to d etermine the ca use o f e ntry into debug mod e. Any regi sters that will be

used while in deb ug mode in addition to R0 and R1 will a lso need to be saved.

8.6.2 Epilogue Instruction Sequence

The epilogue sequence of instructions is used to restore the machine context when

leaving debug mode. It restores the two general-purpose registers and then issues the

rfi instruction. If additional regi sters were us ed whil e in debug mode, t hey also need

to be restored before the rfi instruction is executed.

Table 8-19 Non-Debug Mode Development Port Usage

This

Step Serial Da ta Shifted into DPDI

(Not in Debug Mode)

Shifted out of

DPDO this

Transmission Development Port Activity Next

Step

6Any CPU instruction or data Null Port ignores data and latches sequence error 7

Data for trap enable control

7 Any (ignored by port) Sequence Error Port ignores data 6

Table 8-20 Prologue Events

Development Port Activity Instruction Processor Activity Purpose

Shift in instruction mtspr DPDR, R0 Transfer R0 to DPDR Save R0 so the register can be

used

Shift out R0 data,

shift in instruction mfspr R0, ECR Transfer ECR to R0 Read the debug mode cause

Shift in instruction mtspr DPDR, R0 Transfer from R0 to DPDR Output reason for debug mode

entry

Shift out stop cause data,

shift in instruction mtspr DPDR, R1 Transfer R1 to DPDR Save R1 so the register can be

used

Shift out R1 data,

shift in instruction First instruction of next

sequence Execute next instruction Continue instruction

processing

MOTOROLA DEVELOPMENT SUPPORT MPC509

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8.6.3 Peek In struction Sequence

The peek sequen ce of i nstru ctions is us ed to r ead a memo ry lo cation a nd tr ansfer the

data to the development port . It starts by moving the memory address into R1 from the

development p ort. Next the location is re ad an d the data loa ded into R0. Finally, R0 is

transferred to the development port.

8.6.4 Poke Instruction Sequence

The poke sequence of instructions is used to write data entered at the development

serial port to a memory location. It starts by moving the memory address into R1 from

the development port. Next the data is moved into R0 from the development port.

Finally, R0 is written to the address in R1.

8.7 Software Monitor Support

When debug mode is disabled, a software monitor debugger can make use of all of

the processor’s development support features. With debug mode disabled, all events

result in regular exception handling, i.e., the processor resumes execution in the

Table 8-21 Epilogue Events

Development Port Activity Instruction Processor Activity Purpose

Shift in instruction,

shift in saved R0 mfspr R0, DPDR Transfer from DPDR to R0 Resto res value of R0 when

stopped

Shift in instruction,

shift in saved R1 mfspr R1, DPDR Transfer from DPDR to R1 Resto res value of R1 when

stopped

Shift in instruction rfi Return from exception Restart execution

Table 8-22 Peek Instruction Sequence

Development Port Activity Instruction Processor Activity Purpose

Shift in instruction mfspr R1, DPDR Transfer address from

DPDR to R1 Point to memory address

Shift in instruction lwzu R0, D(R1) Load data from memory

address (R1) into R0 Read data from memory

Shift in instruction mtspr DPDR, R0 Transfer data from R0 to

DPDR Write memory data to the port

Shift in instruction,

shift out memory data First instruction of next

sequence Execute next instruction Output memory data

Table 8-23 Poke Instruction Sequence

Development Port Activity Instruction Processor Activity Purpose

Shift in instruction mfspr R1, DPDR Transfer address from

DPDR to R1 Point to memory address

Shift in instruction,

shift in memory data mfspr R0, DPDR Transfer data from DPDR

to R0 Read memory data from the

port

Shift in instruction stwu R0, D(R1) Store data from R0 to

memory address (R1) Write data to memory

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-43

appropriate exception handler. The ECR and the DER only influence the assertion and

negation of the freeze indication.

The internal freeze signal is connected to all relevant internal modules. These modules

can be programmed to stop all operations in response to the assertion of the freeze

signal. In order to enable a software monitor debugger to broadcast the fact that the

debug software is now executing, it is possible to assert and negate the internal freeze

signal when debug mode is disabled. (The freeze signal can be asserted externally

only when the processor enters debug mode.)

The internal freeze signal is asserted whenever an enabled event occurs, regardless

of whether debug mode is enabled or disabled. To enable an event to cause freeze

assertion , software needs to set the relevant bit in the DER. To cle ar the freeze si gnal,

software needs to read the ECR to clear the register and then perform an rfi

instruction.

If the ECR is not cleared before the rfi instruction is executed, freeze is not negated.

It is therefore p ossible to nest inside a software monitor debugger without affecting the

value of the freeze signal, even though rfi is pe rforme d. Only be fore the last rfi does

the software need to clear the ECR.

Figure 8-14 shows how the ECR and DER control the assertion and negation of the

freeze signal and the internal debug mode signal.

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-44 Rev. 15 June 98 USER’S MANUAL

Figure 8-14 Debug Mode Logic

8.8 Development Support Registers

Table 8-24 lists the registers used for development support. The registers are

accessed with the mtspr and mfspr instructions.

DECODER

EXCEPTION CAUSE REGISTER (ECR)

DEBUG ENABLE REGISTER (DER)

EVENT

RESET

EVEN T VALI D

SET

RFI

FREEZE

DEBUG MODE ENABLE INTERNAL DEBUG

MODE SIGNAL

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-45

8.8.1 Register Protection

Table 8-25 and Table 8-26 summarize protection features of development support

registers during read and write accesses, respectively.

Table 8-24 Development Support Programming Model

SPR Number

(Decimal) Mnemonic Name

144 CMPA Comparator A Value Register

145 CMPB Comparator B Value Register

146 CMPC Comp arat or C Value Register

147 CMPD Comp arat or D Value Register

148 ECR Exception Cause Register

149 DER Debug Enable Register

150 COUNTA Breakpoint Counter A Value and Control Register

151 COUNTB Breakpoint Counter B Value and Control Register

152 CMPE Comparator E Value Register

153 CMPF Comparator F Value Register

154 CMPG Comparator G Value Register

155 CMPH Comp arat or H Value Register

156 LCTRL1 L-Bus Support Control Register 1

157 LCTRL2 L-Bus Support Control Register 2

158 ICTRL I-Bus Support Control Regis ter

159 BAR Breakpoint Address Register

630 DPDR Deve lop ment Port Data Register

Table 8-25 Development Support Registers Read Access Protection

MSR[PR] Debug Mo de

Enable In Debug

Mode Result

00X

Read is perfor med.

ECR is cleared when read.

Reading DPDR yields indeterminate data.

010

Read is perfor med.

ECR is

not

cleared when r ead.

Reading DPDR yields indeterminate data.

011

Read is perfor med.

ECR is cleared when read.

1XX

Program exception is generated.

Read is not performed.

ECR is

not

cleared when r ead.

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-46 Rev. 15 June 98 USER’S MANUAL

8.8.2 Comparator A–D Va lue Registers (CMPA– CMPD)

The reset state of these registers is undefined.

8.8.3 Comparator E–F Value Registers

Table 8-26 Development Support Registers Write Access Protection

MSR[PR] Debug Mode

Enable In Debug

Mode Result

00X

Write is performed.

Write to ECR is ignored.

Writing to DPDR is ignored.

010

Write is

not

performed.

Writing to DPDR is ignored.

011

Write is performed.

Write to ECR is ignored.

1XX

Write is

not

performed.

Program exception is generated.

CMPA–CMPD — Comparator A–D Value Register SPR 144 – SP R 147

012345678910 11 12 13 14 15

CMPAD

RESET: UNDEFINED

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

CMPAD RESERVED

RESET: UNDEFINED

Table 8-27 CMPA–CMPD Bit Settings

Bits Mnemonic Description

0:29 CMPAD Address bits to be compared

30:31 — Reserved

CMPE–CMPF — Comparator E–F Value Registers SPR 152, 153

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

CMPEF

RESET: UNDEFINED

Table 8-28 CMPE–CMPF Bit Settings

Bits Mnemonic Description

0:31 CMPV Address bits to be compared

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-47

The reset state of these registers is undefined.

8.8.4 Comparator G–H Value Registers (CMPG–CMPH)

The reset state of these registers is undefined.

8.8.5 I-Bus Support Control Register

CMPG–CMPH — Comparator G–H Va lue Regi ste rs SPR 154, 155

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

CMPGH

RESET: UNDEFINED

Table 8-29 CMPG–CMPH Bit Settings

Bits Mnemonic Description

0:31 CMPGH Data bits to be compared

ICTRL — I-Bus Supp ort Control Register SPR 158

012345678910 11 12 13 14 15

CTA CTB CTC CTD IW0 IW1

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

IW2 IW3 SIW0

EN SIW1

EN SIW2

EN SIW3

EN DIW0

EN DIW1

EN DIW2

EN DIW3

EN IIFM ISCT_SER

RESET:

0000000000000000

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-48 Rev. 15 June 98 USER’S MANUAL

Table 8-30 ICTRL Bit Settings

Bits Mnemonic Description Function

0:2 CTA Compare type of comparator A 0xx - not activ e (reset value)

100 - equal

101 - less than

110 - greater than

111 - not equal

3:5 CTB Compare type of comparator B

6:8 CTC Compare type of comparator C

9:11 CTD Compare type of comparator D

12:13 IW0 I-bus 1st watchpoint programming 0x - not active (reset value)

10 - match from comparator A

11 - match from comparators (A&B)

14:15 W1 I-bus 2nd watchpoint programming 0x - not active (reset value)

10 - match from comparator B

11 - match from comparators (A | B)

16:17 IW2 I-bus 3rd watchpoint programming 0x - not active (reset value)

10 - match from comparator C

11 - match from comparators (C&D)

18:19 IW3 I-bus 4th watchpoint programming 0x - not active (reset value)

10 - match from comparator D

11 - match from comparators (C | D)

20 SIW0EN Software trap enable selection of

the 1st I-bus watchpoint

0 - trap disabled (reset value)

1 - tr ap enabled

21 SIW1EN Software trap enable selection of

the 2nd I-bus watchpoint

22 SIW2EN Software trap enable selection of

the 3rd I-bus watchpoint

23 SIW3EN Software trap enable selection of

the 4th I-bus watchpoint

24 DIW0EN Development port trap enable

selection of the 1st I-bus watchpoint

(read only bit)

0 - trap disabled (reset value)

1 - tr ap enabled

25 DIW1EN Development port trap enable

selection of the 2nd I-bus

watchpoint (read onl y bit)

26 DIW2EN Development port trap enable

selection of the 3rd I-bus watchpoint

(read only bit)

27 DIW3EN Development port trap enable

selection of the 4th I-bus watchpoint

(read only bit)

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-49

The ICTRL is cle ared followin g reset. Note that the machine is fetch serialized when-

ever SER = 0b0 or ISCTL = 0b00.

8.8.6 L-Bus Support Control Register 1

28 IIFM Ignore first match, only for I-bus

breakpoints 0 - Do not igno re first match, used for “go to x” (re-

set v alue)

1 - Ignore first match (used for “continue”)

29:31 ISCT_SER Instruction fetch show cycle and

RCPU serialize control

000 - RCPU is fully serialized and show cycle will

be performed for all fetched instructions

(reset value).

001 - RCPU is fully serialized and show cycle will

be performed for all changes in the program

flow

010 - RCPU is fully serialized and show cycle will

be perform ed for al l indi rect ch anges in the

program flow

011 - RCPU is full y serialized and no show cy cles

will be pe rfo rmed for fetched instructions

100 - Ille gal

101 - RCPU is not se rial ized ( normal mode) and

show cycle will be performed for all

changes in the program flow

110 - RCPU is not se rial ized ( normal mode) and

show cy cle will be perfo rmed for all indi rect

changes in the program flow

111 - RCPU is not se rial ized ( normal mode) and

no show cycles will be performed for

fetched ins t ruc ti ons

LCTRL1 — L-Bus Support Control Register 1 SPR 156

012345678910 11 12 13 14 15

CTE CTF CTG CTH CRWE CRWF

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

CSG CSH SUSG SUSH CGBMSK CHBMSK UNUSED

RESET:

0000000000000000

Table 8-30 ICTRL Bit Settings (Continued)

Bits Mnemonic Description Function

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-50 Rev. 15 June 98 USER’S MANUAL

LCTRL1 is cleare d following res et.

8.8.7 L-Bus Support Control Register 2

Table 8-31 LCTRL1 Bit Settings

Bits Mnemonic Description Function

0:2 CTE Compare type, comparator E 0xx - not active (reset value)

100 - equal

101 - less than

110 - greater than

111 - not equal

3:5 CTF Compare type, comparator F

6:8 CTG Compare type, comparator G

9:11 CTH Compare type, comparator H

12:13 CRWE Select match on read/write of

comparator E 0X - don’t care (reset value)

10 - match on read

11 - match on write

14:15 CRWF Select match on read/write of

comparator F

16:17 CSG Compare size, comparator G 00 - reserved

01 - word

10 - half word

11 - byte

(Must be programmed to word for floating point

compares)

18:19 CSH

Compare size, comparator H

20 SUSG Signed/unsigned operating mode

for comparator G 0 - unsigned

1 - signed

(Must be programmed to signed for floating

point compares)

21 SUSH Signed/unsigned operating mode

for comparator H

22:25 CGBMSK Byte mask for 1st L-data

comparator 0000 - all bytes are not masked

0001 - the last byte of the word is masked

1111 - all bytes are masked

26:29 CHBMSK Byte mask for 2nd L-data

comparator

30:31 — Reserved —

LCTRL2 — L-Bus Support Control Register 2 SPR 157

012345678910 11 12 13 14 15

LW0E

NLW0IA LW0

IADC LW0LA LW0

LADC LW0LD LW0

LDDC LW1E

NLW1IA LW1

IADC LW1LA

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

LW1

LADC LW1LD LW1

LDDC

BRK

NOM-

SK RESERVED DLW0

EN DLW1

EN SLW0

EN SLW1

RESET:

0000000000000000

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-51

Table 8-32 LCTRL2 Bit Settings

Bits Mnemonic Description Function

0LW0EN

1st L-bus watchpoint enable bit 0 - watchpoint not enabled (reset value)

1 - watchpoint enabled

1:2 LW0IA 1st L-bus watchpoint I-addr

watchpoint selection 00 - first I-bus watchpoint

01 - second I-bus w atchpoint

10 - third I-bus watch point

11 - fourth I-bus watchpoint

3LW0IADC

1st L-bus watchpoint

care/don’t care I-addr events 0 - don’t care

1 - care

4:5 LW0LA 1st L-bus watchpoint

L-addr events selection 00 - match from comparator E

01 - match from comparator F

10 - match from comparators (E&F)

11 - match from comparators (E | F)

6 LW0LADC 1st L-bus watchpoint

care/don’t care L-addr events 0 - don’t care

1 - care

7:8 LW0LD 1st L-bus watchpoint

L-data events selection 00 - match from comparator G

01 - match from comparator H

10 - match from comparators (G&H)

11 - match from comparators (G | H)

9 LW0LDDC 1st L-bus wat chpoint

care/don’t care L-data events 0 - don’t care

1 - care

10 LW1EN 2nd L-bus watchpoint enable bit 0 - watchpoint not enabled (reset value)

1 - watchpoint enabled

11:12 LW1IA 2nd L-bus watchpoint I-addr

watchpoint selection 00 - first I-bus watchpoint

01 - second I-bus w atchpoint

10 - third I-bus watch point

11 - fourth I-bus watchpoint

13 LW1IADC 2nd L-bus watchpoint

care/don’t care I-addr events 0 - don’t care

1 - care

14:15 LW1LA 2nd L-bus watchpoint

L-addr events selection 00 - match from comparator E

01 - match from comparator F

10 - match from comparators (E&F)

11 - match from comparators (E | F)

16 LW1LADC 2nd L-bus watchpoint

care/don’t care L-addr events 0 - don’t care

1 - care

17:18 LW1LD 2nd L-bus watchpoint

L-data events selection 00 - match from comparator G

01 - match from comparator H

10 - match from comparators (G&H)

11 - match from comparator (G | H)

19 LW1LDDC 2nd L-bus watchpoint

care/don’t care L-data events 0 - don’t care

1 - care

20 BRKNOMSK Internal breakpoints non-mask

bit 0 - masked mode; breakpoints are recognized only

when MSR[RI] = 1 (reset value)

1 - non-masked mode; brea kpoints are always rec-

ognized

21:27 — Reserved —

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-52 Rev. 15 June 98 USER’S MANUAL

LCTRL2 is cleare d following res et.

For each watchpoint, three control register fields (LWxIA, LWxLA, LWxLD) must be

programmed. For a watch point to be asse rted, all three con ditions must be detected.

8.8.8 Breakpoint Counter A Value and Control Register

COUNTA[16:31] are cleared following reset; COUNTA[0:15] are undefined.

28 DLW0EN Development port trap enable

selection of the 1st L-bus

watchpoint (read only bit)

0 - trap disabled (reset value)

1 - tr ap enabled

29 DLW1EN Development port trap enable

selection of the 2nd L-bus

watchpoint (read only bit)

30 SLW0EN Software trap enable selection

of the 1st L-bus watchpoint

31 SLW1EN Software trap enable selection

of the 2nd L-bus watchpoint

COUNTA — Breakpoint Counter A Value and Control Register SPR 150

012345678910 11 12 13 14 15

CNTV

RESET: UNDEFINED

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED CNTC

RESET:

0000000000000000

Table 8-33 Breakpoint Counter A Value and Control Register (COUNTA)

Bit(s) Name Description

0:15 CNTV Counter pr eset value

16:29 — Reserved

30:31 CNTC

Counter source select

00 - not active (reset value)

01 - I-bus first watchpoint

10 - L-bus first watchpoint

11 - Reserved

Table 8-32 LCTRL2 Bit Settings (Continued)

Bits Mnemonic Description Function

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-53

8.8.9 Breakpoint Counter B Value and Control Register

COUNTB[16:31] are cleared following reset; COUNTB[0:15] are undefined.

8.8.10 Exception Cause Register (ECR)

The ECR indicates the cause of entry into debug mode. All bits are set by the hardware

and cleared when the register is read when debug mode is disabled, or if the processor

is in debug mode. Attempts to write to this register are ignored. When the hardware

sets a bit in this register, debug mode is entered only if debug mode is enabled and

the corresponding mask bit in the DER is set.

All bits are cleared to zero following reset.

COUNTB — Breakpoint Counter B Value and Control Register SPR 151

012345678910 11 12 13 14 15

CNTV

RESET: UNDEFINED

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RESERVED CNTC

RESET:

0000000000000000

Table 8-34 Breakpoint Counter B Value and Control Register (COUNTB)

Bit(s) Name Description

0:15 CNTV Counter pr eset value

16:29 — Reserved

30:31 CNTC

Counter source select

00 - not active (reset value)

01 - I-bus second watchpoint

10 - L-bus second watchpoint

11 - Reserved

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-54 Rev. 15 June 98 USER’S MANUAL

ECR — Exception Cause Register SPR 148

012345678910 11 12 13 14 15

RESERVED CHST

PMCE DSE ISE EXTI ALE PRE FPUV

EDECE RESERVED SYSE TR FPAS

RESET:

0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0SEE RESERVED LBRK IBRK EBRK

DDPI

RESET:

0000000000000000

Table 8-35 ECR Bit Settings

Bit(s) Name Description

0:1 — Reserved

2 CHSTP Checkstop bit. Set when the processor enters checkstop state.

3MCE

Machine check interrupt bit. Set when a machine check exception (other than one caused by a

data stor age or ins truction storage error) is asserted.

4DSE

Data st orage exception bit. Set when a mac hine check excep tion caused b y a data storage erro r

is assert ed.

5ISE

Inst ruction sto rage excep tion bit. Set w hen a machi ne check exce ption caus ed by an inst ruction

storage error is asserted.

6 EXTI External interrupt bit. Set when the external interrupt is asserted.

7 ALE Alignment exception bit. Set when the alignment exception is asserted.

8 PRE Program exception bit. Set when the program exception is asserted.

9 FPUVE Floati ng point unavailable exception bit. Set when the program exception is asserted.

10 DECE Decrementer exception bit. Set when the decrementer exception is asserted.

11:12 — Reserved

13 SYSE System call exception bit. Set when the system call exception is asserted.

14 TR Trace exception bit. Set when in single-step mode or when in branch trace mode.

15 FPASE Floating point assist exception bit. Set when the floating-point assist exception is asserted.

16 — Reserved

17 SEE Software emulation exception. Set when the software emulation exception is asserted.

18:27 Reserved

28 LBRK L-bus breakpoint exception bit. Set when an L-bus breakpoint is asserted.

29 IBRK I-bus breakpoint exception bit. Set when an I-bus breakpoint is asserted.

30 EBRK External breakpoint exception bit. Set when an external breakpoint is asserted (by an on-chip

IMB or L-bus module, or by an external device or development system through the development

port).

31 DPI Development port interrupt bit. Set by the development port as a result of a debug station non-

maskable request or when debug mode is entered immediately out of reset.

MPC509 DEVELOPMENT SUPPORT MOTOROLA

USER’S MANUAL Rev. 15 June 98 8-55

8.8.11 Debug Enable Register (DER)

This register enables the user to selectively mask the events that may cause the pro-

cessor to enter into debug mode.

DER — Debug Enable Register SPR 149

012345678910 11 12 13 14 15

RESERVED CH

STPE MCEE DSEE ISEE EXTIE ALEE PREE FPU-

VEE DE-

CEE RESERVED SY-

SEE TRE FPA-

SEE

RESET:

0010000000000010

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0SEEE RESERVED LBRK

EIBRKE EBRK

EDPIE

RESET:

0000000000001111

Table 8-36 DER Bit Settings

Bit(s) Name Description

0:1 — Reserved

2CHSTPE

Checkstop enable bit

0 = Debug mode entry disabled

1 = Debug mode entry enabled (reset value)

3MCEE

Machine check exception enable bit

0 = Debug mode entry disabled (reset value)

1 = Debug mode entry enabled

4 DSEE Data storage exception (type of machine check exception) enable bit

0 = Debug mode entry disabled (reset value)

1 = Debug mode entry enabled

5 ISEE Instruction storage exception (type of machine check exception) enable bit

0 = Debug mode entry disabled (reset value)

1 = Debug mode entry enabled

6 EXTIE External interrupt enable bit

0 = Debug mode entry disabled (reset value)

1 = Debug mode entry enabled

7ALEE

Alig nm ent ex cep tio n enab le bit

0 = Debug mode entry disabled (reset value)

1 = Debug mode entry enabled

8PREE

Program exception enable bit

0 = Debug mode entry disabled (reset value)

1 = Debug mode entry enabled

9 FPUVEE Floating point unavailable exception enable bit

0 = Debug mode entry disabled (reset value)

1 = Debug mode entry enabled

10 DECEE Decrement er except ion enable bit

0 = Debug mode entry disabled (reset value)

1 = Debug mode entry enabled

11:12 — Reserved

MOTOROLA DEVELOPMENT SUPPORT MPC509

8-56 Rev. 15 June 98 USER’S MANUAL

13 SYSEE System call exception enable bit

0 = Debug mode entry disabled (reset value)

1 = Debug mode entry enabled

14 TRE Trace exception enable bit

0 = Debug mode entry disabled

1 = Debug mode entry enabled (reset value)

15 FPASEE Floating point assist exception enable bit

0 = Debug mode entry disabled (reset value)

1 = Debug mode entry enabled

16 — Reserved

17 SEEE Software emulation exception enable bit

0 = Debug mode entry disabled (reset value)

1 = Debug mode entry enabled

18:27 — Reserved

28 LBRKE L-bus breakpoint exception enable bit

0 = Debug mode entry disabled

1 = Debug mode entry enabled (reset value)

29 IBRKE I-bus breakpoint exception enable bit

0 = Debug mode entry disabled

1 = Debug mode entry enabled (reset value)

30 EBRKE External breakpoint exception enable bit

0 = Debug mode entry disabled

1 = Debug mode entry enabled (reset value)

31 DPIE Development port interrupt e nable bit

0 = Debug mode entry disabled

1 = Debug mode entry enabled (reset value)

Table 8-36 DER Bit Settings (Continued)

Bit(s) Name Description

MPC509 IEEE 1149.1-COMPLIANT INTERFACE MOTOROLA

USER’S MANUAL Rev. 15 June 98 9-1

SECTION 9

IEEE 1149.1-COMPLIANT INTERFACE

The MPC509 includes dedicated user-accessible test logic that is fully compatible with

the

IEEE 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture

Problem s a ssoci a ted w i th testi n g h i gh-d ensi ty circu it b oar d s ha ve le d to develo pm en t

of this standard under the sponsorship of the Test Technology Committee of IEEE and

the Joint Test Action Group (JTAG). The MPC509 supports circuit-board test strate-

gies based on this standard.

This section is intended to be used with the supporting IEEE 1149.1-1990 standard.

The scope of this description includes those items required by the standard to be de-

fined and, in cer tain cases, provid es additional information specific to the implemen ta-

tion. For internal details and applications of the standard, refer to the IEEE 1149.1-

1990 docu ment.

An overview of the JTAG pins on the MPC509 is shown in Figure 9-1.

Figure 9-1 JTAG P ins

Boun dary scan cells (BSC ) are placed at the digital bound ary of the chip (n ormally the

package pins). The boundary scan cells are chaine d together to form a boundary scan

shifted out through the output port (TDO).

9.1 JTAG Interface Bloc k Diagram

A block d i agra m o f th e M PC 5 09 im pl e me nta tion of the IEE E 11 49 .1- 19 90 test lo gi c i s

shown in Figure 9-2.

T A P

TDO

TRST

TMS

TCK

TDI

BSC

MPC509

BSCBSCBSCBSC

BSC

BSC BSC BSC BSC

MOTOROLA IEEE 1149.1-COMPLIANT INTERFACE MPC509

9-2 Rev. 15 June 98 USER’S MANUAL

Figure 9-2 Test Logic Block Diagram

9.2 JTAG Signal Descriptions

The MPC509 has five dedicated JTAG pins, which are described in Table 9-1. The TDI

and TDO scan ports are us ed to scan instructions as well as dat a into the vario us scan

registers f or JTAG opera tions. The scan operation is controll ed by the test access port

(TAP) controller, which in turn is con trolled by the TMS input sequence.

Table 9-1 JTAG Interface Pin Descriptions

Signal Name Input/Output Internal Pull-Up/

Pulldown Provided Description

TDI Input Pull-up Test data input pin. Sampled on the rising edge of TCK.

Has pull-up resistor.

TDO Output None Test data ou tput pin. Actively dri ven during the shift -IR and

shift-DR controller states. Changes on the falling edge of

TCK. Can be placed in high-impedance state.

TMS Input Pull-up Test mode select pin. Sampled on the rising edge of TCK

to sequen ce the te st contr oll er’s sta te machin e. Has a pull-

up resistor.

TCK Input Pulldown Test clock input to synchronize the test logic. Has a pull-

down resistor.

TRST Input Pull-up TAP controller asynchronous reset. Provides initialization

of the TAP controller and other logic as required by the

standard. Has a pull-up resistor.

DEVICE ID

BOUNDARY SCAN

BYPASS

INSTRUCTION

TAP

CONTROLLER

TEST DATA REGISTERS

IR DECODER

MODE

RESET

RESET*

UPDATE-IR

UPDATE-DR

CLOCK-IR

CLOCK-DR

SHIFT-IR

SHIFT-DR

TDRSEL(2)

TMS

TCK

TRST

TDI

DQTDO

SELECT

ENABLE

TCK

I3I2I1I0

MPC509 IEEE 1149.1-COMPLIANT INTERFACE MOTOROLA

USER’S MANUAL Rev. 15 June 98 9-3

9.3 Operating Frequency

The TCK fre quenc y must be be tween 5 MH z and 10 MHz. This pin i s intern all y driven

to a low value when disconnected.

9.4 TAP Controller

TRST is used to reset th e TAP con troller asynchrono usly. Th e TRST pin ensures that

the JTAG logic does not interfere with the normal operation of the chip. This pin is op-

tional in the JTAG specification.

The TAP controller changes state either on the rising edge of TCK or when TRST is

asserted.

The TDO sign al remains in a h igh-impedance sta te except during t he shift-DR or shift-

IR cont roller stat es. Duri ng these con troller sta tes, TDO i s updated on the fal ling edg e

of TCK.

The TAP controller states are designed as specified in the IEEE 1149.1 standard.

9.5 Instruction Register

The MP C509 imp lem entation of the IEEE 11 49.1 inte rf ace i ncl u des the thre e m and a-

tory public instructions (BYPASS, SAMPLE/PRELOAD, and EXTEST) and five public

instructions (CLAMP, HIGHZ, EXTEST_PULLUP, TMSCAN, and IDCODE). The

MPC509 contains a four-bit instruct ion register without parit y consisting of a shift reg-

ister w ith four para llel output s. Data is tr ansfer red for m the shift regi ster to the p arall el

outputs during update-IR controller state. The four bits are used to decode eight

unique instruc tions as shown in Table 9-2.

The parallel output of the instruction register is reset to 1101 in the Test-Logic-Reset

controller state. Note that this preset state is equivalent to the IDCODE instruction. In

the Capture-IR state, 1101 is loaded into the instruction shift register stage. New in-

structions can be shifted into the instruction shift register stage on Shift-IR state.

Table 9-2 Instruction Register Encoding

Code Instruction

B3 B2 B1 B0

1 1 1 1 BYPASS

1 1 1 0 SAMPLE/PRELOAD

1 1 0 1 IDCODE

1100 TMSCAN

10xx Reserved

01xx Reserved

0011 CLAMP

0010 HIGHZ

0 0 0 1 EXTEST_PULLUP

0 0 0 0 EXTEST

MOTOROLA IEEE 1149.1-COMPLIANT INTERFACE MPC509

9-4 Rev. 15 June 98 USER’S MANUAL

9.5. 1 EXTEST (0 000)

The external test (EXTEST) instruction enables the boundary scan register between

TDI and TDO, including cells for all device signal and clock pins and associated control

signals. The XTA L, EXTA L, XFC_S , X FC_C a nd XFC _I p ins ar e assoc iated with ana-

log signals and are not included in the boundary scan register.

EXTEST also asserts internal reset for the MPC509 system logic for the duration of

EXTEST in order t o force a predictabl e intern al state whi le perfo rming ex ternal boun d-

ary scan operations.

By using the TAP, the boundary scan register is capable of:

• Scanning user-defined values into the output buffer;

• Capturing values presented to input signals; and

• Controlling the direction and value of bi-directional pins.

Figure 9-3 Sample EXTEST Connection

The follow ing steps show an example of how the EXTES T instructi on is initia lized and

invoked for board interconnection test.

1. Shift in the PRELOAD instruction in chip 1.

2. Shift in data to the boundary scan cells of chip 1 through the TDI (preload).

3. Shift the EXTEST instruction into chip 1. As soon as the Update-IR state is

reached, the data in the boundary scan cells of chip 1 will be driven immediately

from chip 1 into its external connections.

4. Shift the S AMPLE instru ction into c hip 2 to ca ptu re the lo gic level on the in put

pins including those driven by the EXTEST instruction of chip 1. Then shift the

boundary scan register out to TDO for discrepancy checking.

EXTEST_PULLU P asserts internal reset for t he MPC509 system logic f or the duration

of the instruction. This forces a predictabl e internal state while external boundary scan

oper ations are pe r formed.

9.5.2 BYPASS (1111)

The BYPASS instruction enables the single-bit BYPASS register between TDI and

TDO as shown in Figure 9-4. This cre ates a shift-register pa th from TDI to the bypass

instruction is used to enhance test efficiency by shortening the overall path between

TDI TDO TDI TDO

EXTEST INSTR.

SAMPL E IN STR.

CHIP 1 CHIP 2 O

MPC509 IEEE 1149.1-COMPLIANT INTERFACE MOTOROLA

USER’S MANUAL Rev. 15 June 98 9-5

TDI and TDO when no test operation of a component is required. In this instruction,

the MPC509 system logic is independent o f the test access port. When th is instruction

is selected, the test logic shall have no effect on the operation of the on-chip system

logic as required in the IEEE 1149.1-1990 specification.

Figur e 9-4 Bypass Register

9.5.3 SAMPLE/PRELOAD (1110)

The SAMPLE /PRELOAD instr uction enables the boun dary scan register be tween TDI

and TDO as t est data regis ter. When t his instructio n is selected , the ope ration of the

test logic shall have no effect on the operation of the on-chip system logic or on the

flow of signal between the system pin and the on-chip system logic as required in the

1149. 1 s pecification.

This in struction provid es two se para te funct ions. Fir st, it pro vid es a me ans to ob tain a

snapshot of system data and control signals (SAMPLE). The snapshot occurs on the

rising edge of TCK in the Capture-DR controller state. The data can be observed by

shifting it transparently through the boundary scan register. In a normal system con-

figuration many signals require external pull-ups to ensure proper system operation.

Consequently, the same is true for the SAMPLE/PRELOAD functionality. The data

latched into the boundary scan register during the Capture-DR state may not match

the drive state of the package signal if the system-required pull-ups are not present

within the tes t envi ronment.

The second function of the SAMPLE/PRELOAD instru ction is to initialize the boundary

scan register output cells (PRELOAD) prior to selection of CLAMP, EXTEST or

EXTEST_PULLUP. This initializati on ensures that known data will appear on the out-

puts when executing the EXTEST instruction. The data held in the shift register stage

is tra nsfer red to the outp ut stag e on the f alli ng ed ge of TCK in th e Upda te-D R contr ol-

ler state.

NOTE

Since ther e is no inte rnal s ynch roni zati on be twee n the I EEE 114 9.1

clock (TCK) and the system clock (CLK), the user must provide some

form of external synchronization to achieve meaningful results when

sampling system values.

9.5.4 CLAMP (0011)

The CLAMP instruction enables the single-bit BYPASS register between TDI and TDO

as test data register. It is provided as a public instruction. When the CLAMP instruction

CLOCKDR

TO TDO MUX

TDI

SHIFTDR

MOTOROLA IEEE 1149.1-COMPLIANT INTERFACE MPC509

9-6 Rev. 15 June 98 USER’S MANUAL

is invoked, the package output signals will respond to the preconditioned values within

the update latches of the boundary scan register, even though the bypass register is

enabled as the test data register.

In-cir cuit testi ng ca n be facili tated by se tting up guar ding si gnal condi tions that contr ol

the operation of logic not involved in the test with use of the SAMPLE/PRELOAD or

EXTEST instructions. Then, as the chip enters into the CLAMP instruction, the state

and driv e of all si gnals rem ain static un til a new inst ruction is inv oked. Whi le the sig -

nals continue to supply the guarding inputs to the in-circuit test site, the bypass is en-

abled and thus should minimize overall test time.

CLAMP asserts internal reset for the MPC509 system logic for the duration of the in-

struction . This fo rc es a pr ed ic tab l e int er na l stat e w hil e exte rn al b ou nda r y scan op er a-

tions are pe rforme d.

The CLAMP in struction performs the same task as the EXTEST in struction. Unlike the

EXTEST instruction, however, once the data in the boundary scan cell is updated, it

remains unchanged until a new instruction is shifted in or reset.

Figure 9-5 Typical Clamp Example

9.5.5 HIGHZ (0010)

The HIGHZ i nstructio n enables t he singl e-bit BYPASS r egister be tween TDI and TDO

to function as test data register. HIGHZ is provided as a public instruction in order to

avoid having to backdrive the output signals during circuit board testing. When the

HIGHZ instruction is invoked, all output drivers are placed in an inactive-drive state.

HIGHZ also asserts internal reset for the MPC509 system logic for the duration of

HIGHZ in order to force a predictable internal state while performing external boundary

scan operat ions.

TDI

TDO

TDI

TDO

EXTEST

BYPASS

TDI TDO

SAMPLE

CLAMP

MPC509 IEEE 1149.1-COMPLIANT INTERFACE MOTOROLA

USER’S MANUAL Rev. 15 June 98 9-7

9.5.6 EXTEST_P ULLUP (0001)

The EXTEST_PULLUP instruction is not included in the IEEE 1149.1-1990 standard.

It is pr ovided as a public in struction to a id in faul t diagnosis dur ing boundar y scan test-

ing of a circuit board. This instruction functions identically to EXTEST except for the

presence of a weak pull-up device on all input signals. The MPC509 is a CMOS design

and co uld theref ore suffer from a logic ally indetermina te input valu e if an input o r bi-

directional signal programmed as an input was inadvertently left unconnected. The

pull-up current will, given an appropriate charging delay, supply a deterministic logic 1

result on an open input.

Note that when this instruction is used in board level testing with heavily loaded nodes,

it may require a c harging del ay greater than the two TCK per iods need ed to change

from the Update-D R stat e to the Capture-DR state. Two metho ds of providing an in-

crease delay are available:

• Traverse into the Run-Test/Idle state for extra TCK periods of charging delay; or

• Limit the maximum TCK frequency (slow down the TCK) so that two TCK periods

are adequate

9.5.7 IDCODE (1101)

The IDCODE enables the IDREGISTER between TDI and TDO as test data register.

It is provided as a public instruction to allow the manufacturer, part number, and ver-

sion of a component to be determined through the TAP. Figure 9-6 shows the IDREG-

ISTER configura tion.

Once the IDCODE instruction is decoded, it selects the IDREGISTER, a 32-bit test

data register. The bypass registe r loads a logic 0 at the start of a scan cycle, where as

an IDREGISTER loads a constant logic 1 into its least significant bit (LSB). Examina-

tion o f the first b it of da ta shifted o ut of a com ponent du ring a test data sca n sequen ce

immediately following exit from the Test-Logic-Reset controller state will therefore

show whether such a register is included in the design.

When the IDCODE instr uctio n is selected , the oper ation of the te st logic has no effe ct

on the operation of the on-chip system logic, as required in the IEEE 1149.1-1990

specification.

Figure 9-6 IDREGISTER Configuration

One application of the device identification register is to distinguish the manufactur-

er(s) of com ponents on a board whe n multiple sourcing is u sed. As more componen ts

LSB

31 111

1227

MANUFACTURER ID

PART NUMBER

VERSION

MSB

MOTOROLA IEEE 1149.1-COMPLIANT INTERFACE MPC509

9-8 Rev. 15 June 98 USER’S MANUAL

emerge which conform to IEEE 114 9.1-199 0, it is desirabl e to al low for a system d iag-

nostic controller unit to blindly interrogate a board design in order to determine the type

of each component in each location. This information is also available for factory pro-

cess monitoring and for failure mode analysis of assembled boards.

9.5.8 TMSCAN (1100)

The TMSCAN instruction enables the 22-bit TMREG register between TDI and TDO

as test d ata regi ste r . It is pr ovid ed a s a M ot orol a p rivate inst ru ction in or de r to ser ial l y

shift in stimulus data to the on-chip test module and serially shift out test result from

the test modu le .

9.6 Re st ric tions

The control afforded by the output enable signals using the boundary scan register and

the EXTEST or CLAMP instructions requires a compatible circuit board test environ-

ment to avoid device-destructive configurations. The user must avoid situations in

which the MPC509 output drivers are enabled into actively driven networks.

9.7 Non-IEEE 1149.1-1990 Operation

In non-IEEE 1149.1-1990 operation, the IEEE 1149.1-1990 test logic must be kept

transparent to the system logic by forcing the TAP controller into th e Test-Logic-Reset

controll er state and ke eping it there. The re are two met hods of forcing the controller to

this state. The first is to assert the TRST signal, forcing the TAP into the Test-Logic-

Reset controller state. The second is to provide at least five TCK pulses with TMS held

high.

To ensure that the controller remains in the Test-Logic-Reset state, several options

are a vailabl e:

• If TMS either remains unconn ected or is co nnecte d to V cc, then th e TAP co ntro l-

ler cannot leave the Test-Logic-Reset state regardless of the state of the TCK pin.

• TRST can b e asserted either by connecti ng it d irectly to g round o r by mean s of a

logic network.

• The controller will remain in the Test-Logic-Reset state in the absence of a rising

edge on the TCK pin regardless of the state of the TMS.

9.8 Boundary Scan Descriptor Language (BSDL)

This section provides an example of the boundary scan descriptor language (BSDL).

-- Motorola MPC509 Model BSDL description

-- Version 1.1 Modified 11/29 by Keeho Kang to accept pad ring fixes for

cpu rev B

entity MPC509 is

generic(PHYSICAL_PIN_MAP:string := “XX_Package”),

-- in = input only

-- buffer = two-state (0 1) output

-- out = three-state or open drain output

-- inout = bidirectional

-- linkage = “other” than above (power, analog, etc.)

MPC509 IEEE 1149.1-COMPLIANT INTERFACE MOTOROLA

USER’S MANUAL Rev. 15 June 98 9-9

-- bit = single pin

-- bit_vector = multiple pins with integer suffix (a01, a1, a2, etc.)

port(TDI: in bit;

TDO: out bit;

TMS: in bit;

TCK: in bit;

TRST_L: in bit;

CS: inout bit_vector(0 to 11);

CSBOOT_L: buffer bit;

PDWU: buffer bit;

CT: inout bit_vector(0 to 3);

BE_L: inout bit_vector(0 to 3);

BI_L: inout bit;

BURST_L: inout bit;

BDIP_L: inout bit;

ARETRY_L: inout bit;

CR_L: inout bit;

ECROUT: buffer bit;

CLKOUT: buffer bit;

SRESET_L: buffer bit;

RESET_L: in bit;

IRQ_L: inout bit_vector(0 to 6);

DSCK: in bit;

DSDI: in bit;

MODCK: in bit;

WP: inout bit_vector(0 to 5);

VFLS: inout bit_vector(0 to 1);

VF: inout bit_vector(0 to 2);

PLLL: inout bit;

AT: inout bit_vector(0 to 1);

A: inout bit_vector(12 to 29);

D: inout bit_vector(0 to 31);

BB_L: inout bit;

BG_L: inout bit;

BR_L: inout bit;

TEA_L: inout bit;

TA_L: inout bit;

AACK_L: inout bit;

TS_L: inout bit;

WR_L: inout bit;

VDDKAP1: linkage bit;

VDDKAP2: linkage bit;

VSSE: linkage bit_vector(0 to 12);

VDDE: linkage bit_vector(0 to 12);

VSSIL: linkage bit;

VDDIL: linkage bit;

VSSIB: linkage bit;

VDDIB: linkage bit;

VSSIR: linkage bit;

VDDIR: linkage bit;

VSSIT: linkage bit;

VDDIT: linkage bit;

VSSSN: linkage bit;

VDDSN: linkage bit;

XFCP: linkage bit;

XFCN: linkage bit;

XTAL: linkage bit;

EXTAL: linkage bit

);

MOTOROLA IEEE 1149.1-COMPLIANT INTERFACE MPC509

9-10 Rev. 15 June 98 USER’S MANUAL

use STD_1149_1_1990.all;

attribute PIN_MAP of MPC509 : entity is PHYSICAL_PIN_MAP;

-- Begin package description for XX_Package

-- 160-PIN QFP (XX Suffix)

-- package pins in same order as port list (a0, a1, a2, etc.) for

bit_vectors

constant XX_Package : PIN_MAP_STRING :=

“VSSE: ( 1, 13, 29, 41, 60, 74, 81, 95, 107, 120, 127, 137, 153 ),

“ &

“VDDE: ( 160, 14, 26, 40, 61, 75, 80, 94, 106, 121, 126, 136, 152 ),

“ &

“VSSIL: 19, “ &

“VDDIL: 20, “ &

“VSSIB: 66, “ &

“VDDIB: 67, “ &

“VDDIR: 100, “ &

“VSSIR: 101, “ &

“VDDIT: 142, “ &

“VSSIT: 143, “ &

“CS: ( 7, 6, 5, 4, 3, 2, 159, 158, 157, 156, 155,

154), “ &

“CSBOOT_L: 8, “ &

“CT: ( 12, 11, 10, 9 ), “ &

“BE_L: ( 18, 17, 16, 15 ), “ &

“CR_L: 25, “ &

“ARETRY_L: 24, “ &

“BDIP_L: 23, “ &

“BURST_L: 22, “ &

“BI_L: 21, “ &

“ECROUT: 27, “ &

“CLKOUT: 28, “ &

“PDWU: 30, “ &

“VDDKAP1: 31, “ &

“XTAL: 32, “ &

“EXTAL: 33, “ &

“VSSSN: 34, “ &

“XFCN: 35, “ &

“XFCP: 36, “ &

“VDDSN: 37, “ &

“SRESET_L: 38, “ &

“RESET_L: 39, “ &

“IRQ_L: ( 43, 42, 53, 54, 55, 56, 57), “ &

“DSCK: 44, “ &

“DSDI: 45, “ &

“VDDKAP2: 46, “ &

“MODCK: 47, “ &

“TRST_L: 48, “ &

“TMS: 49, “ &

“TCK: 50, “ &

“TDO: 51, “ &

“TDI: 52, “ &

“WP: (65, 64, 63, 62, 59, 58), “ &

“VFLS: ( 69, 68 ), “ &

“VF: ( 72, 71, 70 ), “ &

“PLLL: 73, “ &

“AT: ( 77, 76 ), “ &

MPC509 IEEE 1149.1-COMPLIANT INTERFACE MOTOROLA

USER’S MANUAL Rev. 15 June 98 9-11

“A: ( 78, 79, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91,

92, 93, 96, 97, 98, 99 ), “ &

“D: (102, 103, 104, 105, 108, 109, 110, 111, 112, 113,114,

115, 116, 117, “ &

“ 118, 119, 122, 123, 124, 125, 128, 129, 130, 131,

132, 133, 134, 135, “ &

“ 138, 139, 140, 141 ), “ &

“BB_L: 144, “ &

“BG_L: 145, “ &

“BR_L: 146, “ &

“TEA_L: 147, “ &

“TA_L: 148, “ &

“AACK_L: 149, “ &

“TS_L: 150, “ &

“WR_L: 151 “ ;

-- Other Pin Maps here when documented

attribute TAP_SCAN_IN of TDI:signal is true;

attribute TAP_SCAN_OUT of TDO:signal is true;

attribute TAP_SCAN_MODE of TMS:signal is true;

attribute TAP_SCAN_RESET of TRST_L:signal is true;

attribute TAP_SCAN_CLOCK of TCK:signal is (10.0e6, BOTH);

attribute INSTRUCTION_LENGTH of MPC509:entity is 4;

attribute INSTRUCTION_OPCODE of MPC509:entity is

“EXTEST (0000),” &

“EXTEST_PULLUP (0001),” &

“HIGHZ (0010),” &

“CLAMP (0011),” &

“TMSCAN (1100),” &

“IDCODE (1101),” &

“SAMPLE (1110),” &

“BYPASS (1111) “;

attribute INSTRUCTION_CAPTURE of MPC509:entity is “0001”;

attribute INSTRUCTION_PRIVATE of MPC509:entity is “TMSCAN”;

attribute IDCODE_REGISTER of MPC509:entity is

“0000” & -- version

“000010” & -- design center

“0000000000” & -- sequence number

“00000001110” & -- motorola

“1”; -- required by 1149.1

attribute REGISTER_ACCESS of MPC509:entity is

“BOUNDARY (EXTEST_PULLUP) “;

attribute BOUNDARY_CELLS of MPC509:entity is

“BC_2, BC_4, BC_6”;

attribute BOUNDARY_LENGTH of MPC509:entity is 217;

attribute BOUNDARY_REGISTER of MPC509:entity is

-- PORT DESCRIPTION DECODE

-- port = port name or port name with suffix such as a(1)

-- cell = BC_4 for inputs, BC_6 for bidirectionals, BC_2 all other

-- function =

-- input = input only

MOTOROLA IEEE 1149.1-COMPLIANT INTERFACE MPC509

9-12 Rev. 15 June 98 USER’S MANUAL

-- bidir = directional

-- controlr = control with jtag_reset

-- output2 = output two state (0 1)

-- safe =

-- X for input, output2, bidir

-- 0 for control cells (0 = input)

-- ccell = controlling cell

-- dsval = disable value = 0 (0 = input)

-- rslt = result of putting dsval in control cell = Z

--num cell port function safe ccell dsval rslt

--tdo = first bit to be shifted out during ShiftDR

“0 (BC_4, MODCK, input, X), “ &

“1 (BC_4, DSDI, input, X), “ &

“2 (BC_4, DSCK, input, X), “ &

“3 (BC_6, IRQ_L(0), bidir, X, 4, 0, Z), “ &

“4 (BC_2, *, controlr, 0), “ &

“5 (BC_6, IRQ_L(1), bidir, X, 6, 0, Z), “ &

“6 (BC_2, *, controlr, 0), “ &

“7 (BC_4, RESET_L, input, X), “ &

“8 (BC_2, SRESET_L, output2, X), “ &

“9 (BC_2, PDWU, output2, X), “ &

“10 (BC_2, CLKOUT, output2, X), “ &

“11 (BC_2, ECROUT, output2, X), “ &

“12 (BC_6, CR_L, bidir, X, 13, 0, Z), “ &

“13 (BC_2, *, controlr, 0), “ &

“14 (BC_6, ARETRY_L, bidir, X, 15, 0, Z), “ &

“15 (BC_2, *, controlr, 0), “ &

“16 (BC_6, BDIP_L, bidir, X, 17, 0, Z), “ &

“17 (BC_2, *, controlr, 0), “ &

“18 (BC_6, BURST_L, bidir, X, 19, 0, Z), “ &

“19 (BC_2, *, controlr, 0), “ &

--num cell port function safe ccell dsval rslt

“20 (BC_6, BI_L, bidir, X, 21, 0, Z), “ &

“21 (BC_2, *, controlr, 0), “ &

“22 (BC_6, BE_L(0), bidir, X, 23, 0, Z), “ &

“23 (BC_2, *, controlr, 0), “ &

“24 (BC_6, BE_L(1), bidir, X, 25, 0, Z), “ &

“25 (BC_2, *, controlr, 0), “ &

“26 (BC_6, BE_L(2), bidir, X, 27, 0, Z), “ &

“27 (BC_2, *, controlr, 0), “ &

“28 (BC_6, BE_L(3), bidir, X, 29, 0, Z), “ &

“29 (BC_2, *, controlr, 0), “ &

“30 (BC_6, CT(0), bidir, X, 31, 0, Z), “ &

“31 (BC_2, *, controlr, 0), “ &

“32 (BC_6, CT(1), bidir, X, 33, 0, Z), “ &

“33 (BC_2, *, controlr, 0), “ &

“34 (BC_6, CT(2), bidir, X, 35, 0, Z), “ &

“35 (BC_2, *, controlr, 0), “ &

“36 (BC_6, CT(3), bidir, X, 37, 0, Z), “ &

“37 (BC_2, *, controlr, 0), “ &

“38 (BC_2, CSBOOT_L, output2, X), “ &

“39 (BC_6, CS(0), bidir, X, 40, 0, Z), “ &

--num cell port function safe ccell dsval rslt

“40 (BC_2, *, controlr, 0), “ &

“41 (BC_6, CS(1), bidir, X, 42, 0, Z), “ &

“42 (BC_2, *, controlr, 0), “ &

“43 (BC_6, CS(2), bidir, X, 44, 0, Z), “ &

“44 (BC_2, *, controlr, 0), “ &

MPC509 IEEE 1149.1-COMPLIANT INTERFACE MOTOROLA

USER’S MANUAL Rev. 15 June 98 9-13

“45 (BC_6, CS(3), bidir, X, 46, 0, Z), “ &

“46 (BC_2, *, controlr, 0), “ &

“47 (BC_6, CS(4), bidir, X, 48, 0, Z), “ &

“48 (BC_2, *, controlr, 0), “ &

“49 (BC_6, CS(5), bidir, X, 50, 0, Z), “ &

“50 (BC_2, *, controlr, 0), “ &

“51 (BC_6, CS(6), bidir, X, 52, 0, Z), “ &

“52 (BC_2, *, controlr, 0), “ &

“53 (BC_6, CS(7), bidir, X, 54, 0, Z), “ &

“54 (BC_2, *, controlr, 0), “ &

“55 (BC_6, CS(8), bidir, X, 56, 0, Z), “ &

“56 (BC_2, *, controlr, 0), “ &

“57 (BC_6, CS(9), bidir, X, 58, 0, Z), “ &

“58 (BC_2, *, controlr, 0), “ &

“59 (BC_6, CS(10), bidir, X, 60, 0, Z), “ &

--num cell port function safe ccell dsval rslt

“60 (BC_2, *, controlr, 0), “ &

“61 (BC_6, CS(11), bidir, X, 62, 0, Z), “ &

“62 (BC_2, *, controlr, 0), “ &

“63 (BC_6, WR_L, bidir, X, 64, 0, Z), “ &

“64 (BC_2, *, controlr, 0), “ &

“65 (BC_6, TS_L, bidir, X, 66, 0, Z), “ &

“66 (BC_2, *, controlr, 0), “ &

“67 (BC_6, AACK_L, bidir, X, 68, 0, Z), “ &

“68 (BC_2, *, controlr, 0), “ &

“69 (BC_6, TA_L, bidir, X, 70, 0, Z), “ &

“70 (BC_2, *, controlr, 0), “ &

“71 (BC_6, TEA_L, bidir, X, 72, 0, Z), “ &

“72 (BC_2, *, controlr, 0), “ &

“73 (BC_6, BR_L, bidir, X, 74, 0, Z), “ &

“74 (BC_2, *, controlr, 0), “ &

“75 (BC_6, BG_L, bidir, X, 76, 0, Z), “ &

“76 (BC_2, *, controlr, 0), “ &

“77 (BC_6, BB_L, bidir, X, 78, 0, Z), “ &

“78 (BC_2, *, controlr, 0), “ &

“79 (BC_6, D(31), bidir, X, 80, 0, Z), “ &

--num cell port function safe ccell dsval rslt

“80 (BC_2, *, controlr, 0), “ &

“81 (BC_6, D(30), bidir, X, 82, 0, Z), “ &

“82 (BC_2, *, controlr, 0), “ &

“83 (BC_6, D(29), bidir, X, 84, 0, Z), “ &

“84 (BC_2, *, controlr, 0), “ &

“85 (BC_6, D(28), bidir, X, 86, 0, Z), “ &

“86 (BC_2, *, controlr, 0), “ &

“87 (BC_6, D(27), bidir, X, 88, 0, Z), “ &

“88 (BC_2, *, controlr, 0), “ &

“89 (BC_6, D(26), bidir, X, 90, 0, Z), “ &

“90 (BC_2, *, controlr, 0), “ &

“91 (BC_6, D(25), bidir, X, 92, 0, Z), “ &

“92 (BC_2, *, controlr, 0), “ &

“93 (BC_6, D(24), bidir, X, 94, 0, Z), “ &

“94 (BC_2, *, controlr, 0), “ &

“95 (BC_6, D(23), bidir, X, 96, 0, Z), “ &

“96 (BC_2, *, controlr, 0), “ &

“97 (BC_6, D(22), bidir, X, 98, 0, Z), “ &

“98 (BC_2, *, controlr, 0), “ &

“99 (BC_6, D(21), bidir, X, 100, 0, Z), “ &

--num cell port function safe ccell dsval rslt

“100 (BC_2, *, controlr, 0), “ &

“101 (BC_6, D(20), bidir, X, 102, 0, Z), “ &

MOTOROLA IEEE 1149.1-COMPLIANT INTERFACE MPC509

9-14 Rev. 15 June 98 USER’S MANUAL

“102 (BC_2, *, controlr, 0), “ &

“103 (BC_6, D(19), bidir, X, 104, 0, Z), “ &

“104 (BC_2, *, controlr, 0), “ &

“105 (BC_6, D(18), bidir, X, 106, 0, Z), “ &

“106 (BC_2, *, controlr, 0), “ &

“107 (BC_6, D(17), bidir, X, 108, 0, Z), “ &

“108 (BC_2, *, controlr, 0), “ &

“109 (BC_6, D(16), bidir, X, 110, 0, Z), “ &

“110 (BC_2, *, controlr, 0), “ &

“111 (BC_6, D(15), bidir, X, 112, 0, Z), “ &

“112 (BC_2, *, controlr, 0), “ &

“113 (BC_6, D(14), bidir, X, 114, 0, Z), “ &

“114 (BC_2, *, controlr, 0), “ &

“115 (BC_6, D(13), bidir, X, 116, 0, Z), “ &

“116 (BC_2, *, controlr, 0), “ &

“117 (BC_6, D(12), bidir, X, 118, 0, Z), “ &

“118 (BC_2, *, controlr, 0), “ &

“119 (BC_6, D(11), bidir, X, 120, 0, Z), “ &

--num cell port function safe ccell dsval rslt

“120 (BC_2, *, controlr, 0), “ &

“121 (BC_6, D(10), bidir, X, 122, 0, Z), “ &

“122 (BC_2, *, controlr, 0), “ &

“123 (BC_6, D(9), bidir, X, 124, 0, Z), “ &

“124 (BC_2, *, controlr, 0), “ &

“125 (BC_6, D(8), bidir, X, 126, 0, Z), “ &

“126 (BC_2, *, controlr, 0), “ &

“127 (BC_6, D(7), bidir, X, 128, 0, Z), “ &

“128 (BC_2, *, controlr, 0), “ &

“129 (BC_6, D(6), bidir, X, 130, 0, Z), “ &

“130 (BC_2, *, controlr, 0), “ &

“131 (BC_6, D(5), bidir, X, 132, 0, Z), “ &

“132 (BC_2, *, controlr, 0), “ &

“133 (BC_6, D(4), bidir, X, 134, 0, Z), “ &

“134 (BC_2, *, controlr, 0), “ &

“135 (BC_6, D(3), bidir, X, 136, 0, Z), “ &

“136 (BC_2, *, controlr, 0), “ &

“137 (BC_6, D(2), bidir, X, 138, 0, Z), “ &

“138 (BC_2, *, controlr, 0), “ &

“139 (BC_6, D(1), bidir, X, 140, 0, Z), “ &

--num cell port function safe ccell dsval rslt

“140 (BC_2, *, controlr, 0), “ &

“141 (BC_6, D(0), bidir, X, 142, 0, Z), “ &

“142 (BC_2, *, controlr, 0), “ &

“143 (BC_6, A(29), bidir, X, 144, 0, Z), “ &

“144 (BC_2, *, controlr, 0), “ &

“145 (BC_6, A(28), bidir, X, 146, 0, Z), “ &

“146 (BC_2, *, controlr, 0), “ &

“147 (BC_6, A(27), bidir, X, 148, 0, Z), “ &

“148 (BC_2, *, controlr, 0), “ &

“149 (BC_6, A(26), bidir, X, 150, 0, Z), “ &

“150 (BC_2, *, controlr, 0), “ &

“151 (BC_6, A(25), bidir, X, 152, 0, Z), “ &

“152 (BC_2, *, controlr, 0), “ &

“153 (BC_6, A(24), bidir, X, 154, 0, Z), “ &

“154 (BC_2, *, controlr, 0), “ &

“155 (BC_6, A(23), bidir, X, 156, 0, Z), “ &

“156 (BC_2, *, controlr, 0), “ &

“157 (BC_6, A(22), bidir, X, 158, 0, Z), “ &

“158 (BC_2, *, controlr, 0), “ &

“159 (BC_6, A(21), bidir, X, 160, 0, Z), “ &

MPC509 IEEE 1149.1-COMPLIANT INTERFACE MOTOROLA

USER’S MANUAL Rev. 15 June 98 9-15

--num cell port function safe ccell dsval rslt

“160 (BC_2, *, controlr, 0), “ &

“161 (BC_6, A(20), bidir, X, 162, 0, Z), “ &

“162 (BC_2, *, controlr, 0), “ &

“163 (BC_6, A(19), bidir, X, 164, 0, Z), “ &

“164 (BC_2, *, controlr, 0), “ &

“165 (BC_6, A(18), bidir, X, 166, 0, Z), “ &

“166 (BC_2, *, controlr, 0), “ &

“167 (BC_6, A(17), bidir, X, 168, 0, Z), “ &

“168 (BC_2, *, controlr, 0), “ &

“169 (BC_6, A(16), bidir, X, 170, 0, Z), “ &

“170 (BC_2, *, controlr, 0), “ &

“171 (BC_6, A(15), bidir, X, 172, 0, Z), “ &

“172 (BC_2, *, controlr, 0), “ &

“173 (BC_6, A(14), bidir, X, 174, 0, Z), “ &

“174 (BC_2, *, controlr, 0), “ &

“175 (BC_6, A(13), bidir, X, 176, 0, Z), “ &

“176 (BC_2, *, controlr, 0), “ &

“177 (BC_6, A(12), bidir, X, 178, 0, Z), “ &

“178 (BC_2, *, controlr, 0), “ &

“179 (BC_6, AT(0), bidir, X, 180, 0, Z), “ &

--num cell port function safe ccell dsval rslt

“180 (BC_2, *, controlr, 0), “ &

“181 (BC_6, AT(1), bidir, X, 182, 0, Z), “ &

“182 (BC_2, *, controlr, 0), “ &

“183 (BC_6, PLLL, bidir, X, 184, 0, Z), “ &

“184 (BC_2, *, controlr, 0), “ &

“185 (BC_6, VF(0), bidir, X, 186, 0, Z), “ &

“186 (BC_2, *, controlr, 0), “ &

“187 (BC_6, VF(1), bidir, X, 188, 0, Z), “ &

“188 (BC_2, *, controlr, 0), “ &

“189 (BC_6, VF(2), bidir, X, 190, 0, Z), “ &

“190 (BC_2, *, controlr, 0), “ &

“191 (BC_6, VFLS(0), bidir, X, 192, 0, Z), “ &

“192 (BC_2, *, controlr, 0), “ &

“193 (BC_6, VFLS(1), bidir, X, 194, 0, Z), “ &

“194 (BC_2, *, controlr, 0), “ &

“195 (BC_6, WP(0), bidir, X, 196, 0, Z), “ &

“196 (BC_2, *, controlr, 0), “ &

“197 (BC_6, WP(1), bidir, X, 198, 0, Z), “ &

“198 (BC_2, *, controlr, 0), “ &

“199 (BC_6, WP(2), bidir, X, 200, 0, Z), “ &

--num cell port function safe ccell dsval rslt

“200 (BC_2, *, controlr, 0), “ &

“201 (BC_6, WP(3), bidir, X, 202, 0, Z), “ &

“202 (BC_2, *, controlr, 0), “ &

“203 (BC_6, WP(4), bidir, X, 204, 0, Z), “ &

“204 (BC_2, *, controlr, 0), “ &

“205 (BC_6, WP(5), bidir, X, 206, 0, Z), “ &

“206 (BC_2, *, controlr, 0), “ &

“207 (BC_6, IRQ_L(2), bidir, X, 208, 0, Z), “ &

“208 (BC_2, *, controlr, 0), “ &

“209 (BC_6, IRQ_L(3), bidir, X, 210, 0, Z), “ &

“210 (BC_2, *, controlr, 0), “ &

“211 (BC_6, IRQ_L(4), bidir, X, 212, 0, Z), “ &

“212 (BC_2, *, controlr, 0), “ &

“213 (BC_6, IRQ_L(5), bidir, X, 214, 0, Z), “ &

“214 (BC_2, *, controlr, 0), “ &

“215 (BC_6, IRQ_L(6), bidir, X, 216, 0, Z), “ &

“216 (BC_2, *, controlr, 0) “ ;

MOTOROLA IEEE 1149.1-COMPLIANT INTERFACE MPC509

9-16 Rev. 15 June 98 USER’S MANUAL

-- tdi

end MPC509;

MPC509 INDEX MOTOROLA

User’s Manual Rev. 15 June 1998 Index-1

INDEX

–A–

AACK 2-10, 5-13, 5-21, 5-49, 5-50

ACKEN 5-43, 5-49

Acknowledge enable 5-43, 5-49

ADDR 2-9, 5-13, 5-20

Address

ackn owle dge signal. See AACK

bus. See also ADDR

phase 5-20

retry. See ARETRY

type. See AT

wrapping 5-24

ADR field (in ICADR) 4-5

ALE 8-54

ALEE 8-55

Alternate functions of chip-select pins 5-36

ALU–BFU 3-6

Arbitration phase 5-20

ARETRY 2-12, 5-13, 5-21, 5-28, 5-34

Asynchronous

interface 5-53, 5-59

with latch enable 5-60

OE 5-53, 5-54, 5-60

AT 2-12, 5-13, 5-14, 5-20

–B–

BA 5-40, 5-4 5

Back tr ace 8 -8

Base address 5-45

of I-bus memory block. See IMEMBASE

of L-bus memory block. See LMEMBASE

registers, chip select 5-39

BB 2-8, 5-14, 5-20

BDIP 2-14, 5-5, 5-14, 5-21, 5-23, 5-53, 5-63

BE and chip selects 5-51

BE 2-10, 5-13, 5-15, 5-20, 5-27, 5-44

BE bit 3-19

BG 2-7, 5-14, 5-20

BI 2-11, 5-13, 5-23

Block size 5-43, 5-45

BMCR 5-11

BME 5-11, 5-91, 5-92

BMLK 5-91, 5-92

BMT 5-91, 5-92

Boundary scan

cells 9-1

descriptor language 9-8

BPU 3-5

BR 2-6, 5-14, 5-20

Branch

prediction 3-5

processing unit 3-5

trace enable 3-19

Breakpoint counter A value and control register 8-52

Breakpoint counter B value and control register 8-53

Breakpoints 8-11

BRKNOMSK 8-51

BSC 9-1

BSDL 9-8

BSIZE 5-43, 5-45

BSR 9-1

Buffers, I/O 2-2

BURST 2-9, 5-13, 5-20

Burst

cycl es 5-2 2

data in progress. See BDIP

inhibit

cycl es 5-2 3