MPC509 User Manual - Motorola / Freescale Semiconductor

MPC500 Fami ly

MPC509

User’s Manual

MPC509UM/AD

PowerPC Microcontrollers

TABLE OF CONTENTS

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MPC509 TABLE OF CONTENTS MOTOROLA

USER’S MANUAL Rev. 15 June 1998 iii

PREFACE

Section 1

INTRODUCTION

1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.3 Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Section 2

SIGNAL DESCRIPTIONS

2.1 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Pin Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.3 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.4 Pins with Internal Pull-Ups and Pulldowns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.5 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.5.1 Bus Arbitration and Reservation Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.5.1.1 Bus Request (B R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.5.1.2 Bus Grant (BG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.5.1.3 Bus Busy (B B ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.5.1.4 Cancel Reservation (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.5.2 Address Phase Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.5.2.1 Address Bus (ADDR[0:29]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.5.2.2 Write/Read (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.5.2.3 Burst Indicator (BURST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.5.2.4 Byte Enables (BE[0:3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.5.2.5 Transfer Start (TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.5.2.6 Address Acknowledge (AACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.5.2.7 Burst Inhibit (BI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.5.2.8 Address Retry (ARETRY). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.5.2.9 Address Type (AT[0:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.5.2.10 Cycle Types (CT[0:3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.5.3 Data Phase Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.5.3.1 Data Bus (DATA[0:31]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.5.3.2 Burst Data in Progress (BDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.5.3.3 Transfer Acknowledge (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.5.3.4 Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.5.3.5 Data Strobe (DS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.5.4 Development Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.5.4.1 Development Port Serial Data Out (DSDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.5.4.2 Development Port Serial Data In (DSDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

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2.5.4.3 Development Port Serial Clock Input (DSCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.5.4.4 Instruction Fetch Visibility Signals (VF[0:2]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.5.4.5 Instruction Flush Count (VFLS[0:1]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.5.4.6 Watchpoints (WP[0:5]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.5.5 Chip-Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.5.5.1 Chip Select for System Boot Memory (CSBOOT) . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.5.5.2 Chip Selects for External Memory (CS[0:11]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.5.6 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.5.6.1 Clock Output (CLKOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.5.6.2 Engineering Clock Output (ECROUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5.6.3 Crystal Oscillator Connections (EXTAL, XTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5.6.4 External Filter Capacitor Pins (XFCP, XFCN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5.6.5 Clock Mode (MODCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5.6.6 Phase-Locked Loop Lock Signal (PLLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5.6.7 Power-Down Wake-Up (PDWU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5.7 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.7.1 Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.7.2 Reset Output (RESETOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.8 SIU General-Purpose Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.8.1 Ports A and B (PA[0:7], PB[0:7]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.8.2 Ports I, J, K, and L (PI[0:7], PJ[0:7], PK[0:7], PL[2:7]. . . . . . . . . . . . . . . . . . . . . . . 2-21

2.5.8.3 Port M (PM[3:7]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.5.9 Interrupts and Port Q Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.5.9.1 Interrupt Requests (IRQ[0:6]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.5.9.2 Port Q (PQ[0:6]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.10 JTAG Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.10.1 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.10.2 Test Data Output (TDO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.10.3 Test Mode Select (TMS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.10.4 Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.10.5 Test Reset (TRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

Section 3

CENTRAL PROCESSING UNIT

3.1 RCPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 RCPU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.3 Instruction Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.4 Independent Execution Units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.4.1 Branch Processing Unit (BPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.4.2 Integer Unit (IU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.4.3 Load/Store Unit (LSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.4.4 Floating-Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.5 Levels of the PowerPC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

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3.6 RCPU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.7 PowerPC UISA Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.7.1 General-Purpose Registers (GPRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.7.2 Floating-Point Registers (FPRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.7.3 Floating-Point Status and Control Register (FPSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.7.4 Condition Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.7.4.1 Condition Register CR0 Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.7.4.2 Condition Register CR1 Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.7.4.3 Condition Regi st er CR

Field — Compare Instruction. . . . . . . . . . . . . . . . . . . . . . 3-15

3.7.5 Integer Exception Register (XER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.7.6 Link Register (LR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.7.7 Count Register (CTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.8 PowerPC VEA Register Set — Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.9 PowerPC OEA Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.9.1 Machine State Register (MSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.9.2 DAE/Source Instruction Service Register (DSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

3.9.3 Data Address Register (DAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.9.4 Time Base Facility (TB) — OEA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.9.5 Decrementer Register (DEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.9.6 Machine Status Save/Restore Register 0 (SRR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.9.7 Machine Status Save/Restore Register 1 (SRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

3.9.8 General SPRs (SPRG0–SPRG3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

3.9.9 Processor Version Register (PVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

3.9.10 Implementation-Specific SPRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.9.10.1 EIE, EID, and NRI Special-Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.9.10.2 Instruction-Cache Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.9.10.3 Development Support Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

3.9.10.4 Floating-Point Exception Cause Register (FPECR). . . . . . . . . . . . . . . . . . . . . . . 3-24

3.10 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

3.10.1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

3.10.2 Recommended Simplified Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

3.10.3 Calculating Effective Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

3.11 Exception Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

3.11.1 Exception Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

3.11.2 Ordered Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

3.11.3 Unordered Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

3.11.4 Precise Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

3.11.5 Exception Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

3.12 Instruction Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

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Section 4

INSTRUCTION CACHE

4.1 Instruction Cache Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 Instruction Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.3 Instruction Cache Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 3

4.4 Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.5 Cache Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Section 5

SYSTEM INTERFACE UNIT

5.1 SIU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 SIU Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3 SIU Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.3.1 SIU Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.3.2 Memory Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.3.3 Internal Module Select Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.3.3.1 Memory Block Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.3.3.2 Accesses to Unimplemented Internal Memory Locations. . . . . . . . . . . . . . . . . . . . . 5-9

5.3.3.3 Control Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5.3.3.4 Internal Memory Mapping Field (LMEMBASE). . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.3.3.5 Memory Mapping Conflicts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.3.4 Internal Cross-Bus Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.3.5 Response to Freeze Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

5.3.5.1 Effects of Freeze and Debug Mode on the Bus Monitor. . . . . . . . . . . . . . . . . . . . . 5-11

5.3.5.2 Effects of Freeze on the Programmable Interrupt Timer (PIT). . . . . . . . . . . . . . . . 5-11

5.3.5.3 Effects of Freeze on the Decrementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.3.5.4 Effects of Freeze on Register Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.4 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.4.2 External Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.4.3 Basic Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

5.4.3.1 Read Cycle Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

5.4.3.2 Write Cycle Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

5.4.4 Basic Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18

5.4.5 Bus Cycle Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

5.4.5.1 Arbitration Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

5.4.5.2 Address Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

5.4.5.3 Data Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21

5.4.6 Burst Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22

5.4.6.1 Termination of Burst Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

5.4.6.2 Burst Inhibit Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

5.4.7 Decomposed Cycles and Address Wrapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

5.4.8 Preventing Speculative Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

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5.4.9 Accesses to 16-Bit Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27

5.4.10 Address Retry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28

5.4.11 Transfer Error Acknowledge Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28

5.4.12 Cycle Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29

5.4.13 Show Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30

5.4.14 Storage Reservation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31

5.4.14.1 PowerPC Architecture Reservation Requirements. . . . . . . . . . . . . . . . . . . . . . . . 5-32

5.4.14.2 E-bus Storage Reservation Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33

5.4.14.3 Reservation Storage Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33

5.5 Chip Selects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34

5.5.1 Chip-Select Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35

5.5.2 Chip-Select Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35

5.5.3 Chip-Select Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36

5.5.4 Chip-Select Registers and Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37

5.5.4.1 Chip-Select Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39

5.5.4.2 Chip-Select Option Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40

5.5.5 Chip-Select Regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44

5.5.6 Multi-Level Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46

5.5.6.1 Main Block and Sub-Block Pairings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46

5.5.6.2 Programming the Sub-Block Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47

5.5.6.3 Multi-Level Protection for CSBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47

5.5.7 Access Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

5.5.7.1 Supervisor Space Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

5.5.7.2 Data Space Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

5.5.7.3 Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

5.5.8 Cache Inhibit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49

5.5.9 Handshaking Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49

5.5.10 Wait State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49

5.5.11 Port Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50

5.5.12 Chip-Select Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50

5.5.12.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51

5.5.12.2 Byte Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51

5.5.12.3 Region Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51

5.5.13 Interface Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52

5.5.13.1 Interface Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53

5.5.13.2 Turn-Off Times for Different Interface Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54

5.5.13.3 Interface Type and BI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55

5.5.14 Chip-Select Operation Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55

5.5.15 Pipe Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56

5.5.15.1 Pipelined Accesses to the Same Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57

5.5.15.2 Pipelined Accesses to Different Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57

5.5.16 Chip-Select Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59

5.5.16.1 Asynchronous Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59

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viii Rev. 15 June 1998 USER’S MANUAL

5.5.16.2 Asynchronous Interface with Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60

5.5.16.3 Synchronous Interface with Asynchronous OE . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60

5.5.16.4 Synchronous Interface with Early Synchronous OE. . . . . . . . . . . . . . . . . . . . . . . 5-61

5.5.16.5 Synchronous Interface with Synchronous OE, Early Overlap . . . . . . . . . . . . . . . 5-62

5.5.16.6 Synchronous Burst Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63

5.5.17 Burst Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66

5.5.18 Chip-Select Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67

5.6 Clock Submodule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67

5.6.1 Clock Submodule Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70

5.6.2 Clock Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70

5.6.3 System Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71

5.6.4 Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71

5.6.4.1 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72

5.6.4.2 Phase Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73

5.6.4.3 Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73

5.6.4.4 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74

5.6.4.5 Multiplication Factor Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74

5.6.4.6 Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74

5.6.5 CLKOUT Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74

5.6.5.1 Multiplication Factor (MF) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75

5.6.5.2 Reduced Frequency Divider (RFD[0:3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77

5.6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78

5.6.6.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78

5.6.6.2 Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78

5.6.6.3 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78

5.6.6.4 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79

5.6.6.5 Exiting Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79

5.6.7 System Clock Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79

5.6.8 Power-Down Wake Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80

5.6.9 Time Base and Decrementer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80

5.6.9.1 Time Base and Decrementer Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81

5.6.9.2 Time Base/Decrementer and Freeze Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81

5.6.9.3 Decrementer Clock Enable (DCE) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81

5.6.10 Clock Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81

5.6.10.1 Loss of PLL Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82

5.6.10.2 Loss of Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82

5.6.11 System Clock Control Register (SCCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83

5.6.12 System Clock Lock and Status Register (SCLSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84

5.7 System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-85

5.7.1 System Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-85

5.7.2 System Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86

5.7.3 Periodic Interrupt Timer (PIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86

5.7.3.1 PIT Clock Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-87

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5.7.3.2 PIT Time-Out Period Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-88

5.7.3.3 PIT Enable Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-89

5.7.3.4 PIT Interrupt Request Level and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-89

5.7.3.5 Periodic Interrupt Control and Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-89

5.7.3.6 Periodic Interrupt Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90

5.7.4 Hardware Bus Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90

5.7.4.1 Bus Monitor Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91

5.7.4.2 Bus Monitor Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91

5.7.4.3 Bus Monitor Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91

5.7.4.4 Bus Monitor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91

5.8 Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92

5.8.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92

5.8.2 Reset Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93

5.8.2.1 External Reset Request Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93

5.8.2.2 Internal Reset Request Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95

5.8.2.3 Reset Behavior for Different Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-97

5.8.3 Configuration During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98

5.8.3.1 Data Bus Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98

5.8.3.2 Internal Default Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99

5.8.3.3 Data Bus Reset Configuration Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99

5.8.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-101

5.9 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-101

5.9.1 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-102

5.9.2 Port M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103

5.9.3 Ports A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-104

5.9.4 Ports I, J, K, and L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-106

5.9.5 Port Replacement Unit (PRU) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108

Section 6

PERIPHERAL CON TROL UNIT

6.1 PCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2 PCU Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.3 Module Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.4 Software Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.4.1 Software Watchdog Service Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.4.2 Software Watchdog Control Register/Timing Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.4.3 Software Watchdog Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.5 Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.5.1 Interrupt Controller Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.5.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.5.2.1 External Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.5.2.2 Periodic Interrupt Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.5.2.3 Interrupt Request Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

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6.5.3 Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.5.3.1 Pending Interrupt Request Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

6.5.3.2 Enabled Active Interrupt Requests Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

6.5.3.3 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

6.5.3.4 PIT/Port Q Interrupt Levels Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.6 Port Q. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.6.1 Port Q Edge Detect/Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

6.6.2 Port Q Pin Assignment Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

6.6.2.1 Port Q Pin Assignment Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

6.6.2.2 Port Q Edge Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

Section 7

STATIC RAM MODULE

7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2 Placement of SRAM in Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.3 SRAM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Section 8

DEVELOPMENT SUPPORT

8.1 Program Flow Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1.1 Indirect Change-of-Flow Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.1.1.1 Marking the Indirect Change-of-Flow Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.1.1.2 Sequential Instructions with the Indirect Change-of-Flow Attribute . . . . . . . . . . . . . 8-3

8.1.2 Instruction Fetch Show Cycle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.1.3 Program Flow-Tracking Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.1.3.1 Instruction Queue Status Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.1.3.2 History Buffer Flush Status Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.1.3.3 Flow-Tracking Status Pins in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.1.3.4 Cycle Type, Write/Read, and Address Type Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.1.4 External Hardware During Program Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.1.4.1 Back Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.1.4.2 Window Trace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.1.4.3 Synchronizing the Trace Window to Internal CPU Events . . . . . . . . . . . . . . . . . . . . 8-8

8.1.4.4 Detecting the Trace Window Starting Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

8.1.4.5 Detecting the Assertion or Negation of VSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

8.1.4.6 Detecting the Trace Window Ending Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

8.1.5 Compress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11

8.2 Watchpoint and Breakpoint Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11

8.2.1 Watchpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

8.2.1.1 Restrictions on Watchpoint Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13

8.2.1.2 Byte and Half-Word Working Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13

8.2.1.3 Generating Six Compare Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15

8.2.1.4 I-Bus Support Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15

8.2.1.5 L-Bus Support Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17

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8.2.1.6 Treating Floating-Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

8.2.2 Internal Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

8.2.2.1 Breakpoint Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

8.2.2.2 Trap-Enable Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

8.2.2.3 Ignore First Match. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

8.2.3 External Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

8.2.4 Breakpoint Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

8.3 Development Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22

8.3.1 Development Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22

8.3.1.1 Development Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23

8.3.1.2 Development Serial Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23

8.3.1.3 Development Serial Data Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24

8.3.2 Development Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24

8.3.2.1 Development Port Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25

8.3.2.2 Trap Enable Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25

8.3.3 Development Port Clock Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25

8.3.4 Development Port Transmissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30

8.3.5 Trap-Enable Input Transmissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30

8.3.6 CPU Input Transmissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31

8.3.7 Serial Data Out of Development Port — Non-Debug Mode . . . . . . . . . . . . . . . . . . . . . . 8-31

8.3.8 Serial Data Out of Development Port — Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 8-32

8.3.8.1 Valid Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32

8.3.8.2 Sequencing Error Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33

8.3.8.3 CPU Exception Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33

8.3.8.4 Null Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34

8.3.9 Use of the Ready Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34

8.4 Debug Mode Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34

8.4.1 Enabling Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35

8.4.2 Entering Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35

8.4.3 Debug Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36

8.4.4 Freeze Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37

8.4.5 Exiting Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37

8.4.6 Checkstop State and Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37

8.5 Development Port Transmission Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38

8.5.1 Port Usage in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38

8.5.2 Debug Mode Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40

8.5.3 Port Usage in Normal (Non-Debug) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40

8.6 Examples of Debug Mode Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41

8.6.1 Prologue Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41

8.6.2 Epilogue Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41

8.6.3 Peek Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42

8.6.4 Poke Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42

8.7 Software Monitor Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42

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8.8 Development Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44

8.8.1 Register Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-45

8.8.2 Comparator A–D Value Registers (CMPA–CMPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46

8.8.3 Comparator E–F Value Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46

8.8.4 Comparator G–H Value Registers (CMPG–CMPH). . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-47

8.8.5 I-Bus Support Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-47

8.8.6 L-Bus Support Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-49

8.8.7 L-Bus Support Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-50

8.8.8 Breakpoint Counter A Value and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-52

8.8.9 Breakpoint Counter B Value and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-53

8.8.10 Exception Cause Register (ECR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-53

8.8.11 Debug Enable Register (DER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-55

Section 9

IEEE 1149.1-COMPLIANT INTERFACE

9.1 JTAG Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2 JTAG Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.3 Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.4 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.5 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.5.1 EXTEST (0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.5.2 BYPASS (1111) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.5.3 SAMPLE/PRELOAD (1110) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.5.4 CLAMP (0011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.5.5 HIGHZ (0010). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.5.6 EXTEST_PULLUP (0001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.5.7 IDCODE (1101) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.5.8 TMSCAN (1100). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.6 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.7 Non-IEEE 1149.1-1990 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.8 Boundary Scan Descriptor Language (BSDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

INDEX

Figure Title Page

LIST OF FIGURES

MPC509 LIST OF FIGURES MOTOROLA

USER’S MANUAL Rev. 15 June 1998 xiii

1-1 MPC509 Block Diagram .................................................................................1-2

1-2 MPC509 Pin Assignments ..............................................................................1-3

1-3 MPC509 Signals .............................................................................................1-4

1-4 MPC509 Memory Map ....................................................................................1-5

2-1 Output-Only and Three-State I/O Buffers .......................................................2-2

3-1 RCPU Block Diagram ............... .... ..... .............. ..... .............. .............. .... ..........3-2

3-2 Sequencer Data Path .....................................................................................3-4

3-3 RCPU Programming Model ............... .............. ..... .............. .............. .... ..........3-9

3-4 Basic Instruction Pipeline .............................................................................3-34

4-1 Instruc tion Cache Organizat ion .................. ..... ..... .... .............. ..... .............. .....4-2

4-2 Instruction Cache Data Path ...........................................................................4-3

5-1 SIU Block Diagram .........................................................................................5-2

5-2 Internal Module Select Scheme ......................................................................5-8

5-3 Placement of Internal Memory in Memory Map ..............................................5-9

5-4 Flow Diagram of a Single Read Cycle ..........................................................5-16

5-5 Example of a Read Cycle .............................................................................5-17

5-6 Flow Diagram of a Single Write Cycle ..........................................................5-18

5-7 Example of Pipelined Bus .............................................................................5-19

5-8 Write Followed by Two Reads on the E-Bus (Using Chip Selects) ..............5-19

5-9 External Burst Read Cycle ...........................................................................5-23

5-10 Storage Reserva tion Sign aling ................... ..... .............. .............. ..... ............5-32

5-11 Simplified Uniprocessor System with Chip-Select Logic ..............................5-34

5-12 Chip-Select Functional Block Diagram .........................................................5-36

5-13 Multi-Level Prote ction ................... ..... .............. .............. ..... .............. .... ........5-46

5-14 Chip-Select Operation Flowchart ..................................................................5-56

5-15 Overlapped Accesses to the Same Region ..................................................5-57

5-16 Pipelined Accesses to Two Different Regions ..............................................5-58

5-17 Asynchronous Read (Zero Wait States) .......................................................5-60

5-18 Asynchronous Write (Zero Wait States) .......................................................5-60

5-19 Synchron ous Read with Asynchronous OE (Zero Wait States) ...................5-61

5-20 Synchronous Write (Zero Wait States) .........................................................5-61

5-21 Synchron ous Read with Early OE (One Wait State) .............. .............. ..... ...5-62

5-22 Synchronous Read with Early Overlap (One Wait State) .............................5-63

5-23 Type 1 Synchronous Burst Read Interface ...................................................5-64

5-24 Type 1 Synchronous Burst Write Interface ...................................................5-65

5-25 Type 2 Synchronous Burst Read Interface ...................................................5-66

5-26 SIU Clock Module Block Diagram ................................................................5-69

Figure Title Page

MOTOROLA LIST OF FIGURES MPC509

xiv Rev. 15 June 1998 USER’S MANUAL

5-27 Phase-Locked Loop Block Diagram .............................................................5-72

5-28 Crystal Oscillator ..........................................................................................5-73

5-29 Charge Pump with Loop Filter Schematic ............ .... ..... ..... .............. .... ........5-73

5-30 Periodic Int errupt Timer Block Diagr am ...... ..... ..... .... .............. ..... .............. ...5-87

5-31 External Reset Request Flow .......................................................................5-94

5-32 Internal Reset Request Flow ........................................................................5-96

6-1 Peripherals Control Unit Block Diagram .........................................................6-1

6-2 Interrupt Structure Block Diagram ..................................................................6-6

6-3 Time-Multiplexing Protocol For IRQ Pins .......................................................6-8

7-1 Placement of Internal SRAM in Memory Map ................................................7-2

8-1 Watchpoint and Breakpoint Support in the RCPU ........................................8-12

8-2 Partially Supported Watchpoint/Breakpoint Example ...................................8-15

8-3 I-Bus Support General Structure ..................................................................8-16

8-4 L-Bus Support General Structure .................................................................8-18

8-5 Development Port Support Logic ..................................................................8-22

8-6 Development Port Registers and Data Paths ...............................................8-24

8-7 Enabling Clock Mode Following Reset .........................................................8-27

8-8 Asynchronous Clocked Serial Communications ...........................................8-28

8-9 Synchronous Clocked Serial Communications .............................................8-29

8-10 Synchronous Self-Clocked Serial Communications .....................................8-30

8-11 Enabling Debug Mode at Reset ....................................................................8-35

8-12 Entering Debug Mode Following Reset ........................................................8-36

8-13 General Port Usage Sequence Diagram ......................................................8-40

8-14 Debug Mode Logic .......................................................................................8-44

9-1 JTAG Pins ......................................................................................................9-1

9-2 Test Logic Block Diagram ...............................................................................9-2

9-3 Sample EXTEST Connection .........................................................................9-4

9-4 Bypass Register .............................................................................................9-5

9-5 Typical Clamp Example ..................................................................................9-6

9-6 IDREGISTER Configuration ...........................................................................9-7

Table Title Page

LIST OF TABLES

MPC509 LIST OF TABLES MOTOROLA

USER’S MANUAL Rev. 15 June 1998 xv

2-1 MPC509 Pin List ..................................................................................................2-1

2-2 EBI Pin Definitions ...............................................................................................2-2

2-3 MPC509 Power Connections.................................................................................2-3

2-4 Pins with Internal Pull-Ups/Pulldowns ...................................................................2-4

2-5 Signal Descriptions ..............................................................................................2-4

2-6 Byte Enable Encodings........................................................................................2-10

2-7 Address Type Definitions.....................................................................................2-12

3-1 RCPU Execution Units .........................................................................................3-5

3-2 FPSCR Bit Categories.........................................................................................3-11

3-3 FPSCR Bit Settings ..........................................................................................3-12

3-4 Floating-Point Result Flags in FPSCR................................................................3-13

3-5 Bit Settings for CR0 Field of CR.........................................................................3-14

3-6 Bit Settings for CR1 Field of CR .......................................................................3-15

3-7 CR

Field Bit Settings for Compare Instructions................................................3-15

3-8 Integer Exception Register Bit Definitions ..........................................................3-16

3-9 Time Base Field Definitions................................................................................3-17

3-10 Machine State Register Bit Settings ...............................................................3-18

3-11 Floating-Point Exception Mode Bits .................................................................3-19

3-12 Time Base Field Definitions..............................................................................3-20

3-13 Uses of SPRG0–SPRG3..................................................................................3-22

3-14 Processor Version Register Bit Settings .........................................................3-23

3-15 Manipulation of MSR[EE] and MSR[RI].............................................................3-23

3-16 Instruction Cache Control Registers..................................................................3-23

3-17 Development Support Registers ......................................................................3-24

3-18 Instruction Set Summary ................................................................................3-26

3-19 MPC509 Exception Classes ............................................................................3-31

3-20 Exception Vector Offset Table ........................................................................3-33

3-21 Instruction Latency and Blockage......................................................................3-35

4-1 Instruction Cache Programming Model .................................................................4-3

4-2 ICCST Bit Settings.................................................................................................4-4

4-3 I-Cache Address Register (ICADR).......................................................................4-5

4-4 I-Cache Data Register (ICDAT).............................................................................4-5

4-5 ICADR Bits Function for the Cache Read Command............................................4-8

4-6 ICDAT Layout During a Tag Read.........................................................................4-8

5-1 SIU Address Map .................................................................................................5-3

5-2 SIUMCR Bit Settings ..........................................................................................5-5

5-3 MEMMAP Bit Settings ........................................................................................5-6

5-4 Internal Memory Array Block Mapping.................................................................5-10

Table Title Page

MOTOROLA LIST OF TABLES MPC509

xvi Rev. 15 June 1998 USER’S MANUAL

5-5 EBI Signal Descriptions .....................................................................................5-13

5-6 Address Type Encodings.....................................................................................5-14

5-7 Byte Enable Encodings........................................................................................5-15

5-8 Signals Driven at Start of Address Phase............................................................5-20

5-9 Burst Access Address Wrapping.........................................................................5-25

5-10 SPECADDR Bit Settings .................................................................................5-26

5-11 SPECMASK Bit Settings .................................................................................5-26

5-12 Example Speculative Mask Values....................................................................5-27

5-13 EBI Read and Write Access to 16-Bit Ports.......... .............. ..... .............. ............5-27

5-14 Cycle Type Encodings .....................................................................................5-29

5-15 EBI Storage Reservation Interface Signals .....................................................5-34

5-16 Chip-Select Pin Functions ...............................................................................5-37

5-17 Chip-Select Module Address Map ...................................................................5-39

5-18 Chip-Select Base Address Registers Bit Settings ...... ..... ..... .............. ............5-40

5-19 Chip-Select Option Register Bit Settings .........................................................5-43

5-20 Block Size Encoding ........................................................................................5-45

5-21 Main Block and Sub-Block Pairings...................................................................5-47

5-22 TADLY and Wait State Control..........................................................................5-50

5-23 Port Size............ .............. .... .............. .............. ..... .............. ..... .............. .... ........5-50

5-24 Pin Configuration Encodings .............................................................................5-51

5-25 BYTE Field Encodings.......................................................................................5-51

5-26 REGION Field Encodings.................................................................................5-52

5-27 Interface Types ................................................................................................5-53

5-28 Pipelined Reads and Writes..............................................................................5-56

5-29 Data Bus Configuration Word Settings for Chip Selects ..................................5-67

5-30 Clocks Module Signal Descriptions ...................................................................5-70

5-31 Clock Module Power Supplies .........................................................................5-70

5-32 System Clock Sources....................... ..... .............. ..... .............. .... .............. ........5-71

5-33 CLKOUT Frequencies with a 4-MHz Crystal ...................................................5-75

5-34 Multiplication Factor Bits....................................................................................5-76

5-35 Reduced Frequency Divider Bits.......................................................................5-77

5-36 Exiting Low-Power Mode...................................................................................5-79

5-37 System Clock Lock Bits.....................................................................................5-80

5-38 SCCR Bit Settings ..........................................................................................5-83

5-39 SCLSR Bit Settings .........................................................................................5-85

5-40 System Protection Address Map .......................................................................5-86

5-41 PCFS Encodings...............................................................................................5-87

5-42 Recommended Settings for PCFS[0:2]..............................................................5-88

5-43 Example PIT Time-Out Periods.........................................................................5-88

5-44 PICSR Bit Settings ..........................................................................................5-90

5-45 BMCR Bit Settings ..........................................................................................5-92

Table Title Page

MPC509 LIST OF TABLES MOTOROLA

USER’S MANUAL Rev. 15 June 1998 xvii

5-46 Reset Status Register Bit Settings ...................................................................5-93

5-47 Reset Behavior for Different Clock Modes .......................................................5-97

5-48 Pin Configuration During Reset.........................................................................5-98

5-49 Data Bus Reset Configuration Word ..............................................................5-100

5-50 SIU Port Registers Address Map..................................................................... 5-102

5-51 Port M Pin Assignments ........... ..... .... .............. ..... .............. .............. ..... ..........5-104

5-52 Port A Pin Assignments .................................................................................5-105

5-53 Port B Pin Assignments .................................................................................5-105

5-54 Port I Pin Assignments ....................................................................................5-107

5-55 Port J Pin Assignments........ ..... .............. ..... .............. .... .............. ..... .............. .5-107

5-56 Port K Pin Assignments...................................................................................5-108

5-57 Port L Pin Assignments ...................................................................................5-108

6-1 PCU Address Map ...............................................................................................6-2

6-2 PCUMCR Bit Settings .........................................................................................6-3

6-3 SWCR/SWTC Bit Settings ..................................................................................6-5

6-4 IMB2 Interrupt Multiplexing....................................................................................6-8

6-5 Interrupt Controller Registers.................................................................................6-8

6-6 PITQIL Bit Settings ...........................................................................................6-10

6-7 Port Q Pin Assignments.......................................................................................6-12

6-8 Port Q Edge Select Field Encoding.....................................................................6-12

7-1 MPC509 SRAM Module Addresses.......................................................................7-1

7-2 SRAMMCR Bit Settings ......................................................................................7-3

8-1 Program Trace Cycle Attribute Encodings.............................................................8-3

8-2 Fetch Show Cycles Control ...................................................................................8-4

8-3 VF Pins Instruction Encodings ............................................................................8-5

8-4 VF Pins Queue Flush Encoding s.............. ..... .... .............. ..... .............. ..... ..............8-6

8-5 VFLS Pin Encodings..............................................................................................8-6

8-6 Cycle Type Encodings...........................................................................................8-7

8-7 Detecting the Trace Buffer Starting Point............................................................8-10

8-8 I-bus Watchpoint Programming Options..............................................................8-17

8-9 L-Bus Data Events .............................................................................................8-18

8-10 L-Bus Watchpoints Programming Options.........................................................8-19

8-11 Trap Enable Data Shifted Into Development Port Shift Register.......................8-31

8-12 Breakpoint Data Shifted Into Development Port Shift Register .........................8-31

8-13 CPU Instructions/Data Shifted into Shift Register..............................................8-31

8-14 Status Shifted Out of Shift Register — Non-Debug Mode................ ..... ............8-32

8-15 Status/Data Shifted Out of Shift Register.................. .............. .... .............. ..... ...8-32

8-16 Sequencing Error Activity ..................................................................................8-33

Table Title Page

MOTOROLA LIST OF TABLES MPC509

xviii Rev. 15 June 1998 USER’S MANUAL

8-17 Checkstop State and Debug Mode......... ..... .... ..... .............. ..... .............. .... ........8-38

8-18 Debug Mode Development Port Usage ...........................................................8-39

8-19 Non-Debug Mode Development Port Usage.....................................................8-41

8-20 Prologue Events................................................................................................8-41

8-21 Epilogue Events.................................................................................................8-42

8-22 Peek Instruction Sequence................................................................................8-42

8-23 Poke Instruction Sequence................................................................................8-42

8-24 Development Support Programming Model .....................................................8-45

8-25 Development Support Registers Read Access Protection ..............................8-45

8-26 Development Support Registers Write Access Protection.................................8-46

8-27 CMPA–CMPD Bit Settings ...............................................................................8-46

8-28 CMPE–CMPF Bit Settings.................................................................................8-46

8-29 CMPG–CMPH Bit Settings................................................................................8-47

8-30 ICTRL Bit Settings ...........................................................................................8-48

8-31 LCTRL1 Bit Settings..........................................................................................8-50

8-32 LCTRL2 Bit Settings ........................................................................................8-51

8-33 Breakpoint Counter A Value and Control Register (COUNTA) .......................8-52

8-34 Breakpoint Counter B Value and Control Register (COUNTB) .......................8-53

8-35 ECR Bit Settings ..............................................................................................8-54

8-36 DER Bit Settings .............................................................................................8-55

9-1 JTAG Interface Pin Descriptions............................................................................9-2

9-2 Instruction Register Encoding................................................................................9-3

MPC509 PREFACE MOTOROLA

USER’S MANUAL xix

PREFACE

This manual defines the functionality of the MPC509 for use by software and hardware

developers. The MPC509 is a member of the PowerPC-based Motorola MPC500 fam-

ily of microcontrolle rs.

Audience

This manual is intended for system software and hardware developers and applica-

tions pr og ram me rs. It is assumed that th e r ea der un de rsta nds ope rat ing systems, m i-

croprocessor and microcontroller system design, and the basic principles of RISC

processing.

Additional Reading

This section lists additional reading that provides background to or supplements the

information in this ma nual.

• John L. Hennessy and David A. Patterson,

Computer Architecture: A Quantitative

Approach

, Morgan Kaufmann Publishers, Inc., San Mateo, CA

•

PowerPC Microprocessor Family: the Programming Environments

(MPCFPE/AD)

•

RCPU Reference Manual

(RCPURM/AD)

•

SIU Reference Manual

(SIURM/AD)

• Additional Motorola MPC500-Family documentation. Refer to Motorola publica-

tion

Advanced Microcontroller Unit (AMCU) Literature

(BR1116/D) for a complete

listing of documentation.

Conventions

This document uses the following notational conventions:

ACTIVE_HIGH Names for signal s that ar e act ive high are shown in uppercase

te xt without an o verbar . Signals that are active high are ref erred

to as asserted when they are high and negated when they are

low.

ACTIVE_LOW A bar over a signal name indicates th at the signal is act iv e l o w.

Active-low signals are referred to as asserted (active) when they

are low and negated when they are high.

MOTOROLA PREFACE MPC509

xx USER’S MANUAL

mnemonics Instruction mnem onics ar e shown in lowercase bold.

italics

Italics indicate variable command parameters, for example,

bcctr

0x0F Hexadecimal numbers

0b0011 Binary numbers

rA|0 The contents of a specified GPR or the value zero.

REG[FIELD] Abbreviations or acronyms for registers are shown in uppercase

text. Specific bit fields or ranges are shown in brackets.

x In ce rtain contexts, such as a sign al encoding, this indicat es a

don’t care. F or example, if a field is binary encoded 0bx001, the

state of the first bit is a don’t care.

Nomenclature

Logic level one is the voltage that corresponds to Boolean true (1) state.

Logic level zero is the voltag e that correspon ds to Boolean false (0 ) state.

To set a bit or bits means to establish logic level one o n the bit or bits.

To clear a bit or bits means to establish logic level zero on the bit or bits.

A signal that is asserted is in its active logic state. An active low signal changes from

logic level one to logic level zero when asserted, and an active high signal changes

from logic level zero to logic level one.

A signal tha t is negated is in its inact ive logic state. An active low signa l changes from

logic level zero to logic level one when negated, and an active high signal changes

from logic level o ne to logic level zero.

LSB means le ast sign i fic an t bit o r b its. MSB mean s most signi fi cant bi t or b it s. R efe r-

ences to low and high bytes are spelled out.

MPC509 INTRODUCTION MOTOROLA

USER’S MANUAL Rev. 15 June 98 1-1

SECTION 1

INTRODUCTION

The MP C509 is a member of th e PowerP C Family of reduced in struction set computer

(RISC) microcontrollers (MCUs). The MPC509 implements the 32-bit portion of the

PowerPC™ architecture, which provides 32-bit effective addresses, integer data types

of eight, 16, and 32 bits, and floating-point data types of 32 and 64 bits.

The RISC MCU processor (RCPU) integrates four execution units: an integer unit (IU),

a load/store unit (LSU), a branch processing unit (BPU), and a floating-point unit

(FPU). The RCPU is capable of issuing one sequential (non-branch) instruction per

clock. In addition, branch instructions are evaluated ahead of time when possible,

resulting in zero-cycle execution time for many branch instructions. Instructions can

complete out of order for increased performance; however, the MPC509 makes them

appear sequential.

The MPC509 includes an on-chip, 4-Kbyte, two-way set associative, physically

addressed instruction cache, chip-select logic to reduce or eliminate external decoding

logic, four Kbytes of static RAM, and extensive processor debugging functionality.

The MPC509 has a high-bandwidth, 32-bit data bus and a 32-bit address bus. The

MCU supports 16-bit and 32-bit memories and both single-beat and burst data mem-

ory accesses.

The MP C509 is avai la bl e in a 3 V- on l y I/O conf igurat i on ( pa rt nu m be r M PC509L) an d

in a TTL-c ompatible 5 V-friendly I/O configuration (par t number MP C509L3 ).

1.1 Fe at ures

• Fully-Integrated Single-Chip Micr ocontroller

• RISC MCU Central Processing Unit (RCPU)

— 32-Bit PowerPC Architecture (Compliant with PowerPC Architecture Book 1)

— Single-Issue Processor

— Integrated Floating-Point Unit

— Branch Prediction for Prefetch

— 32 Bit x 32 Bit General-Purpo se Regist er File

— 32 Bit x 64 Bit Floating-Point Register File

— Precise Exception Model

— Internal Harvard Architecture: Load/Store Bus (L-Bus), Instruction Bus (I-Bus)

— PowerPC Time Base and Decrementer

• System Interface Unit (SIU)

— Chip-Select Logic to Reduce or Eliminate External Decoding Logic

— External Bus Interface (EBI) that Supports Synchronous, Asynchronous, Burst

Transfer, and Pipeline Transfer Memory Types

— System Protection Features Including Bus Monitor and Periodic Interrupt

Timer

MOTOROLA INTRODUCTION MPC509

1-2 Rev. 15 June 98 USER’S MANUAL

— On-Chip Phase-Locked Loop (PLL), 16 MHz to 44 MHz

— Five Dual-Purpose I/O Ports, Two Dual-Purpose Output Ports

• Peripheral Control Unit (PCU)

— Software Watchdog

— Interrupt Controller to Manage External and Internal Interrupts to the CPU

— Dual-Purpose I/O Port

— L-Bus IMB Interface (LIMB) Connecting L-Bus to Intermodule Bus 2 (IMB2)

• 4-Kbyte On-Chip Instruction Cache (I-Cache)

• 4-Kbyte On-Chip Sta tic Data RAM (SRAM)

• 3.3-V Sup ply Voltag e

• Tolerates Input Signals from 5-V Peripherals

1.2 Bl ock Diagram

Figure 1-1 MPC509 Block Diagram

Notice in Figure 1-1 that the IMB2 connects the p rocessor to any on-chip p eripher als.

No such peripherals are present on the MPC509.

INTERMODULE BUS 2 (IMB2)

DEVELOPMENT

SUPPORT

RISC MCU

PROCESSOR

4-KBYTE SR AM

PERIPHERAL

4-KBYTE

DEVELOPMENT

EXTERNAL

PORT

I-CACHE

CONTROL UNIT

INTERNAL LO AD/ ST O RE BU S (L-BUS)

INTERNAL INSTRUCTION BUS (I-BUS)

(PCU)

SYSTEM

INTERFACE

UNIT

(RCPU) BUS

(SIU)

IRQs

MPC509 INTRODUCTION MOTOROLA

USER’S MANUAL Rev. 15 June 98 1-3

1.3 Pin Connections

Figure 1-2 MPC509 Pin Assignments

VSSE9

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

DATA4

VSSE8

DATA14

DATA0

DATA1

ADDR27

ADDR26

VSSE7

VDDE7

ADDR25

ADDR21

ADDR20

VDDE8

DATA6

DATA5

DATA7

DATA3

VDDIR

DATA15

DATA2

ADDR29

ADDR28

ADDR24

ADDR23

ADDR22

VSSE6

ADDR19

ADDR18

ADDR17

ADDR16

ADDR15

VSSIR

ADDR14

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

VSSE0

DDR3/CS3

ADDR2/CS2

ADDR1/CS1

ADDR0/CS0

CSBOOT

CT3

VSSE1

VDDE1

ADDR4/CS4

VSSIL

BE0

ARETRY

CR/DS

VDDE2

ECROUT

CLKOUT

XTAL

EXTAL

BE3

CT1

CT0

CT2

BE2

ADDR5/CS5

BE1

BURST

BDIP

VSSE2

PDWU

VDDKAP1

VDDE3

VSSSN

XFCN

XFCP

VDDSN

RESETOUT

VDDIL

RESET

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

VDDE0

ADDR8/CS8

ADDR9/CS9

ADDR10/CS10

ADDR11/CS11

VSSE12

VDDE12

TEA

ADDR7/CS7

VDDIT

VSSIT

VSSE11

VDDE11

DATA27

DATA26

DATA25

DATA21

DATA20

AACK

DATA30

ADDR6/CS6

DATA29

DATA28

DATA24

DATA23

DATA22

VDDE9

VSSE10

VDDE10

DATA19

DATA18

DATA17

DATA31

DATA16

VSSE3

DSCK

DSDI

VDDKAP2

MODCLK

TRST

TMS

IRQ2

IRQ3

IRQ0

WP4

WP5

VSSIB

VDDIB

VFLS1

VF0

DSDO/PLLL

IRQ4

TDO

TDI

TCK

IRQ5

VDDE4

IRQ1

IRQ6

WP3

VFLS0

VF2

VF1

VDDE6

VSSE5

VDDE5

AT1

AT0

ADDR12

VSSE4

ADDR13

WP2

WP1

WP0

MPC509

121

MOTOROLA INTRODUCTION MPC509

1-4 Rev. 15 June 98 USER’S MANUAL

Figure 1-3 MPC509 Si gna ls

BG/PM6

BR/PM4

BR BB/PM5

CS[0:7]/ADDR[0:7]/PA[0:7]

ADDR[16:29]

PORT B

ADDR[12:15]/PB[4:7]

CS[8:11]/ADDR[8:11]/PB[0:3]

DATA[0:31]

CSBOOT

BE[2:3]/PI[6:7]

TS/PJ3

AACK/PI2

TA/PI3

TEA/PI1

PORT J

PORT M

BI/PM3

BURST/PI0

BDIP/PK0

ARETRY/PM7

PLLL/DSDO/PK2

VF[0:2]/PK[3:5]

VFLS[0:1]/PK[6:7]

WP[0:5]/PL[2:7]

CR/DS

RESETOUT

CONTROL

CHIP SELECTS

EXTERNAL BUS

INTERFACE

CLOCKS

SIU

CT[0:3]/PJ[4:7]

PORT I

PORT A

BE[0:1]/PI[4:5]

PORT KPORT L

AT1/PJ2

RESET

DSDI

DSCK

PDWU

ADDR[0:29]

BE[0:3]

CS[0:11]

AACK

TEA

BURST

BDIP

ARETRY

DSDI

VF[0:2]

VFLS[0:1]

WP[0:5]

CT[0:3]

DSCK

PLLL/DSDO

PERIPHERAL

CONTROL

PORT Q

PQ[0:6]/IRQ[0:6]IRQ[0:1]

UNIT (PCU)

XTAL

EXTAL

XFCN, XFCP

MODCLK

CLKOUT

ECROUT

AT[0:1] AT0/PJ1

WR/PK1

MPC509 INTRODUCTION MOTOROLA

USER’S MANUAL Rev. 15 June 98 1-5

1.4 Memory Map

Figure 1-4 MPC509 Memory Map

The MPC family has a unified memory map including instruction memory (I-Mem),

load/store memory (L-Mem), and all memory-mapped registers. I-Mem resides on the

instruction bus; L-Mem resides on the load/store bus. The locations of I-Mem and L-

Mem are selected in the MEMMAP register located in the SIU. In the MPC509, the

SRAM module serves as L-Mem. The MPC509 has no I-Mem module.

0x0000 0000

0x000F EFFF

0xFFF0 0000

0xFFFF EFFF

0x8007 E000

0x8007 EFFF

EXTERNAL

POSS IBLE SRAM

ONE OF FOUR POSSIBLE LOCATIONS

PERIPHERAL

EXTERNAL

CONTROL UNIT

(PCU)

CONTROL REGISTERS

0x8000 0000

EXTERNAL/RESERVED

0x8007 FFFF

0x8007 F000

VECTOR TABLE LOCATION

(IP BIT = 0)

VECTOR TABLE LOCATION

(IP BIT = 1)

LOCATION

(28 KBYTES)

POSS IBLE SRAM

LOCATION

(28 KBYTES)

POSS IBLE SRAM

LOCATION

(28 KBYTES)

POSS IBLE SRAM

LOCATION

(28 KBYTES)

0xFFFF E000

0xFFF0 6FFF

0x0000 6FFF

0x000F E000

SELECTED FOR SRAM

MOTOROLA INTRODUCTION MPC509

1-6 Rev. 15 June 98 USER’S MANUAL

MPC509 SIGNAL DESCRIPTIONS MOTOROLA

USER’S MANUAL Rev. 15 June 98 2-1

SECTION 2

SIGNAL DESCRIPTIONS

This section describes the MPC509 signals and pins. For a more detailed discussion

of a particular signal, refer to the section of the manual that discusses the function

involved.

2.1 Pin List

Table 2-1 MPC509 Pin List

Primary Function(s) Port Function

Address Bus, Data Bus, Chip Selects

ADDR[0:11]/CS[0:11] PA[0:7], PB[0:3]

ADDR[12:15] PB[4:7]

ADDR[16:29] —

DATA[0:31] —

CSBOOT —

Bus Control, Clock, Development Support

BURST, TEA, AACK, TA, BE[0:1],

BE2/ADDR30, BE3 PI[0:7]

AT[0:1], TS, CT[0:3] PJ[1:7]

BDIP, WR, PLLL/DSDO, VF[0:2], VFLS[0: 1] PK[0:7]

WP[0:5] PL[2:7]

BI, BR, BB, BG, ARETRY PM[3:7]

CR/DS —

DSCK, DSDI —

XTAL, EXTAL, XFCN, XFCP, CLKOUT,

ECROUT, PDWU, MODCLK —

Reset, Interrupts

RESET, RESETOUT —

IRQ[0:6] PQ[0:6]

Test

TDI, TDO, TCK, TMS, TRST —

Power

VDDSN, VSSSN —

VDDI, VSSI —

VDDE, VSSE —

VDDKAP1, VDDKAP2 —