DESCRIPTION
The A1128 is a field-programmable, unipolar Hall-effect switch
designed for use in high-temperature applications. This device
uses a chopper-stabilization technique to eliminate offset
inherent in single-element devices.
The devices are externally programmable. A wide range of
programmability is available on the magnetic operate point,
BOP
, while the hysteresis remains fixed. This advanced
feature allows optimization of the sensor IC switchpoint and
can drastically reduce the effects of mechanical placement
tolerances found in end-use production environments.
A proprietary dynamic offset cancellation technique, with
an internal high-frequency clock, reduces the residual offset
voltage, which is normally caused by device overmolding,
temperature dependencies, and thermal stress. Having the Hall
element and amplifier in a single chip minimizes many problems
normally associated with low-level analog signals.
Two package styles provide a magnetically optimized package
for most applications. Type LT is a miniature SOT89/TO-243AA
surface mount package that is thermally enhanced with an
exposed ground tab, and type UA is a three-lead ultramini SIP
for through-hole mounting. The packages are lead (Pb) free,
with 100% matte-tin-plated leadframes.
A1128-DS, Rev. 4
MCO-0000498
FEATURES AND BENEFITS
• Chopper stabilization for stable switchpoints throughout
operating temperature range
• Externally programmable:
▫Operatepoint
(through the
VCC
pin)
▫Outputpolarity
▫OutputfalltimeforreducedEMIin
automotive applications
• On-board voltage regulator for 3 to 24 V operation
• On-chip protection against:
▫Supplytransients
▫Outputshort-circuits
▫Reversebatterycondition
Highly Programmable Hall-Effect Switch
PACKAGES:
Functional Block Diagram
Not to scale
A1128
Trim Control
Program Control
TC Trim Switchpoint
Output Fall Time
Output Polarity
Signal Recovery
Regulator
GND
VC
V+
C
CBYPASS
VOUT
Dynamic Offset
Cancellation
To All Subcircuits
Amp
December 7, 2018
3-pin SIP
(suffix UA,
TS leadform)
3-pin SIP
(suffix UA)
3-pin SOT89
(suffix LT)
LAST-TIME
BUY
Highly Programmable Hall-Effect Switch
A1128
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Notes Rating Unit
Forward Supply Voltage VCC 28 V
Reverse Supply Voltage VRCC –18 V
Forward Output Voltage VOUT 26.5 V
Reverse Output Voltage VROUT –0.7 V
Output Sink Current IOUT(SINK) VCC to VOUT 20 mA
Operating Ambient Temperature TAL temperature range –40 to 150 °C
Maximum Junction Temperature TJ(max) 165 °C
Storage Temperature Tstg –65 to 170 °C
Pinout Diagrams
Terminal List Table
Number Name Function
1 VCC Input power supply
2 GND Ground
3 VOUT Output signal
SELECTION GUIDE
Part Number Packing [1] Package
A1128LLTTR-T [2] 7-in. reel, 1000 pieces/reel 3-pin SOT89/TO-243 surface mount
A1128LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
A1128LUATS-T 13-in. reel, 4000 pieces/reel 3-pin SIP, TS leadform, surface mount
[1] Contact Allegro™ for additional packaging options.
[2] Last-Time Buy: This package variant has reached the end of its life cycle and will no longer be offered by
Allegro. This product is considered obsolete and customer notification has been provided. All orders are
accepted as final builds.
Date of status change: September 3, 2018. Recommended replacement: A1128LUATS-T.
1
3
2
GND
VOUT
VCC
1
3
2
GND
VOUT
VCC
LT Package UA Package
Highly Programmable Hall-Effect Switch
A1128
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ELECTRICAL CHARACTERISTICS
Supply Voltage VCC 3 12 24 V
Supply Current ICC No load on VOUT – – 5.5 mA
Supply Zener Clamp Voltage VZSUPPLY TA = 25°C, ICC = ICC(max) + 3 mA 28 – – V
Output Zener Clamp Voltage VZOUTPUT IOUT = 3 mA 28 – – V
Reverse Battery Zener VRCC – – –18 V
Reverse Battery Current IRCC VCC = –18 V –5 – – mA
Chopping Frequency fC– 400 – kHz
POWER-ON CHARACTERISTICS
Power-On Time tPO TA = 25°C; CLOAD (PROBE) = 10 pF – – 30 µs
Power-On State [2] POS POL = 0; B < BRP
, t > ton – High – –
POL = 1; B < BRP
, t > ton – Low – –
OUTPUT STAGE CHARACTERISTICS
Output Saturation Voltage VOUT(sat) IOUT = 20 mA – 175 400 mV
Output Leakage Current IOFF VOUT = 24 V; Switch state = Off – – 10 µA
Output Current Limit IOUT(lim) Short-Circuit Protection, Output = On 30 – 90 mA
Output Rise Time [3][4] tr
VCC = 12 V, RLOAD = 820 Ω, CLOAD = 10 pF – – 2 µs
VCC = 12 V, RLOAD = 2 kΩ, CLOAD = 4.7 nF – 21 – µs
Output Fall Time [4] tf
FALL = 0, VCC = 12 V, RLOAD = 820 Ω,
CLOAD = 10 pF – – 2 µs
FALL = 1, VCC = 12 V, RLOAD = 2 kΩ,
CLOAD = 4.7 nF – 6.5 – µs
FALL = 2, VCC = 12 V, RLOAD = 2 kΩ,
CLOAD = 4.7 nF – 10 – µs
FALL = 3, VCC = 12 V, RLOAD = 2 kΩ,
CLOAD = 4.7 nF – 12.5 – µs
Output Polarity [2] POL
POL = 0 B > BOP – Low – –
B < BRP – High – –
POL = 1 B > BOP – High – –
B < BRP – Low – –
OPERATING CHARACTERISTICS: Valid with TA = –40°C to 150°C, CBYPASS = 0.1 µF, VCC = 12 V, unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ. Max. Unit [1]
Continued on the next page…
tf
tr
V+ %
100
90
10
0
VOUT(High)
VOUT(Low)
Rise Time and Fall Time Definitions
Highly Programmable Hall-Effect Switch
A1128
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
OPERATING CHARACTERISTICS (continued): Valid with TA = –40°C to 150°C, CBYPASS = 0.1 µF, VCC = 12 V,
unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ. Max. Unit [1]
MAGNETIC CHARACTERISTICS (valid VCC = 3 to 24 V, TJ ≤ TJ(max), unless otherwise noted)
Pre-Programming BOP Target BOPinit
TA = 25°C, BOPPOL = 0 – –35 – G
TA = 25°C, BOPPOL = 1 – 35 – G
Switchpoint Thermal Drift [5] ΔBOP
LT package, BOP = ±650 G –0.14 –0.03 0.08 %/°C
UA package, BOP = ±650 G –0.08 0.00 0.08 %/°C
Hysteresis Bhys BOP – BRP 5 15 30 G
PROGRAMMING CHARACTERISTICS
Switchpoint Magnitude Selection Bits BitBOPSEL – 8 – bit
Switchpoint Polarity Bits BitBOPPOL – 1 – bit
Output Polarity Bits BitPOL – 1 – bit
Fall Time Bits BitFALL – 2 – bit
Device Lock Bits BitLOCK – 1 – bit
Programmable BOP Range BOP
TA = 25°C, BOPPOL = 1 (minimum at
BOPSEL = 255, maximum at BOPSEL = 0) –650 – 20 G
TA = 25°C, BOPPOL = 0 (minimum at
BOPSEL = 0, maximum at BOPSEL = 255) –20 – 650 G
BOP Step Size ResBOP Bit = LSB of BOPSEL – 4 8 G
[1] 1 G (gauss) = 0.1 mT (millitesla).
[2] Output state when device configured as shown in figure 1.
[3] Output Rise Time is governed by external circuit tied to VOUT.
[4] Measured from 10% to 90% steady state output.
[5] Internal trimming utilized to minimize switchpoint drift across the operating temperature range.
Highly Programmable Hall-Effect Switch
A1128
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see Application Information
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA
Package UA, 1-layer PCB with copper limited to solder pads 165 °C/W
Package LT, 1-layer PCB with copper limited to solder pads 180 °C/W
Package LT, 2-layer PCB with 0.94 in2 copper each side 78 °C/W
*Additional thermal information available on Allegro website.
6
7
8
9
2
3
4
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
20 40 60 80 100 120 140 160 180
TA (ºC)
Maximum Allowable VCC (V)
Power Derating Curve
(RθJA = 165 ºC/W)
1-layer PCB, Package UA
(RθJA = 180 ºC/W)
1-layer PCB, Package LT
(RθJA = 78 ºC/W)
2-layer PCB, Package LT
VCC(min)
VCC(max)
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
20 40 60 80 100 120 140 160 180
Temperature (°C)
Power Dissipation, P
D
(mW)
Power Dissipation
(R
θJA
= 165 ºC/W)
1-layer PCB, Package UA
(R
θJA
= 180 ºC/W)
1-layer PCB, Package LT
(RθJA = 78 ºC/W)
2-layer PCB, Package LT
Highly Programmable Hall-Effect Switch
A1128
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE
500
400
300
200
100
0
Ambient Temperature, TA (°C)
Saturation Voltage, VOUT(sat) (V)
-50 -25 0 25 50 75 100 150125 175
VCC (V)
3.3
5
24
ICC = 20 mA
Saturation Voltage versus Ambient Temperature
Ambient Temperature, TA (°C)
Supply Current, ICC (mA)
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 150125 175
VCC (V)
3.3
5
24
Supply Current (Off) versus Ambient Temperature
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 150125 175
Ambient Temperature, TA (°C)
Supply Current, ICC (mA)
VCC (V)
3.3
5
24
Supply Current (On) versus Ambient Temperature
Highly Programmable Hall-Effect Switch
A1128
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APPLICATION INFORMATION
Figure 1. Typical Application Circuit
Figure 2. Concept of Chopper Stabilization Technique
CHOPPER STABILIZATION TECHNIQUE
When using Hall-effect technology, a limiting factor for switch
point accuracy is the small signal voltage developed across the
Hall element. This voltage is disproportionally small relative to
the offset that can be produced at the output of the Hall sensor IC.
This makes it difficult to process the signal while maintaining an
accurate, reliable output over the specified operating temperature
and voltage ranges. Chopper stabilization is a unique approach
used to minimize Hall offset on the chip. Allegro employs a
technique to remove key sources of the output drift induced by
thermal and mechanical stresses. This offset reduction technique
is based on a signal modulation-demodulation process. The
undesired offset signal is separated from the magnetic field-
induced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
its original spectrum at base band, while the DC offset becomes
a high-frequency signal. The magnetic-sourced signal then can
pass through a low-pass filter, while the modulated DC offset is
suppressed. In addition to the removal of the thermal and stress
related offset, this novel technique also reduces the amount of
thermal noise in the Hall sensor IC while completely removing
the modulated residue resulting from the chopper operation. The
chopper stabilization technique uses a high frequency sampling
clock. For demodulation process, a sample and hold technique is
used. This high-frequency operation allows a greater sampling
rate, which results in higher accuracy and faster signal-processing
capability. This approach desensitizes the chip to the effects
of thermal and mechanical stresses, and produces devices that
have extremely stable quiescent Hall output voltages and precise
recoverability after temperature cycling. This technique is made
possiblethroughtheuseofaBiCMOSprocess,whichallowsthe
use of low-offset, low-noise amplifiers in combination with high-
density logic integration and sample-and-hold circuits.
Amp
Regulator
Clock/Logic
Hall Element
Tuned
Filter
Anit-aliasing
LP Filter
2
VCC
1.2 kΩ
100 Ω
V+
IC Output
Tie to device pins using
traces as short as possible
GND
VOUT
C
BYPASS
0.1 µF
120 pF
R
LOAD
C
LOAD
A1128
1
3
A
A
A
A
A
Highly Programmable Hall-Effect Switch
A1128
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FUNCTIONAL DESCRIPTION
When the Output Polarity bit is not set (POL = 0), the A1128
output switches on after the magnetic field at the Hall sensor IC
exceeds the operate point threshold, BOP
. When the magnetic field
is reduced to below the release point threshold, BRP, the device
output switches off. The difference between the magnetic operate
and release points is called the hysteresis of the device, BHYS.
In the alternative case, in which the Output Polarity bit is set
(POL = 1), the A1128 output switches off when the magnetic field
at the Hall sensor IC exceeds the operate point threshold, BOP .
When the magnetic field is reduced to below the release point
threshold, BRP , the device output switches on.
Note that for the Pre-Programming BOP Target, BOPinit , when BOPPOL
= 0 although the operating range is 0 to B+, the initial BOPinit is
actually negative, and likewise, when BOPPOL = 1, although the
operating range 0 to B– , the initial BOPinit is actually positive.
BOP
BRP
BHYS
VOUT(off)
VOUT
VOUT(on)(sat)
Switch On
Switch Off
B+
V+
0
BOPinit
BRP
BOP
BHYS
VOUT(off)
VOUT
VOUT(on)(sat)
Switch On
Switch Off
0
V+
B–
VOUT(off)
VOUT
VOUT(on)(sat)
V+
BOP
BRP
BHYS
Switch Off
Switch On
B+0BOPinit
VOUT(off)
VOUT
VOUT(on)(sat)
V+
BRP
BOP
BHYS
Switch Off
Switch On
0 BOPinit
B–
(A) BOPPOL = 0
POL = 0
(C) BOPPOL = 1
POL = 0
(B) BOPPOL = 0
POL = 1
(D) BOPPOL = 1
POL = 1
BOPinit
Figure 3. Hysteresis Diagrams. These plots demonstrate the behavior of the A1128 with the applied magnetic field
impinging on the branded face of the device case (refer to Package Outline Drawings section). On the horizontal axis,
the B+ direction indicates increasing south or decreasing north magnetic flux density, and the B– direction indicates
increasing north or decreasing south magnetic flux density.
Highly Programmable Hall-Effect Switch
A1128
9
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
OVERVIEW
Programming is accomplished by sending a series of input volt-
age pulses serially through the VCC (supply) pin of the device.
A unique combination of different voltage level pulses controls
the internal programming logic of the device to select a desired
programmable parameter and change its value. There are three
voltage levels that must be taken into account when program-
ming. These levels are referred to as high (VPH), mid (VPM), and
low (VPL).
The A1128 features three programmable modes, Try mode, Blow
mode,andReadmode:
• In Try mode, programmable parameter values are set and mea-
sured simultaneously. A parameter value is stored temporarily,
and reset after cycling the supply voltage.
• In Blow mode, the value of a programmable parameter may
be permanently set by blowing solid-state fuses internal to the
device. Device locking is also accomplished in this mode.
•InReadmode,eachbitmaybeverifiedasblownornotblown.
The programming sequence is designed to help prevent the device
from being programmed accidentally; for example, as a result of
noise on the supply line. Note that, for all programming modes, no
parameter programming registers are accessible after the device-
level LOCK bit is set. The only function that remains accessible is
the overall Fuse Checking feature.
Although any programmable variable power supply can be used
to generate the pulse waveforms, for design evaluations, Allegro
highly recommends using the Allegro Sensor IC Evaluation Kit,
available on the Allegro website On-line Store. The manual for
that kit is available for download free of charge, and provides
additional information on programming these devices. (Note: This
kit is not recommended for production purposes.)
DEFINITION OF TERMS
Register The section of the programming logic that controls the
choice of programmable modes and parameters.
Bit Field The internal fuses unique to each register, represented
as a binary number. Changing the bit field settings of a particular
register causes its programmable parameter to change, based on
the internal programming logic.
PROGRAMMING GUIDELINES
Table 1. Programming Pulse Requirements, Protocol at TA = 25°C
Characteristics Symbol Notes Min. Typ. Max. Unit
Programming Voltage
VPL
Measured at the VCC pin
4.5 5 5.5 V
VPM 12.5 – 14 V
VPH 21 – 27 V
Programming Current IPP
VCC = 5 → 26 V, CBLOW = 0.1 µF (min); minimum supply current required to
ensure proper fuse blowing. 175 – – mA
Pulse Width
tLOW Duration of VPL separating pulses at VPM or VPH 20 – – µs
tACTIVE Duration of pulses at VPM or VPH for key/code selection 20 – – µs
tBLOW Duration of pulse at VPH for fuse blowing 90 100 – µs
Pulse Rise Time tPr VPL to VPM or VPL to VPH 5 – 100 µs
Pulse Fall Time tPf VPM to VPL or VPH to VPL 5 – 100 µs
Blow Pulse Slew Rate SRBLOW 0.375 – – V/µs
Figure 4. Programming pulse definitions (see table 1)
Supply Voltage, V
CC
GND
(Supply
cycled)
Programming
pulses
Blow
pulse
t
ACTIVE
t
LOW
t
LOW
t
BLOW
t
Pr
t
Pf
V
PH
V
PM
V
PL
Highly Programmable Hall-Effect Switch
A1128
10
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Key A series of voltage pulses used to select a register or mode.
Code The number used to identify the combination of fuses
activated in a bit field, expressed as the decimal equivalent of the
binary value. The LSB of a bit field is denoted as code 1, or bit 0.
Addressing Increasing the bit field code of a selected register
by serially applying a pulse train through the VCC pin of the
device. Each parameter can be measured during the addressing
process, but the internal fuses must be blown before the program-
ming code (and parameter value) becomes permanent.
Fuse Blowing Applying a high voltage pulse of sufficient
duration to permanently set an addressed bit by blowing a fuse
internal to the device. Once a bit (fuse) has been blown, it cannot
be reset.
Blow Pulse A high voltage pulse of sufficient duration to blow
the addressed fuse.
Cycling the Supply Powering-down, and then powering-up the
supply voltage. Cycling the supply is used to clear the program-
ming settings in Try mode.
Programming Procedure
Programming involves selection of a register and mode, and then
setting values for parameters in the register for evaluation or fuse
blowing. Figure 8 provides an overview state diagram.
REGISTER SELECTION
Each programmable parameter can be accessed through a specific
register. To select a register, from the Initial state, a sequence of
voltage pulses consisting of one VPH pulse, one VPM pulse, and
then a unique combination of VPH and VPM pulses, is applied
serially to the VCC pin (with no VCC supply interruptions). This
sequence of pulses is called the key, and uniquely identifies each
register. An example register selection key is shown in figure 5.
To simplify Try mode, the A1128 provides a set of four virtual
registers, one for each combination of: BOP selection (BOPSEL),
BOP polarity (BOPPOL), and a facility for transiting BOP magni-
tude values in an increasing or decreasing sequence. These reg-
isters also allow wrapping back to the beginning of the register
after transiting the register.
MODE SELECTION
The same physical registers are used for all programming modes.
TodistinguishBlowmodeandReadmode,whenselectingthe
registers an additional pulse sequence consisting of eleven VPM
pulses followed by one VPH pulse is added to the key. The com-
bined register and mode keys are shown in table 3.
TRY MODE
In Try mode, the bit field addressing is accomplished by apply-
ing a series of VPM pulses to the VCC pin of the device, as shown
in figure 6. Each pulse increases the total bit field value of the
selected parameter, increasing by one on the falling edge of each
additional VPM pulse. When addressing a bit field in Try mode,
the number of VPM pulses is represented by a decimal number
called a code. Addressing activates the corresponding fuse loca-
tions in the given bit field by increasing the binary value of an
internal DAC, up to the maximum possible code. As the value
of the bit field code increases, the value of the programmable
parameterchanges.MeasurementscanbetakenaftereachVPM
pulse to determine if the desired result for the programmable
parameter has been reached. Cycling the supply voltage resets
all the locations in the bit field that have un-blown fuses to their
initial states. This should also be done before selection of a differ-
ent register in Try mode.
When addressing a parameter in Try mode, the bit field address
(code) defaults to the value 1, on the falling edge of the final reg-
ister selection key VPH pulse (see figure 6). A complete example
is shown figure 10. Note that, in the four BOP selection virtual
registers,afterthemaximumcodeisentered,thenextVPMpulse
wraps back to the beginning of the register, and selects code 0.
Figure 5. Example of Try mode register selection pulses, for the BOP
Negative Trim, Up-Counting register.
Figure 6. Try mode bit field addressing pulses.
V
PH
V
PM
V
PL
GND
VCC
V
PH
V
PM
V
PL
GND
VCC
Code 2
Code 1
Code 3
Code 2
n
–2
Code 2
n
–1
Highly Programmable Hall-Effect Switch
A1128
11
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
The four BOP selecting virtual registers allow the programmer
to adjust the BOP parameter for use in north or south magnetic
fields. In addition, values can be traversed from low to high, or
from high to low. Figure 12 shows the relationship between the
BOP parameter and the different Try mode registers. Note: See the
Output Polarity section for information about setting the POL bit
before using Try mode.
The FALL and POL fields are in the same register (FALL is
bits 1:0, and POL is bit 2). Therefore, in Try mode both can be
programmed simultaneously by adding the codes for the two
parameters, and send the sum as the code. For example, sending
code 7 (111) sets FALL to 3 (x11) and sets POL (1xx).
BLOW MODE
After the required code is determined for a given parameter, its
value can be set permanently by blowing individual fuses in the
appropriate register bit field. Blowing is accomplished by select-
ing the register and mode selection key, followed by the appro-
priate bit field address, and ending the sequence with a Blow
pulse. The Blow mode selection key is a sequence of eleven VPM
pulses followed by one VPH pulse. The Blow pulse consists of a
VPH pulse of sufficient duration, tBLOW
, to permanently set an
addressed bit by blowing a fuse internal to the device. The device
power must be cycled after each individual fuse is blown.
Duetopowerrequirements,a0.1μFblowingcapacitor,CBLOW
,
must be mounted between the VCC pin and the GND pin dur-
ing programming, to ensure enough current is available to blow
fuses. If programming in the application, CBYPASS (see figure 1)
can serve the same purpose.
The fuse for each bit in the bit field must be blown individually.
The A1128 built-in circuitry allows only one fuse at a time to be
blown. During Blow mode, the bit field can be considered a “one-
hot” shift register. Table 2 illustrates how to relate the number of
VPM pulses to the binary and decimal value for Blow mode bit
field addressing. It should be noted that the simple relationship
between the number of VPM pulses and the required code is:
2n = Code,
where n is the number of VPM pulses, and the bit field has an ini-
tial state of decimal code 1 (binary 00000001). To correctly blow
the required fuses, the code representing the required parameter
value must be translated to a binary number. For example, as
shown in figure 7, decimal code 5 is equivalent to the binary
number 101. Therefore bit 2 must be addressed and blown, the
device power supply cycled, and then bit 0 must be addressed
and blown. The order of blowing bits, however, is not impor-
tant. Blowing bit 0 first, and then bit 2 is acceptable. A complete
example is shown in figure 11.
Note: After blowing, the programming is not reversible, even
after cycling the supply power. Although a register bit field fuse
cannot be reset after it is blown, additional bits within the same
register can be blown at any time until the device is locked. For
example, if bit 1 (binary 10) has been blown, it is still possible to
blow bit 0. The end result would be binary 11 (decimal code 3).
LOCKING THE DEVICE
After the required code for each parameter is programmed, the
device can be locked to prevent further programming of any
parameters. To do so, perform the following steps:
1. Ensure that the CBLOW capacitor is mounted.
2. Select the Output/Lock Bit register key.
3. Select Blow mode selection key.
4. Address bit 4 (10000) by sending four VPM pulses.
5. Send one Blow pulse, at IPPandSRBLOW, and sustain it for
tBLOW.
6. Delay for a tLOW interval, then power-down.
7. Optionally check all fuses.
Figure 7. Example of code 5 broken into its binary components.
Table 2. Blow Mode Bit Field Addressing
Quantity of
VPM Pulses
Binary
Register Bit Field
Decimal Equivalent
Code
0 0000 0001 1
1 0000 0010 2
2 0000 0100 4
3 0000 1000 8
4 0001 0000 16
5 0010 0000 32
6 0100 0000 64
7 1000 0000 128
(Decimal Equivalent)
Code 5
Bit Field Selection
Address Code Format
Code in Binary
Fuse Blowing
Target Bits
Fuse Blowing
Address Code Format
(Binary)
1 0 1
Bit 2 Bit 0
Code 4 Code 1
(Decimal Equivalents)
Highly Programmable Hall-Effect Switch
A1128
12
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Table 3. Programming Logic Table
Register Name
[Selection Key]
Bit Field Address (Code)
Notes
Binary
(MSB→LSB)
Decimal
Equivalent
TRY MODE REGISTER SELECTIONS
BOP Positive, Trim Up-Counting
[ 2 × VPH ]
0000 0000 0 Increase BOP (South field). Code 1 automatically selected when register
entered, wraps back to code 0.
1111 1111 255 BOP selection is at maximum value.
BOP Negative, Trim Up-Counting
[ VPH → VPM → 2 × VPH ]
0000 0000 0 Increase BOP (North field). Code 1 automatically selected when register
entered, wraps back to code 0.
1111 1111 255 BOP selection is at maximum value.
BOP Positive, Trim Down-Counting
[ 2 × VPH → 4 × VPM → VPH ]
1111 1111 0
Decrease BOP (South field). Code 1 automatically selected when register
entered, wraps back to code 0. Code is automatically inverted (code 1 selects
BOP selection maximum value minus 1.)
0000 0000 255 BOP selection is at minimum value.
BOP Negative, Trim Down-Counting
[VPH → VPM → 2 × VPH
→ 4 × VPM → VPH ]
1111 1111 0
Decrease BOP (North field). Code 1 automatically selected when register
entered, wraps back to code 0. Code is automatically inverted (code 1 selects
BOP selection maximum value minus 1.)
0000 0000 255 BOP selection is at minimum value.
Output / Fuse Checking
[ VPH → 3 × VPM → VPH ]
x01 1 Output Fall Time (FALL). Code 1 automatically selected. Minimum value.
x11 3 Output Fall Time (FALL) selection is at maximum value.
0xx 0 Output Polarity Bit (POL). Default, no fuse blowing required.
POL = 0, see figures 3A and 3C.
1xx 4 Output Polarity Bit (POL). Code 1 automatically selected.
POL = 1, see figures 3B and 3D. Code references a single bit only.
1000 8 Fuse Threshold Low Register. Code 1 automatically selected when register
entered. Checks un-blown fuses. Code references a single bit only.
1001 9 Fuse Threshold High Register. Checks blown fuses.
BLOW OR READ MODE REGISTER SELECTIONS
BOP Selection
(BOPSEL)
[ 2 × VPH
→ 11 × VPM → VPH ]
0000 0000 0 BOP magnitude selection. Default, no fuse blowing required.
Minimum value, corresponding to BOP(min).
1111 1111 255 BOP magnitude selection. Maximum value, corresponding to BOP(max).
BOP Polarity
(BOPPOL)
[ VPH → VPM → VPH
→ 11 × VPM → VPH ]
0 0 South field polarity. Default, no fuse blowing required.
1 1 North field polarity. Code 1 (bit 0) automatically selected.
Output / Lock Bit
[ VPH → 3 × VPM → VPH
→ 11 × VPM → VPH ]
00 0 Output Fall Time (FALL). Default, no fuse blowing required.
11 3 Output Fall Time (FALL) selection is at maximum value. Code 1 (bit 0)
automatically selected.
000 0 Output Polarity Bit (POL). Default, no fuse blowing required.
POL = 0, see figures 3A and 3C.
100 4 Output Polarity Bit (POL). Code 1 (bit 0) automatically selected. Code refers to
bit 2 only. POL = 1, see figures 3B and 3D.
10000 16
Lock bit (LOCK). Locks access to all registers with exception of Fuse
Threshold registers. Code 1 (bit 0) automatically selected in Blow mode. Code
refers to bit 5 only.
0 to 111 1111 –
Read mode bit values. Sequentially selects each bit in selected Blow
mode register for reading bit status as blown or not blown. Code 1 (bit 0)
automatically selected. Monitor VOUT after each pulse.
Highly Programmable Hall-Effect Switch
A1128
13
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
VPH
VPH
(Blow Pulse)
VPH
(Blow Pulse)
VPH
(Blow Pulse)
[Read fuse status on VOUT]
[Optional: test output or check fuse integrity]
VPM
→VPH
VPM VPM
3 × VPM
→VPH
3 × VPM
→VPH
→11×VPM
→VPH
→11×VPM
→VPH
→11×VPM
→VPH
VPH VPH
Register Selection
Try Mode
Read Mode
Initial State
(BOPSEL)
BOP
Selection
(BOPPOL)
BOP
Polarity
VPM
→VPH
→VPH
VPH
→4 × VPM
→ VPH
VPM
→2 × VPH
→4 × VPM
→ VPH
BOP
Positive
Trim Up
BOP
Negative
Trim Up
Code 0
BOP
Positive
Trim Down
BOP
Negative
Trim Down
Output/
Lock Bit
Output/
Fuse
Checking
VPM
Power-up
User power-down
required
Code 2 Code 2n–1
VPM VPM
Code 1
Bit 1 Bit n-1
VPM
Yes
VPM
Bit 0
Bit 1 Bit n-1
VPM VPM
Bit 0
Blow Mode
Blow Fuse
BOP Trim
register?
Figure 8. Programming State Diagram
Highly Programmable Hall-Effect Switch
A1128
14
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FUSE CHECKING
Incorporated in the A1128 is circuitry to simultaneously check
the integrity of the fuse bits. The fuse checking feature is enabled
by using the Fuse Checking registers, and while in Try mode,
applying the codes shown in table 3. The register is only valid
in Try mode and is available before or after the programming
LOCK bit is set.
Selecting the Fuse Threshold High register checks that all blown
fuses are properly blown. Selecting the Fuse Threshold Low
register checks all un-blown fuses are properly intact. The supply
current, ICC,increasesby250μAifamarginalfuseisdetected.
If all fuses are correctly blown or fully intact, there will be no
change in supply current.
OUTPUT POLARITY
When selecting the BOP registers in Try mode, the output polarity
is determined by the value of the Output Polarity bit (POL). The
default value is POL = 0 (fuse un-blown). For applications that
require the output states defined by POL = 1 (see Operating Char-
acteristics table), it is recommended to first permanently blow the
POL bit by selecting the Output / Lock bit register, and code 4.
The output is then defined by POL = 1 when selecting the BOP
Try mode registers. See table 3 for parameter details.
ADDITIONAL GUIDELINES
The additional guidelines in this section should be followed to
ensure the proper behavior of these devices:
• The power supply used for programming must be capable of
delivering at least VPH and 175 mA.
• Be careful to observe the tLOW delay time before powering
down the device after blowing each bit.
• Set the LOCK bit (only after all other parameters have been
programmed and validated) to prevent any further programming
of the device.
READ MODE
TheA1128featuresaReadmodethatallowsthestatusofeach
programmable fuse to be read back individually. The status,
blown or not blown, of the addressed fuse is determined by moni-
toring the state of the VOUT pin. A complete example is shown
in figure 9.
ReadmodeusesthesameregisterselectionkeysasBlowmode
(see table 3), allowing direct addressing of the individual fuses in
the BOPPOL and BOPSEL registers (do not inadvertently send a
BlowpulsewhileinReadmode).Aftersendingtheregisterand
mode selection keys, that is, after the falling edge of the final VPH
pulse in the key, the first bit (the LSB) is selected. Each addi-
tional VPM pulse addresses the next bit in the selected register, up
Figure 9. Read mode example. Pulse sequence for accessing the BOP Selection register
(BOPSEL) and reading back the status of each of the eight bit fields. In this example, the code
(blown fuses) is 20 + 23 + 24 + 26 = 89 (0101 1001). After each address pulse is sent, the voltage
on the VOUT pin will be at GND for blown fuses and at VCC (at VPL or VPM) for un-blown fuses.
V
PH
V
PM
V
PL
V
PH
V
PM
V
PL
GND
Register (and Mode) Selection Key Bit Field (Fuse) Address Codes
Read-out on VOUT pin
1234567 1234567891011
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 0 Blown
Bit 1 Un-Blown
Bit 2 Un-Blown
Bit 3 Blown
Bit 4 Blown
Bit 5 Un-Blown
Bit 6 Blown
Bit 7 Un-Blown
GND
Fuse intact
Fuse blown
VOUT VCC
Don’t Care
Highly Programmable Hall-Effect Switch
A1128
15
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
totheMSB.ReadmodeisavailableonlybeforetheLOCKbit
has been set.
After the final VPH key pulse, and after each VPM address pulse,
if VOUT is low, the corresponding fuse can be considered blown
(thestatusoftheOutputPolaritybit,POL,doesnotaffectRead
mode output values, allowing POL to be tested also). If the output
stateishigh,thefusecanbeconsideredun-blown.DuringRead
mode VOUT must be pulled high using a pull-up resistor (see
RLOAD in the Typical Application Circuit diagram).
Figure 11. Example of Blow mode programming pulses applied to the VCC pin. In this example, the BOP Magnitude
Selection register (BOPSEL) is addressed to code 8 (bit 3, or 3 VPM pulses) and its value is permanently blown.
Figure 10. Example of Try mode programming pulses applied to the VCC pin. In this example, BOP Positive Trim, Down-
Counting register is addressed to code 12 by the eleven VPM pulses (code 1 is selected automatically at the falling edge
of the register-mode selection key).
V
PH
V
PM
V
PL
GND
Register (and Mode) Selection Key
Bit Field (Fuse)
Address Codes
1 2 3 4 5 6 7 1 2 38 9 10 11
VCC
Bit 1
Bit 2
Bit 3
Blow
Pulse
t
LOW
Code 8
V
PH
V
PM
V
PL
GND
Register (and Mode)
Selection Key
Bit Field
Address Codes
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11
VCC
Code 7
Code 8
Code 9
Code 10
Code 11
Code 12
Code 4
Code 5
Code 6
Code 1
Code 2
Code 3
Highly Programmable Hall-Effect Switch
A1128
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Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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BOP SELECTION
The A1128 allows accurate trimming of the magnetic operate
point, BOP , within the application. This programmable feature
reduces effects due to mechanical placement tolerances and
improves performance when used in proximity or vane sensing
applications.
BOP can be set to any value within the range allowed by the
BOPSEL registers. This includes switchpoints of south or north
polarity, and switchpoints at or near the zero crossing point for B.
However, switching is recommended only within the Programma-
ble BOPRange,specifiedintheOperatingCharacteristicstable.
Trimming of BOP is typically done in two stages. In the first
stage, BOP is adjusted temporarily using the Try mode program-
ming features, to find the fuse value that corresponds to the
optimum BOP . After a value is determined, then it can be perma-
nently set using the Blow mode features.
As an aid to programming the A1128 has several options avail-
ableinTryModeforadjustingtheBOP parameter. As shown in
figure 12, these allow trimming of BOP for operation in north or
south polarity magnetic fields. In addition the BOP parameter can
either trim-up, start at the BOP minimum value and increase to
the maximum value, or trim-down, starting at the BOP maximum
value and decreasing to the minimum value.
(A) BOP Positive, Trim Up-Counting Register (B) BOP Positive, Trim Down-Counting Register
(C) BOP Negative, Trim Up-Counting Register (D) BOP Negative, Trim Down-Counting Register
BOP(max)
B+ (south)
B– (north)
BOP(max)
B+ (south)
B– (north)
B+ (south)
B– (north)
B+ (south)
B– (north)
BOP(min)
BOP(max) BOP(max)
BOP(min)
BOP(min) BOP(min)
Try Mode, Bit Field Code
Magnetic Field Intensity, B (G)
00
0255
Try Mode, Bit Field Code
Magnetic Field Intensity, B (G)
0255
Try Mode, Bit Field Code
Magnetic Field Intensity, B (G)
0255
Try Mode, Bit Field Code
Magnetic Field Intensity, B (G)
00
0255
BOP Setpoint BOP Setpoint
BOP Setpoint
BOP Setpoint
Figure 12. BOP profiles for each of the four BOP Selection virtual registers available in Try mode.
Highly Programmable Hall-Effect Switch
A1128
17
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
The device must be operated below the maximum junction tem-
perature of the device, TJ(max) . Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
AllegroMicroSystemswebsite.)
ThePackageThermalResistance,RθJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiationfromthediethroughthedevicecase,RθJC, is relatively
small component of RθJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × IIN
(1)
 ΔT = PD × RθJA (2)
TJ = TA + ΔT (3)
For example, given common conditions such as: TA= 25°C,
VIN = 12 V, IIN = 4 mA, and RθJA = 140 °C/W, then:
PD = VIN × IIN = 12 V × 4 mA = 48 mW
ΔT = PD × RθJA = 48 mW × 140 °C/W = 7°C
TJ = TA + ΔT = 25°C + 7°C = 32°C
A worst-case estimate, PD(max) , represents the maximum allow-
able power level, without exceeding TJ(max) , at a selected RθJA
and TA.
Example:ReliabilityforVCC at TA
=
150°C, package UA, using a
single-layer PCB.
Observe the worst-case ratings for the device, specifically:
RθJA=
165 °C/W, TJ(max) =
165°C, VCC(max)
=
24
V, and
ICC(max) = 5.5 mA.
Calculate the maximum allowable power level, PD(max) . First,
invert equation 3:
ΔTmax = TJ(max) – TA = 165
°C
–
150
°C = 15
°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 165 °C/W = 91 mW
Finally, invert equation 1 with respect to voltage:
 VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 5.5 mA = 16.5 V
The result indicates that, at TA, the application and device can
dissipateadequateamountsofheatatvoltages≤VCC(est) .
Compare VCC(est) to VCC(max) . If VCC(est) ≤VCC(max) , then
reliable operation between VCC(est) and VCC(max) requires
enhanced RθJA. If VCC(est) ≥VCC(max) , then operation between
VCC(est) and VCC(max) is reliable under these conditions.
POWER DERATING
Highly Programmable Hall-Effect Switch
A1128
18
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
DActive Area Depth, 0.77 mm
Hall element; not to scale
D
E
E
EE
1.14
2.24
B
Parting Line
3
2
1
A
C
A
10° REF
10° REF
6° REF
Gate and tie bar burr area
B
1.04 ±0.15
2.16 REF
0.38 MIN
1.73 ±0.10
2X 1.50 NOM
Reference land pattern layout;
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances
4.47 +0.13
–0.08
2.57 +0.03
–0.28
4.14 +0.10
–0.20
0.41 +0.03
–0.06
0.51 +0.05
–0.07
0.43 +0.05
–0.07
1.45 +0.15
–0.05
Branding scale and appearance at supplier discretion
Standard Branding Reference View
NNN
1
= Supplier emblem
N = Last three digits of device part number
Branded Face
For Reference Only; not for tooling use (reference DWG-9064)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Updated package drawing only. Allegro package assembly tooling has not changed.
1.50
1.20
0.80
2.60
2.00
2.50
0.70
4.60
CPCB Layout Reference View
Basic pads for low-stress, not self-aligning
Additional pad for low-stress, self-aligning
Additional area for IPC reference layout
PACKAGE OUTLINE DRAWINGS
Package LT 3-Pin SOT-89
LAST-TIME
BUY
Highly Programmable Hall-Effect Switch
A1128
19
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Package UA 3-Pin SIP
2 31
0.79 REF
1.27 NOM
2.16
MAX
0.51
REF
45°
C
45°
B
E
E
E
2.04
1.44
Gate burr area
A
B
C
Dambar removal protrusion (6X)
A
D
E
D
Branding scale and appearance at supplier discretion
Hall element, not to scale
Active Area Depth, 0.50 mm REF
For Reference Only; not for tooling use (reference DWG-9049)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Standard Branding Reference View
= Supplier emblem
N = Last three digits of device part number
NNN
1
Mold Ejector
Pin Indent
Branded
Face
4.09 +0.08
–0.05
0.41 +0.03
–0.06
3.02 +0.08
–0.05
0.43 +0.05
–0.07
15.75 ±0.51
1.52 ±0.05
Highly Programmable Hall-Effect Switch
A1128
20
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Package UA 3-Pin SIP, TS Leadform
E
1.57
0.97
1.27
PCB Layout Reference View
For Reference Only; Not for Tooling Use
(For package, reference DWG-9065; for lead forming, reference DWG-9116)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
DActive Area Depth, 0.50 mm ±0.08
EReference land pattern layout;
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances
Branding scale and appearance at supplier discretion
Gate and tie bar burr area
A
B
C
Dambar removal protrusion (8×)
CStandard Branding Reference View
NNN
1
= Supplier emblem
N = Last three digits of device part number
45°
B
4.09 +0.08
–0.05
0.79 REF
45°
Enlargement View A
0.41 +0.03
–0.06
0+0.10
–0.051
8°
0°
0.51 MIN
View A
45°
D
1.52 ±0.05
Mold Ejector
Pin Indent
10°
Branded
Face
1.27 NOM
2.41 ±0.13 1.02
MAX
A
0.43 +0.05
–0.07
3.02 +0.08
–0.05
2 31
Highly Programmable Hall-Effect Switch
A1128
21
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Number Date Description
3 September 6, 2018 Minor editorial updates
4 December 7, 2018 Updated -LT package option status to Last-Time Buy; added UA package TS leadform option
Copyright ©2018, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
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