Data Sheet Low Power, 24-Bit, Sigma-Delta ADC with 10 V and 0 mA to 20 mA Inputs AD4112 FEATURES GENERAL DESCRIPTION 24-bit ADC with integrated analog front end Up to 6.2 kSPS per channel (161 s per channel) 16 noise free bits at 1 kSPS per channel 85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel 10 V inputs, 4 differential or 8 single-ended Overrange up to 20 V 1 M impedance 0.06% accuracy at 25C 0 mA to 20 mA inputs, 4 single-ended Overrange from -0.5 mA to +24 mA 60 impedance 0.08% accuracy at 25C On-chip 2.5 V reference 0.12% accuracy at 25C, 5 ppm/C (typical) drift Internal or external clock Power supplies AVDD = 3.0 V to 5.5 V IOVDD = 2 V to 5.5 V Total IDD = 3.9 mA Temperature range: -40C to +105C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible The AD4112 is a low power, low noise, 24-bit, sigma-delta (-) analog-to-digital converter (ADC) that integrates an analog front end (AFE) for fully differential or single-ended, high impedance (1 M) bipolar, 10 V voltage inputs, and 0 mA to 20 mA current inputs. APPLICATIONS Process control PLC and DCS modules Rev. 0 The AD4112 also integrates key analog and digital signal conditioning blocks to configure eight individual setups for each analog input channel in use. The AD4112 features a maximum channel scan rate of 6.2 kSPS (161 s) for fully settled data. The embedded 2.5 V, low drift (5 ppm/C), band gap internal reference (with output reference buffer) reduces the external component count. The digital filter allows flexible settings, including simultaneous 50 Hz and 60 Hz rejection at a 27.27 SPS output data rate. The user can select between the different filter settings depending on the demands of each channel in the application. The automatic channel sequencer enables the ADC to switch through each enabled channel. The precision performance of the AD4112 is achieved by integrating the proprietary iPassivesTM technology from Analog Devices, Inc. The AD4112 is factory calibrated to achieve a high degree of specified accuracy. The AD4112 operates with a single power supply, making it easy to use in galvanically isolated applications. The specified operating temperature range is -40C to +105C. The AD4112 is housed in a 40-lead, 6 mm x 6 mm LFCSP package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD4112 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 CRC Calculation......................................................................... 39 Applications ....................................................................................... 1 Integrated Functions ...................................................................... 41 General Description ......................................................................... 1 General-Purpose Ouputs .......................................................... 41 Revision History ............................................................................... 3 Delay ............................................................................................ 41 Functional Block Diagram .............................................................. 4 16-Bit/24-Bit Conversions......................................................... 41 Specifications..................................................................................... 5 DOUT_RESET ........................................................................... 41 Timing Characteristics ................................................................ 8 Synchronization .......................................................................... 41 Absolute Maximum Ratings.......................................................... 10 Error Flags ................................................................................... 42 Thermal Resistance .................................................................... 10 DATA_STAT ............................................................................... 42 ESD Caution ................................................................................ 10 IOSTRENGTH ........................................................................... 42 Pin Configuration and Function Descriptions ........................... 11 Internal Temperature Sensor .................................................... 42 Typical Performance Characteristics ........................................... 13 Applications Information .............................................................. 43 Noise Performance and Resolution .............................................. 18 Grounding and Layout .............................................................. 43 Theory of Operation ...................................................................... 20 Register Summary .......................................................................... 44 Power Supplies ............................................................................ 21 Register Details ............................................................................... 46 Digital Communication............................................................. 21 Communications Register ......................................................... 46 AD4112 Reset.............................................................................. 22 Status Register ............................................................................. 47 Configuration Overview ........................................................... 23 ADC Mode Register ................................................................... 48 Circuit Description ......................................................................... 26 Interface Mode Register ............................................................ 49 Multiplexer .................................................................................. 26 Register Check ............................................................................ 50 Current Inputs ............................................................................ 27 Data Register ............................................................................... 50 Voltage Inputs ............................................................................. 27 GPIO Configuration Register ................................................... 51 AD4112 Reference ...................................................................... 27 ID Register................................................................................... 52 Buffered Reference Input........................................................... 29 Channel Register 0 ..................................................................... 52 Clock Source ............................................................................... 29 Channel Register 1 to Channel Register 15 ............................ 53 Digital Filter .................................................................................... 30 Setup Configuration Register 0 ................................................ 54 Sinc5 + Sinc1 Filter..................................................................... 30 Sinc3 Filter ................................................................................... 30 Setup Configuration Register 1 to Setup Configuration Register 7 ..................................................................................... 54 Single Cycle Settling ................................................................... 31 Filter Configuration Register 0 ................................................. 55 Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 31 Filter Configuration Register 1 to Filter Configuration Register 7 ..................................................................................... 56 Operating Modes ............................................................................ 34 Continuous Conversion Mode ................................................. 34 Continuous Read Mode ............................................................. 35 Single Conversion Mode ........................................................... 36 Standby and Power-Down Modes ............................................ 37 Calibration ................................................................................... 37 Digital Interface .............................................................................. 38 Offset Register 0 ......................................................................... 56 Offset Register 1 to Offset Register 7 ....................................... 56 Gain Register 0............................................................................ 57 Gain Register 1 to Gain Register 7 ........................................... 57 Outline Dimensions ....................................................................... 58 Ordering Guide .......................................................................... 58 Checksum Protection................................................................. 38 Rev. 0 | Page 2 of 58 Data Sheet AD4112 REVISION HISTORY 8/2018--Revision 0: Initial Version Rev. 0 | Page 3 of 58 AD4112 Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDD REGCAPA REF- REF+ IOVDD BUFFERED PRECISION REFERENCE 1.8V LDO VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VINCOM REFOUT REGCAPD 1.8V LDO INT REF PRECISION VOLTAGE DIVIDER RAIL TO RAIL REFERENCE INPUT BUFFERS CS SCLK MUX VBIAS- DIGITAL FILTER - ADC SERIAL INTERFACE IIN3+ IIN2+ IIN1+ IIN0+ DIN DOUT/RDY SYNC ERROR 50 AD4112 GPO CONTROL TEMPERATURE SENSOR AVSS GPO0 Figure 1. Rev. 0 | Page 4 of 58 GPO1 XTAL AND INTERNAL CLOCK OSCILLATOR CIRCUITRY XTAL1 XTAL2/CLKIO 16465-001 IIN0- IIN1- IIN2- IIN3- Data Sheet AD4112 SPECIFICATIONS AVDD = 3.0 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = 0 V, DGND = 0 V, VBIAS- = 0 V, REF+ = 2.5 V, REF- = AVSS, internal master clock (MCLK) = 2 MHz, TA = TMIN to TMAX (-40C to +105C), unless otherwise noted. Table 1. Parameter VOLTAGE INPUTS Differential Input Voltage Range1 Absolute (Pin) Input Voltage Input Impedance Offset Error2 Offset Drift Gain Error Gain Drift Integral Nonlinearity (INL) Total Unadjusted Error (TUE)4 Power Supply Rejection Common-Mode Rejection At DC At 50 Hz, 60 Hz Normal Mode Rejection4 Resolution Noise CURRENT INPUTS Input Current Range Absolute (Pin) Input Voltage Input Impedance6 Offset Error2 Offset Drift Gain Error Gain Drift INL TUE4 Power Supply Rejection Normal Mode Rejection4 Resolution Noise ADC SPEED AND PERFORMANCE ADC Output Data Rate (ODR) No Missing Codes4 Test Conditions/Comments Min Specified performance Functional AVDD 4.75 V AVDD = 3.0 V -10 -VREF x 10 -20 -12 1 Max Unit +10 +VREF x 10 +20 +12 70 V V V V M mV V/C % of FS ppm/C % of FSR % of FSR % of FSR % of FSR % of FSR dB 85 120 dB dB 71 90 85 90 dB dB 25C 1.5 7 0.05 1 0.01 Internal full-scale calibration3, 25C 25C, internal VREF -40C to +105C, internal VREF 25C, external VREF -40C to +105C, external VREF AVDD for VIN = 1 V VIN = 1 V 20 Hz output data rate (postfilter), 50 Hz 1 Hz and 60 Hz 1 Hz 50 Hz 1 Hz and 60 Hz 1 Hz Internal clock, 20 SPS ODR (postfilter) External clock, 20 SPS ODR (postfilter) See Table 6 and Table 8 See Table 6 and Table 8 0.06 0.1 0.06 0.08 -0.5 AVSS -0.05 54 Factory calibrated gain, 25C 25C, internal VREF -40C to +105C, internal VREF 25C, external VREF -40C to +105C, external VREF AVDD for IIN = 10 mA 50 Hz 1 Hz and 60 Hz 1 Hz Internal clock, 20 SPS ODR (postfilter) External clock, 20 SPS ODR (postfilter) See Table 7 and Table 9 See Table 7 and Table 9 One channel, see Table 6 Excluding sinc3 filter 15 kHz notch Rev. 0 | Page 5 of 58 Typ 60 2 3 0.02 10 0.01 +24 AVDD +0.055 75 0.08 0.2 0.08 0.2 0.5 71 90 85 90 1.25 24 mA V A nA/C % of FS ppm/C % of FSR % of FSR % of FSR % of FSR % of FSR A/V dB dB 31,250 SPS Bits AD4112 Parameter INTERNAL REFERENCE Output Voltage Initial Accuracy4, 7 Temperature Coefficient Reference Load Current, ILOAD Power Supply Rejection Load Regulation Voltage Noise Voltage Noise Density Turn On Settling Time Short-Circuit Current, ISC EXTERNAL REFERENCE INPUTS Differential Input Range Absolute Voltage Limits Buffers Disabled Buffers Enabled REF Input Current Buffers Disabled Input Current Input Current Drift Buffers Enabled Input Current Input Current Drift Normal Mode Rejection Common-Mode Rejection TEMPERATURE SENSOR Accuracy Sensitivity GENERAL-PURPOSE OUTPUTS (GPO0, GPO1) Floating State Output Capacitance Output Voltage4 High, VOH Low, VOL CLOCK Internal Clock Frequency Accuracy Duty Cycle Output Voltage Low, VOL High, VOH Crystal Frequency Start-Up Time External Clock (CLKIO) Duty Cycle Data Sheet Test Conditions/Comments 100 nF external capacitor to AVSS REFOUT with respect to AVSS REFOUT, TA = 25C Min Typ 2.5 -0.12 5 -10 AVDD (line regulation) VOUT/ILOAD eN, 0.1 Hz to 10 Hz, 2.5 V reference eN, 1 kHz, 2.5 V reference 100 nF REFOUT capacitor VREF = (REF+) - (REF-) Max +0.12 +12 +10 95 32 4.5 215 200 25 1 2.5 AVSS -0.05 AVSS External clock Internal clock Unit V % of V ppm/C mA dB ppm/mA V rms nV/Hz s mA AVDD V AVDD +0.05 AVDD V V 9 0.75 2 A/V nA/V/C nA/V/C 100 0.25 nA nA/C 95 dB 2 477 C V/K 5 pF See the rejection parameter After user calibration at 25C With respect to AVSS Source current (ISOURCE) = 200 A Sink current (ISINK) = 800 A AVDD - 1 AVSS + 0.4 2 -2.5% +2.5% 50 30 Rev. 0 | Page 6 of 58 16 10 2 50 MHz % % 0.4 V V 16.384 MHz s MHz % 0.8 x IOVDD 14 V V 2.048 70 Data Sheet Parameter LOGIC INPUTS Input Voltage4 High, VINH Low, VINL Hysteresis Leakage Current LOGIC OUTPUT (DOUT/RDY) Output Voltage4 High, VOH Low, VOL Leakage Current4 Output Capacitance POWER REQUIREMENTS Power Supply Voltage AVDD to AVSS AVSS to DGND IOVDD to DGND IOVDD to AVSS POWER SUPPLY CURRENTS8 Full Operating Mode AVDD Current IOVDD Current Standby Mode Power-Down Mode POWER DISSIPATION Full Operating Mode Standby Mode Power-Down Mode AD4112 Test Conditions/Comments Min 2 V IOVDD < 2.3 V 0.65 x IOVDD 0.7 x IOVDD 2.3 V IOVDD 5.5 V 2 V IOVDD < 2.3 V 2.3 V IOVDD 5.5 V IOVDD 2.7 V IOVDD < 2.7 V Typ 0.35 x IOVDD 0.7 0.25 0.2 +10 0.8 x IOVDD 0.8 x IOVDD 0.8 x IOVDD 0.4 0.4 0.4 +10 -10 10 3.0 -2.75 2 For AVSS < DGND All outputs unloaded, digital inputs connected to IOVDD or DGND Including internal reference Internal clock All VIN = 0 V All VIN = 0 V 3.3 0.6 120 90 19.5 600 450 1 Unit V 0.08 0.04 -10 IOVDD 4.5 V, ISOURCE = 1 mA 2.7 V IOVDD < 4.5 V, ISOURCE = 500 A IOVDD < 2.7 V, ISOURCE = 200 A IOVDD 4.5 V, ISINK = 2 mA 2.7 V IOVDD < 4.5 V, ISINK = 1 mA IOVDD < 2.7 V, ISINK = 400 A Floating state Floating state Max V V V V V A V V V V V V A pF 5.5 0 5.5 6.35 V V V V 3.7 0.8 mA mA A A mW W W The full specification is guaranteed for a differential input signal of 10 V. The device is functional up to a differential input signal of VREF x 10. However, the specified absolute (pin) voltage must not be exceeded for the proper function. Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. 3 The gain calibration register is overwritten by performing an internal full-scale calibration. Alternatively, a system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate for the channel that is calibrated. 4 Specification is not production tested but is supported by characterization data at the initial product release. 5 This maximum specification is only possible if IINx- is biased so that the current through the resistor is less than 24 mA. It is not possible with IINx- connected to 0 V. 6 This specification shows the impedance seen between current input pins. The current is measured across a 50 sense resistor. 7 This specification includes moisture sensitivity level (MSL) preconditioning effects. 8 This specification is with no load on the REFOUT pin and the digital output pins. 2 Rev. 0 | Page 7 of 58 AD4112 Data Sheet TIMING CHARACTERISTICS IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, capacitive load (CLOAD) = 20 pF, unless otherwise noted. Table 2. Parameter SCLK t3 t4 READ OPERATION t1 t23 t55 t6 t7 WRITE OPERATION t8 t9 t10 t11 Limit at TMIN, TMAX Unit Description1, 2 25 25 ns min ns min SCLK high pulse width SCLK low pulse width 0 15 40 0 12.5 25 2.5 20 0 10 ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min CS falling edge to DOUT/RDY active time IOVDD = 4.75 V to 5.5 V IOVDD = 2 V to 3.6 V SCLK active edge to data valid delay4 IOVDD = 4.75 V to 5.5 V IOVDD = 2 V to 3.6 V Bus relinquish time after CS inactive edge 0 8 8 5 ns min ns min ns min ns min CS falling edge to SCLK active edge setup time4 Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high/low 1 Sample tested during initial release to ensure compliance. See Figure 2 and Figure 3. 3 This parameter is defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 DOUT/RDY returns high after a read of the data register. In single-conversion mode and continuous conversion mode, the same data can be read again, if required, while DOUT/RDY is high. However, care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. 2 Rev. 0 | Page 8 of 58 Data Sheet AD4112 Timing Diagrams CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 16465-002 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 2. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 3. Write Cycle Timing Diagram Rev. 0 | Page 9 of 58 16465-003 DIN (I) AD4112 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. THERMAL RESISTANCE Table 3. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Parameter AVDD to AVSS AVDD to DGND IOVDD to DGND IOVDD to AVSS AVSS to DGND VINx to AVSS IINx+ to AVSS IINx- to AVSS Current Input Current1 Reference Input Voltage to AVSS Digital Input Voltage to DGND Digital Output Voltage to DGND Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Soldering, Reflow Temperature 1 Rating -0.3 V to +6.5 V -0.3 V to +6.5 V -0.3 V to +6.5 V -0.3 V to +7.5 V -3.25 V to +0.3 V -50 V to +50 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -50 mA to +50 mA -0.3 V to AVDD + 0.3 V -0.3 V to IOVDD + 0.3 V -0.3 V to IOVDD + 0.3 V 10 mA -40C to +105C -65C to +150C 150C 260C JA is specified for a device soldered on a JEDEC test board for surface-mount packages. Table 4. Thermal Resistance Package Type CP-40-151 4-Layer JEDEC Board 1 JA Unit 34 C/W Thermal impedance simulated values are based on JEDEC 2S2P thermal test board with 16 thermal vias. See JEDEC JESD51. ESD CAUTION The absolute maximum current input current, current input voltage, and IINx- voltage must all be within the specified limits. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 10 of 58 Data Sheet AD4112 40 39 38 37 36 35 34 33 32 31 REF+ REF- GPO1 IIN3+ IIN2+ IIN1+ IIN0+ IIN0- IIN1- IIN2- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 AD4112 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 IIN3- VIN7 VIN6 VIN5 VIN4 GPO0 DNC DNC REGCAPD DGND NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT ANYTHING TO THIS PIN. PIN 24 IS INTERNALLY CONNECTED TO AVSS. 2. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON THE PCB UNDER THE EXPOSED PAD TO CONFER MECHANICAL STRENGTH AND FOR HEAT DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO AVSS THROUGH THIS PAD ON THE PCB. 16465-004 VBIAS- XTAL1 XTAL2/CLKIO DOUT/RDY DIN SCLK CS ERROR SYNC IOVDD 11 12 13 14 15 16 17 18 19 20 VINCOM VIN0 VIN1 VIN2 VIN3 REFOUT REGCAPA AVSS AVDD DNC Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic1 VINCOM Type2 AI 2 VIN0 AI 3 VIN1 AI 4 VIN2 AI 5 VIN3 AI 6 REFOUT AO 7 REGCAPA AO 8 9 10 11 AVSS AVDD DNC VBIAS- P P N/A AI 12 13 XTAL1 XTAL2/CLKIO AI AI/DI 14 DOUT/RDY DO 15 DIN DI Description Voltage Input Common. Voltage inputs are referenced to this pin when configured as single-ended. Connect this pin to analog ground. Voltage Input 0. Input referenced to VINCOM in single ended configuration, or a positive input of an input pair with VIN1 in differential configuration. Voltage Input 1. Input referenced to VINCOM in single ended configuration, or a negative input of an input pair with VIN0 in differential configuration. Voltage Input 2. Input referenced to VINCOM in single ended configuration, or a positive input of an input pair with VIN3 in differential configuration. Voltage Input 3. Input referenced to VINCOM in single ended configuration, or a negative input of an input pair with VIN2 in differential configuration. Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS. Decouple this pin to AVSS using a 0.1 F capacitor. Analog Low Dropout (LDO) Regulator Output. Decouple this pin to AVSS using a 1 F capacitor and a 0.1 F capacitor. Negative Analog Supply. This supply ranges from -2.75 V to 0 V and is nominally set to 0 V. Analog Supply Voltage. This voltage ranges from 3.0 V to 5.5 V with respect to AVSS. Do Not Connect. Do not connect anything to this pin. Voltage Bias Negative. The pin is setting bias voltage for the voltage input analog front-end. Connect this pin to AVSS. Input 1 for Crystal. Input 2 for Crystal/Clock Input or Output. See the CLOCKSEL bit settings in the ADCMODE register for more information. Serial Data Output/Data Ready Output. This pin serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. The data-word/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register address (RA) bits of the communications register identifying the appropriate register. Data is clocked in on the rising edge of SCLK. Rev. 0 | Page 11 of 58 AD4112 Data Sheet Pin No. 16 Mnemonic1 SCLK Type2 DI 17 CS DI 18 ERROR DI/O 19 SYNC DI 20 IOVDD P 21 22 DGND REGCAPD P AO 23 24 25 26 DNC DNC GPO0 VIN4 N/A N/A DO AI 27 VIN5 AI 28 VIN6 AI 29 VIN7 AI 30 31 32 33 34 35 36 37 38 39 IIN3- IIN2- IIN1- IIN0- IIN0+ IIN1+ IIN2+ IIN3+ GPO1 REF- AI AI AI AI AI AI AI AI DO AI 40 REF+ AI EP P 1 2 Description Serial Clock Input. This serial clock input is for data transfers to and from the ADC. SCLK has a Schmitt triggered input. Chip Select Input. This pin is an active low logic input used to select the ADC. Use CS to select the ADC in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT/RDY used to interface with the device. When CS is high, the DOUT/RDY output is tristated. Error Input/Output or General-Purpose Output. This pin can be used in one of the following three modes: Active low error input mode. This mode sets the ADC_ERROR bit in the status register. Active low, open-drain error output mode. The status register error bits are mapped to the ERROR pin. The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any device can be observed. General-purpose output mode. The status of the pin is controlled by the ERR_DAT bit in the GPIOCON register. The pin is referenced between IOVDD and DGND. Synchronization Input. Allows synchronization of the digital filters and analog modulators when using multiple AD4112 devices. Digital I/O Supply Voltage. The IOVDD voltage ranges from 2 V to 5.5 V (nominal). IOVDD is independent of AVDD. For example, IOVDD can be operated at 3.3 V when AVDD equals 5 V, or vice versa. If AVSS is set to -2.5 V, the voltage on IOVDD must not exceed 3.6 V. Digital Ground. Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using a 1 F capacitor. Do Not Connect. Do not connect anything to this pin. Do Not Connect. Do not connect anything to this pin. This pin is internally connected to AVSS. General-Purpose Output. Logic output on this this pin is referred to the AVDD and AVSS supplies. Voltage Input 4. Input referenced to VINCOM in single ended configuration, or a positive input of an input pair with VIN5 in differential configuration. Voltage Input 5. Input referenced to VINCOM in single ended configuration, or a negative input of an input pair with VIN4 in differential configuration. Voltage Input 6. Input referenced to VINCOM in single ended configuration, or a positive input of an input pair with VIN7 in differential configuration. Voltage Input 7. Input referenced to VINCOM in single ended configuration, or a negative input of an input pair with VIN6 in differential configuration. Current Input Return 3. Connect this pin to analog ground. Current Input Return 2. Connect this pin to analog ground. Current Input Return 1. Connect this pin to analog ground. Current Input Return 0. Connect this pin to analog ground. Current Input 0. Current Input 1. Current Input 2. Current Input 3. General-Purpose Output. Logic output on this pin is referred to the AVDD and AVSS supplies. Reference Input Negative Terminal. REF- can span from AVSS to AVDD - 1 V. Reference can be selected through the REF_SELx bits in the setup configuration registers. Reference Input Positive Terminal. An external reference can be applied between REF+ and REF-. REF+ can span from AVDD to AVSS + 1 V. Reference can be selected through the REF_SELx bits in the setup configuration registers. Exposed Pad. Solder the exposed pad to a similar pad on the PCB under the exposed pad to confer mechanical strength to the package and for heat dissipation. The exposed pad must be connected to AVSS through this pad on the PCB. Note that, throughout this data sheet, the dual function pin mnemonics are referenced by the relevant function only. AI means analog input, AO means analog output, P means power supply, N/A means not applicable, DI means digital input, DO means digital output, and DI/O means bidirectional digital input/output. Rev. 0 | Page 12 of 58 Data Sheet AD4112 TYPICAL PERFORMANCE CHARACTERISTICS 300 8388628 8388627 250 8388626 200 OCCURRENCE ADC CODE 8388625 8388624 8388623 8388622 150 100 8388621 50 8388620 900 1000 SAMPLE NUMBER 0 ADC CODE Figure 5. Noise (Voltage Input, Output Data Rate = 1.25 SPS) Figure 8. Histogram (Voltage Input, Output Data Rate = 1.25 SPS) 8388680 35 8388660 30 8388640 OCCURRENCE 25 8388600 20 15 8388580 10 8388560 5 0 100 200 300 400 500 600 700 800 900 1000 SAMPLE NUMBER 0 8388559 8388563 8388567 8388571 8388575 8388579 8388583 8388587 8388591 8388595 8388599 8388603 8388607 8388611 8388615 8388619 8388623 8388627 8388631 8388635 8388639 8388643 8388647 8388651 8388655 8388659 8388663 8388540 ADC CODE 16465-109 8388620 16465-106 ADC CODE 16465-108 800 8388627 700 8388626 600 8388625 500 8388624 400 8388623 300 8388622 200 8388621 100 8388620 0 16465-105 8388619 Figure 9. Histogram (Voltage Input, Output Data Rate = 2.5 kSPS) Figure 6. Noise (Voltage Input, Output Data Rate = 2.5 kSPS) 20 8388750 18 8388700 16 14 OCCURRENCE 8388600 8388550 12 10 8 6 4 8388500 2 100 200 300 400 500 600 700 800 900 1000 SAMPLE NUMBER Figure 7. Noise (Voltage Input, Output Data Rate = 31.25 kSPS) 0 ADC CODE 16465-110 0 1 10 19 28 37 46 55 64 73 82 91 100 109 118 127 136 145 154 163 172 181 190 199 208 217 8388450 16465-107 ADC CODE 8388650 Figure 10. Histogram (Voltage Input, Output Data Rate = 31.25 kSPS) Rev. 0 | Page 13 of 58 AD4112 Data Sheet 1000 8388382.5 900 8388382.0 800 700 OCCURRENCE ADC CODE 8388381.5 8388381.0 8388380.5 600 500 400 300 200 8388380.0 100 100 200 300 400 500 600 700 800 900 1000 SAMPLE NUMBER 0 8388380 8388382 ADC CODE Figure 14. Histogram (Current Input, Output Data Rate = 1.25 SPS) Figure 11. Noise (Current Input, Output Data Rate = 1.25 SPS) 60 8388420 50 8388400 40 OCCURRENCE 8388440 8388380 30 8388360 20 8388340 10 100 200 300 400 500 600 700 800 900 1000 SAMPLE NUMBER 8388330 8388334 8388338 8388342 8388346 8388350 8388354 8388358 8388362 8388366 8388370 8388374 8388378 8388382 8388386 8388390 8388394 8388398 8388402 8388406 8388410 8388414 8388418 8388422 8388426 0 ADC CODE Figure 15. Histogram (Current Input, Output Data Rate = 31.25 SPS) Figure 12. Noise (Current Input, Output Data Rate = 2.5 kSPS) 25 8388750 8388700 20 OCCURRENCE 8388650 8388600 8388550 15 10 5 8388500 100 200 300 400 500 600 700 800 900 1000 SAMPLE NUMBER 8388297 8388304 8388311 8388318 8388325 8388332 8388339 8388346 8388353 8388360 8388367 8388374 8388381 8388388 8388395 8388402 8388409 8388416 8388423 8388430 8388437 8388444 8388451 8388458 8388465 0 ADC CODE Figure 13. Noise (Current Input, Output Data Rate = 31.25 kSPS) 16465-116 0 8388450 16465-113 ADC CODE 16465-115 0 8388320 16465-112 ADC CODE 8388381 16465-114 0 16465-111 8388379.5 Figure 16. Histogram (Current Input, Output Data Rate = 31.25 kSPS) Rev. 0 | Page 14 of 58 AD4112 -60 10 -70 8 -80 6 -90 4 INL (ppm OF FSR) -100 -110 -120 0 -2 -130 -4 -140 -6 -150 -8 10 20 30 40 50 -10 -10 16465-117 -160 60 VIN FREQUENCY (Hz) Figure 17. Common-Mode Rejection Ratio (CMRR) vs. VIN Frequency (VIN = 0.1 V, 10 Hz to 70 Hz, Output) -8 -6 -4 -2 0 VIN (V) 2 4 6 8 10 Figure 20. Integral Nonlinearity (INL) vs. Input Range (Voltage Input) -50 35 -60 30 -70 25 OCCURRENCE PSRR (dB) 2 16465-120 CMRR (dB) Data Sheet -80 -90 -100 20 15 10 -110 5 10 100 1k 10k 100k 1M 10M 100M VIN FREQUENCY (Hz) Figure 18. Power Supply Rejection Ratio (PSRR) vs. VIN Frequency 0 1.996 1.997 1.998 1.999 2.000 2.001 2.002 2.003 FREQUENCY (MHz) 16465-121 1 16465-118 -120 Figure 21. Internal Oscillator Frequency/Accuracy Distribution Histogram 10 2.01 8 2.00 6 FREQUENCY (MHz) 2 0 -2 -4 1.99 1.98 1.97 -6 -10 -0.5 4.5 9.5 14.5 19.5 24.5 IIN (mA) 1.95 -40 -30 -20 -10 0 10 20 30 40 50 60 TEMPERATURE (C) 70 80 90 100 Figure 22. Internal Oscillator Frequency vs. Temperature Figure 19. Integral Nonlinearity (INL) vs. Input (Current Input) Rev. 0 | Page 15 of 58 16465-122 1.96 -8 16465-119 INL (ppm OF FSR) 4 AD4112 Data Sheet 35 900 800 30 700 OCCURRENCE OCCURRENCE 25 600 500 400 300 20 15 10 200 -5 -4 -3 -2 -1 0 1 2 3 OFFSET ERROR (mV) 4 5 6 0 16465-123 0 7 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 GAIN ERROR DRIFT (ppm/C) Figure 23. Offset Error Distribution Histogram (Voltage Input) 16465-126 5 100 Figure 26. Gain Error Drift Distribution Histogram (Voltage Input) 30 25 25 20 OCCURRENCE 15 10 15 10 5 5 4 5 6 7 8 9 10 11 OFFSET ERROR DRIFT (V/C) 0 16465-124 0 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 OFFSET ERROR (A) Figure 24. Offset Error Drift Distribution Histogram (Voltage Input) 16465-127 OCCURRENCE 20 Figure 27. Offset Error Distribution Histogram (Current Input) 35 20 18 30 16 OCCURRENCE 14 20 15 12 10 8 6 10 4 5 -0.055 -0.050 -0.045 -0.040 -0.035 -0.030 -0.025 GAIN ERROR (% of Full-Scale) Figure 25. Gain Error Distribution Histogram (Voltage Input) 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OFFSET DRIFT (nA/C) 5.5 6.0 6.5 16465-128 2 0 16465-125 OCCURRENCE 25 Figure 28. Offset Error Drift Distribution Histogram (Current Input) Rev. 0 | Page 16 of 58 Data Sheet AD4112 20 30 18 25 16 OCCURRENCE 20 12 10 8 6 4 15 10 5 0 GAIN ERROR (% of Full-Scale) 6 16465-129 0.0250 0.0225 0.0200 0.0175 0.0150 0.0125 0.0100 0.0075 0 7 8 9 10 11 12 13 GAIN ERROR DRIFT (ppm/C) Figure 30. Gain Error Drift Distribution Histogram (Current Input) Figure 29. Gain Error Distribution Histogram (Current Input) Rev. 0 | Page 17 of 58 16465-130 2 0.0050 OCCURRENCE 14 AD4112 Data Sheet NOISE PERFORMANCE AND RESOLUTION Table 6 to Table 9 show the rms noise, peak-to-peak noise, effective resolution, and the noise free (peak-to-peak) resolution of the AD4112 for various ODRs. These values are typical and are measured with an external 2.5 V reference and with the ADC continuously converting on multiple channels. The values in Table 6 and Table 8 are generated for the 10 V voltage input range, with a differential input voltage of 0 V. The values in Table 7 and Table 9 are generated for the 0 mA to 20 mA input range, with an input current of 0 mA. It is important to note that the peak-to-peak resolution is calculated based on the peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker. Table 6. 10 V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc5 + Sinc1 Filter Default Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled 31,250 15,625 10,417 5208 2597 1007 504 381 200.3 100.2 59.52 49.68 20 16.67 10 5 2.5 1.25 1 2 Output Data Rate (SPS per Channel); SING_CYC = 1 or Multiple Channels Enabled 6211 5181 4444 3115 2597 1007 504 381 200.3 100.2 59.52 49.68 20.01 16.63 10 5 2.5 1.25 Settling Time1 161 s 193 s 225 s 321 s 385 s 993 s 1.99 ms 2.63 ms 4.99 ms 9.99 ms 16.8 ms 20.13 ms 49.98 ms 60.13 ms 100 ms 200 ms 400 ms 800 ms Notch Frequency (Hz) 31,250 15,625 10,417 5208 3906 1157 539 401 206 102 59.98 50 20 16.67 10 5 2.5 1.25 Noise (V rms)2 106 94 82 62 47 27 21 17 13 8 7 7 4 4 3.7 3.4 2.4 2.3 Effective Resolution (Bits) 17.5 17.7 17.9 18.3 18.7 19.5 19.9 20.2 20.6 21.3 21.4 21.4 22.3 22.3 22.4 22.5 23 23.1 Noise (V p-p) 750 580 512 372 312 190 140 92 62 45 33 33 22 21 18 17 12 11 Peak-to-Peak Resolution (Bits) 14.7 15.1 15.3 15.7 16.0 16.7 17.1 17.7 18.3 18.8 19.2 19.2 19.8 19.9 20.1 20.2 20.7 20.8 The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 / settling time. Based on 1000 samples for data rates 381 SPS per channel, based on 100 samples for data rates 200.3 SPS per channel. Table 7. 0 mA to 20 mA Current Input Noise and Resolution vs. Output Data Rate Using a Sinc5 + Sinc1 Filter Default Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled 31,250 15,625 10,417 5208 2597 1007 504 381 200.3 100.2 59.52 49.68 20 16.67 10 5 2.5 1.25 1 2 Output Data Rate (SPS per Channel); SING_CYC = 1 or Multiple Channels Enabled 6211 5181 4444 3115 2597 1007 503.8 381 200.3 100.2 59.52 49.68 20.01 16.63 10 5 2.5 1.25 Settling Time1 161 s 193 s 225 s 321 s 385 s 993 s 1.99 ms 2.63 ms 4.99 ms 9.99 ms 16.8 ms 20.13 ms 49.98 ms 60.13 ms 100 ms 200 ms 400 ms 800 ms Notch Frequency (Hz) 31,250 15,625 10,417 5208 3906 1157 539 401 206 102 59.98 50 20 16.67 10 5 2.5 1.25 Noise (nA rms)2 155 136 113 84 75 43 29 21 18 13 10 9 6 5.3 4.6 3 2.8 2.7 Effective Resolution (Bits) 17.0 17.2 17.4 17.9 18.0 18.8 19.4 19.9 20.1 20.6 20.9 21.1 21.7 21.8 22.1 22.7 22.8 22.8 Noise (nA p-p) 1100 920 720 580 480 220 150 125 95 71 48 41 30 23 18 12 12 6 Peak-to-Peak Resolution (Bits) 14.2 14.4 14.8 15.1 15.3 16.5 17.0 17.3 17.7 18.1 18.7 18.9 19.3 19.7 20.1 20.7 20.7 21.7 The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 / settling time. Based on 1000 samples for data rates 381 SPS per channel, based on 100 samples for data rates 200.3 SPS per channel. Rev. 0 | Page 18 of 58 Data Sheet AD4112 Table 8. 10 V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc3 Filter Default Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled 31,250 15,625 10,417 5208 3906 1157 539 401 206 102 59.98 50 20 16.67 10 5 2.5 1.25 1 2 Output Data Rate (SPS per Channel); SING_CYC = 1 or Multiple Channels Enabled 6211 5181 4444 3115 2597 1007 504 381 200.3 100.2 59.52 49.68 20.01 16.63 10 5 2.5 1.25 Settling Time1 96 s 192 s 288 s 576 s 1.15 ms 2.98 ms 5.95 ms 7.49 ms 14.99 ms 29.85 ms 50.02 ms 60 ms 149.93 ms 179.96 ms 300 ms 600 ms 1.2 sec 2.4 sec Notch Frequency (Hz) 31,250 15,625 10,417 5208 3906 1157 539 401 206 102 59.98 50 20 16.67 10 5 2.5 1.25 Noise (V rms)2 1035 158 77 50 34 22 15 13 10 7.3 6.2 5.3 4.9 4.2 3.7 3.5 3 2.9 Effective Resolution (Bits) 14.2 16.9 18 18.6 19.2 19.8 20.3 20.5 20.9 21.4 21.6 21.8 22 22.1 22.4 22.4 22.7 22.7 Noise (V p-p) 6037 954 536 334 205 137 15 13 10 39 35 36 33 29.8 20.9 17.8 17.8 14.9 Peak-to-Peak Resolution (Bits) 11.7 14.4 15.2 15.9 16.6 17.2 17.5 17.9 18.2 18.9 19.1 19.1 19.2 19.35 19.9 20.1 20.1 20.4 The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 / settling time. Based on 1000 samples for data rates 381 SPS per channel, based on 100 samples for data rates 200.3 SPS per channel. Table 9. 0 mA to 20 mA Current Input Noise and Resolution vs. Output Data Rate Using a Sinc3 Filter Default Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled Output Data Rate (SPS per Channel); SING_CYC = 1 or Multiple Channels Enabled 31,250 15,625 10,417 5208 3906 1157 539 401 206 102 59.98 50 20 16.67 10 5 2.5 1.25 6211 5181 4444 3115 2597 1007 503.8 381 200.3 100.2 59.52 49.68 20.01 16.63 10 5 2.5 1.25 1 2 Settling Time1 96 s 192 s 288 s 576 s 1.15 ms 2.98 ms 5.95 ms 7.49 ms 14.99 ms 29.85 ms 50.02 ms 60 ms 149.93 ms 179.96 ms 300 ms 600 ms 1.2 sec 2.4 sec Notch Frequency (Hz) 31,250 15,625 10,417 5208 3906 1157 539 401 206 102 59.98 50 20 16.67 10 5 2.5 1.25 Noise (nA rms)2 2177 309 121 72 49 30 22 19 14 10 7.6 7.2 4.8 4.4 3.8 3.1 2.6 2.4 Effective Resolution (Bits) 15.5 18.3 19.7 20.4 20.9 21.6 22.1 2.3 22.8 23.2 23.6 23.7 24 24 24 24 24 24 Noise (nA p-p) 13315 1830 781 452 339 214 149 125 77 71 53 41 29.8 29.8 23.8 17.9 11.9 11.9 Peak-to-Peak Resolution (Bits) 12.9 15.8 17 17.8 18.2 18.8 19.4 19.6 20.3 20.4 20.8 21.2 21.7 21.7 22 22.4 23 23 The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 / settling time. Based on 1000 samples for data rates 381 SPS per channel, based on 100 samples for data rates 200.3 SPS per channel. Rev. 0 | Page 19 of 58 AD4112 Data Sheet THEORY OF OPERATION The AD4112 offers the user a fast settling, high resolution, multiplexed ADC with high levels of configurability, including the following features: The AD4112 includes two separate linear regulator blocks for both the analog and digital circuitry. The analog LDO regulator regulates the AVDD supply to 1.8 V. The linear regulator for the digital IOVDD supply performs a similar function, regulating the input voltage applied at the IOVDD pin to 1.8 V. The serial interface signals always operate from the IOVDD supply seen at the pin; meaning that, if 3.3 V is applied to the IOVDD pin, the interface logic inputs and outputs operate at this level. The AD4112 includes a precision, 2.5 V, low drift (5 ppm/C), band gap internal reference. This reference can be selected for use in ADC conversions, reducing the external component count. When enabled, the internal reference is output to the REFOUT pin. It can be used as a low noise biasing voltage for the external circuitry and must be connected to a 0.1 F decoupling capacitor. The AD4112 is designed for a multitude of factory automation and process control applications, such as programmable logic controller (PLC) and distributed control system (DCS) modules. The AD4112 reduces overall system cost and design burden while maintaining a very high level of accuracy. The AD4112 offers the following system benefits: A single 5 V or 3.3 V power supply. Guaranteed minimum 1 M input impedance. Overrange voltage greater than 10 V. Integrated sense resistors for direct current input measurement. Reduced calibration costs. 16MHz CX2 CX1 OPTIONAL EXTERNAL CRYSTAL CIRCUITRY CAPACITORS XTAL1 12 2 VIN0 XTAL2/CLKIO 13 3 VIN1 DOUT/RDY 14 DOUT/RDY DIN DIN 15 SCLK 1 VINCOM 34 IIN0+ CLKIN OPTIONAL EXTERNAL CLOCK INPUT SCLK 16 CS CS 17 IOVDD AD4112 IOVDD 20 0.1F DGND 21 33 IIN0- REGCAPD 22 0.1F 11 1F AVDD AVDD 9 VBIAS- 0.1F REFOUT 6 0.1F REGCAPA 7 AVSS 8 Figure 31. Typical Connection Diagram Rev. 0 | Page 20 of 58 0.1F 1F 16465-010 Four fully differential or eight single-ended voltage inputs. High impedance voltage divider with integrated precision matched resistors Four current inputs with integrated current sense resistors. Embedded proprietary iPassivesTM technology within a very small device footprint. Per channel configurability--up to eight different setups can be defined. A separate setup can be mapped to each of the channels. Each setup allows the user to configure whether the buffers are enabled or disabled, gain and offset correction, filter type, ODR, and reference source selection. Data Sheet AD4112 POWER SUPPLIES The AD4112 has two independent power supply pins: AVDD, and IOVDD. The AD4112 has no specific requirements for a power supply sequence. However, when all power supplies are stable, a device reset is required. See the AD4112 Reset section for details on how to reset the device. AVDD powers the internal 1.8 V analog LDO regulator, which powers the ADC core. AVDD also powers the crosspoint multiplexer and integrated input buffers. AVDD is referenced to AVSS, and AVDD - AVSS = 3.3 V or 5 V. AVDD and AVSS can be a single 3.3 V or 5 V supply, or a 1.65 V or 2.5 V split supply. When using split supplies, consider the absolute maximum ratings (see the Absolute Maximum Ratings section). IOVDD powers the internal 1.8 V digital LDO regulator. This regulator powers the digital logic of the ADC IOVDD sets the voltage levels for the serial peripheral interface (SPI) of the ADC. IOVDD is referenced to DGND, and IOVDD to DGND can vary from 2 V (minimum) to 5.5 V (maximum). Single-Supply Operation (AVSS = DGND) determine the specific register to which the read or write operation applies. When the read or write operation to the selected register is complete, the interface returns to its default state, where it expects a write operation to the communications register. In situations where interface synchronization is lost, a write operation of at least 64 serial clock cycles with DIN high returns the ADC to its default state by resetting the entire device, including the register contents. Alternatively, if CS is being used with the digital interface, returning CS high resets the digital interface to its default state and aborts any current operation. Figure 33 and Figure 34 show writing to and reading from a register by first writing the 8-bit command to the communications register followed by the data for the addressed register. Reading the ID register is the recommended method for verifying correct communication with the device. The ID register is a read only register and contains the value 0x30DX for the AD4112 The communication register and ID register details are described in Table 10 and Table 11. When the AD4112 is powered from a single supply connected to AVDD, the supply can be either 3.3 V or 5 V. In this configuration, AVSS and DGND can be shorted together on one single ground plane. 8-BIT COMMAND 8 BITS, 16 BITS, OR 24 BITS OF DATA CMD DATA CS IOVDD can range from 2 V to 5.5 V in this unipolar input configuration. DIN DIGITAL COMMUNICATION SCLK 16465-012 The AD4112 has a 3-wire or 4-wire SPI interface that is compatible with QSPITM, MICROWIRE(R), and DSPs. The interface operates in SPI Mode 3 and can be operated with CS tied low. In SPI Mode 3, SCLK idles high, the falling edge of SCLK is the drive edge, and the rising edge of SCLK is the sample edge. Data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. Figure 33. Writing to a Register (8-Bit Command with Register Address Followed by Data of 8 Bits, 16 Bits, or 24 Bits; Data Length Is Dependent on the Register Selected) 8-BIT COMMAND 8 BITS, 16 BITS, 24 BITS, OR 32 BITS OUTPUT CS DRIVE EDGE SAMPLE EDGE CMD 16465-011 DIN DOUT/RDY Figure 32. SPI Mode 3 SCLK Edges DATA The communications register controls access to the full register map of the ADC. This register is an 8-bit write only register. On power-up or after a reset, the digital interface defaults to a state where it is expecting a write to the communications register. Therefore, all communication begins by writing to the communications register. SCLK 16465-013 Accessing the ADC Register Map Figure 34. Reading from a Register (8-Bit Command with Register Address Followed by Data of 8 Bits, 16 Bits, 24, or 32 Bits; Data Length on DOUT Is Dependent on the Register Selected) The data written to the communications register determines which register is being accessed and if the next operation is a read or write. The RA bits (Bits[5:0] in Register 0x00) Rev. 0 | Page 21 of 58 AD4112 Data Sheet the default state by resetting the entire device, including the register contents. Alternatively, if CS is being used with the digital interface, returning CS high sets the digital interface to the default state and halts any serial interface operation. AD4112 RESET E After a power-up cycle and when the power supplies are stable, a device reset is required. In situations where interface synchronization is lost, a device reset is also required. A write operation of at least 64 serial clock cycles with DIN high returns the ADC to E Table 10. Communications Register Bit Map Reg. 0x00 Name COMMS Bits [7:0] Bit 7 WEN Bit 6 R/W Bit 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 0x00 RW W Bit 2 Bit 1 Bit 0 Reset 0x30DX1 RW R RA Table 11. ID Register Bit Map Reg. 0x07 1 Name ID Bits [15:8] [7:0] Bit 4 Bit 3 ID[15:8] ID[7:0] X means don't care. Rev. 0 | Page 22 of 58 Data Sheet AD4112 CONFIGURATION OVERVIEW Channel Configuration After power-on or reset, the AD4112 default configuration is as follows: The AD4112 has 16 independent channels and 8 independent setups. The user can select any of the input pairs on any channel, as well as any of the eight setups for any channel, giving the user full flexibility in the channel configuration. This flexibility also allows per channel configuration when using differential inputs and single-ended inputs because each channel can have its own dedicated setup. Channel configuration: Channel 0 is enabled, the VIN0 and VIN1 pair is selected as the input. Setup 0 is selected. Setup configuration: the analog input buffers are disabled and the reference input buffers are also disabled. The REF pins are selected as the reference source. Note that for this setup, the default channel does not operate correctly because the input buffers need to be enabled for a VIN input. Filter configuration: the sinc5 + sinc1 filter is selected and the maximum output data rate of 31.25 kSPS is selected. ADC mode: continuous conversion mode and the internal oscillator are enabled. The internal reference is disabled. Interface mode: CRC and the data and status output are disabled. Note that only a few of the register setting options are shown. This list is only an example. For full register information, see the Register Details section. Channel Registers The channel registers select which of the voltage or current inputs is used for that channel. This register also contains a channel enable/disable bit and the setup selection bits, which are used to select which of the eight available setups to use for this channel. When the AD4112 is operating with more than one channel enabled, the channel sequencer cycles through the enabled channels in sequential order, from Channel 0 to Channel 15. If a channel is disabled, it is skipped by the sequencer. Details of the channel register for Channel 0 are shown in Table 12. Figure 35 shows an overview of the suggested flow for changing the ADC configuration, divided into the following three blocks: Channel configuration (see Box A in Figure 35) Setup configuration (see Box B in Figure 35) ADC mode and interface mode configuration (see Box C in Figure 35) A CHANNEL CONFIGURATION SELECT INPUT AND SETUP FOR EACH ADC CHANNEL B SETUP CONFIGURATION 8 POSSIBLE ADC SETUPS SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE C ADC MODE AND INTERFACE MODE CONFIGURATION SELECT ADC OPERATING MODE, CLOCK SOURCE, ENABLE CRC, DATA AND STATUS, AND MORE 16465-137 Figure 35. Suggested ADC Configuration Flow Table 12. Channel Register 0 Reg. 0x10 Name CH0 Bits [15:8] [7:0] Bit 7 CH_EN0 Bit 6 Bit 5 Bit 4 SETUP_SEL0 Bit 3 INPUT[7:0] Rev. 0 | Page 23 of 58 Bit 2 Reserved Bit 1 Bit 0 INPUT[9:8] Reset 0x8001 RW RW AD4112 Data Sheet ADC Setups Setup Configuration Registers The AD4112 has eight independent setups. Each setup consists of the following four registers: The setup configuration registers allow the user to select the output coding of the ADC by selecting between bipolar mode and unipolar mode. The user can select the reference source using these registers. Three options are available: a reference connected between the REF+ and REF- pins, the internal reference, or using AVDD - AVSS. The input and reference buffers can also be enabled or disabled using these registers. Setup configuration register Filter configuration register Gain register Offset register For example, Setup 0 consists of Setup Configuration Register 0, Filter Configuration Register 0, Gain Register 0, and Offset Register 0. Figure 36 shows the grouping of these registers The setup is selectable from the channel registers (see the Channel Configuration section), which allows each channel to be assigned to one of eight separate setups. Table 13 through Table 16 show the four registers that are associated with Setup 0. This structure is repeated for Setup 1 to Setup 7. SETUP CONFIG REGISTERS Filter Configuration Registers The filter configuration registers select which digital filter is used at the output of the ADC modulator. The order of the filter and the output data rate are selected by setting the bits in these registers. For more information, see the Digital Filter section. FILTER CONFIG REGISTERS GAIN REGISTERS* OFFSET REGISTERS SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 SETUPCON4 0x24 FILTCON4 0x2C GAIN4 0x3C OFFSET4 0x34 SETUPCON5 0x25 FILTCON5 0x2D GAIN5 0x3D OFFSET5 0x35 SETUPCON6 0x26 FILTCON6 0x2E GAIN6 0x3E OFFSET6 0x36 SETUPCON7 0x27 FILTCON7 0x2F GAIN7 0x3F OFFSET7 0x37 SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE INPUT BUFFERS 31.25kSPS TO 1.25SPS REFERENCE INPUT BUFFERS REFERENCE SOURCE SINC5 + SINC1 SINC3 SINC3 MAP ENHANCED 50Hz/60Hz GAIN CORRECTION OPTIONALLY PROGRAMMED PER SETUP AS REQUIRED (FACTORY CALIBRATED FOR CURRENT INPUT) OFFSET CORRECTION OPTIONALLY PROGRAMMED PER SETUP AS REQUIRED 16465-138 SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL 0x31 Figure 36. ADC Setup Register Grouping Table 13. Setup Configuration Register 0 Reg. 0x20 Name Bits Bit 7 SETUPCON0 [15:8] [7:0] Reserved Bit 6 Reserved Reserved Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BI_UNIPOLAR0 REFBUF0+ REFBUF0- REF_SEL0 Reserved Bit 0 INBUF0 Reset 0x1000 RW RW Reset 0x0500 RW RW Table 14. Filter Configuration Register 0 Reg. 0x28 Name FILTCON0 Bits Bit 7 [15:8] SINC3_MAP0 [7:0] Reserved Bit 6 Bit 5 Bit 4 Reserved ORDER0 Bit 3 Bit 2 ENHFILTEN0 ODR0 Bit 1 Bit 0 ENHFILT0 Table 15. Gain Register 0 Reg. 0x38 Name GAIN0 Bits [23:0] Bits[23:0] GAIN0[23:0] Reset RW 0x5XXXX0 RW Bits[23:0] OFFSET0[23:0] Reset RW 0x800000 RW Table 16. Offset Register 0 Reg. 0x30 Name OFFSET0 Bits [23:0] Rev. 0 | Page 24 of 58 Data Sheet AD4112 Gain Registers ADC Mode Register The gain registers are 24-bit registers that hold the gain calibration coefficient for the ADC. The gain registers are read/write registers. At power-on, these registers are configured for current inputs with factory calibrated coefficients. Therefore, every device has different default coefficients. When enabling a voltage input on a channel register (see the Channel Registers section), the user must also update the gain register for the corresponding setup. For more information, see the Adjusting Voltage Input Gain section. The ADC mode register primarily sets the conversion mode of the ADC to either continuous or single conversion. The user can also select the standby and power-down modes, as well as any of the calibration modes. In addition, this register contains the clock source select bits and internal reference enable bit. The reference select bits are contained in the setup configuration registers (see the ADC Setups section for more information). The details of this register are shown in Table 17. Offset Registers The interface mode register configures the digital interface operation. This register allows the user to control data-word length, CRC enable, data plus status read, and continuous read mode. The details of this register are shown in Table 18. For more information, see the Digital Interface section. Interface Mode Register The offset registers hold the offset calibration coefficient for the ADC. The power-on reset value of the offset registers is 0x800000. The offset registers are 24-bit read and write registers. ADC Mode and Interface Mode Configuration The ADC mode register and the interface mode register configure the core peripherals for use by the AD4112 and the mode for the digital interface. Table 17. ADC Mode Register Reg. 0x01 Name ADCMODE Bits [15:8] [7:0] Bit 7 REF_EN Reserved Bit 6 Reserved Bit 5 SING_CYC Mode Bit 4 Bit 3 Reserved Bit 2 CLOCKSEL Bit 1 Bit 0 Delay Reserved Reset 0x2000 RW RW Reset 0x0000 RW RW Table 18. Interface Mode Register Reg. 0x02 Name IFMODE Bits [15:8] [7:0] Bit 7 CONTREAD Bit 6 Reserved DATA_STAT Bit 5 REG_CHECK Bit 4 ALT_SYNC Reserved Bit 3 Bit 2 Bit 1 IOSTRENGTH Reserved CRC_EN Reserved Rev. 0 | Page 25 of 58 Bit 0 DOUT_RESET WL16 AD4112 Data Sheet CIRCUIT DESCRIPTION AVDD MULTIPLEXER MULTIPLEXER IIN0+ There are nine voltage pins and eight current inputs: VIN0- to VIN7, VINCOM, IIN0+ to IIN3+, and IIN0- to IIN3-. Each of these pins connects to the internal multiplexer. The multiplexer enables these inputs to be configured as input pairs (see the Voltage Inputs section and the Current Inputs section for more information on how to set up these inputs). The AD4112 can have up to 16 active channels. When more than one channel is enabled, the channels are automatically sequenced in order from the lowest enabled channel number to the highest enabled channel number. The output of the multiplexer is connected to the input of the integrated true rail-to-rail buffers. These buffers can be bypassed and the multiplexer output can be directly connected to the switched capacitor input of the ADC. The simplified input circuits are shown in Figure 37 and Figure 38. +IN 5 AVSS RSENSE 50 AVDD -IN 5 16465-014 IIN0- AVSS Figure 37. Simplified Current Input Circuit AVDD AVDD 222k VIN0 222k 222k MULTIPLEXER +IN 1M AVSS AVDD VIN1 1M AVSS AVDD 222k VBIAS- -IN 222k 222k AVSS Figure 38. Simplified Voltage Input Circuit Rev. 0 | Page 26 of 58 16465-015 VINCOM 1M Data Sheet AD4112 Alternatively, the gain can be calibrated by connecting a precision voltage source to the voltage input and performing a full-scale system calibration. CURRENT INPUTS There are four current input pins (IIN0+ to IIN3+) and four current return pins (IIN0- to IIN3-). Connect these pins in numbered pairs (for example, IIN0+ and IIN0-). AD4112 REFERENCE Disable the input buffers for the current inputs. The AD4112 offers the user the option of either supplying an external reference to the REF+ and REF- pins of the device, using AVDD - AVSS, or by allowing the use of the internal 2.5 V, low noise, low drift reference. Select the reference source to be used by the analog input by setting the REF_SELx bits, Bits[5:4], in the setup configuration registers appropriately. The structure of the Setup Configuration 0 register is shown in Table 19. By default, the AD4112 uses an external reference on power-up. To achieve specified accuracy, the current channels are factory calibrated. This calibration value is stored in on-chip nonvolatile memory and is copied to all gain registers after a power-up or reset. VOLTAGE INPUTS The AD4112 can be set up to have eight single-ended inputs or four fully differential inputs. The voltage divider on the analog front end has a division ratio of 10 and consists of precision matched resistors that enable an input range of 20 V from a single 5 V power supply. Internal Reference The AD4112 includes a low noise, low drift voltage reference. The internal reference has a 2.5 V output. The internal reference is output on the REFOUT pin after the REF_EN bit in the ADC mode register is set and is decoupled to AVSS with a 0.1 F capacitor. The AD4112 internal reference is disabled by default on power-up. Enable the input buffers in the setup register for voltage input channels. Fully Differential Inputs Due to the matching resistors on the analog front end, the differential inputs must be paired together in the following pairs: VIN0 and VIN1, VIN2 and VIN3, VIN4 and VIN5, and VIN6 and VIN7. If any two voltage inputs are paired in a configuration other than what is described in this data sheet, the accuracy of the device cannot be guaranteed. External Reference The AD4112 has a fully differential reference input applied through the REF+ and REF- pins. Standard low noise, low drift voltage references, such as the ADR4525, are recommended for use. Apply the external reference to the AD4112 reference pins as shown in Figure 39. Decouple the output of any external reference to AVSS. As shown in Figure 39, the ADR4525 output is decoupled with a 0.1 F capacitor at the output for stability purposes. The output is then connected to a 4.7 F capacitor, which acts as a reservoir for any dynamic charge required by the ADC, and is followed by a 0.1 F decoupling capacitor at the REF+ input. This capacitor is placed as close as possible to the REF+ and REF- pins. Single-Ended Inputs The user can also choose to measure up to eight different single-ended voltage inputs. In this case, each of the voltage inputs must be paired with VINCOM. Connect VINCOM externally to AVSS. Adjusting Voltage Input Gain After a power up or reset, all gain registers are loaded with factory calibration coefficients for current inputs. When using a voltage input, the corresponding gain register must be modified after powering up or resetting the device. Perform this modification by running an internal full-scale calibration (see the Calibration section for more information). Alternatively, the gain register can be overwritten with a nominal value of 0x55567C. However, a calibration is recommended because the ideal value varies from device to device. The REF- pin is connected directly to the AVSS potential. When an external reference is used instead of the internal reference to supply the AD4112, attention must be paid to the output of the REFOUT pin. The internal reference is controlled by the REF_EN bit (Bit 15) in the ADC mode register, which is shown in Table 20. If the internal reference is not being used elsewhere in the application, ensure that the REF_EN bit is disabled. AD4112 3V TO 18V ADR45252 1 2.5V VREF 1 0.1F 1 4.7F 1 39 REF- 1 1 ALL DECOUPLING IS TO AVSS. 2ANY OF THE ADR4525 FAMILY REFERENCES CAN BE USED. ADR4525 ENABLES REUSE OF THE 3.3V ANALOG SUPPLY NEEDED FOR AVDD TO POWER THE REFERENCE VIN. Figure 39. ADR4525 Connected to AD4112 REF Pins Rev. 0 | Page 27 of 58 16465-016 0.1F 40 REF+ 0.1F AD4112 Data Sheet Table 19. Setup Configuration 0 Register Reg. 0x20 Name SETUPCON0 Bits [15:8] [7:0] Bit 7 Reserved Bit 6 Reserved Reserved Bit 5 Bit 4 BI_UNIPOLAR0 REF_SEL0 Bit 3 REFBUF0+ Bit 2 Bit 1 REFBUF0- Reserved Bit 0 INBUF0 Reset 0x1000 RW RW Table 20. ADC Mode Register Reg. 0x01 Name ADCMODE Bits [15:8] [7:0] Bit 7 REF_EN Reserved Bit 6 Reserved Bit 5 SING_CYC Mode Bit 4 Bit 3 Reserved Rev. 0 | Page 28 of 58 Bit 2 CLOCKSEL Bit 1 Bit 0 Delay Reserved Reset 0x2000 RW RW Data Sheet AD4112 BUFFERED REFERENCE INPUT External Crystal The AD4112 has true rail-to-rail, integrated, precision unity gain buffers on both ADC reference inputs. The buffers provide the benefit of providing high input impedance and allowing high impedance external sources to be directly connected to the reference inputs. The integrated reference buffers can fully drive the internal reference switch capacitor sampling network, simplifying the reference circuit requirements. Each reference input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f noise of the buffer. When using a reference, such as the ADR4525, these buffers are not required because these references, with proper decoupling, can drive the reference inputs directly. If higher precision, lower jitter clock sources are required, the AD4112 can use an external crystal to generate the master clock. The crystal is connected to the XTAL1 and XTAL2/CLKIO pins. A recommended crystal for use is the FA-20H, a 16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom that is available in a surface-mount package. As shown in Figure 40, insert two capacitors (CX1 and CX2) from the traces connecting the crystal to the XTAL1 and XTAL2/CLKIO pins. These capacitors allow circuit tuning. Connect these capacitors to the DGND pin. The value for these capacitors depends on the length and capacitance of the trace connections between the crystal and the XTAL1 and XTAL2/CLKIO pins. Therefore, the values of these capacitors differ depending on the PCB layout and the crystal used. CLOCK SOURCE The AD4112 uses a nominal master clock of 2 MHz. The AD4112 can source its sampling clock from one of three sources: CX1 1 XTAL1 12 An internal oscillator. An external crystal (use a 16 MHz crystal automatically divided internally to set the 2 MHz clock). An external clock source. XTAL2/CLKIO 13 CX2 1 All output data rates listed in the data sheet relate to a master clock rate of 2 MHz. Using a lower clock frequency from, for instance, an external source scales any listed data rate proportionally. To achieve the specified data rates, particularly rates for rejection of 50 Hz and 60 Hz, use a 2 MHz clock. The source of the master clock is selected by setting the CLOCKSEL bits (Bits[3:2]) in the ADC mode register, as shown in Table 20. The default operation on power-up and reset of the AD4112 is to operate with the internal oscillator. It is possible to fine tune the output data rate and filter notch at low output data rates using the SINC3_MAPx bits. Internal Oscillator The internal oscillator runs at 16 MHz and is internally divided down to 2 MHz for the modulator and can be used as the ADC master clock. The internal oscillator is the default clock source for the AD4112 and is specified with an accuracy of -2.5% to +2.5%. There is an option to allow the internal clock oscillator to be output on the XTAL2/CLKIO pin. The clock output is driven to the IOVDD logic level. This option can affect the dc performance of the AD4112 due to the disturbance introduced by the output driver. The extent to which the performance is affected depends on the IOVDD voltage supply. Higher IOVDD voltages create a wider logic output swing from the driver and affect performance to a greater extent. This effect is further exaggerated if the IOSTRENGTH bit is set at higher IOVDD levels (see Table 27 for more information). 1DECOUPLE TO DGND 16465-017 AD4112 Figure 40. External Crystal Connections The external crystal circuitry can be sensitive to the SCLK edges, depending on the SCLK frequency, IOVDD voltage, crystal circuitry layout, and the crystal used. During crystal startup, any disturbances caused by the SLCK edges may cause double edges on the crystal input, resulting in invalid conversions until the crystal voltage has reached a high enough level such that any interference from the SCLK edges is insufficient to cause double clocking. This double clocking can be avoided by ensuring that the crystal circuitry has reached a sufficient voltage level after startup before applying any SCLK. Because of the nature of the crystal circuitry, it is recommended that empirical testing of the circuit be performed under the required conditions, with the final PCB layout and crystal, to ensure correct operation. External Clock The AD4112 can also use an externally supplied clock. In systems where an externally supplied clock is used, the external clock is routed to the XTAL2/CLKIO pin. In this configuration, the XTAL2/ CLKIO pin accepts the externally sourced clock and routes it to the modulator. The logic level of this clock input is defined by the voltage applied to the IOVDD pin. Rev. 0 | Page 29 of 58 AD4112 Data Sheet DIGITAL FILTER The AD4112 has three flexible filter options to allow optimization of noise, settling time, and rejection: The sinc3 filter achieves the best single-channel noise performance at lower rates and is, therefore, most suitable for single-channel applications. The sinc3 filter always has a settling time equal to The sinc5 + sinc1 filter. The sinc3 filter. Enhanced 50 Hz and 60 Hz rejection filters. SINC1 Figure 43 shows the frequency domain filter response for the sinc3 filter. The sinc3 filter has good roll-off over frequency and has wide notches for good notch frequency rejection. 50Hz AND 60Hz POSTFILTER 0 16465-018 SINC5 tSETTLE = 3/Output Data Rate SINC3 -10 -20 Figure 41. Digital Filter Block Diagram FILTER GAIN (dB) -30 The filter and output data rate are configured by setting the appropriate bits in the filter configuration register for the selected setup. Each channel can use a different setup and therefore, a different filter and output data rate. See the Register Details section for more information. -70 -80 -100 The sinc5 + sinc1 filter is targeted at multiplexed applications and achieves single cycle settling at output data rates of 2.6 kSPS and less. The sinc5 block output is fixed at the maximum rate of 31.25 kSPS, and the sinc1 block output data rate can be varied to control the final ADC output data rate. Figure 42 shows the frequency domain response of the sinc5 + sinc1 filter at a 50 SPS output data rate. The sinc5 + sinc1 filter has a slow roll-off over frequency and narrow notches. 0 -20 FILTER GAIN (dB) -50 -60 -90 SINC5 + SINC1 FILTER -40 -110 -120 0 50 100 150 FREQUENCY (Hz) Figure 43. Sinc3 Filter Response The output data rates with the accompanying settling time and rms noise for the sinc3 filter are shown in Table 8 and Table 9. It is possible to fine tune the output data rate for the sinc3 filter by setting the SINC3_MAPx bit in the filter configuration registers. If this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter. All other options are eliminated. The data rate when on a single channel can be calculated using the following equation: Output Data Rate = fMOD/(32 x FILTCONx[14:0]) -60 where: fMOD is the modulator rate (MCLK/2) and is equal to 1 MHz. FILTCONx[14:0] are the contents on the filter configuration registers, excluding the MSB. -80 0 50 100 150 FREQUENCY (Hz) 16465-019 -100 -120 -40 16465-020 SINC3 FILTER For example, an output data rate of 50 SPS can be achieved with SINC3_MAPx enabled by setting the FILTCONx[14:0] bits to a value of 625. Figure 42. Sinc5 + Sinc1 Filter Response at 50 SPS ODR The output data rates with the accompanying settling time and rms noise for the sinc5 + sinc1 filter are shown in in Table 6 and Table 7. Rev. 0 | Page 30 of 58 Data Sheet AD4112 The AD4112 can be configured by setting the SING_CYC bit in the ADC mode register so that only fully settled data is output, thus effectively putting the ADC into a single cycle settling mode. This mode achieves single cycle settling by reducing the output data rate to be equal to the settling time of the ADC for the selected output data rate. This bit has no effect with the sinc5 + sinc1 filter at output data rates of 2.6 kSPS and less or when multiple channels are enabled. Figure 44 shows a step on the analog input with single cycle settling mode disabled and the sinc3 filter selected. The analog input requires at least three cycles after the step change for the output to reach the final settled value. ANALOG INPUT 16465-021 FULLY SETTLED ADC OUTPUT 1/ODR Figure 44. Step Input Without Single Cycle Settling Figure 45 shows the same step on the analog input but with single cycle settling enabled. The analog input requires at least a single cycle for the output to be fully settled. The output data rate, as indicated by the RDY signal, is now reduced to equal the settling time of the filter at the selected output data rate. ANALOG INPUT FULLY SETTLED ADC OUTPUT 16465-033 SINGLE CYCLE SETTLING tSETTLE Figure 45. Step Input with Single Cycle Settling ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS The enhanced filters provide rejection of 50 Hz and 60 Hz simultaneously and allow the user to trade off settling time and rejection. These filters can operate at up to 27.27 SPS or can reject up to 90 dB of 50 Hz 1 Hz and 60 Hz 1 Hz interference. These filters are operated by postfiltering the output of the sinc5 + sinc1 filter. For this reason, the sinc5 + sinc1 filter must be selected when using the enhanced filters to achieve the specified settling time and noise performance. Table 21 and Table 22 show the output data rates with the accompanying settling time, rejection, and rms noise. Figure 46 to Figure 53 show the frequency domain plots of the responses from the enhanced filters. Table 21. Enhanced Filters Output Data Rate, Voltage Input Noise, Settling Time, and Rejection Using the Enhanced Filters Output Data Rate (SPS) 27.27 25 20 16.667 1 Settling Time (ms) 36.67 40.0 50.0 60.0 Simultaneous Rejection of 50 Hz 1 Hz and 60 Hz 1 Hz(dB)1 47 62 85 90 Noise (V rms) 6.44 6.09 5.54 5.38 Peak-to-Peak Resolution (Bits) 19.1 19.2 19.35 19.51 Comments See Figure 46 and Figure 49 See Figure 47 and Figure 50 See Figure 48 and Figure 51 See Figure 52 and Figure 53 Master clock = 2.00 MHz. Table 22. Enhanced Filters Output Data Rate, Current Input Noise, Settling Time, and Rejection Using the Enhanced Filters Output Data Rate (SPS) 27.27 25 20 16.667 1 Settling Time (ms) 36.67 40.0 50.0 60.0 Simultaneous Rejection of 50 Hz 1 Hz and 60 Hz 1 Hz(dB)1 47 62 85 90 Noise (nA rms) 7.69 7.68 7.26 7.25 Master clock = 2.00 MHz. Rev. 0 | Page 31 of 58 Peak-to-Peak Resolution (Bits) 21.4 21.2 21.7 21.7 Comments See Figure 46 and Figure 49 See Figure 47 and Figure 50 See Figure 48 and Figure 51 See Figure 52 and Figure 53 Data Sheet 0 0 -10 -10 -20 -20 -30 -30 FILTER GAIN (dB) -40 -50 -60 -70 -80 -60 -70 100 200 300 400 500 600 -20 -20 -30 -30 FILTER GAIN (dB) 0 -10 -40 -50 -60 -70 -70 -90 500 600 FREQUENCY (Hz) -100 40 16465-023 400 -10 -10 -20 -20 -30 -30 FILTER GAIN (dB) 0 -40 -50 -60 -70 FREQUENCY (Hz) 600 16465-024 500 70 -70 -90 400 65 -60 -90 300 60 -50 -80 200 55 -40 -80 100 50 Figure 50. 25 SPS ODR, 40 ms Settling Time (40 Hz to 70 Hz) 0 0 45 FREQUENCY (Hz) Figure 47. 25 SPS ODR, 40 ms Settling Time -100 70 -60 -80 300 65 -50 -90 200 60 -40 -80 100 55 Figure 49. 27.27 SPS ODR, 36.67 ms Settling Time (40 Hz to 70 Hz) 0 0 50 FREQUENCY (Hz) -10 -100 45 16465-026 0 16465-025 -90 -100 40 16465-022 -90 -100 Figure 46. 27.27 SPS ODR, 36.67 ms Settling Time FILTER GAIN (dB) -50 -80 FREQUENCY (Hz) FILTER GAIN (dB) -40 Figure 48. 20 SPS ODR, 50 ms Settling Time -100 40 45 50 55 60 65 FREQUENCY (Hz) Figure 51. 20 SPS ODR, 50 ms Settling Time (40 Hz to 70 Hz) Rev. 0 | Page 32 of 58 70 16465-027 FILTER GAIN (dB) AD4112 AD4112 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -70 -40 -50 -60 -70 -80 -80 -90 -90 -100 0 100 200 300 400 500 FREQUENCY (Hz) 600 Figure 52. 16.667 SPS ODR, 60 ms Settling Time -100 40 45 50 55 60 65 70 FREQUENCY (Hz) Figure 53. 16.667 SPS ODR, 60 ms Settling Time (40 Hz to 70 Hz) Rev. 0 | Page 33 of 58 16465-029 FILTER GAIN (dB) 0 16465-028 FILTER GAIN (dB) Data Sheet AD4112 Data Sheet OPERATING MODES The AD4112 has a number of operating modes that can be set from the ADC mode register and interface mode register (see Table 26 and Table 27). These modes are as follows: Continuous conversion mode Continuous read mode Single conversion mode Standby mode Power-down mode Calibration modes (four) CONTINUOUS CONVERSION MODE Continuous conversion mode is the default power-up mode. The AD4112 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the RDY output also goes low when a conversion is complete. To read a conversion, write to the communications register to indicate that the next operation is a read of the data register. When the data-word has been read from the data register, the DOUT/RDY pin goes high. The user can read this register additional times, if required. However, ensure that the data register is not being accessed at the completion of the next conversion. Otherwise, the new conversion word is lost. When several channels are enabled, the ADC automatically sequences through the enabled channels, performing one conversion on each channel. When all the channels are converted, the sequence starts again with the first channel. The channels are converted in order from the lowest enabled channel to the highest enabled channel. The data register is updated as soon as each conversion is available. The RDY output pulses low each time a conversion is available. The user can then read the conversion while the ADC converts the next enabled channel. If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion data, are output each time the data register is read. The four LSBs of the status register indicates the channel to which the conversion corresponds. CS 0x44 0x44 DIN DATA DATA 16465-030 DOUT/RDY SCLK Figure 54. Continuous Conversion Mode Rev. 0 | Page 34 of 58 Data Sheet AD4112 mode register. When this bit is set, the only serial interface operations possible are reads from the data register. To exit continuous read mode, issue a dummy read of the ADC data register command (0x44) while the RDY output is low. Alternatively, apply a software reset (that is, 64 SCLKs with CS = 0 and DIN = 1) to reset the ADC and all register contents. The dummy read and the software reset are the only commands that the interface recognizes after it is placed in continuous read mode. Hold DIN low in continuous read mode until an instruction is to be written to the device. CONTINUOUS READ MODE In continuous read mode, it is not required to write to the communications register before reading ADC data. Apply only the required number of SCLKs after the RDY output goes low to indicate the end of a conversion. When the conversion is read, the RDY output returns high until the next conversion is available. In this mode, the data can be read only once. Ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the AD4112 to read the data-word, the serial output register is reset shortly before the next conversion is complete, and the new conversion is placed in the output serial register. The ADC must be configured for continuous conversion mode to use continuous read mode. To enable continuous read mode, set the CONTREAD bit in the interface If multiple ADC channels are enabled, each channel is output in turn, with the status bits being appended to the data if the DATA_STAT bit is set in the interface mode register. The four LSBs of the status register indicates the channel to which the conversion corresponds. CS DOUT/RDY 0x02 0x0080 DATA DATA DATA 16465-031 DIN SCLK Figure 55. Continuous Read Mode Rev. 0 | Page 35 of 58 AD4112 Data Sheet SINGLE CONVERSION MODE In single conversion mode, the AD4112 performs a single conversion and is placed in standby mode after the conversion is complete. The RDY output goes low to indicate the completion of a conversion. When the data-word has been read from the data register, the RDY output goes high. The data register can be read several times, if required, even when the RDY output goes high. If several channels are enabled, the ADC automatically sequences through the enabled channels and performs a conversion on each channel. When the first conversion is started, the RDY output goes high and remains high until a valid conversion is available and CS is low. When the conversion is available, the RDY output goes low. The ADC then selects the next channel and begins a conversion. The user can read the present conversion while the next conversion is being performed. When the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. When the ADC has performed a single conversion on each of the selected channels, it returns to standby mode. If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion, are output each time the data register is read. The four LSBs of the status register indicate the channel to which the conversion corresponds. CS DIN 0x01 0x8010 0x44 DATA 16465-032 DOUT/RDY SCLK Figure 56. Single Conversion Mode Rev. 0 | Page 36 of 58 Data Sheet AD4112 STANDBY AND POWER-DOWN MODES In standby mode, most blocks are powered down. The LDO regulators remain active so that the registers maintain their contents. The crystal oscillator remains active if selected. To power down the clock in standby mode, set the CLOCKSEL bits in the ADC mode register to 00 (internal oscillator mode). In power-down mode, all blocks are powered down, including the LDO regulators. All registers lose their contents, and the GPIO outputs are placed in three-state. To prevent accidental entry to power-down mode, the ADC must first be placed in standby mode. Exiting power-down mode requires 64 SCLKs with CS = 0 and DIN = 1, that is, a serial interface reset. A delay of 500 s is recommended before issuing a subsequent serial interface command to allow the LDO regulator to power up. CALIBRATION The AD4112 allows a two-point calibration to be performed to eliminate any offset and gain errors. Four calibration modes are used to eliminate these offset and gain errors on a per setup basis: Internal zero-scale calibration mode Internal full-scale calibration mode System zero-scale calibration mode System full-scale calibration mode Only one channel can be active during calibration. After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register. The default value of the offset register is 0x800000, and the nominal value of the gain register is factory calibrated for the current channels; therefore, this value can vary from 0x500000 to 0x5FFFFF. When enabling a voltage channel, run an internal full-scale calibration. The following equations show the calculations that are used. In unipolar mode, the ideal relationship (that is, not taking into account the ADC gain error and offset error) is as follows: Data = ((0.075 x VIN/VREF) x 223 - (Offset - 0x800000)) x (Gain/0x400000) x 2 For a current input, the ideal relationship is as follows: Data = ((0.75 x (IIN x 50)/VREF) x 2123 - (Offset - 0x800000)) x (Gain/0x400000) x 2 In bipolar mode, the ideal relationship (that is, not taking into account the ADC gain error and offset error) is as follows: Data = ((0.075 x VIN/VREF) x 223 - (Offset - 0x800000)) x (Gain/0x400000) + 0x800000 For a current input, the ideal relationship is as follows: Data = ((0.75 x (IIN x 50)/VREF) x 223 - (Offset - 0x800000)) x (Gain/0x400000) + 0x800000 the calibration is complete, the contents of the corresponding offset or gain register are updated, the RDY bit in the status register is reset and the RDY output pin returns low (if CS is low), and the AD4112 reverts to standby mode. During an internal offset calibration both modulator inputs are connected internally to the selected negative analog input pin. Therefore, it is necessary to ensure that the voltage on the selected negative analog input pin does not exceed the allowed limits and is free from excessive noise and interference. To perform an internal full-scale calibration, a full-scale input voltage is automatically connected to the ADC input for this calibration. Internal full-scale calibrations must only be performed on voltage inputs. Do not perform internal full-scale calibrations on the current inputs. However, for system calibrations, the system zero-scale (offset) and system full-scale (gain) voltages must be applied to the input pins before initiating the calibration modes. As a result, errors external to the AD4112 are removed. The calibration range of the ADC gain for a system full-scale calibration on a voltage input is from 3.75 x VREF to 10.5 x VREF. However, if 10.5 x VREF is greater than the absolute input voltage specification for the applied AVDD, use the specification as the upper limit instead of 10.5 x VREF (see the Specifications section). Current inputs are factory calibrated. Therefore, it is not necessary to perform a system calibration. However if a system calibration is required, apply a full-scale value of 24 mA for a VREF = 2.5 V. An internal zero-scale calibration only removes the offset error of the ADC core. It does not remove error from the resistive front end. A system zero-scale calibration reduces the offset error to the order of the noise on that channel. From an operational point of view, treat a calibration like another ADC conversion. An offset calibration, if required, must always be performed before a full-scale calibration. Set the system software to monitor the RDY bit in the status register or the RDY output to determine the end of a calibration via a polling sequence or an interrupt driven routine. All calibrations require a time equal to the settling time of the selected filter and output data rate to be completed. Any calibration can be performed at any output data rate. Using lower output data rates results in better calibration accuracy and is accurate for all output data rates. A new offset calibration is required for a given channel if the reference source for that channel is changed. The AD4112 provides the user with access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and to write its own calibration coefficients. A read or write of the offset and gain registers can be performed at any time except during an internal or self calibration. To start a calibration, write the relevant value to the mode bits in the ADC mode register. The DOUT/RDY pin and the RDY bit in the status register go high when the calibration initiates. When Rev. 0 | Page 37 of 58 AD4112 Data Sheet DIGITAL INTERFACE Figure 2 and Figure 3 show timing diagrams for interfacing to the AD4112 using CS to decode the device. Figure 2 shows the timing for a read operation from the AD4112, and Figure 3 shows the timing for a write operation to the AD4112. It is possible to read from the data register several times, even though the RDY output returns high after the first read operation. However, take care to ensure that the read operations are completed before the next output update occurs. In continuous read mode, the data register can be read only once. The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the AD4112. The end of the conversion can also be monitored using the RDY bit in the status register. The serial interface can be reset by writing 64 SCLKs with CS = 0 and DIN = 1. A reset returns the interface to the state in which it expects a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, allow a period of 500 s before addressing the serial interface. CHECKSUM PROTECTION The AD4112 has a checksum mode that can be used to improve interface robustness. Using the checksum ensures that only valid data is written to a register and allows data read from a register to be validated. If an error occurs during a register For CRC checksum calculations during a write operation, the following polynomial is always used: x8 + x2 + x + 1 During read operations, the user can select between this polynomial and a similar exclusive OR (XOR) function. The XOR function requires less time to process on the host microcontroller than the polynomial-based checksum. The CRC_EN bits in the interface mode register enable and disable the checksum and allow the user to select between the polynomial check and the simple XOR check. The checksum is appended to the end of each read and write transaction. The checksum calculation for the write transaction is calculated using the 8-bit command word and the 8-bit to 24bit data. For a read transaction, the checksum is calculated using the command word and the 8-bit to 32-bit data output. Figure 57 and Figure 58 show SPI write and read transactions, respectively. 8-BIT COMMAND UP TO 24-BIT INPUT CMD DATA 8-BIT CRC CS DIN CRC SCLK 16465-157 The DOUT/RDY pin also functions as a data ready signal, with the line going low if CS is low when a new data-word is available in the data register. The pin is reset high when a read operation from the data register is complete. The RDY output also goes high before updating the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. Take care to avoid reading from the data register when RDY is about to go low. The best method to ensure that no data read occurs is to always monitor the RDY output. Start reading the data register as soon as RDY goes low, and ensure a sufficient SCLK rate, such that the read is completed before the next conversion result. CS is used to select a device. CS can be used to decode the AD4112 in systems where several components are connected to the serial bus. write, the CRC_ERROR bit is set in the status register. However, to ensure that the register write was completed. It is important to read back the register and verify the checksum. Figure 57. SPI Write Transaction with CRC 8-BIT COMMAND UP TO 32-BIT OUTPUT 8-BIT CRC CS DIN DOUT/ RDY CMD DATA CRC SCLK 16465-158 The programmable functions of the AD4112 are accessible via the SPI serial interface. The serial interface of the AD4112 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line transfers data into the on-chip registers. The DOUT output accesses data from the on-chip registers. SCLK is the serial clock input for the device. All data transfers (either on DIN or on DOUT) occur with respect to the SCLK signal. Figure 58. SPI Read Transaction with CRC If checksum protection is enabled when continuous read mode is active, there is an implied read data command of 0x44 before every data transmission that must be accounted for when calculating the checksum value. The checksum protection ensures a nonzero checksum value even if the ADC data equals 0x000000. Rev. 0 | Page 38 of 58 Data Sheet AD4112 CRC CALCULATION Polynomial The checksum, which is eight bits wide, is generated using the following polynomial: that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process is repeated until the original data is reduced to a value less than the polynomial. This value is the 8-bit checksum. Example of a Polynomial CRC Calculation--24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) x8 + x2 + x + 1 To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 0s. The polynomial is aligned so that its MSB is adjacent to the leftmost Logic 1 of the data. An exclusive OR (XOR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned so An example of generating the 8-bit checksum using the polynomial based checksum is as follows. Initial value 011001010100001100100001 01100101010000110010000100000000 left shifted eight bits x8 + x2 + x + 1 = 100000111 polynomial 100100100000110010000100000000 XOR result 100000111 polynomial 100011000110010000100000000 XOR result 100000111 polynomial 11111110010000100000000 XOR result 100000111 polynomial value 1111101110000100000000 XOR result 100000111 polynomial value 111100000000100000000 XOR result 100000111 polynomial value 11100111000100000000 XOR result 100000111 polynomial value 1100100100100000000 XOR result 100000111 polynomial value 100101010100000000 XOR result 100000111 polynomial value 101101100000000 XOR result 100000111 polynomial value 1101011000000 XOR result 100000111 polynomial value 101010110000 XOR result 100000111 polynomial value 1010001000 XOR result 100000111 polynomial value 10000110 Rev. 0 | Page 39 of 58 checksum = 0x86. AD4112 Data Sheet XOR Calculation The XOR calculation is then as follows: The checksum, which is eight bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes. 01100101 0x65 01000011 0x43 Example of an XOR Calculation--24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) 00100110 XOR result 00100001 0x21 Using the example shown in the Polynomial section, divide the checksum into three bytes: 0x65, 0x43, and 0x21. 00000111 CRC Rev. 0 | Page 40 of 58 Data Sheet AD4112 INTEGRATED FUNCTIONS The AD4112 has a number of integrated functions. to ensure that synchronization occurs. If multiple channels are enabled, the sequencer is reset to the first enabled channel. GENERAL-PURPOSE OUPUTS The AD4112 has two general-purpose digital output pins (GPO0, GPO1). The GPO pins are enabled using the OP_EN0_1 bit in the GPIOCON register. The GP_DATA0 and GP_DATA1 bits determines the logic level output at the pin, respectively. The logic levels for these pins are referenced to AVDD and AVSS. Therefore, outputs have an amplitude of either 5 V or 3.3 V depending on the AVDD - AVSS voltage. The ERROR pin can also be used as a general-purpose output if the ERR_EN bits in the GPIOCON register are set to 11. In this configuration, the ERR_DAT bit in the GPIOCON register determines the logic level output at the ERROR pin. The logic level for the pin is referenced to IOVDD and DGND, and the ERROR pin has an active pull-up resistor. DELAY It is possible to insert a programmable delay before the AD4112 begins to take samples. This delay allows an external amplifier or multiplexer to settle and can also alleviate the specification requirements for the external amplifier or multiplexer. Eight programmable settings, ranging from 0 s to 8 ms, can be set using the delay bits in the ADC mode register (Register 0x01, Bits[10:8]). If multiple AD4112 devices are operated from a common master clock, they can be synchronized so that their data registers are updated simultaneously. Synchronization is normally done after each AD4112 has performed its own calibration or has calibration coefficients loaded into its calibration registers. A falling edge on the SYNC pin resets the digital filter and the analog modulator and places the AD4112 into a consistent known state. While the SYNC pin is low, the AD4112 is maintained in this state. On the SYNC rising edge, the modulator and filter are taken out of this reset state, and on the next master clock edge, the device starts to gather input samples again. The device is taken out of reset on the master clock falling edge following the SYNC low-to-high transition. Therefore, when multiple devices are being synchronized, take the SYNC pin high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. If the SYNC pin is not taken high in sufficient time, it is possible to have a difference of one master clock cycle between the devices, that is, the instant at which conversions are available differs from device to device by a maximum of one master clock cycle. By default, the AD4112 generates 24-bit conversions. However, the width of the conversions can be reduced to 16 bits. Setting Bit WL16 in the interface mode register to 1 rounds all data conversions to 16 bits. Clearing this bit sets the width of the data conversions to 24 bits. The SYNC input can also be used as a start conversion command for a single channel when in normal synchronization mode. In this mode, the rising edge of the SYNC input starts a conversion, and the falling edge of the RDY output indicates when the conversion is complete. The settling time of the filter is required for each data register update. After the conversion is complete, bring the SYNC input low in preparation for the next conversion start signal. DOUT_RESET Alternate Synchronization The serial interface uses a shared DOUT/RDY pin. By default, this pin outputs the RDY signal. During a data read, this pin outputs the data from the register being read. After the read is complete, the pin reverts to outputting the RDY signal after a short fixed period of time (t7). However, this time may be too short for some microcontrollers and can be extended until the CS pin is brought high by setting the DOUT_RESET bit in the interface mode register to 1. This setting means that CS must frame each read operation and complete the serial interface transaction. In alternate synchronization mode, the SYNC input operates as a start conversion command when several channels of the AD4112 are enabled. Setting the ALT_SYNC bit in the interface mode register to 1 enables an alternate synchronization scheme. When the SYNC input is taken low, the ADC completes the conversion on the enabled channel, selects the next channel in the sequence, and then waits until the SYNC input is taken high to start the conversion. The RDY output goes low when the conversion is complete on the current channel, and the data register is updated with the corresponding conversion. Therefore, the SYNC input does not interfere with the sampling on the currently selected channel but allows the user to control the instant at which the conversion begins on the next channel in the sequence. 16-BIT/24-BIT CONVERSIONS SYNCHRONIZATION Normal Synchronization When the SYNC_EN bit in the GPIOCON register is set to 1, the SYNC pin functions as a synchronization pin. The SYNC input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the device. This reset allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of SYNC. This pin must be low for at least one master clock cycle Alternate synchronization mode can be used only when several channels are enabled. It is not recommended to use this mode when a single channel is enabled. Rev. 0 | Page 41 of 58 AD4112 Data Sheet ERROR FLAGS The status register contains three error bits (ADC_ERROR, CRC_ERROR, and REG_ERROR) that flag errors with the ADC conversion, errors with the CRC check, and errors caused by changes in the registers, respectively. In addition, the ERROR output can indicate that an error has occurred. ADC_ERROR The ADC_ERROR bit in the status register flags any errors that occur during the conversion process. The flag is set when an overrange or underrange result is output from the ADC. The ADC also outputs all 0s or all 1s when an undervoltage or overvoltage occurs. This flag is reset only when the overvoltage or undervoltage is removed. This flag is not reset by a read of the data register. CRC_ERROR If the CRC value that accompanies a write operation does not correspond with the information sent, the CRC_ERROR flag is set. The flag is reset as soon as the status register is explicitly read. REG_ERROR The REG_ERROR flag is used in conjunction with the REG_CHECK bit in the interface mode register. When the REG_CHECK bit is set, the AD4112 monitors the values in the on-chip registers. If a bit changes, the REG_ERROR bit is set to 1. Therefore, for writes to the on-chip registers, set the REG_CHECK bit to 0. When the registers have been updated, the REG_CHECK bit can be set to 1. The AD4112 calculates a checksum of the on-chip registers. If one of the register values has changed, the REG_ERROR bit is set to 1. If an error is flagged, the REG_CHECK bit must be set to 0 to clear the REG_ERROR bit in the status register. The register check function does not monitor the data register, status register, or interface mode register. ERROR Input/Output The ERROR pin functions as an error input/output pin or as a general-purpose output pin. The ERR_EN bits in the GPIOCON register determine the function of the pin. When ERR_EN is set to 10, the ERROR pin functions as an open-drain error output. The three error bits in the status register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are OR'ed, inverted, and mapped to the ERROR output. Therefore, the ERROR output indicates that an error has occurred. The status register must be read to identify the error source. When ERR_EN is set to 01, the ERROR pin functions as an error input. The error output of another component can be connected to the AD4112 ERROR input so that the AD4112 indicates when an error occurs on either itself or the external component. The value on the ERROR input is inverted and OR'ed with the errors from the ADC conversion, and the result is indicated via the ADC_ERROR bit in the status register. The value of the ERROR input is reflected in the ERR_DAT bit in the GPIO onfiguration register. The ERROR input/output is disabled when ERR_EN is set to 00. When the ERR_EN bits are set to 11, the ERROR pin operates as a general-purpose output where the ERR_DAT bit is used to determine the logic level of the pin. DATA_STAT The contents of the status register can be appended to each conversion on the AD4112 using the DATA_STAT bit in the IFMODE register. This function is useful if several channels are enabled. Each time a conversion is output, the contents of the status register are appended. The four LSBs of the status register indicate to which channel the conversion corresponds. In addition, the user can determine if any errors are being flagged by the error bits. IOSTRENGTH The serial interface can operate with a power supply as low as 2 V. However, at this low voltage, the DOUT/RDY pin may not have sufficient drive strength if there is moderate parasitic capacitance on the board or if the SCLK frequency is high. The IOSTRENGTH bit in the interface mode register increases the drive strength of the DOUT/RDY pin. INTERNAL TEMPERATURE SENSOR The AD4112 has an integrated temperature sensor. The temperature sensor can be used as a guide for the ambient temperature at which the device is operating. The ambient temperature can be used for diagnostic purposes or as an indicator of when the application circuit must rerun a calibration routine to take into account a shift in operating temperature. The temperature sensor is selected using the multiplexer and is selected in the same way as an input channel. The temperature sensor requires that the input buffers be enabled on both inputs and the internal reference be enabled. To use the temperature sensor, the first step is to calibrate the device in a known temperature (25C) and take a conversion as a reference point. The temperature sensor has a nominal sensitivity of 477 V/K. The difference in this ideal slope and the slope measured can calibrate the temperature sensor. The temperature sensor is specified with a 2C typical accuracy after calibration at 25C. Calculate the temperature as follows: Temperature (C) = (Conversion Result / 477 V) - 273.15 Rev. 0 | Page 42 of 58 Data Sheet AD4112 APPLICATIONS INFORMATION GROUNDING AND LAYOUT The inputs and reference inputs are differential and, therefore, most of the voltages in the analog modulator are common-mode voltages. The high common-mode rejection of the device removes common-mode noise on these inputs. The analog and digital supplies to the AD4112 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the master clock frequency. The digital filter also removes noise from the analog inputs and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, the AD4112 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD4112 is high and the noise levels from the converter are so low, take care with regard to grounding and layout. The PCB that houses the ADC must be designed so that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes because it results in the best shielding. In any layout, the user must keep in mind the flow of currents in the system, ensuring that the paths for all return currents are as close as possible to the paths the currents took to reach their destinations. Avoid running digital lines under the device because this couples noise onto the die and allows the analog ground plane to run under the AD4112 to prevent noise coupling. The power supply lines to the AD4112 must use as wide a trace as possible to provide low impedance paths and reduce glitches on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This layout reduces the effects of feedthrough on the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side. Proper decoupling is important when using high resolution ADCs. The AD4112 has two power supply pins: AVDD and IOVDD. The AVDD pin is referenced to AVSS, and the IOVDD pin is referenced to DGND. Decouple AVDD with a 10 F tantalum capacitor in parallel with a 0.1 F capacitor to AVSS on each pin. Place the 0.1 F capacitor as near as possible to the device on each supply, ideally right up against the device. Decouple IOVDD with a 10 F tantalum capacitor, in parallel with a 0.1 F capacitor to DGND. Decouple all inputs to AVSS. If an external reference is used, decouple the REF+ and REF- pins to AVSS. The AD4112 also has two on-board LDO regulators: one that regulates the AVDD supply, and one that regulates the IOVDD supply. For the REGCAPA pin, it is recommended that 1 F and 0.1 F capacitors to AVSS be used. Similarly, for the REGCAPD pin, it is recommended that 1 F and 0.1 F capacitors to DGND be used. Rev. 0 | Page 43 of 58 AD4112 Data Sheet REGISTER SUMMARY Table 23. Register Summary Reg. Name 0x00 COMMS Bits [7:0] Bit 7 WEN 0x00 Status [7:0] RDY ADC_ERROR CRC_ERROR REG_ERROR Channel REF_EN Reserved Reserved Delay 0x2000 RW Reserved Reserved DOUT_RESET 0x0000 RW Reserved WL16 0x000000 R 0x01 ADCMODE [15:8] [7:0] 0x02 IFMODE [15:8] [7:0] 0x03 REGCHECK [23:16] [15:8] [7:0] 0x04 Data [23:16] [15:8] [7:0] 0x06 GPIOCON [15:8] [7:0] 0x07 ID [15:8] [7:0] 0x10 CH0 [15:8] [7:0] 0x11 CH1 [15:8] [7:0] 0x12 CH2 [15:8] [7:0] 0x13 CH3 [15:8] [7:0] 0x14 CH4 [15:8] [7:0] 0x15 CH5 [15:8] [7:0] 0x16 CH6 [15:8] [7:0] 0x17 CH7 [15:8] [7:0] 0x18 CH8 [15:8] [7:0] 0x19 CH9 [15:8] [7:0] 0x1A CH10 [15:8] [7:0] 0x1B CH11 [15:8] [7:0] 0x1C CH12 [15:8] [7:0] 0x1D CH13 [15:8] [7:0] 0x1E CH14 [15:8] [7:0] 0x1F CH15 [15:8] [7:0] 0x20 SETUPCON0 [15:8] [7:0] 0x21 SETUPCON1 [15:8] [7:0] CONTREAD Reserved GP_DATA1 Bit 6 R/W Reserved DATA_STAT Reserved GP_DATA0 CH_EN0 CH_EN1 CH_EN2 CH_EN3 CH_EN4 CH_EN5 CH_EN6 CH_EN7 CH_EN8 CH_EN9 CH_EN10 CH_EN11 CH_EN12 CH_EN13 CH_EN14 CH_EN15 Reserved Reserved Reserved Reserved Reserved Reserved Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RA SING_CYC Mode Reserved CLOCKSEL ALT_SYNC IOSTRENGTH REG_CHECK Reserved CRC_EN REGISTER_CHECK[23:16] REGISTER_CHECK[15:8] REGISTER_CHECK[7:0] Data [23:16] Data [15:8] Data [7:0] OP_EN0_1 Reserved SYNC_EN ERR_EN Reserved ID[15:8] ID[7:0] SETUP_SEL0 Reserved INPUT0 [7:0] SETUP_SEL1 Reserved INPUT1[7:0] SETUP_SEL2 Reserved INPUT2[7:0] SETUP_SEL3 Reserved INPUT3[7:0] SETUP_SEL4 Reserved INPUT4[7:0] SETUP_SEL5 Reserved INPUT5[7:0] SETUP_SEL6 Reserved INPUT6[7:0] SETUP_SEL7 Reserved INPUT7[7:0] SETUP_SEL8 Reserved INPUT8[7:0] SETUP_SEL9 Reserved INPUT9[7:0] SETUP_SEL10 Reserved Input10[7:0] SETUP_SEL11 Reserved INPUT11[7:0] SETUP_SEL12 Reserved INPUT12[7:0] SETUP_SEL13 Reserved INPUT13[7:0] SETUP_SEL14 Reserved INPUT14[7:0] SETUP_SEL15 Reserved INPUT15[7:0] BI_UNIPOLAR0 REFBUF0+ REFBUF0- REF_SEL0 Reserved BI_UNIPOLAR1 REFBUF1+ REFBUF1- REF_SEL1 Reserved Rev. 0 | Page 44 of 58 Reset 0x00 RW W 0x80 R 0x000000 R ERR_DAT 0x0800 RW 0x30Dx R INPUT0[9:8] 0x8001 RW INPUT1[9:8] 0x0001 RW INPUT2[9:8] 0x0001 RW INPUT3[9:8] 0x0001 RW INPUT4[9:8] 0x0001 RW INPUT5[9:8] 0x0001 RW INPUT6[9:8] 0x0001 RW INPUT7[9:8] 0x0001 RW INPUT8[9:8] 0x0001 RW INPUT9[9:8] 0x0001 RW INPUT10[9:8] 0x0001 RW INPUT11[9:8] 0x0001 RW INPUT12[9:8] 0x0001 RW INPUT13[9:8] 0x0001 RW INPUT14[9:8] 0x0001 RW INPUT15[9:8] 0x0001 RW INBUF0 0x1000 RW INBUF1 0x1000 RW Data Sheet Reg. Name Bits 0x22 SETUPCON2 [15:8] [7:0] 0x23 SETUPCON3 [15:8] [7:0] 0x24 SETUPCON4 [15:8] [7:0] 0x25 SETUPCON5 [15:8] [7:0] 0x26 SETUPCON6 [15:8] [7:0] 0x27 SETUPCON7 [15:8] [7:0] 0x28 FILTCON0 [15:8] [7:0] 0x29 FILTCON1 [15:8] [7:0] 0x2A FILTCON2 [15:8] [7:0] 0x2B FILTCON3 [15:8] [7:0] 0x2C FILTCON4 [15:8] [7:0] 0x2D FILTCON5 [15:8] [7:0] 0x2E FILTCON6 [15:8] [7:0] 0x2F FILTCON7 [15:8] [7:0] 0x30 OFFSET0 [23:0] 0x31 OFFSET1 [23:0] 0x32 OFFSET2 [23:0] 0x33 OFFSET3 [23:0] 0x34 OFFSET4 [23:0] 0x35 OFFSET5 [23:0] 0x36 OFFSET6 [23:0] 0x37 OFFSET7 [23:0] 0x38 GAIN0 [23:0] 0x39 GAIN1 [23:0] 0x3A GAIN2 [23:0] 0x3B GAIN3 [23:0] 0x3C GAIN4 [23:0] 0x3D GAIN5 [23:0] 0x3E GAIN6 [23:0] 0x3F GAIN7 [23:0] AD4112 Bit 7 Reserved Reserved Reserved Reserved Reserved Reserved SINC3_MAP0 Reserved SINC3_MAP1 Reserved SINC3_MAP2 Reserved SINC3_MAP3 Reserved SINC3_MAP4 Reserved SINC3_MAP5 Reserved SINC3_MAP6 Reserved SINC3_MAP7 Reserved Bit 6 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 5 Bit 4 Bit 3 BI_UNIPOLAR2 REFBUF2+ REF_SEL2 BI_UNIPOLAR3 REFBUF3+ REF_SEL3 BI_UNIPOLAR4 REFBUF4+ REF_SEL4 BI_UNIPOLAR5 REFBUF5+ REF_SEL5 BI_UNIPOLAR6 REFBUF6+ REF_SEL6 BI_UNIPOLAR7 REFBUF7+ REF_SEL7 Reserved ENHFILTEN0 ORDER0 Reserved ENHFILTEN1 ORDER1 Reserved ENHFILTEN2 ORDER2 Reserved ENHFILTEN3 ORDER3 Reserved ENHFILTEN4 ORDER4 Reserved ENHFILTEN5 ORDER5 Reserved ENHFILTEN6 ORDER6 Reserved ENHFILTEN7 ORDER7 OFFSET0[23:0] OFFSET1[23:0] OFFSET2[23:0] OFFSET3[23:0] OFFSET4[23:0] OFFSET5[23:0] OFFSET6[23:0] OFFSET7[23:0] GAIN0[23:0] GAIN1[23:0] GAIN2[23:0] GAIN3[23:0] GAIN4[23:0] GAIN5[23:0] GAIN6[23:0] GAIN7[23:0] Rev. 0 | Page 45 of 58 Bit 2 Bit 1 Bit 0 REFBUF2- INBUF2 Reserved REFBUF3- INBUF3 Reserved REFBUF4- INBUF4 Reserved REFBUF5- INBUF5 Reserved REFBUF6- INBUF6 Reserved REFBUF7- INBUF7 Reserved ENHFILT0 ODR0 ENHFILT1 ODR1 ENHFILT2 ODR2 ENHFILT3 ODR3 ENHFILT4 ODR4 ENHFILT5 ODR5 ENHFILT6 ODR6 ENHFILT7 ODR7 Reset 0x1000 RW RW 0x1000 RW 0x1000 RW 0x1000 RW 0x1000 RW 0x1000 RW 0x0500 RW 0x0500 RW 0x0500 RW 0x0500 RW 0x0500 RW 0x0500 RW 0x0500 RW 0x0500 RW 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW AD4112 Data Sheet REGISTER DETAILS COMMUNICATIONS REGISTER Address: 0x00, Reset: 0x00, Name: COMMS All access to the on-chip registers must start with a write to the communications register. This write determines which register is accessed next and whether that operation is a write or a read. Table 24. Bit Descriptions for COMMS Bits 7 Bit Name WEN 6 R/W Settings 0 1 [5:0] RA 000000 000001 000010 000011 000100 000110 000111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Description This bit must be low to begin communications with the ADC Reset 0x0 Access W This bit determines if the command is a read or write operation Write command Read command The register address bits determine the register to be read from or written to as part of the current communication Status register ADC mode register Interface mode register Register checksum register Data register GPIO configuration register ID register Channel 0 register Channel 1 register Channel 2 register Channel 3 register Channel 4 register Channel 5 register Channel 6 register Channel 7 register Channel 8 register Channel 9 register Channel 10 register Channel 11 register Channel 12 register Channel 13 register Channel 14 register Channel 15 register Setup Configuration 0 register Setup Configuration 1 register Setup Configuration 2 register Setup Configuration 3 register Setup Configuration 4 register Setup Configuration 5 register Setup Configuration 6 register Setup Configuration 7 register Filter Configuration 0 register Filter Configuration 1 register Filter Configuration 2 register Filter Configuration 3 register Filter Configuration 4 register Filter Configuration 5 register Filter Configuration 6 register Filter Configuration 7 register 0x0 W 0x00 W Rev. 0 | Page 46 of 58 Data Sheet Bits Bit Name AD4112 Settings 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Description Offset 0 register Offset 1 register Offset 2 register Offset 3 register Offset 4 register Offset 5 register Offset 6 register Offset 7 register Gain 0 register Gain 1 register Gain 2 register Gain 3 register Gain 4 register Gain 5 register Gain 6 register Gain 7 register Reset Access STATUS REGISTER Address: 0x00, Reset: 0x80, Name: Status The status register is an 8-bit register that contains ADC and serial interface status information. The register can optionally be appended to the data register by setting the DATA_STAT bit in the interface mode register. Table 25. Bit Descriptions for STATUS Bits 7 Bit Name RDY Settings 0 1 6 ADC_ERROR 0 1 5 CRC_ERROR 0 1 4 REG_ERROR 0 1 Description The status of RDY is output to the DOUT/RDY pin when CS is low and a register is not being read. This bit goes low when the ADC writes a new result to the data register. In ADC calibration modes, this bit goes low when the ADC writes the calibration result. RDY is brought high automatically by a read of the data register. New data result available. Awaiting new data result. By default, this bit indicates if an ADC overrange or underrange occurred. The ADC result is clamped to 0xFFFFFF for overrange errors and 0x000000 for underrange errors. This bit is updated when the ADC result is written and is cleared at the next update after removing the overrange or underrange condition. No error. Error. This bit indicates if a CRC error occurred during a register write. For register reads, the host microcontroller determines if a CRC error occurred. This bit is cleared by a read of this register. No error. CRC error. This bit indicates if the content of one of the internal registers changes from the value calculated when the register integrity check is activated. The check is activated by setting the REG_CHECK bit in the interface mode register. This bit is cleared by clearing the REG_CHECK bit. No error. Error. Rev. 0 | Page 47 of 58 Reset 0x1 Access R 0x0 R 0x0 R 0x0 R AD4112 Bits [3:0] Bit Name Channel Data Sheet Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description These bits indicate which channel was active for the ADC conversion whose result is currently in the data register. This may be different from the channel currently being converted. The mapping is a direct map from the channel register; therefore, Channel 0 results in 0x0 and Channel 15 results in 0xF. Channel 0. Channel 1. Channel 2. Channel 3. Channel 4. Channel 5. Channel 6. Channel 7. Channel 8. Channel 9. Channel 10. Channel 11. Channel 12. Channel 13. Channel 14. Channel 15. Reset 0x0 Access R ADC MODE REGISTER Address: 0x01, Reset: 0x2000, Name: ADCMODE The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets the filter and the RDY bits and starts a new conversion or calibration. Table 26. Bit Descriptions for ADCMODE Bits 15 Bit Name REF_EN Settings 0 1 14 13 Reserved SING_CYC 0 1 [12:11] [10:8] Reserved Delay 000 001 010 011 100 101 110 111 7 Reserved Description Enables internal reference and outputs a buffered 2.5 V to the REFOUT pin. Disabled. Enabled. This bit is reserved. Set this bit to 0. This bit can be used when only a single channel is active to set the ADC to only output at the settled filter data rate. Disabled. Enabled. These bits are reserved; set these bits to 0. These bits allow a programmable delay to be added after a channel switch to allow the settling of external circuitry before the ADC starts processing its input. 0 s. 32 s. 128 s. 320 s. 800 s. 1.6 ms. 4 ms. 8 ms. This bit is reserved. Set this bit to 0. Rev. 0 | Page 48 of 58 Reset 0x0 Access RW 0x0 0x1 RW RW 0x0 0x0 R RW 0x0 R Data Sheet Bits [6:4] Bit Name Mode AD4112 Settings 000 001 010 011 100 101 110 111 [3:2] CLOCKSEL 00 01 10 11 [1:0] Reserved Description These bits control the operating mode of the ADC. See the Operating Modes section for more information. Continuous conversion mode. Single conversion mode. Standby mode. Power-down mode. Internal offset calibration. Internal gain calibration System offset calibration. System gain calibration. These bits select the ADC clock source. Selecting the internal oscillator also enables the internal oscillator. Internal oscillator. Internal oscillator output on the XTAL2/CLKIO pin. External clock input on the XTAL2/CLKIO pin. External crystal on the XTAL1 pin and the XTAL2/CLKIO pin. These bits are reserved; set these bits to 0. Reset 0x0 Access RW 0x0 RW 0x0 R Reset 0x0 0x0 Access R RW 0x0 RW 0x0 0x0 R RW 0x0 RW 0x0 RW INTERFACE MODE REGISTER Address: 0x02, Reset: 0x0000, Name: IFMODE The interface mode register configures various serial interface options. Table 27. Bit Descriptions for IFMODE Bits [15:13] 12 Bit Name Reserved ALT_SYNC Settings 0 1 11 IOSTRENGTH 0 1 [10:9] 8 Reserved DOUT_RESET 0 1 7 CONTREAD 0 1 6 DATA_STAT 0 1 Description These bits are reserved; set these bits to 0. This bit enables a different behavior of the SYNC pin to allow the use of SYNC as a control for conversions when cycling channels Disabled. Enabled. This bit controls the drive strength of the DOUT/RDY pin. Set this bit when reading from the serial interface at high speed with a low IOVDD supply and moderate capacitance. Disabled (default). Enabled. These bits are reserved; set these bits to 0. See the DOUT_RESET section Disabled. Enabled. This bit enables the continuous read mode of the ADC data register. The ADC must be configured in continuous conversion mode to use continuous read mode. For more details, see the Operating Modes section. Disabled. Enabled. This bit enables the status register to be appended to the data register when read so that channel and status information are transmitted with the data. This is the only way to be sure that the channel bits read from the status register correspond to the data in the data register. Disabled. Enabled. Rev. 0 | Page 49 of 58 AD4112 Bits 5 Bit Name REG_CHECK Data Sheet Settings 0 1 4 [3:2] Reserved CRC_EN 00 01 10 1 0 Reserved WL16 0 1 Description This bit enables a register integrity checker, which can be used to monitor any change in the value of the user registers. To use this feature, configure all other registers as desired with this bit cleared. Then, write to this register to set the REG_CHECK bit to 1. If the contents of any of the registers change, the REG_ERROR bit is set in the status register. To clear the error, set the REG_CHECK bit to 0. Neither the interface mode register nor the ADC data or status registers are included in the registers that are checked. If a register must have a new value written, this bit must first be cleared; otherwise, an error is flagged when the new register contents are written. Disabled. Enabled. This bit is reserved. Set this bit to 0. These bits enable CRC protection of register reads/writes. CRC increases the number of bytes in a serial interface transfer by one. Disabled XOR checksum enabled for register read transactions; register writes still use CRC with these bits set. CRC checksum enabled for read and write transactions. This bit is reserved. Set this bit to 0. This bit changes the ADC data register to 16 bits. The ADC is not reset by a write to the interface mode register; therefore, the ADC result is not rounded to the correct word length immediately after writing to these bits. The first new ADC result is correct. 24-bit data. 16-bit data. Reset 0x0 Access RW 0x0 0x00 R RW 0x0 0x0 R RW REGISTER CHECK Address: 0x03, Reset: 0x000000, Name: REGCHECK The register check register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK bit in the interface mode register must be set for this checksum to operate; otherwise, the register reads 0. Table 28. Bit Descriptions for REGCHECK Bits [23:0] Bit Name REGISTER_CHECK Settings Description This register contains the 24-bit checksum of user registers when the REG_CHECK bit is set in the interface mode register. Reset 0x000000 Access R DATA REGISTER Address: 0x04, Reset: 0x000000, Name: Data The data register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the BI_UNIPOLARx bits in the setup configuration registers. Reading the data register brings the RDY bit and the RDY output high if it is low. The ADC result can be read multiple times. However, because the RDY output is brought high, it is not possible to determine if another ADC result is imminent. After the command to read the ADC register is received, the ADC does not write a new result into the data register. Table 29. Bit Descriptions for Data Bits [23:0] Bit Name Data Settings Description This register contains the ADC conversion result. If DATA_STAT is set in the interface mode register, the status register is appended to this register when read, making this a 32-bit register. If WL16 is set in the interface mode register, this register is reduced to 16 bits. Rev. 0 | Page 50 of 58 Reset 0x000000 Access R Data Sheet AD4112 GPIO CONFIGURATION REGISTER Address: 0x06, Reset: 0x0800, Name: GPIOCON The GPIO configuration register controls the general-purpose I/O pins of the ADC. Table 30. Bit Descriptions for GPIOCON Bits [15:14] 13 Bit Name Reserved OP_EN0_1 Settings 0 1 12 11 Reserved SYNC_EN 0 1 [10:9] ERR_EN 00 01 10 11 8 ERR_DAT 0 1 7 GP_DATA1 0 1 6 GP_DATA0 0 1 [5:0] Reserved Description Reserved. GPO0/GPO1 output enable. This bit enables the GPO0 and GPO1 pins. The outputs are referenced between AVDD and AVSS. Disabled. Enabled. Reserved SYNC input enable. This bit enables the SYNC pin as a sync input. When set low, the SYNC pin holds the ADC and filter in reset until SYNC goes high. An alternative operation of the SYNC pin is available when the ALT_SYNC bit in the interface mode register is set. This mode works only when multiple channels are enabled. In such cases, a low on the SYNC pin does not immediately reset the filter/modulator. Instead, if the SYNC pin is low when the channel is due to be switched, the modulator and filter are prevented from starting a new conversion. Bringing SYNC high begins the next conversion. This alternative sync mode allows SYNC to be used while cycling through channels. Disabled. Enabled. Error pin mode. These bits enable the ERROR pin as an error input/output. Disabled. Enable error input (active low). ERROR is an error input. The (inverted) readback state is OR'ed with other error sources and is available in the ADC_ERROR bit in the status register. The ERROR pin state can also be read from the ERR_DAT bit in this register. Enable open-drain error output (active low). ERROR is an open-drain error output. The status register error bits are OR'ed, inverted, and mapped to the ERROR pin. ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any device can be observed. General-purpose output (active low). ERROR is a general-purpose output. The status of the pin is controlled by the ERR_DAT bit in this register. This output is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the GPIOx pins. The output has an active pull-up resistor in this case. Error pin data. This bit determines the logic level at the ERROR pin if the pin is enabled as a general-purpose output. This bit reflects the readback status of the pin if the pin is enabled as an input. Logic 0. Logic 1. GPO1 data. This bit is the write data for GPO1. GPO1 = 0. GPO1 = 1. GPO0 data. This bit is the write data for GPO0. GPO0 = 0. GPO0 = 1. Reserved. Rev. 0 | Page 51 of 58 Reset 0x0 0x0 Access R R/W 0x0 0x1 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R AD4112 Data Sheet ID REGISTER Address: 0x07, Reset: 0x30DX, Name: ID The ID register returns a 16-bit ID. For the AD4112, this value is 0x30DX. Table 31. Bit Descriptions for ID Bits [15:0] Bit Name ID Settings Description Product ID. The ID register returns a 16-bit ID code that is specific to the ADC. Reset 0x30DX Access R CHANNEL REGISTER 0 Address: 0x10, Reset: 0x8001, Name: CH0 The channel registers are 16-bit registers that select the currently active channels, the selected inputs for each channel, and the setup to be used to configure the ADC for that channel. Table 32. Bit Descriptions for CH0 Bits 15 Bit Name CH_EN0 Settings 0 1 [14:12] SETUP_SEL0 000 001 010 011 100 101 110 111 [11:10] [9:0] Reserved INPUT0 0000000001 0000010000 0000100000 0000110000 0001000011 0001010000 0001100010 0001110000 0010000101 0010010000 0010100100 0010110000 0011000111 0011010000 0011100110 0011110000 0110001011 0110101010 0111001001 Description This bit enables Channel 0. If more than one channel is enabled, the ADC automatically sequences between them. Disabled. Enabled. These bits identify which of the eight setups is used to configure the ADC for this channel. A setup comprises a set of four registers: a setup configuration register, a filter configuration register, an offset register, and a gain register. All channels can use the same setup, in which case the same 3-bit value must be written to these bits on all active channels, or up to eight channels can be configured differently. Setup 0. Setup 1. Setup 2. Setup 3. Setup 4. Setup 5. Setup 6. Setup 7. Reserved. These bits select which input pair is connected to the input of the ADC for this channel. VIN0, VIN1. VIN0, VINCOM. VIN1, VIN0. VIN1, VINCOM. VIN2, VIN3. VIN2, VINCOM. VIN3, VIN2. VIN3, VINCOM. VIN4, VIN5. VIN4, VINCOM. VIN5, VIN4. VIN5, VINCOM. VIN6, VIN7. VIN6, VINCOM. VIN7, VIN6. IN7, VINCOM. IIN3+,IIN3-. IIN2+,IIN2-. IIN1+,IIN1-. Rev. 0 | Page 52 of 58 Reset 0x1 Access R/W 0x0 R/W 0x0 0x1 R R/W Data Sheet Bits Bit Name AD4112 Settings 0111101000 1000110010 1010110110 Description IIN0+,IIN0-. Temperature sensor. Reference. Reset Access CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 Address: 0x11 to Address 0x1F, Reset: 0x0001, Name: CH1 to CH7 The remaining 15 channel registers share the same layout as Channel Register 0. Table 33. CH1 to CH15 Register Map Reg. 0x11 Name CH1 0x12 CH2 0x13 CH3 0x14 CH4 0x15 CH5 0x16 CH6 0x17 CH7 0x18 CH8 0x19 CH9 0x1A CH10 0x1B CH11 0x1C CH12 0x1D CH13 0x1E CH14 0x1F CH15 Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 7 CH_EN1 CH_EN2 CH_EN3 CH_EN4 CH_EN5 CH_EN6 CH_EN7 CH_EN8 CH_EN9 CH_EN10 CH_EN11 CH_EN12 CH_EN13 CH_EN14 CH_EN15 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SETUP_SEL1 Reserved INPUT1[7:0] SETUP_SEL2 Reserved INPUT2[7:0] SETUP_SEL3 Reserved INPUT3[7:0] SETUP_SEL4 Reserved INPUT4[7:0] SETUP_SEL5 Reserved INPUT5[7:0] SETUP_SEL6 Reserved INPUT6[7:0] SETUP_SEL7 Reserved INPUT7[7:0] SETUP_SEL8 Reserved INPUT8[7:0] SETUP_SEL9 Reserved INPUT9[7:0] SETUP_SEL10 Reserved INPUT10[7:0] SETUP_SEL11 Reserved INPUT11[7:0] SETUP_SEL12 Reserved INPUT12[7:0] SETUP_SEL13 Reserved INPUT13[7:0] SETUP_SEL14 Reserved INPUT14[7:0] SETUP_SEL15 Reserved INPUT15[7:0] Rev. 0 | Page 53 of 58 Bit 1 Bit 0 INPUT1[9:8] Reset 0x0001 RW RW INPUT2[9:8] 0x0001 RW INPUT3[9:8] 0x0001 RW INPUT4[9:8] 0x0001 RW INPUT5[9:8] 0x0001 RW INPUT6[9:8] 0x0001 RW INPUT7[9:8] 0x0001 RW INPUT8[9:8] 0x0001 RW INPUT9[9:8] 0x0001 RW INPUT10[9:8] 0x0001 RW INPUT11[9:8] 0x0001 RW INPUT12[9:8] 0x0001 RW INPUT13[9:8] 0x0001 RW INPUT14[9:8] 0x0001 RW INPUT15[9:8] 0x0001 RW AD4112 Data Sheet SETUP CONFIGURATION REGISTER 0 Address: 0x20, Reset: 0x1000 Name: SETUPCON0 The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC. Table 34. Bit Descriptions for SETUPCON0 Bits [15:13] 12 Bit Name Reserved BI_UNIPOLAR0 Settings 0 1 11 REFBUF0+ 0 1 10 REFBUF0- 0 1 [9:8] INBUF0 00 01 10 11 7 6 [5:4] Reserved Reserved REF_SEL0 00 10 11 [3:0] Reserved Description These bits are reserved; set these bits to 0. Bipolar/unipolar. This bit sets the output coding of the ADC for Setup 0. Unipolar coded output. Bipolar coded output. REF+ buffer. This bit enables or disables the REF+ input buffer. Disabled. Enabled. REF- buffer. This bit enables or disables the REF- input buffer. Disabled. Enabled. Input buffer. This bit enables or disables input buffers. Disabled. Reserved. Reserved. Enabled. This bit is reserved. Set this bit to 0. This bit is reserved. Set this bit to 0. These bits allow the user to select the reference source for ADC conversion on Setup 0. External reference - REF. Internal 2.5 V reference, must be enabled via ADCMODE (see Table 26). AVDD - AVSS. These bits are reserved; set these bits to 0. Reset 0x0 0x1 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 0x0 R R R/W 0x0 R SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 Address: 0x21 to Address 0x27, Reset: 0x1000, Name: SETUPCON1 to SETUPCON7 The remaining seven setup configuration registers share the same layout as Setup Configuration Register 0. Table 35. SETUPCON1 to SETUPCON7 Register Map Reg. 0x21 Name SETUPCON1 0x22 SETUPCON2 0x23 SETUPCON3 0x24 SETUPCON4 0x25 0x26 0x27 SETUPCON5 SETUPCON6 SETUPCON7 Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 6 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 5 Bit 4 BI_UNIPOLAR1 REF_SEL1 BI_UNIPOLAR2 REF_SEL2 BI_UNIPOLAR3 REF_SEL3 BI_UNIPOLAR4 REF_SEL4 BI_UNIPOLAR5 REF_SEL5 BI_UNIPOLAR6 REF_SEL6 BI_UNIPOLAR7 REF_SEL7 Rev. 0 | Page 54 of 58 Bit 3 REFBUF1+ REFBUF2+ REFBUF3+ REFBUF4+ REFBUF5+ REFBUF6+ REFBUF7+ Bit 2 REFBUF1- Reserved REFBUF2- Reserved REFBUF3- Reserved REFBUF4- Reserved REFBUF5- Reserved REFBUF6- Reserved REFBUF7- Reserved Bit 1 Bit 0 Reset INBUF1 0x1000 RW RW INBUF2 0x1000 RW INBUF3 0x1000 RW INBUF4 0x1000 RW INBUF5 0x1000 RW INBUF6 0x1000 RW INBUF7 0x1000 RW Data Sheet AD4112 FILTER CONFIGURATION REGISTER 0 Address: 0x28, Reset: 0x0500, Name: FILTCON0 The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets any active ADC conversion and restarts converting at the first channel in the sequence. Table 36. Bit Descriptions for FILTCON0 Bits 15 Bit Name SINC3_MAP0 [14:12] 11 Reserved ENHFILTEN0 Settings 0 1 [10:8] ENHFILT0 010 011 101 110 7 [6:5] Reserved ORDER0 00 11 [4:0] ODR0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 Description If this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter for Setup 0. All other options are eliminated. This bit allows fine tuning of the output data rate and filter notch for rejection of specific frequencies. The data rate when on a single channel equals fMOD/(32 x FILTCON0[14:0]). These bits are reserved; set these bits to 0. This bit enables various postfilters for enhanced 50 Hz/60 Hz rejection for Setup 0. The ORDER0 bits must be set to 00 to select the sinc5 + sinc1 filter for this function to work. Disabled. Enabled. These bits select between various postfilters for enhanced 50 Hz/ 60 Hz rejection for Setup 0. 27 SPS, 47 dB rejection, 36.7 ms settling 25 SPS, 62 dB rejection, 40 ms settling 20 SPS, 86 dB rejection, 50 ms settling 16.67 SPS, 92 dB rejection, 60 ms settling This bit is reserved. Set this bit to 0. These bits control the order of the digital filter that processes the modulator data for Setup 0. Sinc5 + sinc1 (default). Sinc3. These bits control the output data rate of the ADC and, therefore, the settling time and noise for Setup 0. Rates shown are for single channel enabled sinc5 + sinc 1 filter. See Table 6 to Table 9 for multiple channels enabled. 31,250 SPS. 31,250 SPS. 31,250 SPS. 31,250 SPS. 31,250 SPS. 31,250 SPS. 15,625 SPS. 10,417 SPS. 5208 SPS. 2597 SPS (3906 SPS for sinc3). 1007 SPS (1157 SPS for sinc3). 503.8 SPS (539 SPS for sinc3). 381 SPS (401 SPS for sinc3). 200.3 SPS (206 SPS for sinc3). 100.2 SPS (102 SPS for sinc3). 59.52 SPS (59.98 SPS for sinc3). 49.68 SPS (50 SPS for sinc3). 20.01 SPS. 16.63 SPS (16.67 SPS for sinc3). 10 SPS. 5 SPS. 2.5 SPS. 1.25 SPS. Rev. 0 | Page 55 of 58 Reset 0x0 Access RW 0x0 0x0 R RW 0x5 RW 0x0 0x0 R RW 0x0 RW AD4112 Data Sheet FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 Address: 0x29 to Address 0x2F, Reset: 0x0500, Name: FILTCON1 to FILTCON7 The remaining seven filter configuration registers share the same layout as Filter Configuration Register 0. Table 37. FILTCON1 to FILTCON7 Register Map Reg. 0x29 Name FILTCON1 0x2A FILTCON2 0x2B FILTCON3 0x2C FILTCON4 0x2D FILTCON5 0x2E FILTCON6 0x2F FILTCON7 Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 7 SINC3_MAP1 Reserved SINC3_MAP2 Reserved SINC3_MAP3 Reserved SINC3_MAP4 Reserved SINC3_MAP5 Reserved SINC3_MAP6 Reserved SINC3_MAP7 Reserved Bit 6 Bit 5 Bit 4 Reserved ORDER1 Reserved ORDER2 Reserved ORDER3 Reserved ORDER4 Reserved ORDER5 Reserved ORDER6 Reserved ORDER7 Bit 3 ENHFILTEN1 Bit 2 Bit 1 Bit 0 ENHFILT1 Reset 0x0500 RW RW ENHFILT2 0x0500 RW ENHFILT3 0x0500 RW ENHFILT4 0x0500 RW ENHFILT5 0x0500 RW ENHFILT6 0x0500 RW ENHFILT7 0x0500 RW ODR1 ENHFILTEN2 ODR2 ENHFILTEN3 ODR3 ENHFILTEN4 ODR4 ENHFILTEN5 ODR5 ENHFILTEN6 ODR6 ENHFILTEN7 ODR7 OFFSET REGISTER 0 Address: 0x30, Reset: 0x800000, Name: OFFSET0 The offset (zero-scale) registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system. Table 38. Bit Descriptions for OFFSET0 Bits [23:0] Bit Name OFFSET0 Settings Description Offset calibration coefficient for Setup 0. Reset 0x800000 Access RW OFFSET REGISTER 1 TO OFFSET REGISTER 7 Address: 0x31 to Address 0x37, Reset: 0x800000, Name: OFFSET1 to OFFSET7 The remaining seven offset registers share the same layout as Offset Register 0. Table 39. OFFSET1 to OFFSET7 Register Map Reg. 0x31 0x32 0x33 0x34 0x35 0x36 0x37 Name OFFSET1 OFFSET2 OFFSET3 OFFSET4 OFFSET5 OFFSET6 OFFSET7 Bits [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] Bits[23:0] OFFSET1[23:0] OFFSET2[23:0] OFFSET3[23:0] OFFSET4[23:0] OFFSET5[23:0] OFFSET6[23:0] OFFSET7[23:0] Reset 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 Rev. 0 | Page 56 of 58 RW RW RW RW RW RW RW RW Data Sheet AD4112 GAIN REGISTER 0 Address: 0x38, Reset: 0x5XXXX0, Name: GAIN0 The gain (full-scale) registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system. Table 40. Bit Descriptions for GAIN0 Bits [23:0] 1 Bit Name GAIN0 Settings Description Gain calibration coefficient for Setup 0. Reset1 0x5XXXX0 Access RW Reset1 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 RW RW RW RW RW RW RW RW X means don't care. GAIN REGISTER 1 TO GAIN REGISTER 7 Address: 0x39 to 0x3F, Reset: 0x5XXXX0, Name: GAIN1 to GAIN7 The remaining seven gain registers share the same layout as Gain Register 0. Table 41. GAIN1 to GAIN7 Register Map Reg. 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 1 Name GAIN1 GAIN2 GAIN3 GAIN4 GAIN5 GAIN6 GAIN7 Bits [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] Bits[23:0] GAIN1[23:0] GAIN2[23:0] GAIN3[23:0] GAIN4[23:0] GAIN5[23:0] GAIN6[23:0] GAIN7[23:0] X means don't care. Rev. 0 | Page 57 of 58 AD4112 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 6.10 6.00 SQ 5.90 40 31 1 30 0.50 BSC 4.70 4.60 SQ 4.50 EXPOSED PAD TOP VIEW 1.00 0.95 0.85 SIDE VIEW PKG-003653/5050 SEATING PLANE 0.45 0.40 0.35 21 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 10 BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5 10-25-2017-C PIN 1 INDICATOR 0.30 0.25 0.18 Figure 59. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm x 6 mm Body and 0.95 mm Package Height (CP-40-15) Dimensions shown in millimeters ORDERING GUIDE Model1 AD4112BCPZ AD4112BCPZ-RL7 EVAL-AD4112SDZ EVAL-SDP-CB1Z 1 Temperature Range -40C to +105C -40C to +105C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP] 40-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Evaluation Controller Board Z = RoHS Compliant Part. (c)2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16465-0-8/18(0) Rev. 0 | Page 58 of 58 Package Option CP-40-15 CP-40-15