19-3884; Rev 2; 2/07 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry Features 15kV ESD Protection on I/O VCC_ Lines Bidirectional Level Translation Without Direction Pin I/O VL_ and I/O VCC_ 10mA Sink-/15mA SourceCurrent Capability Slew-Rate Enhancement Circuitry Supports Larger Capacitive Loads or Larger External Pullup Resistors 6Mbps Push-Pull/1Mbps Open-Drain Guaranteed Data Rate Wide Supply-Voltage Range: Operation Down to +1.2V on VL and +1.65V on VCC Low Supply Current in Tri-State Output Mode (3A typ) Low Quiescent Current Thermal-Shutdown Protection UCSP, TDFN, and TQFN Packages PIN-PACKAGE PKG CODE MAX3394EETA+T 8 TDFN-EP** MAX3394EEBL+T 9 UCSP MAX3395EETC+ 12 TQFN-EP** T833-1 MAX3395EEBC+T 12 UCSP B12-1 MAX3396EEBP+T* 20 UCSP B20-1 B9-5 T1244-4 MAX3396EETP+* 20 TQFN-EP** T2055-4 Note: All devices specified over the -40C to +85C operating range. +Denotes lead(Pb)-free/RoHS-compliant package. *Future product--contact factory for availability. **EP = Exposed paddle. Selector Guide appears at end of data sheet. 8 GND TOP VIEW (LEADS ON BOTTOM) I/O VL1 Pin Configurations I/O VL2 High-Speed Bus Fan-Out Expansion Cell Phones PART VL Applications Multivoltage Bidirectional Level Translation SPITM, MICROWIRETM, and I2C Level Translation Open-Drain Rise-Time Speed-Up Ordering Information 7 6 5 *EP Telecom, Networking, Servers, RAID/SAN MAX3394E SPI is a trademark of Motorola, Inc. UCSP is a trademark of Maxim Integrated Products, Inc. 3 4 I/O VCC2 MICROWIRE is a trademark of National Semiconductor Corp. 2 I/O VCC1 VCC 1 EN + TDFN *CONNECT EXPOSED PAD TO GROUND Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX3394E/MAX3395E/MAX3396E General Description The MAX3394E/MAX3395E/MAX3396E bidirectional level translators provide level shifting required for data transfer in a multivoltage system. Internal slew-rate enhancement circuitry features 10mA current-sink and 15mA current-source drivers to isolate capacitive loads from lower current drivers. In open-drain systems, slewrate enhancement enables fast data rates with larger pullup resistors and increased bus load capacitance. Externally applied voltages, VCC and VL, set the logichigh levels for the device. A logic-low signal on one I/O side of the device appears as a logic-low signal on the opposite I/O side, and vice-versa. Each I/O line is pulled up to VCC or VL by an internal pullup resistor, allowing the devices to be driven by either push-pull or open-drain drivers. The MAX3394E/MAX3395E/MAX3396E feature a tristate output mode, thermal-shutdown protection, and 15kV Human Body Model (HBM) ESD protection on the VCC side for greater protection in applications that route signals externally. The MAX3394E/MAX3395E/MAX3396E accept VCC voltages from +1.65V to +5.5V, and VL voltages from +1.2V to VCC, making them ideal for data transfer between low voltage ASIC/PLDs and higher voltage systems. The MAX3394E/MAX3395E/MAX3396E operate at a guaranteed data rate of 6Mbps with push-pull drivers and 1Mbps with open-drain drivers. The MAX3394E is a dual-level translator available in 9-bump UCSPTM and 8-pin 3mm x 3mm TDFN packages. The MAX3395E is a quad-level translator available in 12bump UCSP, and 12-pin 4mm x 4mm TQFN packages. The MAX3396E is an octal-level translator available in 20bump UCSP and 20-pin 5mm x 5mm TQFN packages. The MAX3394E/MAX3395E/MAX3396E operate over the extended -40C to +85C temperature range. MAX3394E/MAX3395E/MAX3396E 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) VCC ......................................................................... -0.3V to +6V VL ............................................................................ -0.3V to +6V I/O VCC_ ...................................................... -0.3V to VCC + 0.3V I/O VL_ ........................................................... -0.3V to VL + 0.3V EN ........................................................................... -0.3V to +6V Short-Circuit Duration I/O VL_, I/O VCC_ to GND ..... Continuous Maximum Continuous Current ........................................ 50mA Continuous Power Dissipation (TA = +70C) 8-Pin TDFN (derate 18.2mW/C above +70C) ........ 1455mW 9-Bump UCSP (derate 4.7mW/C above +70C) ........ 379mW 12-Pin TQFN (derate 16.9mW/C above +70C) ........1349mW 12-Bump UCSP (derate 6.5mW/C above +70C) ..... 519mW 20-Pin TQFN (derate 20.8mW/C above +70C) ........1667mW 20-Bump UCSP (derate 10.0mW/C above +70C) .....800mW Operating Temperature Range ......................... -40C to +85C Storage Temperature Range ........................... -65C to +150C Junction Temperature .....................................................+150C Bump Temperature (soldering) ...................................... +235C Lead Temperature (soldering, 10s) ............................... +300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +1.65V to +5.5V, VL = +1.2V to VCC; CIOVL 15pF, CIOVCC 15pF; TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER POWER SUPPLY VL Supply Range VCC Supply Range Supply Current from VCC Supply Current from VL SYMBOL CONDITIONS VL VCC ICC IL I/O lines internally pulled up I/O lines internally pulled up MIN TYP MAX UNITS 1.2 VCC V 1.65 5.50 V MAX3394E 150 MAX3395E 300 MAX3396E 600 MAX3394E 30 MAX3395E 30 MAX3396E VCC Tri-State Supply Current VL Tri-State Supply Current A A 30 ICC-3 EN = GND, TA = +25C 3 6 A IL-3 EN = GND, TA = +25C 0.7 2 A 0.7 x VL V LOGIC I/O I/O VL_ Input-Voltage High Threshold VIHL I/O VL_ Input-Voltage Low Threshold VILL I/O VL_ Internal Pullup DC Resistance RL EN = VCC or VL I/O VL_ Source Current During Low-to-High Transition IIHL VL = +1.2V 15 mA I/O VL_ Sink Current During Highto-Low Transition IILL VCC = +1.65V 10 mA 2 0.3 x VL 5 V 10 _______________________________________________________________________________________ 20 k 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry (VCC = +1.65V to +5.5V, VL = +1.2V to VCC; CIOVL 15pF, CIOVCC 15pF; TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL I/O VL_ Low-to-High Transition Threshold VL-TH I/O VL_ Output-Voltage Low VOLL CONDITIONS VCC = +3.3V, VL = +1.8V MIN TYP 0.3 x VL 0.5 x VL I/O VL_ sink current = 5mA, VILC = 0V I/O VL_ Tri-State Output Leakage Current UNITS V 0.25 I/O VL_ sink current = 10mA, VILC 0.4V or 0.2 x VL EN = GND, TA = +25C MAX -1 VILC + 0.4V V +1 A 0.7 x VCC V I/O VCC_ Input-Voltage High Threshold VIHC (Note 2) I/O VCC_ Input-Voltage Low Threshold VILC (Note 2) I/O VCC_ Internal Pullup DC Resistance RCC EN = VCC or VL I/O VCC_ Source Current During Low-to-High Transition IIHCC VCC = +1.65V 15 mA I/O VCC_ Sink Current During High-to-Low Transition IILCC VCC = +1.65V 10 mA 0.5 x VCC V I/O VCC_ Low-to-High Transition Threshold VCC-TH VCC = +3.3V, VL = +1.8V 0.3 x VCC 5 0.3 x VCC V 10 I/O VCC_ sink current = 5mA, VILL = 0V I/O VCC_ Output-Voltage Low VOLC I/O VCC_ Tri-State Output Leakage Current EN Input-Voltage High Threshold VIHE EN Input-Voltage Low Threshold VILE EN Pin Input Leakage Current -1 VILL + 0.4V V +1 A 0.7 x VL V 0.3 x VL TA = +25C k 0.25 I/O VCC_ sink current = 10mA, VILL 0.4V or 0.2 x VL EN = GND, TA = +25C 20 V -1 +1 A ESD PROTECTION I/O VCC_ ESD Protection CVCC = 1F, Human Body Model 15 kV _______________________________________________________________________________________ 3 MAX3394E/MAX3395E/MAX3396E ELECTRICAL CHARACTERISTICS (continued) MAX3394E/MAX3395E/MAX3396E 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry TIMING CHARACTERISTICS (VCC = +1.65V to +5.5V, VL = +1.2V to VCC; CIOVL 15pF, CIOVCC 15pF; TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL I/O VCC_ Rise Time tRVCC I/O VCC_ Fall Time tFVCC I/O VL_ Rise Time tRVL I/O VL_ Fall Time tFVL tI/OVL-VCC Propagation Delay tI/OVCC-VL Propagation Delay After EN Channel-to-Channel Skew Maximum Data Rate tEN tSKEW CONDITIONS MIN TYP MAX Push-pull driver, Figure 1 50 Open-drain driver, internal pullup, Figure 2 500 Push-pull driver, Figure 1 50 Open-drain driver, internal pullup, Figure 2 50 Push-pull driver, Figure 3 50 Open-drain driver, internal pullup, Figure 4 500 Push-pull driver, Figure 3 50 Open-drain driver, internal pullup, Figure 4 50 Push-pull driver, Figure 1 50 Open-drain driver, internal pullup, Figure 2 600 Push-pull driver, Figure 3 50 Open-drain driver, internal pullup, Figure 4 600 Push-pull or open-drain driver, Figure 5 5 Push-pull driver 5 Open-drain driver, internal pullup 100 Push-pull driver, Figures 1, 3 6 Open-drain driver, internal pullup, Figures 2, 4 1 UNITS ns ns ns ns ns s ns Mbps Note 1: All units are 100% production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design and not production tested. Note 2: During a low-to-high transition, the threshold at which the I/O changes state is the lower of VILL and VILC since the two sides are internally connected by an internal switch while the device is in the logic-low state. 4 _______________________________________________________________________________________ 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry 1.0 0.5 1.5 6Mbps PUSH-PULL 1.0 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 VCC SUPPLY VOLTAGE (V) VL SUPPLY VOLTAGE (V) VL SUPPLY CURRENT vs. TEMPERATURE VCC SUPPLY CURRENT vs. LOAD CAPACITANCE 0.30 6Mbps PUSH-PULL 0.25 0.20 1Mbps OPEN-DRAIN 0.15 0.10 4.5 3.0 DRIVING I/O VL_ 2.5 2.0 1.5 6Mbps PUSH-PULL 1.0 -15 10 35 0.7 0.6 0.5 0.4 0.3 1Mbps OPEN-DRAIN 0.1 6Mbps PUSH-PULL 0 0 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 OPEN-DRAIN FALL TIME vs. LOAD CAPACITANCE PUSH-PULL RISE TIME vs. LOAD CAPACITANCE 100 30 20 25 RISE TIME (ns) DRIVING I/O VCC_ 150 25 FALL TIME (ns) DRIVING I/O VL_ DRIVING I/O VCC_ MAX3394E-96E toc08 30 MAX3394E-96E toc07 300 MAX3394E-96E toc03 0.8 OPEN-DRAIN RISE TIME vs. LOAD CAPACITANCE 350 85 DRIVING I/O VL_ 0.9 LOAD CAPACITANCE (pF) 400 200 60 LOAD CAPACITANCE (pF) 450 250 35 1.0 0.2 0 85 10 TEMPERATURE (C) 500 RISE TIME (ns) 60 -15 VL SUPPLY CURRENT vs. LOAD CAPACITANCE 0 -40 0.3 TEMPERATURE (C) 1Mbps OPEN-DRAIN 0 1Mbps OPEN-DRAIN 0.4 -40 0.5 0.05 0.5 5.0 MAX3394E-96E toc05 DRIVING I/O VL_ VCC SUPPLY CURRENT (mA) 0.35 0.6 0 1.5 5.5 VL SUPPLY CURRENT (mA) 2.5 MAX3394E-96E toc04 2.0 0.7 0.1 1Mbps OPEN-DRAIN 0 1.5 6Mbps PUSH-PULL 0.8 0.2 0.5 1Mbps OPEN-DRAIN 0 VL SUPPLY CURRENT (mA) 2.0 DRIVING I/O VL_ 0.9 MAX3394E-96E toc06 1.5 2.5 1.0 15 DRIVING I/O VL_ 20 15 DRIVING I/O VCC_ 10 10 MAX3394E-96E toc09 6Mbps PUSH-PULL VCC = +5.0V DRIVING I/O VL_ VCC SUPPLY CURRENT (mA) 2.0 3.0 MAX3394E-96E toc02 VL = +1.2V DRIVING I/O VL_ VL SUPPLY CURRENT (mA) MAX3394E-96E toc01 VCC SUPPLY CURRENT (mA) 3.0 2.5 VCC SUPPLY CURRENT vs. TEMPERATURE VL SUPPLY CURRENT vs. SUPPLY VOLTAGE VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE 5 5 50 DRIVING I/O VL_ 0 0 0 0 10 20 30 40 50 60 70 80 90 100 CAPACITIVE LOAD (pF) 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (pF) 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (pF) _______________________________________________________________________________________ 5 MAX3394E/MAX3395E/MAX3396E Typical Operating Characteristics (VCC = +2.5V, VL = +1.8V, CL = 15pF, TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +2.5V, VL = +1.8V, CL = 15pF, TA = +25C, unless otherwise noted.) 8 6 4 DRIVING I/O VL_ 25 tPDHL 20 15 10 2 5 0 0 10 8 6 tPDHL tPDLH 2 10 20 30 40 50 60 70 80 90 100 0 PROPAGATION DELAY vs. LOAD CAPACITANCE PROPAGATION DELAY vs. LOAD CAPACITANCE (DRIVING I/O VL_, VCC = +2.5V, VL = +1.8V, CL = 15pF, DATA RATE = 6Mbps) tPDHL 30 25 20 15 10 DRIVING I/O VCC_ PUSH-PULL SEE FIGURE 3 18 MAX3394E-96E toc15 MAX3394E-96E toc14 20 16 14 I/O VL_ 1V/div 12 10 8 tPDHL I/O VCC_ 1V/div 6 4 tPDLH 5 2 0 0 0 10 20 30 40 50 60 70 80 90 100 0 40ns/div 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) (DRIVING I/O VL_, VCC = +5.0V, VL = +3.3V, CL = 100pF, DATA RATE = 1Mbps) (DRIVING I/O VL_, VCC = +5.0V, VL = +3.3V, CL = 400pF, EXTERNAL 4.7k PULLUPS, DATA RATE = 1Mbps) MAX3394E-96E toc16 200ns/div 6 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (pF) 40 35 12 LOAD CAPACITANCE (pF) DRIVING I/O VL_ PUSH-PULL 45 14 LOAD CAPACITANCE (pF) PROPAGATION DELAY (ns) 50 16 0 0 10 20 30 40 50 60 70 80 90 100 DRIVING I/O VCC_ OPEN-DRAIN 18 4 tPDLH 0 20 MAX3394E-96E toc12 DRIVING I/O VL_ OPEN-DRAIN PROPAGATION DELAY (ns) DRIVING I/O VCC_ MAX3394E-96E toc13 FALL TIME (ns) 10 MAX3394E-96E toc11 12 30 PROPAGATIN DELAY (ns) MAX3394E-96E toc10 14 PROPAGATION DELAY vs. LOAD CAPACITANCE PROPAGATION DELAY vs. LOAD CAPACITANCE PUSH-PULL FALL TIME vs. LOAD CAPACITANCE PROPAGATION DELAY (ns) MAX3394E/MAX3395E/MAX3396E 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry MAX3394E-96E toc17 I/O VL_ 2V/div I/O VL_ 2V/div I/O VCC_ 2V/div I/O VCC_ 2V/div 200ns/div _______________________________________________________________________________________ 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry PIN MAX3394E TDFN 1 UCSP A1 MAX3395E TQFN 11 UCSP B1 MAX3396E TQFN 14 4 NAME FUNCTION VCC VCC Supply Voltage +1.65V VCC +5.5V. Bypass VCC to GND with a 0.1F ceramic capacitor and a 1F or greater ceramic capacitor as close to the device as possible. EN Enable Input. Drive EN logic high for normal operation. Drive EN logic low to force all I/O lines to a high-impedance state and disconnect internal pullup resistors. UCSP D3 2 B1 6 B3 A4 3 A2 10 C1 18 C1 I/O VCC1 4 A3 9 C2 16 D1 I/O VCC2 5 B3 5 B4 13 D4 GND 6 C3 2 A2 20 A1 I/O VL2 I/O 2 Referred to VL 7 C2 1 A1 19 B1 I/O VL1 I/O 1 Referred to VL 8 C1 12 B2 3 A3 VL -- -- 3 A3 1 B2 I/O VL3 I/O 3 Referred to VL -- -- 4 A4 2 A2 I/O VL4 I/O 4 Referred to VL -- -- 7 C4 15 D2 I/O VCC4 I/O 4 Referred to VCC -- -- 8 C3 17 C2 I/O VCC3 I/O 3 Referred to VCC -- -- -- -- 12 C3 I/O VCC5 I/O 5 Referred to VCC -- -- -- -- 11 D5 I/O VCC6 I/O 6 Referred to VCC -- -- -- -- 10 C4 I/O VCC7 I/O 7 Referred to VCC -- -- -- -- 9 C5 I/O VCC8 -- -- -- -- 5 B3 I/O VL5 I/O 5 Referred to VL -- -- -- -- 6 A5 I/O VL6 I/O 6 Referred to VL -- -- -- -- 7 B4 I/O VL7 I/O 7 Referred to VL -- -- -- -- 8 B5 I/O VL8 I/O 8 Referred to VL EP -- EP -- EP -- EP Detailed Description The MAX3394E/MAX3395E/MAX3396E bidirectional level translators provide level shifting required for data transfer in a multivoltage system. Internal slew-rate enhancement circuitry features 10mA current-sink and 15mA current-source drivers to isolate capacitive loads from lower current drivers. In open-drain systems, slewrate enhancement enables fast data rates with larger I/O 1 Referred to VCC I/O 2 Referred to VCC Ground Logic Supply Voltage +1.2V VL VCC. Bypass VL to GND with a 0.1F or greater ceramic capacitor as close to the device as possible. I/O 8 Referred to VCC Exposed Pad. Connect exposed pad to GND. pullup resistors and increased bus load capacitance. Externally applied voltages, VCC and VL, set the logichigh levels for the device. A logic-low signal on one I/O side of the device appears as a logic-low signal on the opposite I/O side and vice-versa. Each I/O line is pulled up to VCC or VL by an internal pullup resistor, allowing the devices to be driven by either push-pull or opendrain drivers. _______________________________________________________________________________________ 7 MAX3394E/MAX3395E/MAX3396E Pin Description MAX3394E/MAX3395E/MAX3396E 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry VL tRVCC VCC VL 90% VCC EN VL MAX3394E MAX3395E MAX3396E tFVCC 90% I/O VL 50% VCC 50% 50% 50% I/O VL_ I/O VCC_ I/O VCC 50 10% 10% CIOVCC tI/OVL-VCC tI/OVL-VCC Figure 1. Push-Pull Driving I/O VL_ Test Circuit and Timing VL tRVCC VCC tFVCC I/O VCC VL VL EN 90% VCC MAX3394E MAX3395E MAX3396E VGATE 50% VCC 50% 50% 50% I/O VL_ 90% I/O VCC_ 10% 10% VGATE CIOVCC tI/OVL-VCC tI/OVL-VCC Figure 2. Open-Drain Driving I/O VL_ Test Circuit and Timing The MAX3394E/MAX3395E/MAX3396E feature a tristate output mode, thermal-shutdown protection, and 15kV Human Body Model (HBM) ESD protection on the VCC side for greater protection in applications that route signals externally. The MAX3394E/MAX3395E/MAX3396E accept VCC voltages from +1.65V to +5.5V, and VL voltages from +1.2V to VCC, making them ideal for data transfer between lowvoltage ASIC/PLDs and higher voltage systems. The MAX3394E/MAX3395E/MAX3396E operate at a guaran- 8 teed data rate of 6Mbps with push-pull drivers and 1Mbps with open-drain drivers. Level Translation The MAX3394E/MAX3395E/MAX3396E utilize a transmission gate architecture to provide bidirectional level translation between I/O VL_ and I/O VCC_. The transmission gate architecture is comprised of a pass-FET, gate-control logic, and slew-rate enhancement circuitry. When both I/O VL _ and I/O VCC_ are logic high, the gate-control logic disables the pass-FET, providing _______________________________________________________________________________________ 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry VL EN I/O VCC VCC MAX3394E MAX3395E MAX3396E VL tFVL tRVL VCC MAX3394E/MAX3395E/MAX3396E VL VCC 90% 50% 90% 50% 50% 50% I/O VCC_ I/O VL_ 50 10% 10% I/O VL CIOVL tI/OVCC-VL tI/OVCC-VL Figure 3. Push-Pull Driving I/O VCC_ Test Circuit and Timing VL tRVL VCC VL VL EN tFVL VCC MAX3394E MAX3395E MAX3396E I/O VL 50% VCC 90% 90% 50% 50% I/O VL_ I/O VCC_ CIOVL 50% 10% VGATE tI/OVCC-VL 10% tI/OVCC-VL Figure 4. Open-Drain Driving I/O VCC_ Test Circuit and Timing capacitive isolation between I/O lines. When one or both I/O lines are at a logic-low level, the gate-control logic turns the pass-FET on. When the pass-FET is active, I/O VL _ and I/O VCC_ are connected, allowing the logic-low signal to be expressed simultaneously on both I/O lines. The MAX3394E/MAX3395E/MAX3396E have internal 10k (typ) pullup resistors from I/O VL_ and I/O VCC_ to the respective supply voltages, allowing operation with open-drain drivers. Internal slew-rate enhancement circuitry accelerates logic-state transitions, maintaining a fast data rate with a higher bus load capacitance. Additionally, the 10mA current sink drivers permit the use of smaller external pullup resistors. Internal Slew-Rate Enhancement Internal slew-rate enhancement circuitry accelerates logic-state changes by turning on MOSFETs MP1 and MP2 during low-to-high logic transitions, and MOSFETs MN3 and MN4 during high-to-low logic transitions (see the Functional Diagram). During logic-state changes, speed-up MOSFETS are triggered by I/O line voltage thresholds. MOSFETS MN3 and MN4 sink 10mA during high-to-low logic transitions. MP1 and MP2 source 15mA during low-to-high logic transitions. Slew-rate enhancement allows a fast data rate despite large capacitive bus loads, and permits larger external pullup resistors. _______________________________________________________________________________________ 9 MAX3394E/MAX3395E/MAX3396E 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry VL VCC VL VCC VCC VL VCC EN EN VL VL MAX3394E MAX3395E MAX3396E VCC RLOAD RLOAD I/O VL_ I/O VCC_ I/O VL_ VL CIOVCC MAX3394E MAX3395E MAX3396E VCC I/O VCC_ CIOVL 50 50 tEN V I/O VCC_ EN 0.5V TIME V tEN EN I/O VL_ 0.2V (VL < 2V) 0.5V (VL 2V) TIME Figure 5. Enable Test Circuit and Timing Power-Supply Sequencing The MAX3394E/MAX3395E/MAX3396E require two supply voltages. For proper operation, ensure that +1.65V VCC +5.5V, and +1.2V VL VCC. There are no restrictions on power-supply sequencing. During power-up or power-down, the MAX3394E/MAX3395E/MAX3396E can withstand either the VL or the VCC supply floating while the other supply is applied. The device will not latch up in this state. 10 Tri-State Output Mode Connect EN to VL or VCC for normal operation. Drive EN low to force the MAX3394E/MAX3395E/MAX3396E to a tri-state output mode. In tri-state output mode, all I/O lines are driven to a high-impedance state, and the pass-FET is disabled to prevent current flow between I/O lines. Tri-state output mode disables the internal pullup resistors on I/O VL_ and I/O VCC_, and reduces supply current to 3A typ (VCC) and 0.7A typ (VL). ______________________________________________________________________________________ 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 100pF RD 1500 IP 100% 90% DISCHARGE RESISTANCE STORAGE CAPACITOR Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) AMPERES DEVICEUNDERTEST 36.8% 10% 0 0 tRL TIME tDL CURRENT WAVEFORM Figure 6a. Human Body ESD Test Model Figure 6b. HBM Discharge Current Waveform The high-impedance state of the I/O lines during tristate output mode facilitates use in multidrop networks. In tri-state output mode, do not exceed (VL + 0.3V) on I/O VL_ or (VCC + 0.3V) on I/O VCC_. To ensure full 15kV ESD protection, bypass VCC to ground with a 0.1F ceramic capacitor and an additional 1F ceramic capacitor as close to the device as possible. Thermal-Shutdown Protection ESD performance depends on a variety of conditions. Contact Maxim for a reliability report documenting test setup, methodology, and results. The MAX3394E/MAX3395E/MAX3396E are protected from thermal damage resulting from short-circuit faults. In the event of a short-circuit fault, when the junction temperature (TJ) reaches +125C, a thermal sensor forces the device into the tri-state output mode. When TJ drops below +115C, normal operation resumes. 15kV ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against ESD encountered during handling and assembly. The I/O VCC_ lines are further protected by advanced ESD structures to guard these pins from damage caused by ESD of up to 15kV. Protection structures prevent damage caused by ESD events in normal operation, tri-state output mode, and when the device is unpowered. After arresting an ESD event, MAX3394E/MAX3395E/MAX3396E continue to function without latching up, whereas competing devices can enter a latched-up state and must be power cycled to restore functionality. Several ESD testing standards exist for gauging the robustness of ESD structures. The ESD protection of the MAX3394E/MAX3395E/MAX3396E is characterized for the human body model (HBM). Figure 6a shows the model used to simulate an ESD event resulting from contact with the human body. The model consists of a 100pF storage capacitor that is charged to a high voltage then discharged through a 1.5k resistor. Figure 6b shows the current waveform when the storage capacitor is discharged into a low impedance. ESD Test Conditions Applications Information Power-Supply Decoupling Bypass V L and V CC to ground with 0.1F ceramic capacitors. To ensure full 15kV ESD protection, bypass VCC to ground with an additional 1F or greater ceramic capacitor. Place all capacitors as close to the device as possible. Open-Drain Mode vs. Push-Pull Mode The MAX3394E/MAX3395E/MAX3396E are compatible with push-pull (active) and open-drain drivers. For pushpull operation, maximum data rate is guaranteed to 6Mbps. For open-drain applications, the MAX3394E/ MAX3395E/MAX3396E include internal pullup resistors and slew-rate enhancement circuitry, providing a maximum data rate of 1Mbps. External pullup resistors can be added to increase data rate when the bus is loaded by high capacitance. (See the Use of External Pullup Resistors section.) Serial-Interface Level Translation The MAX3395E provides level translation on four I/O lines, making it an ideal device for multivoltage I2C, MICROWIRE, and SPI serial interfaces. Use of External Pullup Resistors The MAX3394E/MAX3395E/MAX3396E include internal 10k pullup resistors. During a low-to-high logic transition, the internal pullup resistors charge the bus capac- ______________________________________________________________________________________ 11 MAX3394E/MAX3395E/MAX3396E RC 1M 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry MAX3394E/MAX3395E/MAX3396E Functional Diagram VCC VL VL MP1 VCC MP2 GATE CONTROL I/O VL_ I/O VCC_ N-CHANNEL PASS-FET SLEW-RATE ENHANCEMENT MN3 MN4 Typical Operating Circuit +1.8V +3.3V 0.1F +1.8V SYSTEM CONTROLLER EN CLK DATA GND VL 1F +3.3V SYSTEM MAX3394E EN I/O VL1 I/O VL2 I/O VCC1 CLK I/O VCC2 DATA GND itance with a characteristic RC charging waveform. When the low-to-high transition threshold (VCC-TH or VLTH) is reached, the rise time accelerators switch on, sourcing 15mA to fully charge the bus capacitance. External pullup resistors reduce the time needed to reach the low-to-high transition threshold, thereby increasing the data rate. In the logic-low state however, external pullup resistors increase the DC current through the internal pass-FET, increasing the output voltage of the device. Smart-Card Interface The MAX3395E provides level translation for Class A, B, and C smart cards. When supply voltage VCC is interrupted due to the disconnection of a smart card, the device does not latch up. Normal operation resumes 12 0.1F VCC GND upon restoration of the V CC supply voltage. The MAX3395E provides bidirectional level translation on four I/O lines, making it well suited for buffering and translating 4-wire serial interfaces. UCSP Applications Information For the latest application details on UCSP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profiles, as well as the latest information on reliability testing results, go to Maxim's web site at www.maximic.com/ucsp to find the Application Note 1891: Wafer-Level Packaging (WLP) and Its Applications. ______________________________________________________________________________________ 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry TOP VIEW (BUMPS ON BOTTOM) 1 2 3 VCC I/O VCC1 I/O VCC2 A B MAX3394E EN GND C VL I/O VL1 I/O VL2 I/O VCC3 I/O VCC4 TOP VIEW (LEADS ON BOTTOM) I/O VCC2 UCSP 9 8 7 TOP VIEW (BUMPS ON BOTTOM) 1 2 3 4 MAX3395E A I/O VCC1 10 VCC 11 VL 12 *EP MAX3395E 6 EN 5 GND 4 I/O VL4 I/O VL1 I/O VL2 I/O VL3 I/O VL4 VCC VL EN GND I/O VCC1 I/O VCC2 I/O VCC3 I/O VCC4 B 1 2 3 I/O VL1 I/O VL2 I/O VL3 + C TQFN UCSP VCC GND I/O VCC5 I/O VCC6 TOP VIEW (LEADS ON BOTTOM) I/O VCC4 *CONNECT EXPOSED PAD TO GROUND 15 14 13 12 11 TOP VIEW (BUMPS ON BOTTOM) 1 2 3 4 5 MAX3396E 10 I/O VCC7 9 I/O VCC8 8 I/O VL8 I/O VL1 19 7 I/O VL7 I/O VL2 20 6 I/O VL6 I/O VCC2 16 *EP I/O VCC3 17 I/O VCC1 18 MAX3396E A I/O VL2 I/O VL4 VL EN I/O VL6 I/O VL1 I/O VL3 I/O VL5 I/O VL7 I/O VL8 I/O VCC1 I/O VCC3 I/O VCC5 I/O VCC7 I/O VCC8 I/O VCC2 I/O VCC4 VCC GND I/O VCC6 B + C TQFN *CONNECT EXPOSED PAD TO GROUND 5 I/O VL5 4 EN 3 VL 2 I/O VL4 I/O VL3 1 D UCSP ______________________________________________________________________________________ 13 MAX3394E/MAX3395E/MAX3396E Pin Configurations (continued) MAX3394E/MAX3395E/MAX3396E 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry Selector Guide NUMBER OF TRANSLATORS TOP MARK MAX3394EETA+T 2 APE MAX3394EEBL+T 2 AEZ MAX3395EETC+ 4 AAFZ MAX3395EEBC+T 4 ACO MAX3396EEBP+T 8 -- MAX3396EETP+ 8 -- PART Chip Information PROCESS: BiCMOS CONNECT EXPOSED PAD TO GND. Note: All devices specified over the -40C to +85C operating range. +Denotes lead(Pb)-free/RoHS-compliant package. 14 ______________________________________________________________________________________ 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry COMMON DIMENSIONS PACKAGE VARIATIONS MIN. MAX. PKG. CODE N D2 E2 e JEDEC SPEC b A 0.70 0.80 T633-2 6 1.500.10 2.300.10 0.95 BSC MO229 / WEEA 0.400.05 1.90 REF D 2.90 3.10 T833-2 8 1.500.10 2.300.10 0.65 BSC MO229 / WEEC 0.300.05 1.95 REF E 2.90 3.10 T833-3 8 1.500.10 2.300.10 0.65 BSC MO229 / WEEC 0.300.05 1.95 REF A1 0.00 0.05 T1033-1 10 1.500.10 2.300.10 0.50 BSC MO229 / WEED-3 0.250.05 2.00 REF L 0.20 0.40 T1033MK-1 10 1.500.10 2.300.10 0.50 BSC MO229 / WEED-3 0.250.05 2.00 REF SYMBOL [(N/2)-1] x e k 0.25 MIN. T1033-2 10 1.500.10 2.300.10 0.50 BSC MO229 / WEED-3 0.250.05 2.00 REF A2 0.20 REF. T1433-1 14 1.700.10 2.300.10 0.40 BSC ---- 0.200.05 2.40 REF T1433-2 14 1.700.10 2.300.10 0.40 BSC ---- 0.200.05 2.40 REF T1433-3F 14 1.700.10 2.300.10 0.40 BSC ---- 0.200.05 2.40 REF ______________________________________________________________________________________ 15 MAX3394E/MAX3395E/MAX3396E Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 9LUCSP, 3x3.EPS MAX3394E/MAX3395E/MAX3396E 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry PACKAGE OUTLINE, 3x3 UCSP 21-0093 16 ______________________________________________________________________________________ L 1 1 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry 12L, UCSP 4x3.EPS PACKAGE OUTLINE, 4x3 UCSP 21-0104 F 1 1 ______________________________________________________________________________________ 17 MAX3394E/MAX3395E/MAX3396E Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX3394E/MAX3395E/MAX3396E 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry 18 ______________________________________________________________________________________ 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry QFN THIN.EPS ______________________________________________________________________________________ 19 MAX3394E/MAX3395E/MAX3396E Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 5x4 UCSP.EPS MAX3394E/MAX3395E/MAX3396E 15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry Revision History Pages changed at Rev 2: 1-4, 9, 11, 12, 14, 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products Boblet is a registered trademark of Maxim Integrated Products, Inc.