P/N: TS32M7MAR00IS1 TS64M7MAR00IS1 SATA III 6Gb/s mSATA SSD Features RoHS compliant Advanced Global Wear-Leveling and Block management for reliability Built-in ECC (Error Correction Code) functionality Transcend mSATA Solid State Drives (SSDs) with high Features a DDR3 DRAM Cache performance and quality Flash Memory assembled Supports Advanced Garbage Collection on a printed circuit board. These devices feature Supports Enhanced S.M.A.R.T. function cutting-edge technology to enhance product life and Power Shield to prevent data loss in the event of a sudden power outage applications, such as Ultrabooks, industrial PCs, Supports partial and slumber mode vehicle PCs and road surveillance recording. Supports Security Command Supports DevSleep mode - Power Supply: 3.3V5% - Fully compatible with devices and OS that support the SATA III 6.0Gb/s standard Supports Hardware Purge and Hardware Write Protect (Optional) Supports Transcend SSD Scope Pro (Optional) Real time full drive encryption with Advanced Encryption Standard (AES) (Optional) data retention. It is designed specifically for various - Non-volatile Flash Memory for outstanding data retention - Supports Trim and NCQ command - Compliant with JEDEC MO-300 Specifications Physical Specification Form Factor MO-300 Storage Capacities 16GB to 1TB Dimensions Length 50.8 0.15 mm 1.175 0.006 inch Width 29.85 0.15 mm 2.000 0.006 inch Height Max 4.85 mm Max 0.111 inch Input Voltage 3.3V 5% Weight 8g Connector PCI Express Mini Card Connector Environmental Specifications Operating Temperature 0 to 70 Storage Temperature -40 to 85 Humidity Operating 0% to 95% (Non-condensing) Non-Operating 0% to 95% (Non-condensing) Performance ATTO CrystalDiskMark IOMeter CAPACITY Max Read * Max Write * 32GB 280 50 280 50 110 64GB 560 100 520 100 200 IOPS Random Read (4KB QD32) *** IOPS Random Write (4KB QD32) *** 55 26K 13K 100 50K 25K Sequential Sequential Random Read Random Write Read Write (4KB QD32) (4KB QD32) ** ** ** ** Note: Maximum transfer speed recorded *25 C, test on ASUS P8Z68-M PRO, 4GB, Windows(R) 7 Professional with AHCI mode, benchmark utility ATTO (version 2.41), unit MB/s **25 C, test on ASUS P8Z68-M PRO, 4GB, Windows(R) 7 Professional with AHCI mode, benchmark utility CrystalDiskMark (version 3.0.1), copied file 1000MB, unit MB/s ***25 C, test on ASUS P8Z68-M PRO, 4GB, Windows(R) 7 Professional with AHCI mode, benchmark utility IOmeter2006 with 4K file size and queue depth of 32, unit IOPs ****The recorded performance is obtained while the SSD is not operating as an OS disk Actual Capacity CAPACITY User Max. LBA Cylinder Head Sector 32GB 62,533,296 16,383 16 63 64GB 125,045,424 16,383 16 63 Power Consumption 3.3V 5% Input Voltage CAPACITY / Power Consumption 32GB 64GB Average (mA) Max Read 190 Max Write 200 Idle 85 Max Read 225 Max Write 245 Idle 85 *Tested with IOmeter running sequential reads/writes and idle mode Reliability Data Reliability Supports BCH ECC 42 bit per 1024 byte MTBF 1,500,000 hours Capacity * TBW ** TBW (Base on JEDEC Standard) 32GB 90TB 45TB 64GB 180TB 90TB 2.2 DWPD Endurance (TeraBytes Written)* *Tested under burn-in tool, TBW value may vary due to host environment. DWPD (Drive Writes Per Day for 3years) **Tested under JESD218A endurance test method and JESD219A endurance workloads specification. Vibration Operating 3.0G, 5 - 800Hz Non-Operating 5.0G, 5 - 800Hz Reference to IEC 60068-2-6 Testing procedures; Operating-Sine wave, 5-800Hz/1 oct., 1.5mm, 3g, 0.5 hr./axis, total 1.5 hrs. Shock Operating 1500G, 0.5ms Non-Operating 1500G, 0.5ms Reference to IEC 60068-2-27 Testing procedures; Operating-Half-sine wave, 1500G, 0.5ms, 3 times/dir., total 18 times. Regulations Compliance CE, FCC and BSMI Package Dimensions The figure below illustrates the Transcend mSATA Solid State Disk product. All dimensions are in mm. Pin Assignments Pin No. Pin Name Pin No. Pin Name 01 NC 02 3.3V 03 NC 04 GND 05 NC 06 NC 07 NC 08 NC 09 GND 10 NC 11 NC 12 NC 13 NC 14 NC 15 GND 16 NC 17 19 NC NC 18 20 GND NC 21 GND 22 NC 23 TX+ 24 3.3V 25 TX- 26 GND 27 GND 28 NC 29 GND 30 NC 31 RX- 32 NC 33 RX+ 34 GND 35 GND 36 NC 37 GND 38 NC 39 3.3V 40 GND 41 3.3V 42 NC 43 NC 44 DEVSLP 45 NC 46 NC 47 NC 48 NC 49 DAS/DSS* 50 GND 51 Presence Detection** 52 3.3V * Device Activity Signal / Disable Staggered Spin-up ** Connect to GND internally Pin Layout Block Diagram Features Global Wear Leveling - Advanced algorithms to enhance wear-leveling efficiency Gloal ear leelig esures eer lok has a ee erase out. B esurig all spare loks i the SSD's flash hips are managed in a single pool, each block can then have an even erase count. This helps to extend the lifespan of a SSD and to provide the best possible endurance. There are three main processes in global wear -leveling: (1) Record the block erase count and save this in the wear-leveling table. (2) Finds the static-block and saves this in the wear-leveling pointer. (3) Checks the erase count when a block is pulled from the pool of spare blocks. If the erased block count is larger than the Wear Count (WEARCNT), then the static blocks are leveraged against the over-countblocks. ECC Algorithm The controller uses a BCH 42 Bit ECC algorithm per 1024 bytes depending on the structure of the flash. BCH42 may correct up to 42 random bit errors within 1024 data bytes. With the help of BCH42 ECC, the endurance of the Transcend SSD is greatly improved. Bad Block Management When the flash encounters an ECC, program or erase failure, the controller will mark the block as a bad block to prevent use of this block and cause data loss in the future. Advanced Garbage Collection Trased's Garage Colletio ehais iproes SSD performance. Advanced Garbage Collection can efficiently iproe eor aageet to esure stale SSD perforae. Trased's adaed flash aageet a aitai the drie's high perforae ee after a eteded operatig tie. Enhanced S.M.A.R.T. function Trased's SSDs support the ioatie S.M.A.R.T. oad (Self-Monitoring, Analysis, and Reporting Technology) which allows users to evaluate the health status of their SSD efficiently. Hardware Purge and Hardware Write Protect (Optional) The SSDs have optional features such as hardware trigger for quick data erase and write protection. These features may be enabled by simply connecting a switch to the designated pins. StaticDataRefresh Technology Normally, the ECC engine corrections take place without affecting normal host operations. Over time, the number of bit errors accumulated in the read transaction exceeds the correcting capacity of the ECC engine, which results in corrupted data being sent to the host. To prevent this, the controller monitors the bit error levels during each read operation; when the number of bit errors reaches the preset threshold value, the controller automatically performs a data refresh to restore the orret harge leels i the ell. Ipleetatio of StatiDataRefresh Technology reinstates the data to its original, error-free state, ad hee, legths the data's lifespa. ATA Command Register This table and the following paragraphs summarize the ATA command set. Command Table Support ATA/ATAPI Command General Feature Set EXECUTE DIAGNOSTICS FLUSH CACHE IDENTIFY DEVICE Initialize Drive Parameters READ DMA READ LOG Ext READ MULTIPLE READ SECTOR(S) READ VERIFY SECTOR(S) SET FEATURES SET MULTIPLE MODE WRITE DMA WRITE MULTIPLE WRITE SECTOR(S) NOP READ BUFFER WRITE BUFFER Power Management Feature Set CHECK POWER MODE IDLE IDLE IMMEDIATE SLEEP STANDBY STANDBY IMMEDIATE Security Mode Feature Set SECURITY SET PASSWORD SECURITY UNLOCK SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY DISABLE PASSWORD SMART Feature Set SMART Disable Operations SMART Enable/Disable Autosave SMART Enable Operations SMART Execute Off-Line Immediate SMART Read LOG SMART Read Data SMART Read THRESHOLD SMART Return Status SMART SAVE ATTRIBUTE VALUES SMART WRITE LOG Host Protected Area Feature Set Code Protocol 90h E7h ECh 91h C8h 2Fh C4h 20h 40h or 41h EFh C6h Cah C5h 30h 00h E4h E8h Device diagnostic Non-data PIO data-In Non-data DMA PIO data-In PIO data-In PIO data-In Non-data Non-data Non-data DMA PIO data-out PIO data-out Non-data PIO data-In PIO data-out E5h or 98h E3h or 97h E1h or 95h E6h or 99h E2h or 96h E0h or 94h Non-data Non-data Non-data Non-data Non-data Non-data F1h F2h F3h F4h F5h F6h PIO data-out PIO data-out Non-data PIO data-out Non-data PIO data-out B0h B0h B0h B0h B0h B0h B0h B0h B0h B0h Non-data Non-data Non-data Non-data PIO data-In PIO data-In PIO data-In Non-data Non-data PIO data-out Read Native Max Address Set Max Address Set Max Set Password Set Max Lock Set Max Freeze Lock Set Max Unlock 48-bit Address Feature Set Flush Cache Ext Read Sector(s) Ext Read DMA Ext Read Multiple Ext Read Native Max Address Ext Read Verify Sector(s) Ext Set Max Address Ext Write DMA Ext Write Multiple Ext Write Sector(s) Ext NCQ Feature Set Read FPDMA Queued Write FPDMA Queued Other Data Set Management SEEK F8h F9h F9h F9h F9h F9h Non-data Non-data PIO data-out Non-data Non-data PIO data-out Eah 24h 25h 29h 27h 42h 37h 35h 39h 34h Non-data PIO data-in DMA PIO data-in Non-data Non-data Non-data DMA PIO data-out PIO data-out 60h 61h DMA Queued DMA Queued 06h 70h DMA Non-data SMART Data Structure BYTE F/V Description 0-1 X Revision code 2-361 X Vendor specific 362 V Off-line data collection status 363 X Self-test execution status byte 364-365 V Total time in seconds to complete off-line data collection activity 366 X Vendor specific 367 F Off-line data collection capability 368-369 F 370 F SMART capability Error logging capability 7-1 Reserved 0 1=Device error logging supported 371 X Vendor specific 372 F Short self-test routine recommended polling time (in minutes) 373 F Extended self-test routine recommended polling time (in minutes) 374 F Conveyance self-test routine recommended polling time (in minutes) 375-385 R Reserved 386-395 F Firmware Version/Date Code 396-397 F Reserved 398-399 V Reserved 400-406 V TS6500 407-415 X Vendor specific 416 F Reserved 417 F Program/write the strong page only 418-419 V Number of spare block 420-423 V Average Erase Count 424-510 X Vendor specific 511 V Data structure checksum F = content (byte) is fixed and does not change. V= content (byte) is variable and may change depending on the state of the device or the commands executed by the device. X= content (byte) is vendor specific and may be fixed or variable. R= content (byte) is reserved and shall be zero. SMART Attributes The following table shows the vendor specific data in byte 2 to 361 of the 512-byte SMART data Attribute Raw Attribute Value Attribute Name ID (hex) 01 05 MSB LSB 00 MSB 00 00 00 00 00 00 00 00 00 00 Read Error Rate Reallocated sectors count 09 LSB - - MSB 00 00 00 Power-on hours 0C LSB - - MSB 00 00 00 Power Cycle Count A0 LSB - - MSB 00 00 00 Uncorrectable sectors count when read/write A1 LSB MSB 00 00 00 00 00 Number of valid spare blocks A3 LSB MSB 00 00 00 00 00 Number of initial invalid blocks A4 LSB - - MSB 00 00 00 Total erase count A5 LSB - - MSB 00 00 00 Maximum erase count A6 LSB - - MSB 00 00 00 Minimum erase count A7 LSB - - MSB 00 00 00 Average erase count A8 LSB - - MSB 00 00 00 Max erase count of spec A9 LSB - - MSB 00 00 00 Remain Life (percentage) AF LSB - - MSB 00 00 00 Program fail count in worst die B0 LSB MSB 00 00 00 00 00 Erase fail count in worst die B1 LSB - - MSB 00 00 00 Total wear level count B2 LSB MSB 00 00 00 00 00 Runtime invalid block count B5 LSB - - MSB 00 00 00 Total program fail count B6 LSB MSB 00 00 00 00 00 Total erase fail count C0 LSB MSB 00 00 00 00 00 Power-off retract Count C2 MSB 00 00 00 00 00 00 Controlled temperature C3 LSB - - MSB 00 00 00 Hardware ECC recovered C4 LSB - - MSB 00 00 00 Reallocation event count C5 LSB MSB 00 00 00 00 00 Current Pending Sector Count C6 LSB - - MSB 00 00 00 Uncorrectable error count off-line C7 LSB MSB 00 00 00 00 00 Ultra DMA CRC Error Count E8 LSB MSB 00 00 00 00 00 Available reserved space F1 LSB - - - - - MSB Total LBA written (each write unit = 32MB) F2 LSB - - - - - MSB Total LBA read (each read unit = 32MB) F5 LSB - - - - - MSB Flash write sector count Version V1.0 Date 2017/03/03 Initial Release Revision History(D) Modification Content