Section 1
CDUSCC User’s Guide
Philips Semiconductors
ICs for Data Communications
Table of Contents 572. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS
1994 Mar 21 2
Table of Contents
Forward 577. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description 578. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configurations — SC26C562 578. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configurations — SC68C562 579. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings 579. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features 580. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description 581. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 1 584. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NDUSCC and CDUSCC Compatibility 585. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Compatibility 585. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Compatibility 585. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
New Capabilities 585. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers 585. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description 586. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description 586. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host Interface 586. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 2 592. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status 593. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Registers 593. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Status Register (GSR) 595. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver and Transmitter Status Registers (RSR, TRSR) 595. . . . . . . . . . . . . . . . . . . . . . . .
Input and Counter/Timer Status Register (ICTSRA, ICTSRB) 596. . . . . . . . . . . . . . . . . . . . .
Transmitter/Receiver Miscellaneous Status Register (TRMSR) 596. . . . . . . . . . . . . . . . . . .
Use of the Status Registers 596. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts 597. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Driven Systems 597. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control 597. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDUSCC Interrupt Modes 599. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Interrupt Mode 599. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Interrupt Mode 599. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vectored Mode (68C562) 602. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Enable Register (IERA, IERB) 602. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Register (IVR) and Modified Vector Register (IVRM) 604. . . . . . . . . . . . . .
DMA Control 605. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Interface 605. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA (DONEN) EOPN Operation 606. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Frame Status Byte (DFSB) 606. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFOs 611. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxFIFO 611. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxFIFO Threshold Criteria 611. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RxFIFO 612. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The FIFO Level Registers 613. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers and Timing Registers 615. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer 615. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1994 Mar 21 3
Timing Circuits 616. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillator 616. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using An External Clock Source 616. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Rate Generator 616. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Selection Circuits 617. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T ransmitter 617. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver 617. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPLL (Digital Phase-Locked Loop) Operation 617. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Phase-Locked Loop 617. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPLL NRZI Mode Operation 617. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPLL FM Mode Operation 620. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/T imers 621. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer Clock Selection 621. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer Control and Value Registers 621. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer Operation 621. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer Example 621. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O and Clock Pin Configuration 625. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration Register (PCRA, PCRB) 625. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose I/O 625. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output and Miscellaneous Register (OMRA, OMRB) 626. . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxRDY Activate Mode 626. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RxRDY Activate Mode 626. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Registers 627. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tx/Rx Command Register (TRCRA/B) 627. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Command Register (CCRA/B) 627. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter CCR Commands 627. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Commands 629. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer Commands 630. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Phase-Locked Loop Commands 630. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Modes 630. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BRGTST – BRG Test (C5h): 630. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TTEST – TxPLA Test Mode (C6h): 631. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTEST – RxPLA Test Mode (C7h): 631. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Commands 631. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter 631. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview 631. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter States 631. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Sections 632. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Control 632. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling the Transmitter 633. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxRDY 633. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxRTS Control 633. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxCTS Operation 633. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver 634. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver RxFIFO, RxRDY 634. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver DCD Control 635. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver RTS Control 635. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 3 637. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASYNC Operational Mode 638. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tx ASYNC Mode 638. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Mode Register 2 (CMR2A, CMR2B) Channel Connection 639. . . . . . . . . . . . . . . .
1994 Mar 21 4
Rx ASYNC Mode 641. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Operation Overview 644. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Oriented Protocol 644. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOP Operational Mode 644. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxBOP Modes 644. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Starting Transmission 645. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address and Control Field Transmission 645. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information Field Transmission and Underrun 647. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ending Transmission 647. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tx Residual Character Length 647. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Caution 647. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control of Number of FLAGs Between Frame 647. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Zero Insertion 647. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abort Transmission 647. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxCRC Accumulation 647. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Status Register (RSRA, RSRB) 649. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxBOP Loop Mode 651. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RxBOP MODE 651. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOP Loop Mode 652. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Character Oriented Protocol 652. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Operational Mode 652. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxCOP Modes 652. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Starting Transmission 652. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transmission and Underrun 655. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ending Transmission 656. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BISYNC 656. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Check Sequence 656. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RxCOP Modes 656. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYN Pattern Stripping 660. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BISYNC FEATURES 660. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 1 663. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fundamental CDUSCC Functions 664. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous vs Synchronous Transmission 664. . . . . . . . . . . . . . . . . . . . . . . . . . .
Characteristics of Data Link Controls 664. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Request for Repeat (ARQ) 665. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Messages 665. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOP Messages 665. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 2 668. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Modes 669. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BRG Test 669. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tx PLA Test 669. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rx PLA Test 669. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing 669. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CROSS-REFERENCE 670. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIGURES
Block Diagram — SC26C562 590. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram — SC68C562 591. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1. Status Register Organization: Default Mode 593. . . . . . . . . . . . . . . . . . . . . . . . . .
1994 Mar 21 5
Figure 2. Status Register Organization: Extended Mode 594. . . . . . . . . . . . . . . . . . . . . . . .
Figure 3. GSR General Status Register [All Protocol Modes] 594. . . . . . . . . . . . . . . . . . . .
Figure 4. ICTSRA (B) Input and Counter/Timer Status Register [All Protocol Modes] 595
Figure 5. TRMSRA (B) Transmitter/Receiver Miscellaneous Status Register
[All Protocol Modes] 596. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6. SC26C562 Interrupt Acknowledge Sequence (Intel family) 598. . . . . . . . . . . . . .
Figure 7. SC68C562 Interrupt Acknowledge Sequence (Motorola family) 599. . . . . . . . . .
Figure 8. Interrupt Control Relationships, Default Mode (TRCR[2] = 0) 600. . . . . . . . . . . .
Figure 9. ICR Interrupt Control Register [All Protocol Modes] 601. . . . . . . . . . . . . . . . . . . .
Figure 10. IERA (B) Interrupt Enable Register [All Protocol Modes] 602. . . . . . . . . . . . . .
Figure 11. IER1,2,3A (B) Interrupt Enable Register 1,2,3 [All Protocol Modes] 603. . . . .
IER2A (B) Interrupt Enable Register 2 603. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IER1A (B) Interrupt Enable Register 1 603. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IER3A (B) Interrupt Enable Register 3 603. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12. IVR Interrupt Vector Register [All Protocol Modes] 604. . . . . . . . . . . . . . . . . . .
Figure 13. IVRM Interrupt Vector Modified Register [All Protocol Modes] 604. . . . . . . . . .
Figure 14. Interrupt Control Relationships, Extended Mode (TRCR[2] = 1) 605. . . . . . . . .
Figure 15. Transmitter DMA Request Operation — SC26C562 Single Address Mode 607
Figure 16. Receiver DMA Request Operation — SC26C562 Single Address Mode 607.
Figure 17. Transmitter DMA Request Operation — SC26C562 Dual Address Mode 608.
Figure 18. Receiver DMA Request Operation — SC26C562 Dual Address Mode 608. . .
Figure 19. Transmitter DMA Request Operation — SC68C562 Dual Address Mode 609.
Figure 20. Receiver DMA Request Operation — SC68C562 Dual Address Mode 609. . .
Figure 21. Transmitter DMA Request Operation — SC68C562 Single Address Mode 610
Figure 22. Receiver DMA Request Operation — SC68C562 Single Address Mode 610.
Figure 23. Transmit FIFO Block Diagram 611. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 24. Receive FIFO Block Diagram 612. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 25. TELRA (B) TxFIFO Empty Level Register [All Protocol Modes] 614. . . . . . . .
Figure 26. RFLRA (B) RxFIFO Filled Level Register [All Protocol Modes] 614. . . . . . . . .
Figure 27. FTLRA (B) FIFO Threshold Level Register [All Protocol Modes] 615. . . . . . . .
Figure 28. Providing an X1/CLK Source 616. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 29. Transmitter Clock Sources 616. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 30. Receiver Clock Sources 617. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 31. TTRA (B) Transmitter Timing Register [All Protocol Modes] 618. . . . . . . . . . .
Figure 32. RTRA (B) Receiver Timing Register [All Protocol Modes] 619. . . . . . . . . . . . .
Figure 33. Counter/Timer Clock Sources 620. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 34. DPLL Waveforms 620. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 35. Counter/Timer Control and Value Registers 621. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 36. CTCRA (B) Counter/Timer Control Register [All Protocol Modes] 622. . . . . . .
Figure 37. CTPRHA (B) Counter/Timer Preset Register High [All Protocol Modes] 623.
Figure 38. CTPRLA (B) Counter/Timer Preset Register Low [All Protocol Modes] 623. .
Figure 39. CTHA (B) Counter/Timer Register High [All Protocol Modes] 623. . . . . . . . . .
Figure 40. CTLA (B) Counter/Timer Register Low [All Protocol Modes] 624. . . . . . . . . . .
Figure 41. TRxC and RTxC Function Select 624. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 42. PCRA (B) Pin Configuration Register [All Protocol Modes] 625. . . . . . . . . . . .
Figure 43. OMRA (B) Output and Miscellaneous Register [All Protocol Modes] 626. . . .
Figure 44. TRCRA (B) Tx/Rx Command Register [All Protocol Modes] 627. . . . . . . . . . .
Figure 45. Transmitter Data Path 631. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 46. Transmitter Status 632. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 47. Receiver Data Path 636. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 48. CMR1A (B) Channel Mode Register 1 [ASYNC Mode] 638. . . . . . . . . . . . . . . .
Figure 49. CMR2A (B) Channel Mode Register 2 [ASYNC Mode] 639. . . . . . . . . . . . . . . .
Figure 50. S1RA (B) SYN1/Secondary Address Register 1 [ASYNC Mode] 640. . . . . . . .
Figure 51. TPRA (B) Transmitter Parameter Register [ASYNC Mode] 640. . . . . . . . . . . . .
Figure 52. RPRA (B) Receiver Parameter Register [ASYNC Mode] 641. . . . . . . . . . . . . . .
1994 Mar 21 6
Figure 53. RSRA (B) Receiver Status Register [ASYNC Mode] 642. . . . . . . . . . . . . . . . . .
Figure 54. TRSRA (B) Transmitter and Receiver Status Register [ASYNC Mode] 643. . .
Figure 55. IER1A (B) Interrupt Enable Register 1 [ASYNC Mode] 643. . . . . . . . . . . . . . . .
Figure 56. IER2A (B) Interrupt Enable Register 2 [ASYNC Mode] 643. . . . . . . . . . . . . . . .
Figure 57. CMR1A (B) Channel Mode Register 1 [BOP Mode] 644. . . . . . . . . . . . . . . . . . .
Figure 58. CMR2A (B) Channel Mode Register 2 [BOP Mode] 645. . . . . . . . . . . . . . . . . . .
Figure 59. S1RA (B) SYN1/Secondary Address Register 1 [BOP] 646. . . . . . . . . . . . . . . .
Figure 60. S2RA (B) SYN2/Secondary Address Register 2 [BOP] 646. . . . . . . . . . . . . . . .
Figure 61. TPRA (B) Transmitter Parameter Register [BOP Mode] 646. . . . . . . . . . . . . . .
Figure 62. RPRA (B) Receiver Parameter Register [BOP Mode] 648. . . . . . . . . . . . . . . . .
Figure 63. RSRA (B) Receiver Status Register [BOP Mode] 648. . . . . . . . . . . . . . . . . . . . .
Figure 64. RSRA (B) Receiver Status Register [BOP - Loop Mode] 649. . . . . . . . . . . . . . .
Figure 65. TRSRA (B) Transmitter and Receiver Status Register [BOP Mode] 650. . . . .
Figure 66. IER1A (B) Interrupt Enable Register 1 [BOP Mode] 650. . . . . . . . . . . . . . . . . .
Figure 67. IER2A (B) Interrupt Enable Register 2 [BOP Mode] 650. . . . . . . . . . . . . . . . . .
Figure 68. CMR1A (B) Channel Mode Register 1 [COP Mode] 653. . . . . . . . . . . . . . . . . . .
Figure 69. CMR2A (B) Channel Mode Register 2 [COP Mode] 654. . . . . . . . . . . . . . . . . . .
Figure 70. S1RA (B) SYN1/Secondary Address Register 1 [COP] 654. . . . . . . . . . . . . . . .
Figure 71. S2RA (B) SYN2/Secondary Address Register 2 [COP] 655. . . . . . . . . . . . . . . .
Figure 72. TPRA (B) Transmitter Parameter Register [COP Mode] 655. . . . . . . . . . . . . . .
Figure 73. RPRA (B) Receiver Parameter Register [COP Mode] 657. . . . . . . . . . . . . . . . .
Figure 74. RSRA (B) Receiver Status Register [COP Mode] 658. . . . . . . . . . . . . . . . . . . . .
Figure 75. TRSRA (B) Transmitter and Receiver Status Register [COP Mode] 659. . . . .
Figure 76. IER1A (B) Interrupt Enable Register 1 [COP Mode] 659. . . . . . . . . . . . . . . . . .
Figure 77. IER2A (B) Interrupt Enable Register 2 [COP Mode] 659. . . . . . . . . . . . . . . . . .
Figure 78. BISYNC BCC Accumulation Examples 661. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 79. Serial Data Stream Formats 664. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TABLES
Table 1. A7 Bit Control 586. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2. CID Definitions 586. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3. CDUSCC Register Address Map 587. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4. Register Bit Assignment Table 588. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5. Interrupt Modes 599. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6. Interrupt Status Encoding 604. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7. CDUSCC DMA Modes 605. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8. DFSB Bit Formats 606. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9. NRZI Mode Count Length 617. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10. FM Mode Count Length 617. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11. Transmitter Baud Rates 618. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12. Receiver Baud Rates 619. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13. Channel Command Register 628. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15. Underrun Control 648. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16. SYN Pattern Processing 660. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17. BISYNC Features 661. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18. Summary of COP Features 662. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19. Protocol Characteristics 667. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
577
1994 Mar 21
FORWARD
This document provides a complete description of the operational
modes of the Philips Semiconductors SC26C562 and 68C562
CMOS Dual Universal Serial Communications Controller
(CDUSCC). AC and DC specifications for the CDUSCC are not
contained in this document, but can be found in the companion
documents, the SC26C562 or SC68C562 data sheet.
Due to the complexity of the many protocols supported by
CDUSCC, this User’s Guide has been organized into three major
sections.
Section 1 — Quick reference data and summary information for
CDUSCC
Section 2 — CDUSCC overview and protocol independent feature
descriptions
Section 3 — CDUSCC protocol dependent feature descriptions
In addition to these sections, an extensive set of appendices have
been provided to supply general protocol background information
and helpful guidance to successful CDUSCC application.
Throughout this document references will be made to the CDUSCC
default and extended modes. The CDUSCC default mode is
identical to the predecessor NMOS component NDUSCC. Thus the
majority of information in this user’s guide is applicable to existing
NDUSCC applications. No special actions are required to achieve
operation in default mode. The extended mode implies the use of
features present on CDUSCC that did not exist on NDUSCC. The
only action required to operate in extended mode is to access
registers not present in NDUSCC by setting A7 bit (see Table 3).
There is no specific default or extended bit or flag, A7 needs to be
set or reset to access the registers, but it is not needed to be
set/reset for actual operation. There are references made to
default/extended Modes, Protocol Modes and DMA Modes. Once
should be careful when interpreting the word ‘Mode’. To avoid
confusion the acronym CDUSCC will be used except when specific
reference to the predecessor component must be made. Any
reference to the SCN26562 and SCN68562 will use the acronym
NDUSCC.
In this document, signals are discussed using the terms ‘active’ and
‘inactive’ or ‘asserted’ and ‘negated’ independent of whether the
signal is active in the High (logic 1) or Low (logic 0) state. An ‘N’ at
the end of a pin name signifies the signal associated with the pin is
Active-Low (see individual pin description for the definition of the
active level of each signal.) Pins which are provided for both
channels are designated by an ‘A/B’ after the name of the pin and
the active-Low state indicator, N, if applicable.
Three aids have been incorporated for locating information in this
document:
1. Table of Contents
2. Cross Reference Index
3. Table 1 (Register Map) identifies the page number that provides
details of the register modes and operations.
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 578
DESCRIPTION
The Philips Semiconductors SC26C562/SC68C562 CMOS Dual
Universal Serial Communications Controller (CDUSCC) is a
single-chip CMOS-LSI communications device that provides two
independent, multi-protocol, full-duplex receiver/transmitter channels
in a single package. It supports bit-oriented and character-oriented
(byte count and byte control) synchronous data link controls as well
as asynchronous protocols. The SC26C562 interfaces to
synchronous bus and SC68C562 interfaces with asynchronous bus
MPUs and are capable of program-polled, interrupt driven,
block-move or DMA data transfers.
The CDUSCC is fully hardware (pin) and software (register)
compatible with the existing NDUSCC. CDUSCC will automatically
configure to the NDUSCC register map (default mode) on power up.
The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multifunction counter/timer , a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides sixteen common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock, making the
CDUSCC well-suited for dual-speed channel applications. Data
rates up to 10Mbits per second are supported.
The transmitter and receiver each contain a sixteen-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to sixteen characters
at a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.
Two modem control inputs (DCD and CTS) and three modem
control outputs (RTS and two general purpose) are provided.
Because the modem control inputs and outputs are general purpose
in nature, they can be optionally programmed for other functions.
The SC26C562 is optimized to interface with processors using a
synchronous bus interface, such as the 80xxx family. The
SC68C562 is used with asynchronous bus, such as the 68xxx
processor family.
PIN CONFIGURATIONS — SC26C562
1
7
8
20
21 33
34
46
47
PLCC
A PACKAGE
INDEX
CORNER
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28
27
26
25
21
22
23
24
IACKN
A3
A2
A1
RTxDAKBN/
GPI1BN
IRQN
RDYN
RSTBN/
SYNOUTBN
TRxCB
RTxCB
DCDBN/
SYNIBN
RxDB
TxDB
TxDAKBN/
GPI2BN
RTxDRQBN/
GPO2BN/RTSBN
CTSBN/LCBN
D7
D6
D5
D4
RDN
RESETN
GND
VCC
TxDRQBN/
GPO1BN
A4
A5
A6
RTxDAKAN/GPI1AN
X1/CLK
X2
RTSAN/SYNOUTAN
TRxCA
RTxCA
DCDAN/SYNIAN
RxDA
TxDA
TxDAKAN/GPI2AN
RTxDRQAN/GPO1AN
CTSAN/LCAN
D0
D1
D2
D3
EOPN
WRN
CSN
TxDRQAN/GPO2AN/
RTSAN
PIN FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
PIN FUNCTION
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
IACKN
A3
A2
A1
RTxDAKBN/
GPI1BN
IRQN
RDYN
RSTBN/
SYNOUTBN
TRxCB
RTxCB
DCDBN/
SYNIBN
RxDB
TxDB
TxDAKBN/
GPI2BN
RTxDRQBN/
GPO2BN/
CTSBN/LCBN
D7
D6
D5
D4
RDN
RESETN
GND
TxDRQBN/
GPO1BN/
VCC
GND D0
D1
D2
D3
EOPN
WRN
CSN
GND
CTSAN/LCAN
TxDRQAN/
RTxDRQAN/
TxDAKAN/
TxDA
RxDA
GND
DCDAN/
RTxCA
TRxCA
RTSAN/
X2
X1/CLK
RTxDAKAN/
A4
A5
A6
VCC
RTSBN
GPO2AN/
GPO1AN/
GPI2AN
SYNIAN
SYNOUTAN
GPI1AN
RTSAN
PIN FUNCTION
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 579
PIN CONFIGURATIONS — SC68C562
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28
27
26
25
21
22
23
24
IACKN
A3
A2
A1
RTxDAKBN/
IRQN
RESETN
RTSBN/
TRxCB
RTxCB
DCDBN/
TxDAKBN/
RTxDRQBN/
TxDRQBN/
CTSBN/LCBN
D7
D6
D5
D4
DTACKN
DTCN
GND CSN
DONEN
D3
D2
D1
D0
CTSAN/LCAN
TxDRQAN/
RTxDRQAN/
TxDAKAN/
TxDA
DCDAN/
RTxCA
TRxCA
RTSAN/
X2/IDCN
X1/CLK
RTxDAKAN/
A6
A5
A4
VCC
N PACKAGE
GPI1BN
SYNOUTBN
SYNIBN
RxDB
TxDB
GPI2BN
GPO1BN
GPO2BN/RTSBN
R/WN
GPO2AN/RTSAN
GPO1AN
GPI2AN
RxDA
SYNIAN
SYNOUTAN
GPI1AN
DIP
Pin Function Pin Function
1 IACKN 27 CSN
2 A3 28 R/WN
3 A2 29 DONEN
4A1 30D3
5 RTxDAKBN/ 31 D2
GPI1BN 32 D1
6 IRQN 33 D0
7 GND 34 VCC
8 RESETN 35 CTSAN/LCAN
9 RTSBN/ 36 TxDRQAN/
SYNOUTBN GPO2AN/RTSAN
10 TRxCB 37 RTxDRQAN/
11 RTxCB GPO1AN
12 DCDBN/ 38 TxDAKAN/
SYNIBN GPI2AN
13 GND 39 TxDA
14 RxDB 40 RxDA
15 TxDB 41 GND
16 TxDAKBN/ 42 DCDAN/
GPI2BN SYNIAN
17 RTxDRQBN/ 43 RTxCA
GPO1BN 44 TRxCA
18 TxDRQBN/ 45 RTSAN/
GPO2BN/RTSBN SYNOUTAN
19 CTSBN/LCBN 46 X2/IDCN
20 D7 47 X1/CLK
21 D6 48 RTxDAKAN/
22 D5 GPI1AN
23 D4 49 A6
24 DTACKN 50 A5
25 DTCN 51 A4
26 GND 52 VCC
INDEX
CORNER A PACKAGE
1
7
8
20
21 33
34
46
47
PLCC
ORDERING INFORMATION
DESCRIPTION
VCC = +5V ±10%,
TA = 0 to +70°CVCC = +5V ±10%,
TA = –40 to +85°C
DWG #
DESCRIPTION
Serial Data Rate =
10Mbps Maximum Serial Data Rate =
8Mbps Maximum
DWG
#
48-Pin Plastic Dual In-Line Package (DIP) SC68C562C1N Not available SOT240-1
52-Pin Plastic Leaded Chip Carrier (PLCC) Package SC68C562C1A SC68C562A8A SOT238-3
ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMETER RATING UNIT
TAOperating ambient temperature 0 to +70 °C
TSTG Storage temperature -65 to +150 °C
VCC Voltage from VCC to GND -0.5 to +7.0 V
TSTG Voltage from any pin to GND -0.5 to VCC +0.5 V
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 580
FEATURES
General Features
•Dual full-duplex synchronous/ asynchronous receiver and
transmitter
•Multi-protocol operation
–BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
–COP: Single SYNC, dual SYNC, BiSYNC, DDCMP
–ASYNC: 5-8 bits plus optional parity
•Sixteen character receive and transmit FIFOs with interrupt
threshold control
•FIFO’d status bits
•W atchdog timer
•0 to 10 Mbit/sec data rate
•High speed data bus interface: 160ns bus cycle
•Programmable bit rate for each receiver and transmitter selectable
from:
–19 fixed rates: 50 to 64K baud
–One user-defined rate derived from programmable
counter/timer
–External 1X or 16X clock
–Digital phase-locked loop
•Parity and FCS (frame check sequence LRC or CRC) generation
and checking
•Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
•Programmable channel mode: full- or half-duplex, auto-echo, or
local loopback
•Programmable data transfer mode: polled, interrupt, DMA, wait
•DMA interface
–Compatible with Synchronous and Asynchronous bus DMA
controllers
–Half- or full-duplex operation
–Single or dual address data transfers
–Automatic frame termination on counter/ timer terminal count or
DMA DONE (EOPN)
–Frame status byte
•DPLL operation up to 312.5kHz with external clock
•Interrupt capabilities
–Vector output (fixed or modified by status)
–Individual interrupt enable bits
–Programmable internal priorities
–Maskable interrupt conditions
–Intel’ s 80XX compatible
–Interrupt Daisy Chain (68C562 only)
•Multi-function programmable 16-bit counter/timer
–Bit rate generator
–Event counter
–Count received or transmitted characters
–Delay generator
–Automatic bit length measurement
•Modem controls
–RTS, CTS, DCD, and up to four general purpose I/O pins per
channel
–CTS and DCD programmable auto-enables for Tx and Rx
–Programmable interrupt on change of CTS or DCD
•T ransmit path clear status
•On-chip oscillator for crystal
•TTL compatible
•Single +5V power supply
Asynchronous Mode Features
•Character length: 5 to 8 bits
•Odd or even parity, no parity, or force parity
•Up to two stop bits programmable in 1/16-bit increments
•1X or 16X Rx and Tx clock factors
•Parity, overrun and framing error detection
•False start bit detection
•Break generation with handshake for counting break characters
•Detection of start and end of received break
•Character compare with optional interrupt on match
•T ransmit and receive up to 10Mbps at 1x data rate
Bit-Oriented Protocol
•Character length: 5 to 8 bits
•Detection and transmission of residual character: 0–7 bits
•Automatic switch to programmed character length for I field
•Zero insertion and deletion
•Optional opening PAD transmission
•Detection and generation of FLAG, ABORT, and IDLE bit patterns
•T ransmit 7 or 8 bit ABORT
•Detection and generation of shared (single) FLAG between
frames
•Detection of overlapping (shared zero) FLAGs
•Idle in MARK or FLAGs
•Secondary address recognition including group and global
address
•Single- or dual-octet secondary address
•Extended address and control fields
•Short frame rejection for receiver
•Detection and notification of received end of message
•CRC generation and checking
•SDLC loop mode capability
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 581
Character-Oriented Protocols
•Character length: 5 to 8 bits
•Odd or even parity, no parity, or force parity
•LRC or CRC generation and checking
•Optional opening PAD transmission
•One or two SYN characters
•External sync capability
•SYN detection and optional stripping
•SYN or MARK linefill or underrun
•Idle in MARKs or SYNs
•Parity, FCS, overrun and underrun error detection
•Optional SYN exclusion from FCS
•BISYNC features
–EBCDIC or ASCII header, text and control messages
–SYN, DLE stripping
–EOM (end of message) detection and transmission
–Auto transparency mode switching
–Auto hunt after receipt of EOM sequence (with closing PAD
check after EOT or NAK)
–Control character sequence detection for both transparent and
normal text
–Parity generation for data and LRC characters
PIN DESCRIPTION
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
MNEMONIC
DIP PLCC
TYPE
NAME
AND
FUNCTION
A1–A6 B 4-2,
47-45 4-2,
51-49 IAddress Lines: Active-high. Address inputs which specify which of the internal
registers is accessed for read/write operation.
D0–D7 B 31-28,
21-18 33-30,
23-20 I/O Bi-directional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All
data, command and status transfers between the CPU and the CDUSCC take place over
this bus. The data bus is enabled when CSN and RDN, or CSN and WRN are low or
during interrupt acknowledge cycles and single address DMA acknowledge cycles.
RDN 26 22 24 I Read Strobe: Active-low input. When active and CSN is also active, causes the content
of the addressed register to be present on the data bus. RDN is ignored unless CSN is
active. (26C562 only)
WRN 26 26 28 I Write Strobe: Active-low input. When active and CSN is also active, the content of the
data bus is loaded into the addressed register. The transfer occurs on the rising edge of
WRN or CSN, whichever occurs first. WRN is ignored unless CSN is active. (26C562
only)
R/WN 68 26 28 I Read/Write: A high input indicates a read cycle and a low indicates a write cycle when
CEN is active. (68C562 only)
CSN
(CEN) 26
68 25 27 I Chip Select (Chip Enable): Active-low input. When active, data transfers between the
CPU and the CDUSCC are enabled on D0–D7 as controlled by RDN or WRN and A1–A6
inputs. When CSN is high, the data lines are placed in the 3-State condition (except
during interrupt acknowledge cycles and single address DMA transfers).
RDYN 26 7 8 O Ready: Active-low, open drain. Used to synchronize data transfers between the CPU
and the CDUSCC. It is valid only during read and write cycles where the CDUSCC is
configured in ‘wait on Rx’, ‘wait on Tx’ or ‘wait on Tx or Rx’ modes, otherwise it is always
inactive. RDYN becomes active on the leading edge of RDN and WRN if the requested
operation cannot be performed (viz, no data in RxFIFO in the case of a read or no room
in the TxFIFO in the case of a write). (26C562 only)
IRQN B 6 6 O Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of
any enabled interrupting condition. The CPU can read the general status register to
determine the interrupting condition(s), or can respond with an interrupt acknowledge
cycle to cause the CDUSCC to output an interrupt vector on the data bus.
IACKN1B 1 1 I Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds
by either forcing the bus into high-impedance, placing a vector number, call instruction or
zero on the data bus. The vector number can be modified or unmodified by the status. If
no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance.
X1/CLK B 43 47 I Crystal 1 or External Clock: When using the crystal oscillator, the crystal is connected
between pins X1 and X2. If a crystal is not used, an external clock is supplied at this
input. This clock is used to drive the internal bit rate generator, as an optional input to the
counter/timer or DPLL, and to provide other required clocking signals. When a crystal is
used, a capacitor must be connected from this pin to ground.
X2 26 42 46 O Crystal 2: Connection for other side of crystal. When a crystal is used, a capacitor must
be connected from this pin to ground. If an external clock is used on X1, this pin should
be left floating. (26C562 only)
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 582
PIN DESCRIPTION (Continued)
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
MNEMONIC
DIP PLCC
TYPE
NAME
AND
FUNCTION
X2/IDCN 68 42 46 O Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the
crystal is connected between pins X1 and X2. When crystal is not used, this pin can be
programmed to provide an interrupt daisy chain active-low output which propagates the
IACKN signal to lower priority devices, if no active interrupt is pending. This pin should
be left floating when an external clock is used on X1 and X2 is not used as an interrupt
daisy chain output. When a crystal is used, a capacitor must be connected from this pin
to ground. (68C562 only)
RESETN 26 23 25 I Master Reset: Active-low. A low on this pin resets the transmitters and receivers and
resets the registers shown in Table 1 of CDUSCC User’s Guide. Reset is asynchronous,
i.e., no clock is required. (26C562)
RESETN 68 7 8 I Master Reset: Active-low. A low on this pin resets the transmitters and receivers and
resets the registers shown in Table 1 of CDUSCC User’s Guide. Reset is asynchronous,
i.e., no clock is required. (68C562)
RxDA, RxDB B 37, 12 40, 14 I Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If
external receiver clock is specified for the channel, the input is sampled on the rising
edge of the clock.
TxDA, TxDB B 36, 13 39, 15 O Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted
first. This output is in the marking (high) condition when the transmitter is disabled or
when the channel is operating in local loopback mode. If external transmitter clock is
specified for the channel, the data is shifted on the falling edge of the clock.
RTxCA,
RTxCB B39, 10 43, 11 I/O Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to
supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply
the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock
(1X).
TRxCA,
TRxCB B40, 9 44, 10 I/O Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),
the transmitter BRG clock (16X), the receiver BRG clock (16X), or the internal system
clock (X1 ÷ 2).
DTACKN 68 22 24 O Data T ransfer Acknowledge: Active-low, 3-state. DTACKN is asserted on a write cycle
to indicate that the data on the bus has been latched, and on a read cycle or interrupt
acknowledge cycle to indicate valid data is on the bus. In a write bus cycle, input data is
latched by the assertion (falling edge) of DTACKN or by the negation (rising edge) of
CSN, whichever occurs first. The signal is negated when completion of the cycle is
indicated by negation of CSN or IACKN input, and returns to the inactive state (3-state) a
short period after it is negated. In single address DMA mode, input data is latched by the
assertion (falling edge) of DTCN or by the negation (rising edge) of the DMA
acknowledge input, whichever occurs first. DTACK is negated when completion of the
cycle is indicated by the assertion of DTCN or negation of DMA acknowledge inputs
(whichever occurs first), and returns to the inactive state (3-state) a short period after it is
negated. When inactive, DTACKN requires an external pull-up resistor . (68C562 only)
DTCN 68 23 25 I Device Transfer Complete: Active-low. DTCN is asserted by the DMA controller to
indicate that the requested data transfer is complete. (68C562 only)
CTSA/BN,
LCA/BN B32, 17 35, 19 I/O Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal
can be programmed to act as an enable for the transmitter when not in loop mode. The
CDUSCC detects logic level transitions on this input and can be programmed to generate
an interrupt when a transition occurs. When operating in the BOP loop mode, this pin
becomes a loop control output which is asserted and negated by CDUSCC commands.
This output provides the means of controlling external loop interface hardware to go on-
line and off-line without disturbing operation of the loop.
DCDA/BN,
SYN1A/BN B38, 11 42, 12 I Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin
is programmable. As a DCD active-low input, it acts as an enable for the receiver or can
be used as a general purpose input. For the DCD function, the CDUSCC detects logic
level transitions on this pin and can be programmed to generate an interrupt when a
transition occurs. As an active-low external sync input, it is used in COP single SYN
mode to obtain character synchronization for the receiver without receipt of a SYN
character. This mode can be used in disc or tape controller applications or for the
optional byte timing lead in X.21.
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 583
PIN DESCRIPTION (Continued)
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
MNEMONIC
DIP PLCC
TYPE
NAME
AND
FUNCTION
RTxDRQA/BN,
GPO1A/BN B34, 15 37, 17 O Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose
Output: Active-low. For half-duplex DMA operation, this output indicates to the DMA
controller that one or more characters are available in the receiver FIFO (when the
receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled).
For full-duplex DMA operation, this output indicates to the DMA controller that data is
available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output
that can be asserted and negated under program control.
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
B33, 16 36, 18 O Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to
the DMA controller that the transmit FIFO is not full and can accept more data. When not
in full-duplex DMA mode, this pin can be programmed as a general purpose or a
Request-to-Send output, which can be asserted and negated under program control.
RTxDAKA/BN,
GPI1A/BN B44, 5 48, 5 I Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-low. For half-duplex single address operation, this input indicates to the CDUSCC
that the DMA controller has acquired the bus and that the requested bus cycle (read
receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter
is enabled) is beginning. For full-duplex single address DMA operation, this input
indicates to the CDUSCC that the DMA controller has acquired the bus and that the
requested read receiver FIFO bus cycle is beginning. Because the state of this input can
be read under program control, it can be used as a general purpose input when not in
single address DMA mode.
TxDAKA/BN,
GPI2A/BN B35, 14 38, 16 I Channel A (B) T ransmitter DMA Acknowledge or General Purpose Input:
Active-low. When the channel is programmed for full-duplex single address DMA
operation, this input is asserted to indicate to the CDUSCC that the DMA controller has
acquired the bus and that the requested load transmitter FIFO bus cycle is beginning.
Because the state of this input can be read under program control, it can be used as a
general purpose input when not in full-duplex single address DMA mode.
EOPN1 (DO-
NEN) 26
68 27 29 I/O EOPN (DONEN): Active-low , open-drain. EOPN (DONEN) can be used and is active in
both DMA and non-DMA modes. As an input, EOPN indicates the last DMA transfer
cycle to the TxFIFO. As an output, EOPN indicates either the last DMA transfer from the
RxFIFO or that the transmitted character count has reached terminal count.
RTSA/BN,
SYNOUTA/BN B41, 8 45, 9 O Channel A (B) Sync Detect or Request-to-Send: Active-low. If programmed as a sync
output, it is asserted one bit time after the specified sync character (COP or BISYNC
modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send
modem control signal, it functions as described previously for the TxDRQN/RTSN pin.
VCC B48 34, 52 I +5V Power Input
GND B 24 26, 13,
41, 7 ISignal and Power Ground Input
B: Both 68C562 and 26C562
26: Intel version only (26C562)
68: Motorola version only (68C562)
NOTES:
1. These pins should be “pulled-up” with an external resistor to VCC if not used.
2. Please refer to data sheet (Product Specification) for timing information.
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 584
SECTION 1
QUICK REFERENCE DATA
Philips Semiconductors
Data Communications
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 585
NDUSCC AND CDUSCC COMPATIBILITY
Hardware Compatibility
Users familiar with the NMOS version of DUSCC (SCN26562)
should be aware that the CDUSCC is fully hardware pin compatible
with NDUSCC. However, Philips Semiconductors recommends for
optimum performance that the following measures be taken for new
card designs utilizing CDUSCC in the PLCC package.
1. Provide additional ground connections to Pins 7, 13 and 41
(previously not connected).
2. Provide additional VCC connection and de-coupling to Pin 34
(previously not connected)
Failure to follow the above guidelines (i.e., use of the CDUSCC in
printed circuit cards designed for NDUSCC) can result in reduced
noise margins for the device. Performance of a CDUSCC device in
an NDUSCC socket will be as good as that for the NMOS device,
but not up to the full potential of the CMOS device with respect to
noise margin.
Designs using external TTL drive to X1 should float X2 when using
CDUSCC (vs grounding X2 for NDUSCC). CDUSCC may be safely
operated with X2 grounded, but power dissipation of the IC will be
increased. In the event that X2 cannot be floated when using TTL
drive (i.e., CDUSCC in an NDUSCC socket) power dissipation can
be reduced by disabling the X2 driver via software (set PCRA [7] =
1, see Figure 42).
Designs with critical AC timing should review the CMOS DUSCC
data sheet, since many AC timings have been improved over the
NMOS DUSCC, and timing problems might occur if the user
hardware is not capable of supporting these improved timings.
Software Compatibility
The CDUSCC supports an extended register set which is accessed
via two previously unused registers in the NDUSCC register space
(addresses 011101 and 111101), the user should verify that no I/O
writes occur to these register locations. Some users use a block
write to initialize all registers, which will write to these locations.
Software that accesses either of these locations and is not intended
to make use of the extended capabilities of CDUSCC should be
modified to eliminate the access.
Since the data FIFOs of CDUSCC are deeper than NDUSCC, it is
possible that software expecting data to overrun the FIFOs’ would
not get overrun and data will not be lost. In most cases this is not a
problem, but some users may have utilized such techniques for
diagnostic purposes. In that case the diagnostic code should be
modified.
New Capabilities
CDUSCC adds the following major features:
•8 bit data bus with 160ns bus cycle
•0 to 10Mbit per second line data rate
•RxFIFO
–16 x 8 data FIFO
–RxRDY triggered by programmable filled level of FIFO
–W atch dog timer
–Status bits for the filled level of RxFIFO
–FIFO all error status bits
–DMA frame status byte
•TxFIFO
–16 x 8 data FIFO
–TxRDY triggered by programmable filled level of FIFO
–Status bits for the empty level of TxFIFO
•Baud Rate Generator — from 50bps up to 64Kbps
•Interrupt control
–Individual interrupt enable bits
•Support X.21 pattern recognition
•Improved BiSYNC support
–Parity/LRC
–SYN exclusion
–ITB block handling
–Header only handling
•Lower power consumption
To access some of these capabilities, additional registers are
required. The technique used to access these additional registers is
to re-use the addresses of eight registers not normally accessed
after initial configuration. The setting of the A7 bit will toggle to the
alternate register set. In this document the term ‘Extended Mode’
will be used to indicate that the A7 bit had been set at some point,
and the value of the alternate register set changed to invoke some
of the new CDUSCC features. It is not necessary for the A7 bit to
remain set for the extended mode features to operate. A7 bit must
be reset to 0 to access some of the old registers, as listed below
(see Table 1). The term ‘Default Mode’ will be used to indicate that
none of the new features were selected, and NDUSCC register
compatibility is being maintained.
A7 = 0 A7 = 1
S1R IER1
S2R IER2
TTR IER3
RTR TRCR
PCR RFLR
IER FTLR
IVR/IVRM TRMSR
ICR/MRR TELR
REGISTERS
The addressable registers of the CDUSCC are shown in Table 4.
The following rules apply to all registers:
1. A read from the SEA location in the map results in all ones for
data.
2. Unused bits of a defined register are read as zeros, unless ones
have been loaded after master reset.
3. Bits that are unused in the chosen mode but are used in others
are readable and writable but their contents are ignored in the
chosen mode.
4. All registers are addressable as 8-bit quantities only.
The operation of the CDUSCC is programmed by writing control
words into the appropriate registers. Operational feedback is
provided via status registers which can be read by the CPU. The
contents of certain control registers are initialized on MASTER
RESET. Care should be exercised if the contents of a register are
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 586
changed during operation, since certain changes may cause
operational problems, e.g., changing the channel mode at an
inappropriate time may cause the reception or transmission of an
incorrect character. In general, the contents of registers which
control transmitter or receiver operation, or the counter/timer, should
be changed only when they are not enabled.
The CDUSCC registers can be separated into five groups to
facilitate their usage:
1. Channel mode configuration and pin description registers
2. T ransmitter and receiver parameter and timing registers
3. Counter/timer control and value registers
4. Interrupt control and status registers
5. Command registers
This arrangement is used in the following description of the
CDUSCC registers. Register bit map is described in the same order
as register address map in Table 3.
FUNCTIONAL DESCRIPTION
Functional Description
As illustrated in the Block Diagram, the CDUSCC consists of eight
major functional blocks:
– Host Interface and Bus Buffer
– DMA Interface
– Special Function Pins
– Interrupt Control
– Channel Timing
– Operation Control
– Transmitter
– Receiver
Other than the Operation Control section, which is very much
dependent upon the communications protocol selected, most of the
functional blocks of CDUSCC operate in essentially the same
manner regardless of protocol mode. The description of CDUSCC
will be separated into PROTOCOL INDEPENDENT RESOURCES
(Section 2), the operation of which is not affected by selection of
protocol mode, and PROTOCOL DEPENDENT RESOURCES
(Section 3), which behave quite differently depending on the
protocol selected.
Host Interface
Two versions of the CDUSCC exist, each supporting a different Host
Interface. The 26C562 supports Intel-like MPUs; the 68C562
supports Motorola-like 68k CPUs.
The host interface of the 26C562 consists of an 8-bit, bi-directional
data bus (D0-D7), 6 address lines (A1-A6), four control inputs (RDN,
WRN, CSN, RESETN) and one control output (RDYN). This host
interface is compatible with iAPX hosts without additional logic
(other than address decoding).
The host interface of the 68C562 consists of an 8-bit, bi-directional
data bus (D0-D7), 6 address lines (A1-A6), three control inputs
(R/WN, CSN, RESETN) and one control output (DTACK). This host
interface is compatible with 68000 hosts without additional logic
(other than address decoding).
Address 7: The CDUSCC has a register space of 128 bytes, but
only 6 address lines are physically present. A7, the 7th address bit,
is generated internally by a flip-flop. Upon reset, the flip-flop is reset
(A7 = 0). The A7 bit can be set or cleared by writing FFh to the SEA
or REA registers at the following addresses:
Table 1. A7 Bit Control
ADDRESS WRITE READ
1Dh REA Reset A7 CID
3Dh SEA Set A7 Not Allowed
By setting the A7 address bit, the user has made available the
complete resource set of the CDUSCC, at the cost of some register
level compatibility with the NDUSCC predecessor part. Only the
eight register pairs indicated in the table on the previous page are
affected by the A7 bit. All other registers have the same function
and bit definitions regardless of the A7 state. It should be noted that
many of the registers in the default mode state (A7 = 0) must be
properly initialized prior to switching to extended mode (A7 = 1).
Once in extended mode, it is not normally necessary to return to
default mode unless a radical change to the channel operation or
protocol is required.
Chip Identification: A read from the CID register at address 1Dh
returns a software signature that identifies the version of CDUSCC
installed on the card. This feature enables a single software driver
to be self adapting to the capabilities of the hardware installed
(NDUSCC, CDUSCC or future derivatives).
Table 2. CID Definitions
Read Data Part Version
FFh NDUSCC – all revisions
7Fh CDUSCC Rev –
BFh CDUSCC Rev A
Master Reset: The contents of each register following a master
reset is shown in Table 3, the CDUSCC Register Address Map. For
68C562, master reset can only be achieved by assertion of the
RESETN signal line (called Hardware Reset). For 26C562, reset
can be achieved by either assertion of the RESETN signal or by
writing FFh to MRR register. The MRR is used to perform reset
function by software. For 26C562, the MRR register must be read
no matter what method is used for reset (Power-up, Hardware
Reset, Software Reset) prior to operation of the CDUSCC.
W ait Mode: Either the receiver or the transmitter or both may be
programmed for wait mode operation, independently for each
channel, via CMR2[5:3].
In this mode, if the host attempts a write to the transmit FIFO and an
empty FIFO position is not available, the RDYN (for 26C562) or
DTACKN (for 68C562) line will not assert until a position empties.
The data will then be written into the FIFO and RDYN will be
negated to signify that the transfer is complete. Similarly, a read of
an empty receive FIFO will be held off until data is available to be
transferred.
CAUTION: This mode can potentially cause the host system to hang up if, for example, a
read request was made and no further data was available.
NOTE: Unless the CMR2 register has been programmed for this mode of operation,
RDYN output is always inactive. It cannot be used to introduce Wait States in other bus
cycles, i.e., command or status register I/O.
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 587
Table 3. CDUSCC Register Address Map
Hex Address Acro-
nym Register Name Mode5R/W Affected By Page
Ch. A Comm. Ch. B Master Reset Ref.
00h 20h CMR1 Channel Mode Register 1 Both R/W Yes — 00 638, 644, 653
01h 21h CMR2 Channel Mode Register 2 Both R/W Yes — 00 639, 645, 654
02h122h1S1R SYN 1/Secondary Address 1 Register Default R/W Yes — 00 640, 646, 654
03h123h1S2R SYN 2/Secondary Address 2 Register Default R/W Yes — 00 646 655
04h 24h TPR T ransmitter Parameter Register Both R/W Yes — 00 640, 646, 655
05h125h1TTR Transmitter Timing Register Default R/W Yes — 00 618
06h 26h RPR Receiver Parameter Register Both R/W Yes — 00 641, 648, 657
07h127h1RTR Receiver T iming Register Default R/W Yes — 00 619
08h 28h CTPRH Counter/Timer Preset Register High Both R/W No 623
09h 29h CTPRL Counter/Timer Preset Register Low Both R/W No 623
0Ah 2Ah CTCR Counter/Timer Control Register Both R/W Yes — 00 622
0Bh 2Bh OMR Output and Miscellaneous Register Both R/W Yes — 00 626
0Ch 2Ch CTH Counter/Timer High Both R No 623
0Dh 2Dh CTL Counter/Timer Low Both R No 624
0Eh12Eh1PCR Pin Configuration Register Default R/W Yes — 00 625
0Fh 2Fh CCR Channel Command Register8Both R/W Yes — 00 628
10h 30h TxFIFO T ransmitter FIFO Both W4Yes — 00 611
14h 34h RxFIFO Receiver FIFO Both R4Yes — 00 612
18h 38h RSR Receiver Status Register Both R/W2Yes — 00 642, 648, 649,
658
19h 39h TRSR Transmitter and Receiver Status Register Both R/W2Yes — 00 643, 650, 659,
1Ah 3Ah ICTSR Input and Counter/T imer Status Register Both R/W2Yes — 00 595
1Bh GSR General Status Register Both R/W2Yes — 00 594
1Ch13Ch1IER Interrupt Enable Register Default R/W2Yes — 00 602
1Dh REA Reset A7 bit Both W Yes A7 = 0 586
1Dh CID Chip ID Register Extended R No 586
1Eh1IVR Interrupt Vector Register — Unmodified Default R/W Yes — 0Fh 604
1Fh1ICR Interrupt Control Register Default R/W Yes — 00 601
3Dh SEA Set A7 bit Both W Yes A7=0 586
3Eh1IVRM Interrupt Vector Register — Modified Default R Yes — FFh 604
3Fh1MRR Master Reset Register Default R/W Yes6586
02h322h3IER1 Interrupt Enable Register 1 Extended R/W Yes — 00 603, 643, 650,
659
03h323h3IER2 Interrupt Enable Register 2 Extended R/W Yes — 00 603, 643, 650,
659
05h325h3IER3 Interrupt Enable Register 3 Extended R/W Yes — 00 603
07h327h3TRCR Tx/Rx Command Register Extended R/W Yes — 00 627
0Eh32Eh3RFLR RxFIFO fill level register7Extended R Yes — 00 614
1Ch33Ch3FTLR FIFO threshold level register Extended R/W Yes — 33h 615
1Eh33Eh3TRMSR Tx/Rx Misc Status Register Extended R/W2Yes — 00 596
1Fh33Fh3TELR TxFIFO empty level register7Extended R Yes — 10h 614
NOTES:
1. Internal A7 bit should be set to ‘0’ thru REA register to access these registers.
2. A write to this register may perform a status resetting operation.
3. Internal A7 bit should be set to ‘1’ thru SEA register to access these registers.
4. FIFOs are addressable at any of four adjacent addresses to allow them to be addressed as byte/word/double word with the iAPX86 Family
MOV instruction.
5. The mode identifies if this register is used in NDUSCC (default), CDUSCC (extended) or both modes of operation. Default and extended
mode registers are mutually exclusive in the address space.
6. SC26C562 version only, a read of MRR must be performed after H/W reset or power-up and before any operation of the 26C562 is enabled.
7. FIFO fill level and empty levels are updated after 5-7 X1 clocks at reset.
8. Minimum of three X1 clocks are required while CEN/CSN is high between two commands for the same channel.
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 588
Table 4. Register Bit Assignment Table
Addr
A / B Register Mode 7 6 5 4 3 2 1 0
00h/20h CMR1 ASYNC data encoding parity type parity mode 1 1 1
BOP data encoding extended
ctrl address mode 0 channel protocol mode
COP data encoding char code parity mode 1 channel protocol mode
01/21h CMR2 ASYNC channel connection data transfer interface 0 0 0
SYNC channel connection data transfer interface frame check sequence select
02/22h S1R ASYNC character compare (5-8 bits)
BOP first address octet
COP SYN1 (5-8 bits)
03/23h S2R BOP second address octet
COP SYN2 (5-8 bits)
04/24h TPR ASYNC stop bits per character TxRTS
control CTS enable
Tx Tx character length
BOP underrun control IDLE TEOM on
Zero or
Done
TxRTS
Control CTS enable
Tx Tx character length
COP underrun control IDLE TEOM on
Zero or
Done
TxRTS
Control CTS enable
Tx Tx character length
05/25h TTR all ext. TxC
source transmitter clock select bit rate select from internal BRG
06/26h RPR ASYNC 0 0 0 RxRTS
control strip parity DCD
enable Rx Rx character length
BOP 0FCS to
FIFO overrun
mode 0all party
address DCD
enable Rx Rx character length
COP SYN strip FCS to
FIFO auto hunt &
pad ck external
sync strip parity DCD
enable Rx Rx character length
07/27h RTR all ext. RxC
source receiver clock select bit rate select from internal BRG
08/28h CTPRH all most significant bits of counter/timer preset value
09/29h CTPRL all least significant bits of counter/timer preset value
0A/2Ah CTCR all zero detect
interrupt zero detect
control output
control prescaler clock source
0B/2Bh OMR all Tx residual character length TxRDY
activate RxRDY
activate OUT2 OUT1 RTS
0C/2Ch CTH all most significant bits of counter/timer
0D/2Dh CTL all least significant bits of counter/timer
0E/2Eh PCR all X2/IDC* GPO2/
RTS SYNOUT/
RTS RTxC pin usage TRxC pin usage
0F/2Fh CCR all command word
10/30h TxFIFO all transmit data port
14/34h RxFIFO all receive data port
18/38h RSR ASYNC character
compare RTS
negated overrun
error not used BRK end
detect BRK start
detect framing
error parity error
BOP EOM
detect abort detect overrun
error short frame
det idle detect flag detect CRC error RCL not
zero
BOP
loop EOM
detect abort/ EOP
det overrun
error short frame
det turn-around
det flag detect CRC error RCL not
zero
COP EOM
detect pad error overrun
error not used not used SYN detect CRC error parity error
* PCRA only, not used in PCRB
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 589
Register Bit Assignment Table (continued)
Addr
A / B Register Mode 7 6 5 4 3 2 1 0
19/39h TRSR ASYNC Tx
underrun CTS
underrun not used send break
ack DPLL error not used not used not used
BOP Tx
underrun CTS
underrun frame
complete send SOM/
abort ack DPLL error Rx residual character length
BOP
loop Tx
underrun Loop
sending frame
complete send SOM/
abort ack DPLL error Rx residual character length
COP Tx
underrun CTS
underrun frame
complete send SOM/
ack DPLL error not used Rx hunt
mode Rx xpnt
mode
1A/3Ah ICTSR all C/T
running C/T zero
count delta DCD delta
CTS/LC DCD CTS/LC GPI2 GPI1
1Bh GSR all external or
C/T status
(chan B)
Rx/Tx
status
(chan B)
TxRDY
(chan B)
RxRDY
(chan B)
external or
C/T status
(chan A)
Rx/Tx
status
(chan A)
TxRDY
(chan A)
RxRDY
(chan A)
1C/3Ch IER all DCD/CTS TxRDY TRSR[7:3] RxRDY RSR [7:6] RSR [5:4] RSR [3:2] RSR [1:0]
1Dh
REA
all reset internal A7 to 0
1Dh
CID
all chip identification
1Eh IVR all 8-bit interrupt vector — unmodified
1Fh ICR all channel A/B interrupt
priority vector mode bits to
modify vector
includes
status
chan A
master int
enable
chan B
master int
enable
3Dh
SEA
all set internal A7 to 1
3Eh IVRM all 8-bit interrupt vector — modified
3Fh MRR all master reset register (26C562/26562 only)
02/22h
IER1
ASYNC character
compare RTS
negated overrun reserved BRK end BRK start frame error parity error
BOP EOM
detect ABORT
detect overrun short frame idle flag detect CRC error RCL not
zero
BOP
loop EOM
detect EOP detect overrun short frame turn-around
det flag detect CRC error RCL not
zero
COP EOM det PAD error overrun reserved reserved SYN det CRC/LRC
error parity error
03/23h
IER2
ASYNC Tx path
empty reserved Tx underrun CTS
underrun send BRK
ACK DPLL error ∆ CTS det ∆ DCD det
BOP Tx path
empty Tx frame
complete Tx underrun CTS
underrun send SOM
ack DPLL error ∆ CTS det ∆ DCD det
BOP
loop Tx path
empty Tx frame
complete Tx underrun CTS
underrun send SOM
ack DPLL error ∆ CTS det ∆ DCD det
COP Tx path
empty Tx frame
complete Tx underrun CTS
underrun send SOM
ack DPLL error ∆ CTS det ∆ DCD det
05/25h
IER3
all ch master
int enable TxRDY int
enable RxRDY int
enable patt recog
int enable reserved reserved reserved reserved
07/27h
TRCR
all watchdog
timer
enable
DMA status
byte enable pattern
recog 0
enable
pattern
recog 1
enable
pattern
recog 01
enable
extended
int mask
enable
extended
bit rate
enable
7-bit abort
ena (BOP
only)
0E/2Eh
RFLR
all reserved reserved reserved Rx FIFO fill level
1C/3Ch
FTLR
all TxFIFO threshold level RxFIFO threshold level
1E/3Eh
TRMSR
all reserved reserved reserved reserved Tx path
empty pattern 0
status pattern 1
status pattern alt
0/1 status
1F/3Fh
TELR
all reserved reserved reserved TxFIFO empty level
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 590
BLOCK DIAGRAM — SC26C562
D0–D7
RDYN
A1–A6
CEN
RESETN
BUS
BUFFER
CHANNEL
TIMING A/B
DPLL CLK
MUX A/B
DPLLA/B
CTCRA/B
CTPRHA/B
CTPRLA/B
RxD A/B
TxD A/B
CONTROL
INTERNAL BUS
BRG
COUNTER
TIMER A/B
C/T CLK
MUX A/B
CTHA/B
CTLA/B
TRANS CLK
MUX
TRANSMIT
A/B
TPRA/B
TTRA/B
TX SHIFT
REG
TRANSMIT
16 DEEP
FIFO
CRC
GENERATOR
SPEC CHAR
GEN LOGIC
RCVR CLK
MUX
RCVR
SHIFT REG
RECEIVER
16 DEEP
FIFO
CRC
ACCUM
RECEIVER
A/B
RPRA/B
RTRA/B
S1RA/B
S2RA/B
BISYNC
COMPARE
LOGIC
ADDRESS
DECODE
DMA
CONTROL
OPERATION
CONTROL
CCRA/B
PCRA/B
RSRA/B
TRSRA/B
ICTSRA/B
R/W
DECODE
GSR
CMR1A/B
CMR2A/B
OMRA/B
HOST
INTERFACE
WRN
RTxDRQAN/GPO1AN
DMA
INTERFACE
RTxDRQBN/GPO1BN
TxDRQAN/GPO2AN
TxDRQBN/GPO2BN
RTxDAKAN/GPI1AN
RTxDAKBN/GPI1BN
TxDAKAN/GPI2AN
TxDAKBN/GPI2BN
EOPN
TRxCA/B
SPECIAL
FUNCTION
PINS
RTxCA/B
CTSAN/LCAN
CTSBN/LCBN
DCDBN/SYNIBN
DCDAN/SYNIAN
RTSBN/SYNOUTBN
RTSAN/SYNOUTAN
INTERRUPT
CONTROL
ICRA/B
IERA/B
IVRM
IER1 A/B
IRQN
IACKN
X1/CLK
X2 OSCILLATOR
CDUSCC
LOGIC
IER2 A/B
IER3 A/B
TRCR A/B
FTLR A/B
TELR
A/B
RFLR
A/B
A7 CONTROL
LOGIC
A7
REA
SEA
TRMSRA/B
CID
RDN
MRR
Philips Semiconductors User’s Guide
CMOS DUSCC User’s Guide
1994 Mar 21 591
BLOCK DIAGRAM — SC68C562
D0–D7
DTACKN
A1–A6
CSN
RESETN
BUS
BUFFER
CHANNEL
TIMING A/B
DPLL CLK
MUX A/B
DPLLA/B
CTCRA/B
CTPRHA/B
CTPRLA/B
RxD A/B
TxD A/B
CONTROL
INTERNAL BUS
BRG
COUNTER
TIMER A/B
C/T CLK
MUX A/B
CTHA/B
CTLA/B
TRANS CLK
MUX
TRANSMIT
A/B
TPRA/B
TTRA/B
TX SHIFT
REG
TRANSMIT
16 DEEP
FIFO
CRC
GENERATOR
SPEC CHAR
GEN LOGIC
RCVR CLK
MUX
RCVR
SHIFT REG
RECEIVER
16 DEEP
FIFO
CRC
ACCUM
RECEIVER
A/B
RPRA/B
RTRA/B
S1RA/B
S2RA/B
BISYNC
COMPARE
LOGIC
ADDRESS
DECODE
DMA
CONTROL
OPERATION
CONTROL
CCRA/B
PCRA/B
RSRA/B
TRSRA/B
ICTSRA/B
R/W
DECODE
GSR
CMR1A/B
CMR2A/B
OMRA/B
HOST
INTERFACE
RWN
RTxDRQAN/GPO1AN
DMA
INTERFACE
RTxDRQBN/GPO1BN
TxDRQAN/GPO2AN
TxDRQBN/GPO2BN
RTxDAKAN/GPI1AN
RTxDAKBN/GPI1BN
TxDAKAN/GPI2AN
TxDAKBN/GPI2BN
DONEN
TRxCA/B
SPECIAL
FUNCTION
PINS
RTxCA/B
CTSAN/LCAN
CTSBN/LCBN
DCDBN/SYNIBN
DCDAN/SYNIAN
RTSBN/SYNOUTBN
RTSAN/SYNOUTAN
INTERRUPT
CONTROL
ICRA/B
IERA/B
IVRM
IER1 A/B
IRQN
IACKN
X1/CLK
X2/IDCN OSCILLATOR
CDUSCC
LOGIC
IER2 A/B
IER3 A/B
TRCR A/B
FTLR A/B
TELR
A/B
RFLR
A/B
A7 CONTROL
LOGIC
A7
REA
SEA
TRMSRA/B
CID
DTCN
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 592
SECTION 2
PROTOCOL INDEPENDENT
FEATURES
Philips Semiconductors
ICs for Data Communications
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 593
STATUS
This group of registers define mechanisms for communications
between the CDUSCC and the host processor and contain the
CDUSCC status information. Selection of the CDUSCC ‘Extended
Mode’ (via SEA) will alter both the number of registers in this group
and functionality of the interface. Extended Mode provides the
greater degree of flexibility and is recommended for all new designs.
The ‘Default Mode’ has been provided to maintain software
compatibility for NDUSCC drivers that must operate with CDUSCC
components. Eight registers comprise this group which consists of
the following:
– Status Registers
– Default Mode
GSR, RSRA/B, TRSRA/B, ICTSRA/B
– Extended Mode
GSR, RSRA/B, TRSRA/B, ICTSRA/B
TRMSRA/B
– Interrupt Control Registers
– Default Mode
IERA/B, IVR, IVRM, ICR
– Extended Mode
IVR, IVRM, ICR, IER1, IER2, IER3
Status Registers
The status registers of CDUSCC have been organized with three
objectives in mind:
– ‘Quick Look’ to minimize programmed I/O overhead
– Accumulation of data integrity status until reset
(non-FIFOed status mode)
– Compatibility with NDUSCC
The ‘Quick Look’ is provided by the General Status Register (GSR)
which in a single byte provides information on both the A and B
channels complete ‘default mode’ status (Figure 1). Since the state
of all pertinent status bits are reflected in the GSR, it is usually not
necessary to read the other status registers unless an error bit is set
in the GSR bits [7:6] or [3:2].
The majority of status bits in all status registers except the
GSR are NOT reset when the event that causes them ceases.
Either the status bit must be reset directly by writing a ‘1’ to that bit
position of the status register, or indirectly by issuing a reset or
similar action to the section controlling that bit (see detailed
discussion in status register bit definitions). This was done so that
in protocols where entire blocks (frames) of data are accepted or
rejected as a whole, the need for status checking could be reduced
to a single check at the end of the block. Of course the user must
be careful to ensure that all status bits are reset prior to beginning
the next block processing.
For FIFOed status bits, every RxFIFO read updates these bits
based on the status of the current character on top of the RxFIFO.
For non-FIFOed status bits, status of these bits is accumulated
(ORed) unless they are cleared by writing ‘1’ in the specific bit
position in the appropriate registers or by resetting the receiver by
CCR command.
By keeping the status bits associated to new CDUSCC
enhancements in separate (TRMSRA/B) registers, software
compatibility has been maintained with NDUSCC (Figure 2). The
GSR[2] (Ch A) and GSR[6] (Ch B) reflect the status of TRMSR[3:0],
TRSR[7:3] and RSR[7:0]. Thus, the GSR continues to provide a
“quick look” status in the extended mode.
When operating in synchronous protocols with DMA, the user of
CDUSCC has the option of enabling the DMA Frame Status Byte
(DFSB). This byte will alleviate the need to check status registers
by programmed I/O when DMA is used for data transfer. The status
bits are appended onto a byte transferred to the host via DMA
following the last data byte of the frame. The DFSB is fully
described in the DMA section on page 606.
C/T C/T XXXX
RUN = 0 DCD CTS
UNDER XXX
RUN *
**ERROR FRAME
TRDYB RRDYB
ICTSRB
(6:4)
TRSRB
(7:3)
RSRB ICTSRA
(6:4)
Transmitter and Receiver Status Register A (TRSRA)
Input & C/T Status Register A (ICTSRA) Receiver Status Register A (RSRA)
General Status Register
Figure 1. Status Register Organization: Default Mode
(7:0)
TRSRA
(7:3)
RSRA
(7:0) TRDYA RRDYA
*Protocol Dependent
Same as
for ‘A’
Channel
—Shaded bits may be reset by writing a ‘1’ to that bit position
****
DPLL
FRAME
COMP
CTS
UNDER
RUN
∆∆ OVR SHORT
[NOTE: Resetting GSR status bits by writing to the GSR is not recommended.]
* – Protocol dependent
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 594
TX
PATH
C/T C/T XXXX
RUN = 0 DCD CTS
UNDER CTS FRAME DPLL X X X
RUN UNDER COMP
RUN *
**ERROR FRAME
TRDYB RRDYB
ICTSRB
(6:4) TRMSRB(3:0)
TRSRB(7:3)
RSRB(7:0) ICTSRA
(6:4)
Transmitter and Receiver Status Register A (TRSRA)
Input & C/T Status Register A (ICTSRA)
Receiver Status Register A (RSRA)
General Status Register
Figure 2. Status Register Organization: Extended Mode
TRMSRA(3:0)
TRSRA(7:3)
RSRA(7:0) TRDYA RRDYA
*Protocol Dependent
Same as
for ‘A’
Channel
—Shaded bits may be reset by writing a ‘1’ to that bit position
CTS FRAME
** **
XXX PATT
PATT ALT
PATT
Transmitter and Receiver Misc Status Register A (TRMSRA)
EMPTY 01
∆∆ OVR SHORT
X
[NOTE: Resetting GSR status bits by writing to the GSR is not recommended.] * – Protocol dependent
Figure 3. GSR General Status Register [All Protocol Modes]
76543210
Ch. A RxRDY
Ch. A TxRDY
Ch. A Rx/Tx status
Ch. A External or C/T
status
Ch. B RxRDY
Ch. B TxRDY
Ch. B Rx/Tx status
Ch. B External or
C/T status
CHANNEL A
CHANNEL B
This bit indicates that one of the following status bits is asserted: ICTSRB[6:4].
This bit indicates that one of the following status bits is asserted: RSRB[7:0], TRSRB[7:3],
TRMSR[3:0]
The assertion of this bit indicates that one or more characters may be loaded into the Channel B
transmitter FIFO to be serialized by the transmit shift register. See description of OMR[4].
The assertion of this bit indicates that one or more characters are available in the channel B receiver
FIFO to be read by the CPU. See description of OMR[3]. This bit is also set when EOM or WDT bits
are set. RxRDY is initially reset (negated) by a chip reset or when a ‘reset channel B receiver’
command is invoked.
This bit indicates that one of the following status bits is asserted: ICTSRA[6:4].
This bit indicates that one of the following status bits is asserted: RSRA[7:0],
TRSRA[7:3], TRMSR[3:0]
The assertion of this bit indicates that one or more characters may be loaded into the
channel A transmitter FIFO to be serialized by the transmit shift register. See description
of OMR[4]. The true status of this bit can be read only when the transmitter is enabled.
The ResetTx command (not the DisableTx command) initially clears the TxFIFO and the
internal TxRDY signal. After the next EnableTx command, the then current status of the
bit may be determined again by reading GSR.
The assertion of this bit indicates that one or more characters are available in the
Channel A receiver FIFO to be read by the CPU. This bit is also set when EOM or WDT
bits are set. See OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a
‘reset channel A receiver’ command is invoked.
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 595
General Status Register (GSR)
This register provides a ‘quick look’ at the overall status of both
channels of the CDUSCC. Resetting bits in the GSR can be
achieved as follows: For TxRDY and RxRDY (Bits 5 and 1, or 4 and
0, respectively), writing a ‘one’ to that bit position of the GSR will
reset the status bit. Multiple bits can be reset simultaneously, and
writing ‘one’ to a bit position not set will have no effect. The other
status bits are reset by resetting the individual status bits that they
point to in the respective source register (RSR, TRSR, ICTSR,
TRMSR).
CAUTION: The TxRDY and RxRDY bits in GSR are edge triggered
and are not synchronized to a write operation to GSR. It is
recommended that the GSR bits NOT be reset via a write operation
when transmitter or receiver are active.
Receiver and Transmitter Status Registers (RSR,
TRSR)
RSR informs the CPU of receiver status. Bits indicated as ‘not used’
in a particular mode will read as zero. The logical OR of these bits
is presented in GSR[2] or GSR[6] (ORed with the bits of TRSR) for
channels A and B, respectively. Unless otherwise indicated,
asserted status bits are reset only by performing a write operation to
the status register with the bits to be reset being ones in the
accompanying data word, or when the RESETN input is asserted, or
when a ‘reset receiver’ command is issued.
Certain status bits are specified as being FIFOed. This means that
they occupy positions in a status FIFO that correspond to the data
FIFO. As the data is brought to the top of the FIFO (the position
read wen the RxFIFO is read), the FIFOed status bits are logically
ORed with the previous contents of the corresponding bits in the
status register. This permits the user to obtain status either
character by character or on a block basis. For character by
character status, the SR bits should be read and then cleared before
reading the character data from RxFIFO. For block status, the
status register is initially cleared and then read after the message is
received. Asserted status bits can be programmed to generate an
interrupt (see Interrupt Enable Registers).
TRSR informs the CPU of transmitter and receiver status. Bits
indicated as not used in a particular mode will read as zero, except
for bits [2:0], which may not be zero. The logical-OR of bits [7:3] is
presented in GSR[2] or GSR[6] (ORed with the bits of RSR) for
channels A and B, respectively. Unless otherwise indicated,
asserted status bits are reset only:
1. By performing a write operation to the status register with the bits
to be reset being ones in the accompanying data word [7:3].
2. When the RESETN input is asserted.
3. For [7:4], when a ‘reset transmitter’ command is issued.
4. For [3:0], when a ‘reset receiver’ command is issued.
5. For [2:0], see description in BOP mode.
76543210
GPI1
GPI2
CTS/LC
DCD
Delta
CTS/LC
Delta
DCD
C/T
zero
count
C/T
running Set when the C/T is started by start C/T command and reset when it is stopped by a stop C/T
command.
Set when the counter/timer reaches zero count, or when the bit length measurement is enabled
(CTCR [2:0] = 011) and the RxD input has returned High. The assertion of this bit causes an
interrupt to be generated if CTCR[7] and the channel’s master interrupt enable are asserted.
The DCD input is sampled approximately every 6.8us using the 32X, 4800 baud output from the
BRG. After synchronizing with the sampling clock, at least two consecutive samples at the same
level are required to establish the level. As a consequence, a change of state at the DCD input,
lasting at least 17us, will set this bit. The reset circuitry initializes the sampling circuits so that a
change is not falsely indicated at power on time. The assertion of this bit causes an interrupt to be
generated if the interrupt enable bit and the channel’s master interrupt enable are asserted.
When not in loop mode, the CTS input is sampled approximately every 6.8us using the 32X, 4800
baud output from the BRG. After synchronizing with the sampling clock, at least two consecutive
samples at the same level are required to establish the level. As a consequence, a change of
state at the CTS input, lasting at least 17us, will set this bit. The reset circuitry initializes the
sampling circuits so that a change is not falsely indicated at power on time. The assertion of this
bit causes an interrupt to be generated if the interrupt enable bit and the channel’s master
interrupt enable are asserted.
In SDLC loop mode, this bit is set upon transitions of the LC output. LC is asserted in response
to the ‘go on-loop’ command when the receiver detects a zero followed by seven ones, and
negated in response to the ‘go off-loop’ command when the receiver detects a sequence of eight
ones.
ICTSRx[3] reflects the state of the DCDxN input pin, while ICTSRx[2] reflects the state of
CTSxN. When the bits are 0, the inputs are high, when they are 1, the pins are low. In SDLC
loop mode, bit [2] reflects the state of LC output. Sampling method for the state of these pins
is same as described for bits 4 and 5.
These bits provide the current state of the channel’s general purpose input pins. The bits’
values are latched at the beginning of the read cycle.
Figure 4. ICTSRA (B) Input and Counter/Timer Status Register [All Protocol Modes]
May be reset by writing ‘1’ to this bit position
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 596
76543210
Pattern alternating 01 status. Set when 16 contiguous 10s or 01s are received on RxD.
Pattern all 1s status. Set when 16 1s are received on RxD.
Pattern all 0s status. Set when 16 0s are received on RxD.
Tx path empty status. Set when TxFIFO is empty and last bit of message has been shifted out on TxD line.
Reserved
Reserved
Reserved
Reserved
Figure 5. TRMSRA (B) Transmitter/Receiver Miscellaneous Status Register [All Protocol Modes]
0
1
2
3
4
5
6
7
May be reset by writing ‘1’ to this bit position
Asserted status bits in [7:3] can be programmed to generate an
interrupt. (See Interrupt Enable Registers.)
These registers have bit formats that vary with operating mode of
the channel. Refer to the detailed operation descriptions of ASYNC,
COP, BOP/BOPL modes in Section 3 for individual bit definition.
Input and Counter/Timer Status Register (ICTSRA,
ICTSRB)
This register informs the CPU of status of the counter/timer and
inputs. The logical-OR of bits [6:4] is presented in GSR[3] or
GSR[7] for channels A and B, respectively. Bits [6:4] of the ICTSR
are reset only:
1. By performing a write operation to the ICTSR with a ‘1’ in the bits
to be reset (ones in the accompanying data word).
2. When a Master RESET is issued (bits [7:4] only).
Transmitter/Receiver Miscellaneous Status
Register (TRMSR)
This register provides pattern recognition status bits and Tx path
empty status bit.
Tx Path Empty status bit (bit 3): This bit is set when the last bit of
the data (ASYNC) or FLAG/SYN(SYN) is being shifted out of TxD
while no more characters are in the FIFO or in the transmitter data
path. A ‘1’ written to this bit can clear the status bit. This bit is also
cleared if the Rx RESET or Master RESET is issued.
Tx path is considered empty after at least one character has been
transmitted and TxFIFO and TxSR are empty; in BOP mode, after
the last bit of EOM flag is shifted out; in COP mode, after the last bit
of FCS or last bit of first Mark character; in ASYNCHRONOUS
mode, after last stop bit (1X mode) or last stop bit plus two transmit
clocks (16X mode).
The Tx path empty status bit is not initially set until at least one data
byte has passed through the transmitter path.
Pattern Recognition: The receiver can detect following patterns
and generate interrupt (if enabled by IER3[4]) for the host through
IRQN signal.
Pattern 0 status bit (bit 2): This bit is set when Rx receives 16
contiguous 0s after the pattern recognition is enabled. A ‘1’ written
to this bit can clear the status bit. This bit is also cleared if the Rx
RESET or Master RESET is issued.
Pattern 1 status bit (bit 1): This bit is set when Rx receives 16
contiguous 1s after pattern recognition is enabled. A ‘1’ written to
this bit can clear the status bit. This bit is also cleared if the Rx
RESET or Master RESET is issued.
Pattern alternating 01 status bit (bit 0): This bit is set when Rx
receives 16 contiguous alternating 01 or 10 after pattern recognition
is enabled. A ‘1’ written to this bit can clear the status bit. This bit is
also cleared if the Rx RESET or Master RESET is issued.
Use of the Status Registers
The host may generally keep informed of the CDUSCC’s
communication channel status by one of three methods:
1. Establish a polling loop in software
2. Enabling interrupts by CDUSCC when certain conditions are met
3. For synchronous protocols when DMA transfers are used, enab-
ling the DMA Frame Status Byte (DFSB)
The method chosen depends upon many factors, including:
1. The number of channels to be serviced
2. The data rate of channels
3. The interrupt overhead of the host CPU
4. The amount of buffering interval to the communication channel
5. The non-communication processing requirements on the host
CPU
In a polled system, the host CPU periodically reads the status
registers of devices that may need service. In the CDUSCC, this
register is the GSR. In one read operation, the host may obtain a
summary of all enabled interrupt sources on CDUSCC. If an
interruptible condition exists, the data in GSR will indicate which
other status registers to read to get more detailed information:
1. RSRA or B for receivers
2. TRSRA or B for transmitters and receivers
3. ICTSRA or B for counter timer, modem control or external I/O
4. TRMSRA or B for Tx path empty and pattern recognition
Philips Semiconductors User’s Guide
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1994 Mar 21 597
If no interrupt conditions are seen in the GSR read, the host may
continue the polling loop by reading a status register in another
peripheral device.
INTERRUPTS
Interrupt Driven Systems
Most host CPUs have provision for temporarily suspending
programmed flow and entering a new subprogram called an
“interrupt service routine”. This change of context can occur as a
result of executing a particular instruction or, more normally ,
because an external “interrupt” input has been asserted. Before the
interrupt service routine can be entered, the interrupting device and
the type of interrupt must be determined unambiguously. Three
commonly used methods for making the determination are:
1. In host CPUs with more than one interrupt input, the interrupting
device may be determined by which pin the interrupt arrives on
or as a coded value on these pins.
2. Once the interrupting device is determined, the interrupt details
may be learned by reading the device’s status register(s).
3. The interrupting device and possibly some details of the interrupt
type may be determined by reading the byte or word returned by
a special read cycle called an interrupt acknowledge cycle. This
is commonly called a vectored interrupt system.
CDUSCC supports all these methods through the use of a single,
open drain interrupt request output, general and specific status
registers and the ability to respond to an IACK cycle with an
“interrupt vector”.
Interrupt Control
A single interrupt output (IRQN) is provided which is activated upon
the occurrence of any of the following conditions:
Channel A external or C/T special condition,
Channel B external or C/T special condition,
Channel A Rx/Tx error or special condition,
Channel B Rx/Tx error or special condition,
Channel A TxRDY,
Channel B TxRDY,
Channel A RxRDY,
Channel B RxRDY.
Each of the above conditions occupies a bit in the general status
register (GSR). If ICR[2] is set, the eight conditions are encoded
into three bits which are inserted into bits [2:0] or [4:2] of the
interrupt vector register. This forms the content of the IVRM during
an interrupt acknowledge cycle. Unmodified and modified vectors
can be read directly through specified registers. Two of the
conditions are the inclusive OR of several other maskable
conditions:
- External or C/T special condition: Delta DCD, delta CTS or C/T
zero count (ICTSR[6:4]).
- Rx/Tx error or special condition: Any condition in the Receiver
Status Register (RSR[7:0]) or a transmitter or DPLL condition in the
transmitter and Receiver Status Register (TRSR[7:3]). The TxRDY
and RxRDY conditions are defined by OMR[4] and OMR[3],
respectively.
Also associated with the interrupt system are the Interrupt Enable
Register (IER, IER1, IER2, IER3), one bit in the Counter/T imer
Control Register (CTCR), and the Interrupt Control Register (ICR).
In the default mode, the IER is programmed to enable specified
conditions or groups of conditions to cause an interrupt by asserting
the corresponding bit. A negated bit prevents an interrupt from
occurring when the condition is active and hence masks the
interrupt. In the extended mode, the bits of IER1, 2 and 3 provide
finer resolution of interrupts. Asserting a bit in any of the IERs will
allow the interrupt masked by that bit to cause an interrupt request
(if master interrupt enable is set). In addition to the IER, CTCR[7]
could be programmed to enable or disable an interrupt upon the C/T
zero count condition. The interrupt priorities within a channel are
fixed. Priority between channels is controlled by ICR[7:6]. Refer to
Table 6 (page 604) and ICR[7:6] (Figure 9).
The ICR and IER3 contain the master interrupt enables for each
channel (ICR[1] and ICR[0]) which must be set if the corresponding
channel is to cause an interrupt. The CPU vector mode is specified
by ICR[5:4] which selects either vectored or non-vectored operation.
If vectored mode is selected, the content of the IVR or IVRM is
placed on the data bus when IACK is activated. If ICR[2] is set, the
content of IVRM is output which contains the content of IVR and the
encoded status of the interrupting condition.
The SC26C562, upon receiving the first interrupt acknowledge edge,
locks its current interrupt status until the end of the acknowledge
cycles. Thereafter, the CDUSCC responds as mandated by
ICR[5:4]. As shown in Figure 6, the internal interrupt priorities
within a channel and among channels stabilize during the first
IACKN. The leading edge of the second IACKN locks the interrupt
status and allows the highest IVRM value to be placed on the data
bus. The interrupt status is unlocked with the trailing edge of the
last IACKN. Note that the interrupt request is inhibited during the
IACKN sequence, this means that if the CDUSCC receives an
IACKN sequence and it did not issue an interrupt request, it inhibits
its interrupt request until the last IACKN is received (second IACKN
in mode 0, third IACKN in modes 1 and 2, and trailing edge of
IACKN in mode 3).
The SC68C562, upon receiving an interrupt acknowledge, locks its
current interrupt status until the end of the acknowledge cycle (see
Figure 7). If it has an active interrupt pending, it responds with the
appropriate vector and then asserts DTACKN. If it does not have an
interrupt, it propagates the acknowledge through its X2/IDCN output
if this function is programmed in PCRA[7]; otherwise, the IACKN is
ignored. Locking the interrupt
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 598
Figure 6. SC26C562 Interrupt Acknowledge Sequence (Intel family)
IRQN
IACKN
D7-D0
D7-D0
D7-D0
MODE 0
MODE 1
MODE 2
MODE 3
VECTOR
HIGH IMPEDANCE
00 hex
IRQN
IACKN
HIGH IMPEDANCE
IRQN
IACKN
HIGH IMPEDANCE VECTOR
VECTOR
CD hex 00 hex
D7-D0 VECTOR
HIGH IMPEDANCE
IRQN
IACKN
RDN
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 599
Figure 7. SC68C562 Interrupt Acknowledge Sequence (Motorola family)
CLEARED BY
SOFTWARE
A
A: VECTOR LOCKED ON THE DATA BUS
IRQN
IACKN
D7-D0
DTACKN
status at the leading edge of IACKN prevents a device at a High
position in the interrupt daisy chain from responding to an IACK
issued for a lower priority device while the acknowledge is being
propagated to that device.
CDUSCC Interrupt Modes
There are two major modes of interrupt generation and acknowledge
in CDUSCC: Default and Extended.
The Default Interrupt Mode is fully NDUSCC compatible and is
entered upon reset. The Extended Interrupt Mode is entered by
setting the ‘Extended Interrupt Mask Enable’ bit in the Tx/Rx
Command Register of the Extended register set (TRCR [2]). To
return to the Default Interrupt Mode, TRCR[2] can simply be reset to
‘0’. In the Default Interrupt Mode not every interrupt source has a
unique enable bit. Additionally, in the Default Interrupt Mode several
‘Extended Mode’ interrupt sources are not accessible for interrupt
generation. It is recommended that the Extended Interrupt Mode be
used for all new software development. The Extended Interrupt
Mode provides more capabilities and a much finer level of control
than the Default mode. Functions and controls in Default mode are
not available in Extended mode and vice versa. Each mode
provides a complete and workable interrupt context. Choice of
mode is a matter of selecting how much interrupt support can or
should be moved from the CPU’s interrupt service routine to the
CDUSCC hardware.
The ICR, Interrupt Control Register, and IVR/IVRM, Interrupt Vector
Register (Modified), serve the same function in both modes.
The interrupt enable registers used by the two modes are different
and disjoint as shown in Table 5. Use of the IER is mutually
exclusive of IER1, 2 and 3.
Table 5. Interrupt Modes
Default Extended
IERA,B IER1A,B
IER2A,B
IER3A,B
The interrupt logic in CDUSCC is level sensitive in both Default and
Extended Modes. This means that Interrupt Request (IRQN) will be
asserted as long as a status bit capable of generating an interrupt
remains set, and is gated ‘thru’ the appropriate Interrupt Enable
Register. The interrupt acknowledge cycle does not reset any status
bits. The interrupt service routine software must reset the
appropriate status bit prior to concluding. If an interrupt is pending
while interrupt is in progress on another interrupt, the IRQN line will
remain asserted until the pending interrupt(s) is serviced. Level, not
edge sensitive interrupt controllers, must be used to ensure that no
interrupt requests are lost.
Default Interrupt Mode
This mode provides basic interrupt control and acknowledge for
receivers, transmitters and modem controls. See Figures 9, 10,
12 and 13 for register bit formats and Figure 8 for register
relationships. The transmit and receive status register formats are
also shown for reference. Refer to the mode dependent sections for
details on the bit definitions in these registers. For example, in
Figure 2 GSR[2] is the logical OR of TRSRA[7:3], TRMSRA[3:0]
and RSRA[7:0]. For example, on the A channel an interrupt to the
host will occur:
If Channel ‘A’ Master Interrupt Enable is set (ICR[1]=1)
— AND —
If an Interrupt Enable (Mask) bit is set (IERA[7:0] or ICTSRA[6])
— AND —
A condition exists that will set a status bit in the general status
register ‘A’ channel position (GSR[3:0])
Extended Interrupt Mode
The Extended Interrupt Mode provides an interrupt enable bit for
virtually every status register bit which can indicate an interruptible
condition. Figure 14 shows the relationship between the IER1-3
bits and corresponding bits in the status registers. Also, see Figures
11 through 13.
NOTE: ICR[1:0] and IER3[7] for A and B channels are redundant.
This arrangement allows the master interrupt enables to be written
without resorting to a command to reset the A7 address bit.
Use of the IER1-3 registers is straightforward. Setting an IER bit will
enable generation of an interrupt if the master enable for the
channel is also set. Figure 14 shows the definitions of all the IER
bits for the Extended Interrupt Mode. The register bit descriptions
for IER1 and IER2 which are protocol dependent appear in Section
3 in the context of each protocol.
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 600
C/T C/T ∆∆
X
XXX
RUN = 0 DCD CTS
UNDER CTS FRAME DPLL XXX
RUN UNDER COMP
RUN *
OVR SHORT
**
ERROR FRAME
Transmitter and Receiver Status Register B (TRSRB)
Input & C/T Status Register B (ICTSRB) Receiver Status Register B (RSRB)
Figure 8. Interrupt Control Relationships, Default Mode (TRCR[2] = 0)
FRAME
** **
ICTSRB RSRB
RRDYN
B Channel Interrupt Enable Register (IERB)
(7:6)
(6) ICTSRB
(5:4) TRDYB TRSRB
(7:3) RSRB
(5:4) RSRB
(3:2) RSRB
(1:0) ICTSRA RSRA
RRDYA (7:6)
(6) ICTSRA
(5:4) TRDYA TRSRA
(7:3) RSRA
(5:4) RSRA
(3:2) RSRA
(1:0)
CTCRB (7) A Channel Interrupt Enable Register (IERA)CTCRA (7)
MOD
IVR VECTOR
AND CHAN
ACHAN
B
STATUS ENABL ENABL
Interrupt Control Register (ICR) Master Channel Interrupt
IRQN to CPU
‘B’ RxRDY‘B’ TxRDY
Similar for ‘A’ Channel
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 601
Figure 9. ICR Interrupt Control Register [All Protocol Modes]
76543210
0
0
1
0
— Channel B Master Interrupt Enable —
— Vector Bits to Modify — Selects which bits of the vector stored in the IVR are to be modified to indicate the highest
priority interrupt pending in the CDUSCC. See Interrupt Vector Register.
0
1
— Vector Includes Status — Selects whether the modified (includes status) (IVRM) or unmodified vector (IVR) is
output in response to an interrupt acknowledge (see Interrupt Vector Register).
0
0
0
1
0
1
0Vectored: 8XX86/88 Mode 0. In this mode, the CDUSCC expects two IACKNs. The bus is put in high impedance on the
first IACKN. The vector is output on the second.
— Vector Mode — (Applies to SC26C562) The value of this field determines the response of the CDUSCC when an
interrupt acknowledge sequence occurs: Interrupting bit(s) should not be reset before IACK cycle.
1Vectored: 8080/8085 Mode 1. In this mode, the CDUSCC expects three IACKNs. The bus is put in high impedance on
the first, the vector is output on the second, and on the third IACKN, the CDUSCC places H‘00’ on the data bus.
0
— Channel A Master Interrupt Enable —
1
0
1
1
1
1
1
0
1
Vectored: 8080/8085 Mode 2. In this mode, the CDUSCC expects three IACKNs. A CALL instruction (H‘CD’) is placed
on the data bus during the first, the vector is output on the second, and on the third IACKN, the CDUSCC places H‘00’ on
the data bus.
Non-vectored: Non-vectored mode, mode 3. In this mode, the bus is put in high impedance during any IACKN sequence.
The internal interrupt status is locked while a read of the IVR is performed. As in the vectored mode, interrupts are priori-
tized and if programmed accordingly, the vector is modified.
Channel A: Channel A has the highest priority. The CDUSCC interrupt priorities from highest to lowest are as follows:
A(0), A(1), A(2), A(3), B(0), B(1), B(2), B(3)
— Channel A/B Interrupt Priority — Selects the relative priority between channels A and B. The state of this bit determines the
value of the interrupt vector (see Interrupt Vector Register). The priority within each channel, from highest to lowest, is as follows:
Channel B: Channel B has the highest priority. The CDUSCC interrupt priorities from highest to lowest are as follows: B(0),
B(1), B(2), B(3), A(0), A(1), A(2), A(3)
Interleaved A: Priorities are interleaved between channels, but channel A has the highest priority between events of equal
channel priority. The CDUSCC interrupt priorities from highest to lowest are as follows: A(0), B(0), A(1), B(1), A(2), B(2), A(3),
B(3)
Interleaved B: Priorities are interleaved between channels, but channel B has the highest priority between events of equal
channel priority. The CDUSCC interrupt priorities from highest to lowest are as follows: B(0), A(0), B(1), A(1), B(2), A(2), B(3),
A(3)
0 - Receiver ready
1 - T ransmitter ready
2 - Rx/Tx status
3 - External or C/T status
If an IACKN sequence is received for which there is no interrupt pending, the CDUSCC will place its data bus in 3-State during
each IACKN assertion in modes 0 and I; in mode 2, a call instruction H‘CD’ is placed on the data bus during the first IACKN and it is
placed in 3-State during the other two IACKNs. If an IACKN is received and the sequence is not completed, the next IACKN occur-
rence is considered the sequence continuation.
Modify bits 4:2 of the vector
Modify bits 2:0 of the vector
Modified vector
Unmodified vector
Channel A interrupts are enabled
Channel A interrupts are disabled
Channel B interrupts are enabled
Channel B interrupts are disabled
— For SC68C562 Vector Mode see note at bottom.
NOTE: For 68C562, all three values of bits [5,4]00, 01, 10 will select single vector mode (see next page).
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 602
Vectored Mode (68C562)
Upon interrupt acknowledge, the DUSCC locks its current interrupt
status until the end of the acknowledge cycle. If it has an active
interrupt pending, it responds with the appropriate vector and then
asserts DTACKN. If it does not have an interrupt, it propagates the
acknowledge through its X2/IDCN output if this function is
programmed in PCRA[7]. Otherwise, the IACKN is ignored.
Locking the interrupt status at the leading edge of IACKN prevents a
device at a High position in the interrupt daisy chain from responding
to an IACK issued for a lower priority device while the acknowledge
is being propagated to that device.
Interrupt Enable Register (IERA, IERB)
This register controls whether the assertion of bits in the channel’s
status registers causes an interrupt to be generated. An additional
condition for an interrupt to be generated is that the channel’s
master interrupt enable bit, ICR[0] or ICR[1], be asserted. This
register is used only in Default Interrupt Mode. For extended mode
TRCR[2] is used to disable default mode.
76543210
RSR[1:0]
RSR[3:2]
RSR[5:4]
RSR[7:6]
RxRDY
TRSR[7:3]
TxRDY
DCD/CTS
1 Interrupt generated if bits 1 or 0 of the RSR are asserted
0 Interrupt not enabled
1 Interrupt generated if bits 3 or 2 of the RSR are asserted
0 Interrupt not enabled
1 Interrupt generated if bits 5 or 4 of the RSR are asserted
0 Interrupt not enabled
1 Interrupt generated if bits 7 or 6 of the RSR are asserted
0 Interrupt not enabled
1 Interrupt generated if RxRDY (GSR[0] or GSR[4] for channels A and B respectively) is asserted
0 Interrupt not enabled.
1 Interrupt generated if bits 7, 6, 5, 4 or 3 of the TRSR are asserted
0 Interrupt not enabled
1 Interrupt generated if TxRDY (GSR[1] or GSR[5] for channels A and B respectively) is asserted
0 Interrupt not enabled
1 Interrupt generated if ICTSR[4] or ICTSR[5] are asserted
0 Interrupt not enabled
Figure 10. IERA (B) Interrupt Enable Register [All Protocol Modes]
Philips Semiconductors User’s Guide
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1994 Mar 21 603
76543210
0
1
2
3
4
5
6
7
Reserved
Reserved
Reserved
Reserved
Pattern recognition interrupt enable bit. Interrupt generated if any of the pattern recognitions are set.
RxRDY interrupt enable bit. This bit is ignored while original IER is being used.
TxRDY interrupt enable
Channel master interrupt enable bit. This bit is used as ICR[1] or ICR[0]. A ‘1’ written to this bit
enables the channel master interrupt. Meanwhile, a ‘0’ written to this bit disables the channel master
interrupt. A read operation can tell the current status of master interrupt.
Figure 11. IER1,2,3A (B) Interrupt Enable Register 1,2,3 [All Protocol Modes]
0 – Interrupt not enabled.
1 – Interrupt generated if RxRDY is asserted.
0 – Interrupt not enabled.
1 – Interrupt generated if TxRDY is asserted.
IER3 — Interrupt Enable Register 3. This register is active only when individual
interrupt enable mode is selected, by setting TRCR[2] to ‘1’.
76543210
0
1
2
3
4
5
6
7
Delta DCD detect
Delta CTS detect
DPLL error
Send break ACK
CTS underrun
Tx underrun
Tx frame complete
Tx path empty — Enables interrupt when Tx is enabled, data serialized from TxFIFO has been
transmitted and there is no data in TxFIFO and TxSR.
This register allows user to enable each individual status bit to cause interrupt. Writing ‘1’ in the
bit position will enable this feature. Master interrupt should also be enabled through ICR or IER3.
IER2A (B) Interrupt Enable Register 2
IER1A (B) Interrupt Enable Register 1
76543210
Parity error
Frame error
BRK start
BRK end
Short frame error
Overrun
RTS negated
Character comparison
This register allows user to enable each individual status bit to cause interrupt. Writing ‘1’ in the
bit position will enable this feature. Master interrupt should also be enabled through ICR or IER3.
IER3A (B) Interrupt Enable Register 3
0
1
2
3
4
5
6
7
NOTE: IER1 and 2 are protocol mode sensitive, but they are shown here for illustration purpose.
See Section 3 for protocol dependent features.
Set to 0
Philips Semiconductors User’s Guide
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1994 Mar 21 604
Interrupt Vector Register (IVR) and Modified Vector
Register (IVRM)
Two separate but related registers are used to create vector values
for interrupt vectoring.
The IVR Register can be loaded by the CPU with an 8-bit vector
value. This value will be output on the data bus when the CDUSCC
receives an interrupt acknowledge cycle if the unmodified vector
mode has been selected (ICR[2] = 0). The IVR Register can be
read by the CPU by a bus read cycle at any time, regardless of if an
interrupt is pending or not. The IVR is initialized to ‘0F’ on master
reset.
The IVRM Register will copy the value contained in the IVR
Register, and modify either bits 2:0 or 4:2 to identify the highest
priority interrupt currently active. The vector value is locked at the
beginning of the IACK cycle until the cycle is completed. The vector
in IVRM is not modified if unmodified vector mode has been
selected (ICR[2] = 0), or regardless of the value of ICR[2] if the CPU
has not written an initial vector into the IVR register. The value
contained in the IVRM Register will be output on the data bus when
the CDUSCC issues an interrupt acknowledge cycle if the modified
vector mode has been selected (ICR[2] = 1). The IVRM Register
can be read by the CPU at any time, but will always read as ‘FF’ if
no interrupt is pending. If an interrupt is pending, the actual value of
the IVRM will be read by the CPU. The vector value is locked at the
beginning of the read cycle until the cycle is completed.
If ‘vector includes status’ is specified by ICR[2] = 1, bits [2:0] or [4:2]
(depending on ICR[3]) of the vector are modified as shown in Table
6 to indicate the highest priority interrupt currently active. The
priority is programmable through the ICR. This modified vector is
stored in the IVRM. When ICR[2] = 1, the content of the IVRM is
output on to the data bus on the interrupt acknowledge. The vector
is not modified, regardless of the value of ICR[2], if the CPU has not
written an initial vector into the IVR register.
Either the modified or unmodified vector can also be read by the
CPU via a normal bus read cycle. The vector value is locked at the
beginning of the IACK or read cycle until the cycle is completed.
The contents of IVR may be read by a bus read cycle at any time,
regardless if an interrupt is pending or not. IVRM always reads as
H‘FF’ if no interrupt is pending. If an interrupt is pending, either the
modified (for ICR[2] = 1) or the unmodified (for ICR[2] = 0) vector is
placed on the data bus when reading IVRM.
76543210
If ICR[2] = 0, the content of the IVR register is output on the data bus when the CDUSCC has issued an
interrupt request and the responding interrupt acknowledge (IACKN) is received. On master reset, IVR is
initialized to ‘0F’
Figure 12. IVR Interrupt Vector Register [All Protocol Modes]
76543210
IF ICR[3] = 0
IVRM
[2:0]/[4:2] Highest Priority Interrupt
Condition
000
001
010
011
100
101
110
111
Chan. A receiver ready
Chan. A transmitter ready
Chan. A Rx/Tx status
Chan. A external or C/T status
Chan. B receiver ready
Chan. B transmitter ready
Chan. B Rx/Tx status
Chan. B external or C/T status
Table 6. Interrupt Status Encoding
76543210
Base vector value written
by Host software to IVR
Base vector value written
by Host software to IVR
IF ICR[3] = 1
Base vector value written
by Host software to IVR
NOTE:
If ICR[2] = 0 the value contained in the IVRM is the same as the IVR.
If the CPU has not written an initial vector into the IVR register, the IVRM vector will not be modified and the value contained in the IVRM is ‘FF’.
On Master Reset the value contained in the IVRM is initialized to ‘FF’.
Figure 13. IVRM Interrupt Vector Modified Register [All Protocol Modes]
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 605
C/T ∆∆
XXXX
= 0 DCD CTS/LC
UNDER CTS FRAME DPLL X X X
RUN UNDER COMP
RUN
OVR SHR
CRR FRM
TX FRAME ∆∆
SND DPLL
CTS
TX
PATH COMP DCDCTS OVR SHORT
RUN FRAME
EMPTY ERR
BRK
SOM
UNDER
RUN
UNDER
RUN
Chr
Comp/
EDM
RB/
PAD/
ABORT
BRKE/
IDLE-
TURN BRKS/
SYN
FE/
CRC
ERR PARITY
RCL
Trans & Rcvr Status Reg A/B
Input & C/T Status Register A/B Receiver Status Register A
IER2A/B IER1A/B
TxIDLE
PATTERN
RECOGNITION
TxRDY RxRDY
MASTER
ENABLE
Figure 14. Interrupt Control Relationships, Extended Mode (TRCR[2] = 1)
Generate IRQN
IER3A/B[7] or
IER3A/B[6:4]
from pattern
comp logic
RxRDYTxRDY
Protocol Dependent
Tx
ICRA/B[1:0]
CTCR
[7]
X
DMA CONTROL
DMA Interface
The DMA control section provides the interface to allow the
CDUSCC to operate with an external DMA controller. One of four
modes of DMA can be programmed for each channel independently
via CMR2[5:3]:
- Half-duplex single address. In this mode a single pin provides
both DMA read and write requests. Acknowledgment of the re-
quests is via a single DMA acknowledge pin. The data transfer is
accomplished in a single bus cycle - the DMA controller places the
memory address of the source or destination of the data on the ad-
dress bus and then issues the acknowledge signal, which causes
the CDUSCC to either write the data into its transmit FIFO (write
request) or to output the contents of the top of the receive FIFO
(read request). T ransmit mode is selected by enabling the transmit-
ter and receive mode is selected by enabling the receiver. This
mode can be used when channel operation is half-duplex (e.g. BI-
SYNC) and allows a single DMA channel to service the receiver and
transmitter. The receiver and transmitter should not be enabled at
the same time when half-duplex mode is programmed.
- Half-duplex dual address. In this mode, a single pin provides
both DMA read and write requests. Acknowledgment of the request
is via normal bus read and write cycles. The data transfer requires
two bus cycles - the DMA controller acquires the data from the
source (memory for a Tx DMA or CDUSCC for a Rx DMA) on the
first cycle and deposits it at the destination (CDUSCC for a Tx DMA
or memory for a Rx DMA) on the second bus cycle. This mode is
used when channel operation is half-duplex (e.g., BISYNC) and
allows a single DMA channel to service the receiver and transmitter.
The receiver and transmitter should not be enabled at the same time
when half-duplex mode is programmed.
Table 7. CDUSCC DMA Modes
4 Modes (Select via CMR2 [5:3]
Single
Address Half Duplex 1 Request Pin 1 Acknowledge
Pin
Dual Address Half Duplex 1 Request Pin PGM’d
Acknowledge
Single
Address Full Duplex 2 Request Pin 2 Acknowledge
Pins
Dual Address Full Duplex 2 Request Pin PGM’d
Acknowledge
- Full-duplex single address. This mode is similar to half- duplex
single address mode but provides separate request and
acknowledge pins for the receiver and transmitter.
- Full-duplex dual address. This mode is similar to half- duplex
dual address mode but provides separate request and acknowledge
pins for the receiver and transmitter.
Figures 15 through 18 describe operation of the CDUSCC in the
various DMA environments. Table 7 summarizes pins used for the
Philips Semiconductors User’s Guide
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1994 Mar 21 606
DMA request and acknowledge function for the transmitter and
receiver for the different DMA modes.
The DMA request signals are functionally identical to the TxRDY
and RxRDY status signals for each serial channel except that the
DMA request signals are negated on the leading edge of the
acknowledge cycle when the subsequent transfer causes the FIFO
to become full (transmitter request) or empty (receiver request). In
non-DMA operation, TxRDY and RxRDY signals are automatically
negated only after the transfer is completed.
The DMA read request can be programmed through OMR[3] to be
asserted either when any character is in the receive FIFO or only
when the receive FIFO reaches threshold level. Likewise, the DMA
write request can be programmed through OMR[4] to be asserted
either when the transmit FIFO is not full or only when the transmit
FIFO reaches threshold level. The request signals are automatically
negated when the respective data transfer cycle is completed and
the FIFO becomes full (transmitter request) or empty (receiver
request). If a transfer is completed and the FIFO is not left full
(transmitter) or empty (receiver), the request stays low. The request
may be negated by the CPU with a status reset write cycle.
Although EOPN terminates all DMA transfers, it has no effect on the
requests.
The requests are a function of the FIFO status, but they can be
negated by writing into the GSR. It is recommended that user
should not write to GSR while transmitter or receiver are active.
When the serial channel is not operating in DMA mode, the request
pins for the channel can be programmed for other functions (see pin
descriptions).
DMA (DONEN) EOPN Operation
The DMA completion I/O line is named EOPN for the 26C562 and
DONE for the 68C562. The behavior of this bi-directional pin is
essentially the same for either device. The terms EOPN and DONE
are interchangeably used in the following text.
As an input, EOPN is asserted by the DMA controller concurrent
with the corresponding DMA acknowledge to indicate to the
CDUSCC that the character being transferred into the TxFIFO is the
last character of the transmission frame. In synchronous modes,
the CDUSCC can be programmed through TPR[4] to automatically
transmit the frame termination sequence (e.g., FCS-FLAG in BOP
mode) upon receipt of this signal.
As an output, EOPN is asserted by the CDUSCC under the
following conditions:
a. In response to the DMA acknowledge for a receiver DMA
request if the FIFO’d RECEIVED EOM status bit (RSR[7]) is set
for the character being transferred. In async mode, RSR[7] (=
char. complete) does not assert EOPN.
b. In response to the DMA acknowledge for a transmitter DMA
request if the counter/timer has been programmed to count
transmitted characters and the terminal count has occurred.
If short frame/Abort on DONEN(EOPN) mode is used, a short frame
will set DONE(EOPN) but it will not set EOM flag in status register
(RSR[7]). (See CCR Commands for DMA, Table 13 on page 628.)
DMA Frame Status Byte (DFSB)
In synchronous modes of receive operation with DMA transfers to
the host, the DFSB offers an efficient method of acquiring the
receive status bits for an entire DMA block. The DFSB will allow the
host to obtain status information for a frame in a single byte rather
than reading RSR and TRSR after every character. The DFSB is
accumulated in a register as frames are received. It is updated
frame by frame by logically ORing the present status byte for the
frame into the DFSB. The DFSB, therefore, contains a running
summary of all frame status bytes (see Table 8).
When this mode is enabled by programming TRCR[6] = 1, the DFSB
will be output after the last data character of the block. The status
bits for the last data byte will be attached to that byte except EOM.
Status bits FIFOed with the DFSB byte are ignored except EOM,
Overrun and DPLL error. The byte containing the DFSB will have
the EOM status bit set. The EOPN will not be set until DFSB pops
to the top of the RxFIFO.
An ABORT condition can cause the DMA frame to be closed if CCR
command ‘EDONE’ is used.
If ‘EDONE’ command (Table 13 on page 628) and DFSB are
enabled (TRCR[6] = 1), then an ‘ABORT detect’ condition will push
contents of DFSB into RxFIFO and DFSB will be cleared for next
frame. If DFSB is not enabled (TRCR[6] = 0), a dummy byte is
pushed into RxFIFO. Whenever either the DFSB or dummy byte
pop to the top of the RxFIFO, the DONE(EOPN) signal will be
asserted.
If ‘EDONE’ command is not enabled, a dummy byte is pushed into
the RxFIFO on ‘ABORT detect’ condition irrespective of DFSB
enable or disable (TRCR[6]). If DFSB is enabled, it is not cleared
and its contents are accumulated with next frame.
A ‘short frame’ condition will also cause DFSB to be pushed into
RxFIFO if ‘EDONE’ command and DFSB (TRCR[6]) are enabled.
When DFSB reaches the top of the RxFIFO, it will generate
DONEN(EOPN) signal.
Table 8. DFSB Bit Formats
76543210
COP Reserved PAD error DPLL error OVERRUN
error BCC* error Parity error
Status
Register
Reference RSR[6] TRSR[5] RSR[5] RSR[1] RSR[0]
BOP/BOPL Residual Character Length ABORT DPLL error OVERRUN
error CRC error Short Frame
Status
Register
Reference TRSR[2:0] RSR[6] TRSR[3] RSR[5] RSR[1] RSR[4]
* The BCC error for non-BISYNC COP mode is only valid when EOM is generated due to C/T timeout.
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1994 Mar 21 607
DMAC MEMORY DUSCC
Initiate Request
1. Assert TxDRQN
Acquire Bus
1. Place address on bus
2. Assert AEN
3. Pulse ADSTB
4. Assert MEMRN
5. Assert TxDAKN
Present Data
1. Decode address
2. Place data on D7-D0
Device Response
1. Negate TxDRQN if FIFO full
after this transfer, on falling
edge of TxDAKN
2. Assert EOPN if terminal
count reached.
Terminate Transfer
1. Negate MEMRN, TxDAKN and AEN
Terminate Cycle Terminate Cycle
1. Negate EOPN
2. Latch Data
Relinquish Bus
or
Start Next Cycle
Address Memory
Figure 15. Transmitter DMA Request Operation —
SC26C562 Single Address Mode
DMAC MEMORY DUSCC
Initiate Request
1. Assert RxDRQN
Acquire Bus
1. Place address on bus
2. Assert AEN
3. Pulse ADSTB
4. Assert MEMWN
5. Assert TxDAKN
Present Data
1. Decode address
2. Place data on D7-D0
Acquire Data
1. Decode address
is empty after this transfer,
2. Load Data
Terminate Transfer
1. Negate MEMRN, TxDAKN and AEN
Terminate Cycle Terminate Cycle
1. Negate EOPN
2. Latch Data
Relinquish Bus
or
Start Next Cycle
Address Memory
Figure 16. Receiver DMA Request Operation —
SC26C562 Single Address Mode
3. Assert EOPN if EOM
4. Negate RTxDRQN if FIFO
or terminal count reached
on falling edge of RTxDAKN
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DMAC DUSCC
Initiate Request
1. Assert TxDRQN
Acquire Bus
1. Place address on bus
2. Pulse ADSTB
3. Assert WRN and CEN
4. Place Data on D7-D0
Device Response
2. Negate TxDRQN if FIFO
full after this transfer*
3. Assert EOPN if terminal
count reached
Terminate Transfer
1. Negate WRN and CEN
Terminate Cycle
1. Negate EOPN
2. Latch Data
Relinquish Bus
or
Start Next Cycle
Address CDUSCC
Figure 17. Transmitter DMA Request Operation —
SC26C562 Dual Address Mode
DMAC DUSCC
Initiate Request
1. Assert RxDRQN
Acquire Bus
1. Place address on bus
2. Pulse ADSTB
3. Assert RDN and CEN
Device Response
1. Decode address
2. Place data on D7-D0
Acquire Data
1. Load data
empty after this transfer*
2. Negate RDN and CEN
Terminate Cycle
1. Remove data from bus
2. Negate EOPN
Relinquish Bus
or
Start Next Cycle
Address CDUSCC
Figure 18. Receiver DMA Request Operation —
SC26C562 Dual Address Mode
3. Negate RxDRQN if FIFO is
1. Decode address
Acquire Data From Memory
*On falling edge of CEN or WRN *On falling edge of CEN or RDN
terminal count is reached
4. Assert EOPN if EOM or
2. Release D7-D0
Transfer Data to Memory
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DMAC DUSCC
Initiate Request
1. Assert TxDRQN
Acquire Bus
1. Set RWN to write
2. Place address on bus
3. Assert ASN
4. Place data on D7-D0
5. Assert LDSN or UDSN
Acquire Data
1. Decode register address
2. Load data from D0-D7
full after this transfer*.
Terminate Transfer
1. Negate ASN and LDSN or UDSN
Terminate Cycle
1. Negate DTACKN
Relinquish Bus
or
Start Next Cycle
Address DUSCC
Figure 19. Transmitter DMA Request Operation —
SC68C562 Dual Address Mode
DMAC DUSCC
Initiate Request
1. Assert RxDRQN
Acquire Bus
1. Set RWN to read
2. Place address on bus
3. Assert ASN
4. Assert LDSN or UDSN
Present Data
1. Decode register address
2. Place data on D7-D0
Acquire Data
1. Load data into holding register
2. Negate ASN and LDSN or UDSN
Terminate Cycle
1. Remove data from D0-D7
2. Negate DTACKN
Relinquish Bus
or
Start Next Cycle
Address DUSCC
Figure 20. Receiver DMA Request Operation —
SC68C562 Dual Address Mode
3. Negate RTxDRQN if FIFO is
4. Assert DTACKN
empty after this transfer*
Acquire Data From Memory
3. Negate TxDRQN if FIFO is
4. Assert DTACKN
2. Remove data from D0-D7
Transfer Data to Memory
*On falling edge of CSN *On falling edge of CSN
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DMAC DUSCC
Initiate Request
1. Assert TxDRQN
Acquire Bus
1. Set RWN to read
2. Place address on bus
3. Assert ASN
4. Assert UDSN or LDSN
Device Response
2. Negate TxDRQN if FIFO
is full after this transfer**
Terminate Transfer
1. Assert DTCN
Terminate Cycle
1. Load data
2. Negate DUSCC DTACKN*
Relinquish Bus
or
Start Next Cycle
Address Memory
Figure 21. Transmitter DMA Request Operation —
SC68C562 Single Address Mode
DMAC DUSCC
Initiate Request
1. Assert RxDRQN
Acquire Bus
1. Set RWN to write
2. Place address on bus
3. Assert ASN
Present Data
1. Place data on D7-D0
2. Assert DUSCC DTACKN
Acquire Data
1. Decode address
empty after this transfer**
2. Assert DTACKN
Terminate Cycle
Negate DUSCC DTACKN*
Relinquish Bus
or
Start Next Cycle
Address Memory
Figure 22. Receiver DMA Request Operation —
SC68C562 Single Address Mode
3. Negate RTxDRQN if FIFO is
1. Assert DUSCC DTACKN
*On falling edge of DTCN
MEMORY MEMORY
5. Assert TxDAKN
Present Data
2. Place data on D7-D0
3. Assert DTACKN
1. Decode address
2. Negate ASN and UDSN or LDSN
Terminate Cycle
1. Negate DTACKN
**On falling edge of TxDAKN *On falling edge of DTCN
**On falling edge of TxDAKN
1. Negate TxDAKN and DTCN
4. Assert RTxDAKN
Enable Data
1. Assert UDSN or LDSN
Terminate Transfer
1. Assert DTCN
2. Negate ASN and UDSN or LDSN
Terminate Cycle
1. Load data
2. Negate DTACKN
1. Negate RTxDAKN and DTCN
Philips Semiconductors User’s Guide
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FIFOs
Each channel’ s transmitter and receiver is buffered by a FIFO with a
depth of 16 characters. The FIFO helps to match differences in data
transfer rates between the serial channels and the host interface.
The FIFOs also provide the storage area that makes burst DMA
transfers feasible.
Figure 23. Transmit FIFO Block Diagram
TRANSMITTER
FIFO
16 WORDS
12 BITSTHRESHOLD
REGISTER
COMPARE
CONTROL
CHARACTER
GENERATOR
TRANSMIT
SHIFT
REGISTER
THRESHOLD
LEVEL
FIFO
EMPTY
LEVEL TX
DATA
TX
CMND
TxRDY
TXD TxC
(to pad)
CRC/LRC GEN
SYN1
BUS
SYN2
BUS
LOAD
SYN1
LOAD
SYN2
LOAD
FLAG
LOAD
MARK
LOAD
DLE
LOAD
ABORT
TEOM
TDLE
RESET
CRC
EXCL
CRC
8
8
8
8
8
AB
454
D[7:0] FROM CCR
(SYNC modes only)
TxFIFO
The major blocks associated with the transmitter FIFO are shown in
Figure 23. The TxFIFO is partitioned into words consisting of 8 bits
of character data and 4 bits of command code. The FIFO is 16
words deep. The character data is provided by the host interface or
via a DMA transfer using the D[7:0] data bus. The TxFIFO may be
addressed at any of four consecutive locations (see Table 1) to allow
use of multiple byte/word instructions (however, only one byte is
transferred to the FIFO at a time). A write to any valid address
always writes data to the next empty FIFO location (individual byte
locations cannot be accessed in the TxFIFO).
In synchronous modes, the remaining 4 bits are used to append
transmit command codes to particular data characters.
These 4 bit ‘command codes’ associated with each data byte are
invoked via the Channel Command Register (CCR), Table 13. The
commands associated with each data byte will travel with that data
byte down the FIFO for execution before or after the serialization of
data byte.
The command FIFO is capable of appending more than one
command to a particular data character. A command appended to a
character may be executed before, during or after transmission of
the character. An example of this is EOM appended to the last
character of a message. The last character is transmitted before the
EOM activates closing the frame and the message. Likewise,
exclude CRC command is executed before the appended character.
Refer to Table 13.
TxFIFO output data may be moved to the T ransmit Shift Register
without modification, always the case in the asynchronous mode, or
may be modified or replaced by the Control Character logic. This
logic inserts special characters, i.e., SYN or DLE, to support the
various synchronous protocols.
The character to be transmitted is shifted out, one bit at a time (LSB
first) from the transmit shift register. The TxC, transmitter clock,
selected from numerous sources is the shift clock for the transmit
shift register.
Data Transfer to TxFIFO
The TxRDY flag (GSR[1] or GSR[5] is used to indicate that the
TxFIFO has room to accept data from the host. Initially the TxRDY
does not become valid until the transmitter is enabled. Characters
can be loaded into the TxFIFO prior to the initial enabling of the
transmitter, however this is not recommended, due to the possibility
of writing data to a full TxFIFO which would result in data loss. If
data is transferred to the TxFIFO prior to the initial enabling of the
transmitter, the only indication of space available in the TxFIFO is
via reading the TxFIFO empty level register (TELR). The TxRDY
flag initially becomes valid once the transmitter has been enabled.
The TxRDY flag will remain valid if the transmitter is disabled only if
the TxFIFO was not empty prior to disabling the transmitter. If the
TxFIFO is allowed to become empty while the transmitter is
disabled, the TxRDY flag will again become invalid. When the
TxRDY flag is invalid, the state of the flag is unasserted (0) even
though the TxFIFO is not full.
Once TxRDY is asserted, the CDUSCC does not clear it
automatically until the TxFIFO is full. The host may reset TxRDY by
a status reset write cycle to the GSR. If the host clears the TxRDY
bit, it will re-assert when the TxFIFO threshold criteria is next
satisfied. Due to the possibility of the host resetting the TxRDY
simultaneously with the CDUSCC attempt to set the TxRDY, host
clearing of the TxRDY flag via writing to the GSR is not
recommended if the transmitter is active.
TxFIFO Threshold Criteria
The TxFIFO is always present in the data path as a 16-byte deep
FIFO. The TxRDY assertion can be programmed to occur at any
level (number of empty bytes) in the TxFIFO. The Output and
Miscellaneous Register (OMR) selects which of two threshold
criteria are to be used. TxRDY assertion depends on the state of
OMR[4]:
1. If OMR[4] is 0, TxRDY is asserted whenever there is any space
in the TxFIFO. If it is not reset by the host, TxRDY remains
asserted until the TxFIFO becomes full, at which time it is
automatically negated. If it is reset by the host, it will remain
negated, regardless of the current state of the TxFIFO, until a
new character is transferred to or from the TxFIFO.
2. If OMR[4] is 1, TxRDY is asserted whenever the number of
empty locations in the TxFIFO is equal to or greater than the
threshold level specified in the FIFO Threshold Level Register
(FTLR). If it is not reset by the host, TxRDY remains asserted
until the TxFIFO becomes full, at which time it is automatically
negated. If it is reset by the host, it will remain negated,
regardless of the current state of the TxFIFO, until sufficient
characters are transferred from the TxFIFO to the TxSR so that
the number of empty locations in the TxFIFO is equal to or
greater than the level specified in the FTLR.
CAUTION: Re-setting TxRDY by the host writing to the GSR is not
recommended. See GSR description (page 594).
Philips Semiconductors User’s Guide
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1994 Mar 21 612
The assertion of TxRDY can generate an interrupt if the proper
interrupt enables are set. Refer to the section on Interrupts for
details.
If DMA operation is programmed, either RTxDRQN (half-duplex) or
TxDRQN (full-duplex) follows the state of TxRDY. These operations
differ from normal TxRDY in that the request signal is negated on
the leading edge of the DMA acknowledge write cycle when the
subsequent transfer causes the transmit FIFO to become full, while
the TxRDY signal is negated only after the transfer is completed.
Underrun status TRSR[7] set indicates that one or more data
characters (not PAD characters) have been transmitted and the
TxFIFO and TxSR are both empty.
In ‘wait on Tx’ (CMR2 [5:3] = 101 or 110), a write to a full FIFO
causes the write cycle to be extended until a FIFO position is
available. RDYN (for 26C562) or DTACKN (for 68C562) is asserted
to extend the cycle, and negates when a FIFO position becomes
available. In non wait modes, write to a full FIFO is not allowed.
Data on the top of the TxFIFO may be lost if it is overwritten and no
indication of this occurrence is provided.
The TxFIFO is cleared on Master RESET, or by a reset transmitter
or transmit ABORT/BREAK command. Disabling the transmitter
does not affect the TxFIFO.
RxFIFO
The major blocks associated with the receiver FIFO are shown in
Figure 24.
The RxFIFO is partitioned into words consisting of 8 bits of
character data and 9 bits of status information. The FIFO is 16
words deep. The character data inputs are always from the RxSR,
Receive Shift Register, except at the end of a DMA frame in some of
the synchronous modes. Here, an optional DFSB, DMA Frame
Status Byte,
may be output as the last character of the DMA block. The DFSB is
a running accumulation (logical OR) of all the status bits received
during the DMA block. Refer to the DFSB description or the
BOP/COP detailed operation section for more details.
The status bits for each received character are FIFO’d with the data.
These bits are character count complete indication (all protocol
modes), character compare indication (ASYNC), EOM indication
(BISYNC/BOP), and parity, framing, and CRC errors.
Caution must be exercised when reading RxFIFO and Status
Registers (RSR, TRMSR) back-to-back. For some versions of
CDUSCC of course, it is possible that fast host processor I/O,
meeting the minimum AC timing specifications of CDUSCC, could
attempt to access status information before that information has
been established at the top of the FIFO. Refer to the latest “Device
Variances and Design Cautions” sheet for more information.
Data is loaded into the RxFIFO from the RxSR and extracted (read)
by the host or DMA controller via the data bus. A RxFIFO read
creates an empty RxFIFO position for new data from the RxSR.
RxRDY assertion depends on the state of OMR[3]:
Figure 24. Receive FIFO Block Diagram
RECEIVER
FIFO
16 WORDS
17 BITSTHRESHOLD
REGISTER
COMPARE
WATCHDOG
THRESHOLD
LEVEL
FIFO FILL
LEVEL
TO INTERNAL
DATA BUS
RxRDY
DFSB
RECEIVE STATUS
OTHER
LOAD
RFIFO
RCVR 1X CLOCK
ABORT DET.
8
AB
45
9
READ
RFIFO
SELECT NEW FIFO STATUS
RSR TRSR
OUT
CLK
CLR
TO INTERNAL DATA BUS
MUX
8 8
RECEIVE
STATUS
RECEIVE SHIFT REGISTER DFSB ACCUMULATOR
SELECT
EN
(PE, FE, CRCE, etc)
9
CLR
8
8
AB
S
RX DATA RX STATUS
9REOM
SH FRM DET
DONE ON ABORT
SHORT FRAME
ABORT
SH
FRM EOM
DONE
(To DMA)
3
53
12
RXD (from pad)
RxC
B ≥ A
EOM
BRK DET
MUX
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1994 Mar 21 613
1. If OMR[3] is 0 (FIFO not empty), RxRDY is asserted each time a
character is transferred from the receive shift register to the re-
ceive FIFO. If it is not reset by the host, RxRDY remains as-
serted until the receive FIFO becomes empty, at which time it is
automatically negated. If it is reset by the host, it will remain
negated, regardless of the current state of the receive FIFO, until
a new character is transferred from the RxSR to the RxFIFO, or
WDT is timed out.
2. If OMR[3] is 1 (FIFO full), RxRDY is asserted:
a. When a character transfer from the receive shift register
causes fill level to reach threshold level for RxFIFO.
b. When a character with a tagged EOM status bit is loaded into
the FIFO (BISYNC or BOP) regardless of RxFIFO full condition.
c. When the counter/timer is programmed to count received
characters and the character which causes it to reach zero count
is loaded into the FIFO (ICTSR [6]).
d. When the beginning of a break is detected in ASYNC mode
regardless of the RxFIFO full condition.
e. When WDT times out.
If it is not reset by the host, RxRDY remains asserted until the FIFO
becomes empty, at which time it is automatically negated. If it is
reset by the host, it will remain negated regardless of the current
state of the receive FIFO, until it is asserted again due to one of the
above conditions.
CAUTION: Re-setting TxRDY by the host writing to the GSR is not
recommended. See GSR description (page 594).
The assertion of RxRDY causes an interrupt to be generated if
IER[4], IER3[5] and the channel’s master interrupt enable (ICR[0],
ICR[1], or IER3[7]) are asserted.
When DMA operation is programmed, the RxRDY status bit is
routed to the DMA control circuitry for use as the channel receiver
DMA request. Assertion of RxRDY results in assertion of
RTxDRQN output.
Several status bits are appended to each character in the RxFIFO.
When the FIFO is read, causing it to be ‘popped’, the status bits
associated with the new character at the top of the RxFIFO are
logically ORed into the RSR. Therefore, the user should read RSR
before reading the RxFIFO in response to RxRDY activation. If
character-by-character status is desired, the RSR should be read
and cleared each time a new character is received. The user may
elect to accumulate status over several characters or over a frame
by clearing RSR at appropriate times.
In ‘wait of Rx’ mode, a read of empty FIFO causes the read cycle to
be extended until a character is available in the FIFO. RDYN (for
26C562) or DTACKN (for 68C562) is asserted to extend the cycle.
If wait mode as specified in CMR2[5:3] is not being used, a read of
empty RxFIFO is not allowed.
In all protocol modes, the CDUSCC protects the contents of the
FIFO and the RxSR from overrun. If a character is received while
the FIFO is full and a character is already in the RxSR waiting to be
transferred into the FIFO, the overrunning character is discarded
and the OVERRUN status bit (RSR[5]) is asserted. If the
overrunning character is an end-of-message character, the
character is lost but the FIFO’d EOM status bit will be asserted
when the character in the RxSR is loaded into the FIFO.
The RxFIFO is cleared on master reset, or by a reset receiver
command. Disabling the receiver does not effect the RxFIFO,
RxRDY or DMA request operations.
The FIFO Level Registers
The CDUSCC provides a set of registers that allows reading the
current levels of the Tx and Rx FiFOs. Another register allows users
to control TxRDY and RxRDY generation by comparison of current
FIFO level to a programmable limit. TELR register (Figure 25)
indicates the TxFIFO empty level, RFLR register (Figure 26)
indicates the RxFIFO fill level and FTLR register (Figure 27) is used
to set threshold levels for TxRDY and RxRDY signals.
Philips Semiconductors User’s Guide
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1994 Mar 21 614
76543210
0
0
0
0
000
001
010
011
100
101
110
111
0 characters (TxFIFO full)
1 character
2 characters
3 characters
4 characters
5 characters
6 characters
7 characters
0
0
0
0
1000
001
010
011
100
1
1
1
1
8 characters
9 characters
10 characters
11 characters
12 characters
101
110
111
1
1
1
13 characters
14 characters
15 characters
000 Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000001 16 characters (TxFIFO empty)
TxFIFO Empty Level Register (TELRA,TELRB) indicates the
TxFIFO empty level. A read from this register returns the count
on available empty locations in the channel’s TxFIFO.
Figure 25. TELRA (B) TxFIFO Empty Level Register
[All Protocol Modes]
76543210
0
0
0
0
000
001
010
011
100
101
110
111
0 characters (RxFIFO empty)
1 character
2 characters
3 characters
4 characters
5 characters
6 characters
7 characters
0
0
0
0
1000
001
010
011
100
1
1
1
1
8 characters
9 characters
10 characters
11 characters
12 characters
101
110
111
1
1
1
13 characters
14 characters
15 characters
000
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000001 16 characters (RxFIFO full)
RxFIFO filled Level Register (RFLRA,RFLRB) indicates the
RxFIFO fill level. A read from this register returns the count
on available characters in the channel’s RxFIFO.
Figure 26. RFLRA (B) RxFIFO Filled Level Register
[All Protocol Modes]
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76543210
0
0
0
0
000
001
010
011
100
101
110
111
— RxFIFO Threshold Level — This field controls the RxFIFO threshold level. When RxFIFO is filled to the
threshold level, RxRDY status bit will be asserted.
1 byte (only one space available)
2 bytes
3 bytes
4 bytes (default mode, set by reset)
5 bytes
6 bytes
7 bytes
8 bytes
0
0
0
0
1000
001
010
011
100
1
1
1
1
9 bytes
10 bytes
11 bytes
12 bytes
13 bytes
101
110
111
1
1
1
14 bytes
15 bytes
16 bytes
0
0
0
0
000
001
010
011
100
101
110
111
0
0
0
0
1000
001
010
011
100
1
1
1
1101
110
111
1
1
1
— TxFIFO Threshold Level — This field controls the TxFIFO threshold level. When TxFIFO is emptied below threshold
level, TxRDY status bit will be asserted.
1 character
2 characters
3 characters
4 characters (default mode, set by master reset)
5 characters
6 characters
7 characters
8 characters
9 characters
10 characters
11 characters
12 characters
13 characters
14 characters
15 characters
16 characters
FIFO Threshold Level Register (FTLRA, FTLRB) controls both TxFIFO and RxFIFO interrupt threshold levels.
Figure 27. FTLRA (B) FIFO Threshold Level Register [All Protocol Modes]
TIMERS AND TIMING REGISTERS
Watchdog Timer
The CDUSCC contains a 7-bit ‘watchdog’ timer (WDT) for each
receiver channel. If the RxFIFO threshold criteria have not been
met, it is possible that data could be left in the RxFIFO with no
indication to the host. This is very likely in asynchronous serial
formats, since no ‘end of message’ identifier exists and the final
characters of the message might be fewer than the RxFIFO
threshold level. In most synchronous formats, the ‘end of message’
identifier will automatically cause assertion of RxRDY regardless of
threshold criteria. [CAUTION: COP protocols with the exception of
BiSync, have no specific end of message identifier.] The WDT can
be used to prevent data remaining in the RxFIFO from becoming
‘stale’.
The WDT functions by counting receiver clock cycles occuring since
the last transaction with the RxFIFO. If 127 consecutive Rx bit times
occur with no RxFIFO transaction, and the RxFIFO is not empty, the
RxRDY status bit will be automatically asserted. The RxRDY may in
turn be used to generate an interrupt or DMA transfer request.
Since the receiver clock (RxC) is the source of the WDT clock, care
should be exercised when external RxC is used (i.e., DCE clock in
synchronous formats). If the RxC is stopped the WDT will never
timeout.
Upon master reset, the WDT is disabled. The WDT operation is
enabled/disabled via the Transmit/Receiver bit 7 (TRCR[7]). If
enabled, the WDT will assert the RxRDY status bit if a timeout
occurs. If interrupts have been enabled for the RxRDY, or if DMA
handshake mode has been selected, the assertion of RxRDY will
cause the interrupt or DMA transaction to occur. The WDT count is
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 616
automatically initialized when a RxFIFO transaction occurs, or a
reset receiver command is issued.
Timing Circuits
The timing block for each channel consists of a crystal oscillator, a
bit rate generator (BRG), a digital phase locked loop (DPLL) and a
16-bit counter/timer (C/T). See Figures 29 and 30.
Crystal Oscillator
The crystal oscillator operates directly from a crystal (normally
14.7456MHz if the internal BRG is to be used) connected across the
X1/CLK and X2 pins with two external capacitors. If an external
clock of the appropriate frequency is available, it may be connected
to the X1/CLK pin, and the X2 pin should be open. This signal is
divided by two to provide the internal system clock (see Figure 28).
The on-chip oscillator circuitry consists of an inverting amplifier and
a feedback resistor which are used to implement a Pierce oscillator
(see Figure 28). The addition of an external crystal and external
capacitance into the feedback loop provides the positive reactance
necessary for oscillation and controls the frequency of oscillation.
The oscillator operates at the frequency of oscillation. The oscillator
operates at the frequency for which the crystal is anti-resonant
(parallel resonant) with the load capacitance across the crystal. The
load capacitance is given by:
CL
((
C
1
C
2) (
C
1
C
2))
Stray
The only difference between “parallel” and “series” crystals is how
they were calibrated. Crystals are calibrated to achieve their
specified frequency either at parallel resonance with a particular
load capacitance, or at series resonance (with no load capacitance).
Crystals which were calibrated at their series resonant frequency will
still operate at parallel resonance in this oscillator, however the
resulting frequency will be slightly higher than the frequency
specified for the crystal.
In general, the oscillator frequency can be adjusted slightly by
trimming the external capacitors, larger capacitors will lower the
oscillators frequency while smaller ones will raise it. The small
errors in frequency, due to using a crystal calibrated at a different
load capacitance than is present in the circuit, are negligible for
typical applications. Reliability is much more important.
For best results, a parallel calibrated crystal should be obtained and
the external capacitors should be adjusted until the total circuit
capacitance matches the capacitance specified for the crystal.
Typical crystal parameters:
Frequency — 2–16MHz
Mode of operation — parallel resonant, fundamental mode
Load Capacitance (CL) — 12–32pF
For operation at nominal frequency, the values recommended below
will give accurate, reliable results. The frequency will vary slightly,
depending on the amount of stray capacitance in the individual
circuit, but will typically be off no more than 0.01%.
C1 = C2 = 24pF
Y1 = Saronix NYP147-20; 14.7456MHz at
CL = 20pF with RS = 25Ω.
Using An External Clock Source
Some designs may have an external clock source available and do
not need to use the on-chip oscillator. In this case, the external
clock should be applied to the X1/CLK pin.
Theoretical Information on CDUSCC Crystal Oscillator
The information contained in Table 7 of SC26C562 is based on
computer simulations over the expected process range and actual
device testing at room temperature.
Bit Rate Generator
The BRG operates from the oscillator or external clock and is
capable of generating 19 bit rates. These are available to the
receiver, transmitter, DPLL, and C/T. The BRG output is at 32X the
base bit rate. Since all nineteen rates are generated simultaneously,
each receiver and transmitter may select its bit rate independently.
The transmitter and receiver timing registers include a 4-bit field for
this purpose
(TTR[3:0], RTR[3:0]).
Bit rates of 14.4k, 56k and 64k are available on CDUSCC only. To
make these rates available, TRCR[1], Tx/Rx command registers
must be set. On reset, these rates are not available. TTR[3:0]
control bits can be used to select these rates. Refer to T ransmit
T iming Register for selection details.
Figure 28. Providing an X1/CLK Source
+5V
470Ω
X1
X2
CLK
OPEN
a. Driving X1 From an External Source
÷2
CDUSCC
TO REST
OF DEVICE
X1
X2
b. Using the Crystal Oscillator
TO DTAK CIRCUIT
NOTE: Pull-up resistor is not required if clock driver has CMOS levels.
Figure 29. Transmitter Clock Sources
TX
TRANSMITTER
CLOCK
MUX
000
001
011
010
110 (1X)
111 (16X)
101 (16X)
100 (1X)
CLK
EXT
CLK
MUX
÷2
÷2
÷2
BRG
DPLL
C/T
(SAME CHAN)
C/T
(OTHER CHAN)
32X
1X
32X
32X
16X
or 1X
16X
16X
or 1X
or 16X
1X
PCR[2:0]=000
PCR[4:3]=00
TTR[7]
PIN RTxC
PIN TRxC
TTR[6:4]
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1994 Mar 21 617
Figure 30. Receiver Clock Sources
RX
RECEIVER
CLOCK
MUX
000 (1X)
001 (16X)*
010*
011* CLK
EXT
CLK
MUX
÷2
BRG
C/T
32X
32X
32X
16X
1X
16X or 1X
PCR[2:0]=000
PCR[4:3]=00
RTR[7]
PIN RTxC
PIN TRxC
RTR[6:4]
*ASYNC MODE ONLY
÷216X
DPLL
DPLL
CLOCK
MUX
111
110
101
100
32X
32X
32X
÷2
64X
X1/CLK
Clock Selection Circuits
Transmitter
The selection control for the transmitter clock is shown in Figure 29.
Receiver
Clock selection circuitry for the receiver is shown in Figure 30.
DPLL (Digital Phase-Locked Loop) Operation
Digital Phase-Locked Loop
Each channel of the CDUSCC includes a DPLL used in
synchronous modes to recover clock information from a received
data stream. The DPLL is driven by a clock at nominally 32 times
the data rate. This clock can be programmed via RTR (7:4), to be
supplied from an external input, from the receiver BRG, from the C/T
or directly from the crystal oscillator.
Table 9. NRZI Mode Count Length
Count When
Transition
Detected
Count Length
Adjustment
Counter Reset
After Count
Reaches
0-7 -2 29
8-15 -1 30
16-23 +1 32
24-30 +2 33
None Detected 0 31
The DPLL uses this clock, along with the data stream to construct a
data clock which may then be used as the CDUSCC receive clock,
transmit clock, or both. The output of the DPLL is a square wave at
1X the data rate. The derived clock can also be programmed to be
output on a CDUSCC pin, only the DPLL receiver output clock is
available at the TRxC pin. Four CCR commands are associated
with DPLL operation: Enter search mode, set FM mode, set NRZI
mode, and disable DPLL. The commands are described in the
channel command register description (See Table 13.).
W aveforms associated with the DPLL are illustrated in Figure 34.
If DPLL is selected as receiver clock (RTR[6]) and transmitter clock
(RTR[6:4]), transmitter clock is free-running until receiver enters the
search mode and finds a transition. After receiver clock has been
established, transmit clock will synchronize with it. Master Reset
disables the DPLL and sets it to NRZI mode.
Table 10. FM Mode Count Length
Count When
Transition
Detected
Count Length
Adjustment
Counter Reset
After Count
Reaches
8-15 -1 30
16-23 +1 32
24-7 Disabled
None Detected 0 31
DPLL NRZI Mode Operation
This mode is used with NRZ and NRZI data encoding. With this
type of encoding, the transitions of the data stream occur at the
beginning of the bit cell. The DPLL has a six bit counter which is
incremented by a 32X clock. The Enter Search Mode command
sets the counter to 16 and forces the DPLL clock output to zero.
The first edge detected during search mode begins operation. The
DPLL output clock then rises at a count of 0 and falls at 16. Data is
sampled on the rising edge of the clock. When a transition in the
data stream is detected, the count length is adjusted by one or two
counts, depending on the counter value when the transition occurs
(see Table 9). A transition detection at the roll-over point (third
column in Table 9) is treated as a transition occurring at zero count.
The count length adjustments cause the rising edge of the DPLL
output clock to converge to the nominal center of the bit cell. In the
worst case, which occurs when a DPLL pulse is coincident with the
data edge, the DPLL converges after 12 data transitions.
For the DPLL to start up correctly, a pre-frame synchronizing pattern
needs to be sent. For NRZ encoded data, a stream of alternating
ones and zeros should be used and for NRZI encoded data, a
stream of zeros should be used.
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1994 Mar 21 618
76543210
0
00
0
RTxC Pin
TRxC Pin
0
1
0
11x external
16x external
0
0
1
1
0
1
DPLL
BRG
1
1
0
0
0
1
1
1
1
1
0
1
2x other channel C/T
32x other channel C/T
2x own channel C/T
32x own channel C/T
TRCR[1] = 0 TRCR[1] = 1 *
Bit Rate Bit Rate
50 14.4k
75 56k
110 64k
134.5 134.5
150 150
200 200
300 300
600 600
1050 1050
1200 1200
2000 2000
2400 2400
4800 4800
9600 9600
19.2k 19.2k
38.4k 38.4k
Table 11. Transmitter Baud Rates
— Bit Rate Select — This field selects an output from the bit rate generator to be used by the transmitter
circuits. The actual frequency output from the BRG is 32X the bit rate shown in Table 11. The BRG
output is divided by two before being applied to the transmitter clock multiplexer (see Figure 29). With a
crystal or external clock of 14.7456 MHz the bit rates are as given in Table 11.
111 Internal clock from the counter/timer of own channel. The C/T should be programmed
to produce a clock at 32X the shift rate.
110 Internal clock from the counter/timer of own channel. The C/T should be
programmed to produce a clock at 2X the shift rate.
101Internal clock from counter/timer of other channel. The C/T should be programmed to
produce a clock at 32X the shift rate.
100Internal clock from counter/timer of other channel. The C/T should be programmed to
produce a clock at 2X the shift rate.
011 Internal clock from the bit rate generator at 32X the shift rate. The clock signal is
divided by two before use in the transmitter which operates at 16X the baud rate. Rate
selected by [3:0].
010Internal clock from the phase locked loop at 1X the bit rate. It should be used only in
half-duplex operation since the DPLL will periodically re-sync itself to the received data if
in full-duplex operation. DPLL clock source is passed to Tx even if DPLL is disabled.
001External clock from TRxC or RTxC at 16X the shift rate.
000External clock from TRxC or RTxC at 1X the shift (baud) rate.
— T ransmitter Clock Select — This field selects the clock for the transmitter.
— External Source — This bit selects the RTxC pin or the TRxC pin of the channel as the transmitter clock input when [6:4] specifies
external. When used for input, the selected pin must be programmed as an input in the PCR [4:3] or [2:0].
0 External input from RTxC pin.
1 External input from TRxC pin.
0
0
0
0
000
001
010
011
100
101
110
111
0
0
0
0
1000
001
010
011
100
1
1
1
1101
110
111
1
1
1
Figure 31. TTRA (B) Transmitter Timing Register [All Protocol Modes]
* extended mode only
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1994 Mar 21 619
76543210
0
00
0
— [3:0] Bit Rate Select — This field selects an output from the bit rate generator to be used by the
receiver circuits. The actual frequency output from the BRG is 32X the bit rate shown in Table 12. The
BRG output is divided by two before being applied to the receiver clock multiplexer (see Figure 30).
With a crystal or external clock of 14.7456MHz, the bit rates are as given in Table 12.
RTxC
TRxC
0
1
0
11x external
16x external (ASYNC only)
0
0
1
1
0
1
BRG (ASYNC only)
C/T of channel (ASYNC only)
1
1
0
0
0
1
1
1
1
1
0
1
DPLL, source = 64 X1/CLK
DPLL, source = 32 external
DPLL, source = 32x BRG
DPLL, source = 32x C/T
— Receiver Clock Select — This field selects the clock for the receiver.
111 Internal clock from the digital phase locked loop. The clock for the DPLL is a 32X
clock from the counter/ timer of the channel.
110 Internal clock from the digital phase locked loop. The clock for the DPLL is a 32X
clock from the BRG. The frequency is programmed by [3:0].
101Internal clock from the digital phase locked loop. The clock for the DPLL is an
external 32X clock from the RTxC or TRxC pin, as selected by [7].
100Internal clock from the digital phase locked loop. The clock for the DPLL is a 64X
clock from the crystal oscillator or system clock input. (The input to the oscillator is
divided by two).
011 Internal clock from counter/timer of own channel. The C/T should be programmed
to produce a clock at 32X the shift rate. Clock is divided by two before use in the
receiver logic. Used for ASYNC mode only.
010Internal clock from the bit rate generator at 32X the shift rate. Clock is divided by
two before use by the receiver logic, which operates at 16X the baud rate. Rate
selected by [3:0]. Used for ASYNC mode only.
001External clock from TRxC or RTxC at 16X the shift rate. Used for ASYNC mode only.
— External Source — This bit selects the RTxC pin or the TRxC pin of the channel as the receiver or DPLL clock input, when [6:4]
specifies external. When used for input, the selected pin must be programmed as an input in the PCR [4:3] or [2:0].
0 External input from RTxC pin.
1 External input from TRxC pin.
000External clock from TRxC or RTxC at 1X the shift (baud) rate.
TRCR[1] = 0 TRCR[1] = 1
Bit Rate Bit Rate
50 14.4k
75 56k*
110 64k*
134.5 134.5
150 150
200 200
300 300
600 600
1050 1050
1200 1200
2000 2000
2400 2400
4800 4800
9600 9600
19.2k 19.2k
38.4k 38.4k
Table 12. Receiver Baud Rates
0
0
0
0
000
001
010
011
100
101
110
111
0
0
0
0
1000
001
010
011
100
1
1
1
1101
110
111
1
1
1
Figure 32. RTRA (B) Receiver Timing Register [All Protocol Modes]
*–A vailable in extended mode.
Should not be used in ASYNC.
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 620
Figure 33. Counter/Timer Clock Sources
C/T
CLOCK
MUX
000
RxD
LOW GATE
PCR[4:3]=00
PCR[2:0]=000
PIN TRxC
PIN RTxC
CTCR[2:0]
C/T
PRESCALER
00
01
10
11
÷1
÷16
÷32
÷64
CTCR[4:3]
001
011
010
100
101
110
111
RxD
÷4
FROM CRYSTAL
OSCILLATOR
RECEIVER RxBRG
32X (BAUD RATE)
TRANSMITTER TxBRG
32X (BAUD RATE)
Rx CHARACTER
COUNT CLOCK
Tx CHARACTER
COUNT CLOCK
CLK
C/T
Figure 34. DPLL Waveforms
101100101
16 0 16 0 16 CLOCK COUNT
16 24 8 24 8 CLOCK COUNT24 8
0 8 24 8 24 CLOCK COUNT82416
NRZ DATA
NRZI DATA
Rx DPLL CLOCK
FM0 DATA
FM1 DATA
Rx DPLL CLOCK
MANCHESTER
DATA
Rx DPLL CLOCK
* Normal data encoding for Asynchronous mode
*
DPLL FM Mode Operation
FM operation is used with FM0, FM1, and Manchester data
encoding. With this type of encoding, transitions in the data stream
always occur at the beginning of the bit cell for FM0 and FM1, or at
the center of the bit cell for Manchester. The DPLL 6-bit counter is
incremented by a 32X clock. The Enter Search Mode command
sets the counter to 16 and forces the DPLL clock output to zero.
The first edge detected during search mode begins operation. The
DPLL receiver clock then rises on a count of 8 and falls on 24. (The
DPLL transmitter clock output falls on a count of 16. It rises on a
count of 0 if a transition has been detected between counts of 16
and 23. For other cases, it rises l/2 count of the 32X input clock
before the zero count is reached.) This provides a 1X clock with
edges positioned at the nominal centers of the two halves of the bit
cell. The transition detection circuit is enabled between counts of 8
and 23, inclusive. When a transition is detected, the count length is
adjusted by one, depending on when the
transition occurs (see Table 10).
If a transition is not detected for two consecutive data bits, the DPLL
is forced into search mode and the DPLL error status bit (TRSR[3])
is asserted. This feature is disabled when the DPLL output, in
addition to being used as the receiver clock, also is used as the
transmitter clock. For the DPLL to start up correctly, a pre-frame
synchronizing pattern needs to be sent. For FM0, a stream of at
least 16 ones should be sent initially. For FM1, a minimum stream
of 16 zeros should be sent and for Manchester encoding the initial
data stream should consist of alternating ones and zeros. For FM0
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 621
format, a separate pre-frame is not necessary if the RxD input is
held marking (receiving logical ‘1’s in FM0) for at least 16 bit times
while the Enter Search Mode command is given and until the arrival
of the first data bit.
Counter/Timers
Each CDUSCC channel has a dedicated counter/timer resource.
The counter/timer, C/T, can be used to generate baud rates, count
external events, count characters received or transmitted. The C/T
value can be preset automatically and read.
Counter/Timer Clock Selection
Clock selection for the Counter/T imers is also available. (See
Figure 33). The TRxC and RTxC pins must be configured as inputs
if they are to serve as a C/T clock source. The C/T clock also allows
divisor 16, 32 or 64 prescaling factor, if desired.
The C/T prescale factor and clock fields are in the CTCR,
Counter/Timer Control Register. Refer to the section on the
Counter/Timer for a description of this register. C/T output is set to
‘0’ at reset.
A block diagram of C/T is shown in Figure 35. The zero detect of
C/T can be used to generate an interrupt or be used to provide a
clock source for the receiver and transmitter.
Counter/Timer Control and Value Registers
There are five registers in this set, the format of each is shown
below. The control register contains the operational information for
each counter/timer. The preset registers contain the count which is
loaded into the counter/timer circuits. The last two registers contain
the current value of the counter/timer as it operates.
Counter/Timer Operation
Once the registers associated to the Counter/T imer have been
loaded, operation of C/T is controlled via Command Register (CCR)
explained in Table 13. A typical sequence of operation is as
follows:
– program CTCR
– load CTPRH
– load CTPRL
– CPRES (preset load) command via CCR register
– CSTRT (C/T Start) command via CCR register
Counter/Timer Example
A frequent use of the C/T is to generate non-standard baud rates. It
it is desired to produce an ASYNC protocol baud rate, the C/T must
be programmed to generate a 32x clock rate, as discussed in the
previous section (RTR, TTR). Since a ‘square’ wave is needed,
another factor of 2x must be incorporated. Thus:
CTPR X14
(32) (2) (Baud Rate)
The value CTPR is the 16 bit combination of CTPRH and CTPRL.
With a ‘standard’ X1 frequency (14.7456MHz), the formula simplifies
to:
CTPR 57600
Baud Rate
Figure 35. Counter/Timer Control and Value Registers
PRESET
CTR VALUE
16-BIT
DOWN CTR
RTxC (PIN)
÷N
TRxC (PIN)
X1 ÷ 4
X1 ÷ 4 (GATED)
RxBRG
TxBRG
Rx CHARS
Tx CHARS
CTC[0:2]
CTC[3:4]
CTC[5]
C/T OUTPUT CONTROL TO XMIT/RCVR
CLOCK SELECTION
MULTIPLEXERS
TO TRxC AND
RTxC MULTIPLEXERS
INTERRUPT
LOGIC
ICTSR[6]
C/T ZERO CNT
STATUS BIT
CTC[6]
(ZERO DETECT CNTL)
CTC[7]
ZERO DETECT
INTERRUPT
000
001
010
011
100
101
110
111
Philips Semiconductors User’s Guide
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1994 Mar 21 622
76543210
0
1
0
1
00
01
000
001
010
011
100
101
110
111
— Clock Source — This field selects the clock source for the counter timer.
— Clock Select — This field selects whether the clock selected by [2:0] is prescaled prior to being applied to the input of
the C/T.
— Counter/Timer Output Control - This bit selects the output waveform when the counter/timer is selected to be output on
TRxC or RTxC.
— Zero Detect Control — This bit determines the action of the counter upon reaching zero count.
RTxC pin
TRxC pin
X1/CLK ÷4
X1/CLK ÷ 4 gated
by RxD
Rx BRG
Tx BRG
Rx characters
Tx characters
No prescaling
Divide clock by 16
Square
Pulse
Preset
Continue
10
11 Divide clock by 32
Divide clock by 64
0
1
— Zero Detect Interrupt — This bit determines whether the assertion of the C/T ZERO COUNT status bit (ICTSR[6]) causes an
interrupt to be generated.
Disable
Enable
000RTxC pin. Pin must be programmed as input.
111 Source is the internal signal which transfers characters from the data bus into
the transmit FIFO. When operating in this mode, and if the TEOM on zero count
control bit (TPR[4]) is asserted, the FIFO’d Send EOM command will be
automatically asserted when the character which causes the count to go to zero
is loaded into the transmit FIFO.
110 Source is the internal signal which loads received characters from the receive
shift register into the receiver FIFO. When operating in this mode the FIFO’d
EOM status bit (RSR[7]) will be set when the character which causes the count
to go to zero is loaded into the receive FIFO.
101Source is the 32X BRG output selected by TTR[3:0] of own channel.
100Source is the 32X BRG output selected by RTR[3:0] of own channel.
011 This selects a special mode of operation. In this mode the counter, after
receiving the ‘start C/T’ command, delays the start of counting until the RxD input
goes low. It continues counting until the RxD input goes High, then stops and
sets the C/T zero count status bit. The CPU can use the value in the C/T to
determine the bit rate of the incoming data. The clock is the crystal oscillator or
system clock input divided by four.
010Source is the crystal oscillator or system clock input divided by four.
001TRxC pin. Pin must be programmed as input.
1 The output is a positive pulse each time the C/T reaches zero count. The duration of this pulse is one clock
period. For the same pre-load value, the O/P frequency of the pulse waveform is twice that of square
waveform.
0 The output toggles each time the C/T reaches zero count. The output is cleared to Low by either of the
preset counter/timer commands.
1 The counter/timer continues counting without preset. The value at the next clock edge will be H‘FFFF’.
0 The counter/timer is preset to the value contained in the counter/timer preset registers (CTPRL, CTPRH) at
the next clock edge.
1 Interrupt enabled if master interrupt enable (IER3[7] or ICR[1:0]) is asserted.
0 Interrupt disabled.
Figure 36. CTCRA (B) Counter/Timer Control Register [All Protocol Modes]
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 623
76543210
Most significant bits of counter/timer preset value
— MSB — This register contains the eight most significant bits of the value loaded into the
counter/timer upon receipt of the load C/T from preset register command or when the
counter/timer reaches zero count and the zero detect control bit (CTCR[6]) is set to zero. The
minimum 16-bit counter/timer preset value is H‘0002’.
Figure 37. CTPRHA (B) Counter/Timer Preset Register High [All Protocol Modes]
For CTPRH and CTPRL, 16-bit value may be calculated as follows:
Value when CTCR[5] is 0 =
Value when CTCR[5] is 1 =
Source frequency (CTCR [2 : 0])
desired frequency 2
Source frequency (CTCR [2 : 0])
desired frequency
76543210
Least significant bits of counter/timer preset value
— LSB — This register contains the eight least significant bits of the value loaded into the
counter/timer upon receipt of the load C/T from preset register command or when the
counter/timer reaches zero count and the zero detect control bit (CTCR[6]) is set to zero. The
minimum 16-bit counter/timer preset value is H‘0002’.
Figure 38. CTPRLA (B) Counter/Timer Preset Register Low [All Protocol Modes]
76543210
Most significant bits of
counter/timer value
— MSB — A read of this ‘register’ provides the eight most significant bits of the current value of
the counter/timer. It is recommended that the C/T be stopped via a stop counter command before
it is read to prevent errors which may occur due to the read being performed while the C/T is
changing. This count may be continued after the register is read.
Figure 39. CTHA (B) Counter/Timer Register High [All Protocol Modes]
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 624
76543210
Least significant bits of
counter/timer value
— LSB — A read of this ‘register’ provides the eight least significant bits of the current value of
the counter/timer. It is recommended that the C/T be stopped via a stop counter command before
it is read, in order to prevent errors which may occur due to the read being performed while the
C/T is changing. This count may be continued after the register is read.
Figure 40. CTLA (B) Counter/Timer Register Low [All Protocol Modes]
Figure 41. TRxC and RTxC Function Select
TO RECEIVER CLOCK MUX
TRANSMITTER CLOCK MUX
C/T CLOCK MUX
OUTPUT FROM C/T MUX
(FROM TRANSMITTER CLOCK MUX) TxCLK
(1X BAUD RATE)
(FROM RECEIVER CLOCK MUX) RxCLK
(1X BAUD RATE)
RECEIVER CLOCK MUX
TRANSMITTER CLOCK MUX
C/T CLOCK MUX
FROM CRYSTAL OSC (OSC INPUT FREQ/2)
TO
FROM DPLL OUTPUT 1X (BAUD RATE)
OUTPUT FROM C/T
(FROM TRANSMITTER BRG
(16X BAUD RATE)
(FROM TRANSMITTER CLOCK MUX) TxCLK
(1X BAUD RATE)
(FROM RECEIVER CLOCK MUX) RxCLK
(1X BAUD RATE)
EXTERNAL PIN RTxC
EXTERNAL PIN TRxC
PIN
RTxC
MUX
PIN
TRxC
MUX
00
01
10
11
000
001
010
011
100
101
110
111
(FROM RECEIVER BRG
(16X BAUD RATE)
PCR [4:3]
PCR [2:0]
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 625
I/O AND CLOCK PIN CONFIGURATION
Pin Configuration Register (PCRA, PCRB)
This register selects the functions for multipurpose I/O pins. (See
Figure 41.)
The CDUSCC allows two pins, GPO2/RTSN and RTSN/SYNOUT to
output signals selectable by the PCR, Pin Configuration Register.
This register also controls the TRxC and RTxC function as shown in
Figure 42.
General Purpose I/O
The CDUSCC provides two GPIs, General Purpose Inputs, and two
GPOs, General Purpose Outputs, per channel. The GP I/O pins are
shared with the DMA request and acknowledge pins. If not required
for use by DMA handshake, the GP I/O pins can be user-defined
I/O. The values may always be read as ICTSRA/B[1:0]. When the
ICTSR is read, the values of the GPI inputs are latched to mask any
changes that may occur while the read cycle is in progress.
The GPO2 output must be configured as General Purpose Output
(not RTSN output) before use. The outputs are driven by writing
inverse data into the channel’s OMR[2] bit for GPO2 and/or OMR[1]
for GPO1.
— X2 Configuration — This bit is defined only for Channel A.
— GP02/RTS — The function of this pin is programmable only when not operating in full duplex DMA mode.
— SYNOUT/RTS —
76543210
0
1
0
1
00
01
000
001
010
011
100
101
110
111
— TRxC — If this pin is programmed as an output, the input signal path remains connected and the se-
lected output clock still can be used as a clock input.
Input
XTAL/2
DPLL
C/T
TxCLK BRG 16x
RxCLK BRG 16x
TxCLK 1x
RxCLK 1x
Input
C/T
SYNOUT
RTS
GPO2
RTS
10
11 TxCLK 1x
RxCLK 1x
0
1Internal crystal oscillator used (an external crystal provides the clock)
For 26C562: Internal crystal oscillator not used (an external clock is driven onto X1)
111 The pin is an output for the receiver shift register clock. T ransmitter and Receiver
Parameter and T iming Registers
110 The pin is an output for the transmitter shift register clock.
101The pin is an output for the receiver BRG at 16X the rate selected by RTR[3:0].
100The pin is an output for the transmitter BRG at 16X the rate selected by TTR[3:0].
011 The pin is an output for the counter/timer. Refer to CTCRA/B description.
010The pin is an output for the DPLL output clock.
001The pin is an output from the crystal oscillator divided by two.
000The pin is an input. It must be programmed for input when used as the external
clock input for the receiver or transmitter clock, the DPLL, or the C/T.
— RTxC — If this pin is programmed as an output, the input signal path remains connected and the selected out-
put clock still can be used as a clock input.
11 The pin is an output for the receiver shift register clock.
10 The pin is an output for the transmitter shift register clock.
01 The pin is an output for the counter/timer. Refer to CTCRA/B description.
00 The pin is an input. It must be programmed for input when used as the external clock input
for the receiver or transmitter clock, the DPLL, or the C/T.
1 The pin is a request-to-send output (see Detailed Operation). The logical state of the pin is controlled
by OMR[0]. When OMR[0] is set, the output is low.
0 The pin is an active-low output which is asserted one bit time after a SYN pattern (COP modes) in
HSRH/HSRL or FLAG (BOP modes) is detected in CCSR.The output remains asserted for one receiver
clock period. See Figure 47 for receiver data path.
1 The pin is a request-to-send output (see detailed Operation). The logical state of the pin is controlled by
OMR[0]. When OMR[0] is set, the output is low.
0 The TxDRQN/GP02N/RTSN pin is a general purpose out- put. It is Low when OMR[2] is a 1 and High when
OMR[2] is 0.
NOTE: If an external clock is driven onto X1, PCR[7] is a ‘don’t care’. However, if X2 is grounded when using an external
clock, setting PCRA[7] = 1 will result in much lower power dissipation. In this output (PCRB[7] is a don’t care).
Figure 42. PCRA (B) Pin Configuration Register [All Protocol Modes]
For 68C562: X2 becomes Interrupt Daisy Chain (IDCN) output.
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 626
Output and Miscellaneous Register (OMRA,
OMRB)
This register is used to set the state of various output pins. It also
provides several miscellaneous functions such as Tx, RxFIFO
activation, and Tx residual character length (see Figure 43 for
details).
TxRDY Activate Mode
FIFO not full: The channel’s TxRDY status bit is asserted each time
a character is transferred from the transmit FIFO to the transmit shift
register. If not reset by the CPU, TxRDY remains asserted until the
FIFO is full, at which time it is automatically negated.
FIFO empty: The channel’s TxRDY status bit is asserted when a
character transfer from the transmit FIFO to the transmit shift
register causes the FIFO to become empty. If not reset by the CPU,
TxRDY remains asserted until the FIFO is full, at which time it is
negated.
If the TxRDY status bit is reset by the CPU, it will remain negated
regardless of the current state of the transmit FIFO, until it is
asserted again due to the occurrence of one of the above
conditions.
RxRDY Activate Mode
FIFO not empty: The channel’s RxRDY status bit is asserted each
time a character is transferred from the receive shift register to the
receive FIFO. If not reset by the CPU, RxRDY remains asserted
until the receive FIFO is empty, at which time it is automatically
negated.
FIFO full: The channel’s RxRDY status bit is asserted when a
character transfer from the receive shift register to the receive FIFO
causes the FIFO to become full. If not reset by the CPU, RxRDY
remains asserted until the FIFO is empty, at which time it is negated.
The RxRDY status bit will also be asserted, regardless of the
receiver FIFO full condition, when an end-of-message character is
loaded in the RxFIFO (BOP/BISYNC), when a BREAK condition
(ASYNC mode) is detected in RSR[2], or when the counter/timer is
programmed to count received characters and the character which
causes it to reach zero is loaded in the FIFO (all protocol modes).
(Refer to the detailed operation of the receiver.)
If reset by the CPU, the RxRDY status bit will remain negated,
regardless of the current state of the receiver FIFO, until it is
asserted again due to one of the above conditions.
76543210
0
0
1
0
— RTS —
— RxRDY Activate —
RTS = high. This bit controls TxDRQN/GPO2N/RTSN and RTSN/SYNOUT pin.
RTS = low.
OUT1 = high. This bit controls RTxDRQN/GPO1 output in non-DMA mode.
FIFO not empty: Assert RxRDY each time a character is transferred from RxSR to RxFIFO.
0
1
— OUT2 —
OUT2 = high. This bit controls TxDRQN/GPO2/RTS pin. (in non-DMA mode)
OUT2 = low
0
11 bit
2 bits
0
0
0
1FIFO filled level ≥ threshold level: Assert RxRDY when fill level of RxFIFO reaches threshold level.
0FIFO not full: Assert TxRDY each time a character is transferred to TxSR from TxFIFO.
— TxRDY Activate —
1FIFO empty level ≥ threshold level: Assert TxRDY when empty level of TxFIFO reaches threshold level.
0
— OUT1 —
1OUT1 true = low
0
1
1
1
0
03 bits
4 bits
0
1
0
0
1
10
1
1
1
1
1
5 bits
6 bits
7 bits
Same as TPR[1:0]
— Tx Residual Character Length —
Figure 43. OMRA (B) Output and Miscellaneous Register [All Protocol Modes]
In BOP mode, this field determines the number of bits transmitted for the last character in Information field.
The character in the transmit FIFO accompanied by the FIFOed TEOM command.
The character loaded into the FIFO by the DMA controller if DONEN is simultaneously asserted and TPR[4] is
asserted.
The character loaded into the FIFO which causes the counter to reach zero count when TPR[4] is asserted.
The length of all other characters in the frame’s information field is selected by TPR[1:0]. If this field is 111, the
number of bits in the last character is the same as programmed in TPR[1:0].
(do not modify while Rx is active)
(do not modify while Tx is active)
(do not modify while Tx is active)
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 627
COMMAND REGISTERS
Tx/Rx Command Register (TRCRA/B)
This register is used to enable some of the features of CDUSCC
which were not available in NDUSCC. At initialization the contents
of this register are 00h, that means all the new features are
disabled. To enable one or more of the features, the user must write
‘1’ in the bit location for that feature. Care must be taken when
writing to this register. Writing a ‘0’ in the bit location that was
enabled earlier will disable this feature.
Channel Command Register (CCRA/B)
Dynamic control of the CDUSCC is achieved by issuing ‘commands’
written to the Channel Control Register (CCR). In the sections that
follow, the term ‘command’ will refer to the commands of Table 13
issued via write cycles to the CCR.
Transmitter CCR Commands
These commands are executed by the transmitter either
immediately upon receipt, or are ‘attached’ to the data byte and
FIFO’d for execution at a known time with respect to the data byte
being serialized. Table 13 identifies the commands for the
transmitter, and if these are immediate or FIFO’d in their operation.
Commands to the CDUSCC are entered through the Channel
Command Register. T ransmitter commands are as follows:
TRST – Reset transmitter (00h): Causes the transmitter to cease
operation immediately. The transmit FIFO is cleared and the TxD
output goes into the marking state. Also clears the transmitter
status bits (TRSR[7:4]) and resets the TxRDY status bit (GSR[1] or
GSR[5] for channels A and B, respectively). The counter/timer and
other registers are not affected.
TRCRC – Reset transmit CRC (01h): This command is appended
to and FIFOed along with the next character loaded into the transmit
FIFO. It causes the transmitter CRC generator to be reset to its
initial state prior to beginning transmission of the appended
character.
TENB – Enable transmitter (02h): Enables transmitter operation,
conditioned by the state of the CTS ENABLE Tx bit, TPR[2]. Has no
effect if invoked when the transmitter has previously been enabled.
TDIS – Disable transmitter (03h): Terminates transmitter operation
and places the TxD output in the marking state at the next
occurrence of a transmit FIFO empty condition. All characters
currently in the FIFO, or any loaded subsequently prior to attaining
an empty condition, will be transmitted.
When the transmitter is first enabled, transmission will not begin until
this command (or the transmit SOM with PAD command, see below)
is issued. The command causes the SYN (COP) or FLAG (BOP)
pattern to be transmitted. SEND SOM ACK (TRSR[4]) is set when
transmission of the SYN/FLAG begins. The CPU may then
re-invoke the command if multiple SYN/FLAGs are to be
transmitted. T ransmission of the FIFO characters begins when the
command is no longer re-invoked. If the FIFO is empty,
76543210
0Default mode.
Figure 44. TRCRA (B) Tx/Rx Command Register [All Protocol Modes]
1Enable 7-bit ABORT. Tx sends out 7 1s instead of 8 1s if Tx ABORT command is issued.
0
1Default mode. No new bit rates can be selected.
Three additional new bit rates (14.4k, 56k and 64k) can be chosen through TTR[3:0].
0
1Default mode. No individual interrupt enable mode.
Enable individual interrupt enable mode. In this mode, IER1, IER2 and IER3 are used and original IER is
ignored.
0
1Disable Pattern Recognition alternating 01.
Enable Pattern Recognition alternating 01. This command has the receiver start to hunt for 16 contiguous
alternating 01 or 10. The status bit is shown in TRMR.
0
1Disable Pattern Recognition all 1s.
Enable Pattern Recognition all 1s. This command has the receiver start to hunt for 16 consecutive 1s. The
status bit is shown in TRMR.
0
1Disable Pattern Recognition all 0s.
Enable Pattern Recognition all 0s. This command has the receiver start to hunt for 16 consecutive 0s.
0
1Disable DMA status byte. See detail in DFSB.
Enable DMA status byte. The status byte for the whole frame is FIFOed following last byte of frame while DMA is in progress.
0
1Disable W atch Dog Timer .
Enable Watch Dog Timer. RxRDY is set if no data is loaded into or read from RxFIFO within 127 consecutive bit times while
the RxFIFO filled level is below the threshold level.
NOTES:
– Reset receiver command (CCR) will not reset pattern recognition counter unless pattern recognition is disabled first.
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 628
Table 13. Channel Command Register
NOTE: — V alues not defined explicitly in Table 13 are reserved for future use and should not be programmed.
— Back-to-back write to CCR must have delay equal or greater than three X1 clocks between two commands.
PRE = command internally executed before the new data (data loaded in FIFO after this command) is transmitted.
EMPTY = command internally executed after TxFIFO becomes empty.
POST = command internally executed after the transmission of data byte that was loaded in TxFIFO immediately after
this command.
COMMAND DESCRIPTION FIFO’d WHEN FLUSH RESPONSE
reset Tx
reset TxCRC
enable Tx
disable Tx
transmit SOM
transmit SOM with PAD
transmit EOM
transmit ABORT/BREAK
transmit DLE
go active on poll
reset go active on poll
go on-loop
go off-loop
exclude from CRC
NO
YES
NO
NO
NO
NO
YES
NO
YES
YES
--
PRE
--
EMPTY
--
EMPTY
POST
--
PRE
PRE
YES
NO
NO
NO
NO
NO
NO
YES
NO
NO
TRSR[4] SEND SOM ACK
TRSR[4] SEND SOM ACK
TRSR[5] FRAME COMPLETE
TRSR[4] SEND ABORT ACK
TRSR[6] LOOP SENDING
ICTSR[4] LCN → Asserted
ICTSR[4] LCN → Negated
reset Rx
enable Rx
disable Rx
start
stop
preset to FFFF
preset from CTPRH/CTPRL
enter search mode
disable DPLL
set FM mode
set NRZI mode
BRG test
COMMAND
NAME
TRST
TRCRC
TENB
TDIS
TSOM
TSOMP
TEOM
TABRK
TDLE
TXCRC
TGOFL
TGONL
TRGAP
TGAP
RRST
RENB
RDIS
CSTRT
CSTOP
CPFF
CPRES
PSRCH
PNRZI
PFM
PDIS
disable new FIFOed status bits
enable new FIFOed status bits RDFSB
REFSB
include Tx SYN in CRC accum
exclude Tx SYN from CRC accum
Tx PLA test
Rx PLA test
Disable DONE(EOPN) on ABORT/SF
Enable DONE(EOPN) on ABORT/SF
TXSCRC
TISCRC
BRGTEST
DDONE
RTEST
TTEST
EDONE
COMMAND
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
40h
42h
43h
44h
45h
80h
81h
82h
83h
C0h
C1h
C2h
C3h
C5h
C6h
C7h
C8h
C9h
Receiver Commands
Counter/Timer Commands
Test Mode Commands
DMA Commands
DPLL Commands
T ransmitter Commands
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 629
SYN/FLAGs continue to be transmitted until a character is loaded
into the FIFO, but the status bit (TRSR[4]) is not set. Insertion of
SYN/FLAGs between frames can be accomplished by invoking this
command after the frame complete status bit (TRSR[5]) has been
asserted in response to transmission of the end-of-message
sequence.
TSOM – T ransmit start of message (04h): Used in COP and BOP
modes to initiate transmission of a frame after the transmitter is first
enabled, prior to sending the contents of the FIFO. Can also be
used to precisely control the number of SYN/FLAGs at the
beginning of transmission or in between frames. TSOM command
may be issued before or after the transmitter enabled, but it will be
executed when the transmitter is enabled.
TSOMP – Transmit start of message with opening PAD (05h):
Used in COP and BOP modes after the transmitter is first enabled to
send a bit pattern for DPLL synchronization prior to transmitting the
opening SYN (COP) or FLAG (BOP). The SYN/FLAG is sent at the
next occurrence of a transmit FIFO empty condition. Once an
opening SYN/FLAG has been transmitted, the TSOMP command
will be ignored until the transmitter is either reset or disabled and
re-enabled. All characters currently in the FIFO, or any loaded
subsequently prior to attaining an empty condition, will be
transmitted. While the PAD characters are transmitted, the
character length is set to 8 bits, (regardless of the programmed
length), and parity generation (COP), zero insertion (BOP), and
LRC/CRC accumulation are disabled. SEND SOM ACK (TRSR[4])
is set when transmission of the SYN/FLAG begins. The CPU may
then invoke the transmit SOM command if multiple SYN/FLAGs are
to be transmitted.
The TSOM/TSOMP commands, described above, are sampled by
the controller in alternate bit times of the transmitter clock. As a
consequence, the first bit time of a COP/BOP frame will be
transmitted on the TxD pin, after a maximum of three bit times, after
the command is issued. (The additional 1-bit delay in the data path
is due to the data encoding logic.)
TEOM – Transmit end-of-message (06h): This command is
prefixed to the next character loaded into the transmit FIFO. It
causes the transmitter to send the end-of-message sequence
(selected FCS in COP modes, FCS–FLAG in BOP modes) after the
appended character is transmitted. Frame complete (TRSR[5]) is
set when transmission of the FCS begins. This command is also
asserted automatically if the TEOM on zero count or done control bit
(TPR[4]) is asserted, and the counter/timer is programmed to count
transmitted characters when the character which causes the count
to got to zero is loaded into the transmit FIFO. TEOM is not
recognized if the transmitter FIFO is full.
TABRK – Transmit Abort (BOP) /Transmit Break (ASYNC) (07h):
In BOP modes, causes an abort (eight 1s) to be transmitted after
transmission of the character currently in the shift register is
completed. The transmitter then sends MARKs or FLAGs
depending on the state of underrun control (TPR[7:6]). Send
SOM/Abort ack (TRSR[4]) is set when the transmission of the abort
begins. If the command is re-asserted before transmission of the
previous ABORT is completed, the process will be repeated. This
can be used to send the idle sequence. The ‘transmit SOM’
command must be used to initiate transmission of a new message.
In either mode, invoking this command causes the transmit FIFO to
be flushed (characters are not transmitted).
In ASYNC mode, causes a break (space) to be transmitted after
transmission of the character currently in the shift register is
completed. Send break ack (TRSR[4]) is set when the transmission
of the break begins. The transmitter keeps track of character times.
If the command is re-asserted, send break ack will be set again at
the beginning of the next character time. The user can use this
mechanism to control the length of the break in character time
multiples. T ransmission of the break is terminated by issuing a
‘reset Tx’ or ‘disable Tx’ command.
TDLE – Transmit DLE (08h): Used in COP modes only. This
command is appended to and FIFOed with the next character
loaded into the transmitter FIFO. It causes the transmitter to send a
DLE, (EBCDIC H‘10’, ASCII H‘10’) prior to transmitting the
appended character. If the transmitter is operating in BISYNC
transparent mode, the transmitter control logic automatically causes
a second DLE to be transmitted whenever a DLE is detected at the
top of the FIFO. In this case, the TDLE command should not be
invoked. An extra (third) DLE, however, will not be sent if the
transmit DLE command is invoked.
TGAP – Go active on poll (09h): Used in BOP loop mode only.
Causes the transmitter, if it is enabled, to begin sending when an
EOP sequence consisting of a zero followed by seven ones is
detected. The last one of the EOP is changed to zero, making it
another FLAG, and then the transmitter operates as described in the
detailed operation section. The loop sending status bit (TRSR[6]) is
asserted concurrent with the beginning of transmission.
TRGAP – Reset go active on poll (0Ah): Clears the stored ‘go
active on poll’ command.
TGONL – Go on-loop (0Bh): Used in BOP loop mode to control
the assertion of the LCN output. This output provides the means of
controlling external loop interface hardware to go on-loop and
off-loop. When the command is asserted, the CDUSCC will look for
the receipt of a zero followed by seven 1s, at which time it will assert
the LCN output and set the delta DCD/LC status bit (ICTSR[4]).
This allows the CDUSCC to break into the loop without affecting
loop operation. This command must be used to initiate loop mode
operation.
TGOFL – Go off-loop (0Ch): Used in BOP loop mode to control
the negation of the LCN output. This output provides the means of
controlling external loop interface hardware to go on-loop and
off-loop. When the command is asserted, the CDUSCC will look for
the receipt of eight contiguous 1s, at which time it will negate the
LCN output and set the delta DCD/LC status bit (ICTSR[4]). This
allows the CDUSCC to get off the loop without affecting loop
operation. This command is normally used to terminate loop mode
operation.
TXCRC – Exclude from CRC (0Dh): This command is appended
to and FIFOed along with the next character loaded into the transmit
FIFO. It causes the transmitter CRC generator to be disabled while
appended character is being transmitted. Thus, that character is not
included in the CRC accumulation.
TISCRC – Disable/SYN Exclusion from CRC (0Eh): Disable Tx
SYN exclusion from Tx CRC accumulation.
TXSCRC – Enable SYN Exclusion from CRC (0Fh): In this mode,
all of the SYN characters in COP mode will be excluded from
TxCRC accumulation including SYN1, SYN1+SYN2, or DLE+SYN1
in BISYNC XPNT mode.
Receiver Commands
These commands are executed by receiver either immediately upon
receipt, or upon completion of serialization of the data byte currently
in the RxSR. FIFOing of status bits (RDFSB/REFSB) should not be
executed or disabled while receiver is enabled.
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RRST – Reset receiver (40h): Causes the receiver to cease
operation, clears the receiver FIFO, clears the data path, and clears
the receiver status (RSR[7:0]), TRSR[3:0], and either GSR[0] or
GSR[4] for channels A and B, respectively). The counter/timer and
other registers are not affected.
RENB – Enable receiver (42h): Causes receiver operation to
begin, conditioned by the state of the DCD ENABLE Rx bit, RPR[2].
Receiver goes into START, SYN, or FLAG search mode depending
on channel protocol mode. Has no effect if invoked when the
receiver has previously been enabled.
RDIS – Disable receiver (43h): Terminates operation of the
receiver. Any character currently being assembled will be lost.
Does not affect FIFO or any status. While in COP mode, disabling
the receiver does not clear the data path; in all other cases, it does.
RDFSB – Disable new FIFOed status bits (44h): Causes only
those status bits to be FIFOed that were in NDUSCC (default
mode). Other status bits which were not FIFOed in NDUSCC are
still active, but are not FIFOed (i.e., will be set immediately). On
master reset the CDUSCC will be automatically set in this mode
(i.e., equivalent operation to NDUSCC). This mode is not
recommended for new software development.
REFSB – Enable new FIFOed status bits (45h): Causes all
status bits to be FIFOed. Note that since abort detect (BOP/BOPL)
does not have a data byte to “attach” to, a dummy data byte (FFh) is
generated by CDUSCC for status attachment. In BOP/BOPL mode,
TRSR[2:0] are always FIFOed regardless of RDFSB/REFSB setting.
See following Table for specific bits that are FIFOed in this mode.
ASYNC
RSR[7]*Character compare
RSR[5] Overrun
RSR[2] BRK start
RSR[1]*FE
RSR[0]*PE
COP
RSR[7]*EOM
RSR[6] Pad error
RSR[5] Overrun
RSR[1]*LRC/CRC error
RSR[0]*PE
BOP/BOPL
RSR[7]*EOM
RSR[6] ABORT/EOP
RSR[5] Overrun
RSR[4] Short frame
RSR[1]*CRC error
RSR[0]*RCL not zero
TRSR[2:0]*Residual character length
* FIFOed status bits in default (NMOS) mode
In this mode above status bits in RSR and TRSR are not
accumulation (ORed) of all previous status conditions for the current
frame. They are updated with every RxFIFO read and reflect the
status of the current character on top of the RxFIFO.
Caution must be exercised when reading RSR and RxFIFO
back-to-back. For some versions of CDUSCC it is possible that fast
host processor I/O, meeting the minimum AC timing specifications of
CDUSCC, could attempt to access status information before that
information has been established at the top of the FIFO. Refer to
the latest “Device Variances and Design Cautions” sheet for more
information. A delay or NOP is recommended between RxFIFO and
RSR read if its is done back-to-back.
Counter/Timer Commands
These commands are executed immediately by the counter/timer.
Commands to preset the counter/timer should only be issued once
the counter/timer has been stopped.
CSTRT – Start (80h): Starts the counter/timer and prescaler.
CSTOP – Stop (81h): Stops the counter/timer and prescaler. Since
the command may be asynchronous with the selected clock source,
the counter/timer and/or prescaler may count one or more additional
cycles before stopping.
CPFF – Preset to FFFF (82h): Presets the counter timer to
H‘FFFF’ and the prescaler to its initial value. This command causes
the C/T output to go Low. Preset commands should not be issued
while C/T is running.
CPRES – Preset from CTPRH/CTPRL (83h): Transfers the current
value in the counter/timer preset registers to the counter/timer and
presets the prescaler to its initial value. This command causes the
C/T output to go Low. Preset commands should not be issued while
C/T is running.
Digital Phase-Locked Loop Commands
These commands are executed immediately by the DPLL. The
DPLL mode (set FM or set NRZI) should be set prior to entering
search mode.
PSRCH – Enter Search Mode (C0h): This command causes the
DPLL counter to be set to the value 16 and the clock output will be
forced low. The counter will be disabled until a transition on the data
line is detected, at which point it will start incrementing. After the
counter reaches a count of 30, it will reset to zero and cause the
clock output to go from Low to High. The DPLL will then continue
normal operation. This allows the DPLL to be locked onto the data
without pre-frame transitions. This command should not be used if
the DPLL is programmed to supply the clock for the transmitter and
the transmitter is active.
PDIS – Disable DPLL (C1h): Disables operation of the DPLL.
PFM – Set FM Mode (C2h): Sets the DPLL to the FM mode of
operation, used when FM0, FM1, or Manchester (NRZ) is selected
by CMR1[7:6].
PNRZI – Set NRZI Mode (C3h): Sets the DPLL to the NRZI mode
of operation, used when NRZ or NRZI is selected by CMR1[7:6].
Test Modes
The test modes are included to improve the test coverage and
reduce testing time and cost. The results of each test mode are
reported as a serial data stream value output via the TxD/SYNOUT
pins. With knowledge of this value, this mode can assist in board
level diagnostics and self-test.
These commands should only be used for diagnostic purposes as
described in Appendix 3.
BRGTST – BRG Test (C5h):
The BRG test mode may be enabled by writing F5h to the CCRA
(NOTE: Use a general device reset [RESTN or MRR] to remove the
CDUSCC from the BRG test mode).
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TTEST – TxPLA Test Mode (C6h):
This test mode can be enabled by writing C6h to the channel’s CCR.
To disable TxPLA test, a TxRST command must be issued. To test
the PLA, RTxC must be used as the clock and the TRxC can be
used to initialize the PLA test.
RTEST – RxPLA Test Mode (C7h):
This PLA test mode is enabled by writing C7h to the channel’s CCR.
To disable the RxPLA test, an RxRST command can be issued.
RTxC is the clock input and TRxC initializes the test.
DMA Commands
The ability to signal DMA completion on an ABORT or SHOR T
FRAME ERROR (BOP only) is provided by these commands.
These commands should not be issued when receiver is enabled.
DDONE – Disable DONE (EOPN) or ABORT/SHORT FRAME
(C8h): Causes the occurrence of an ABORT status or SHORT
FRAME detect status (BOP) to not generate a DMA completion
signal (DONE or EOPN). This is the mode of operation for
NDUSCC, and is automatically selected following a master reset.
This mode is not recommended for new software development.
EDONE – Enable DONE (EOPN) on ABORT/SHORT FRAME
(C9h): Causes the occurrence of an ABORT status or SHORT
FRAME detect status (BOP) to generate a DMA completion signal
(DONE or EOPN).
TRANSMITTER
Overview
The transmitter of CDUSCC, like any other UART or USART device
consists primarily of a buffered data path followed by a shift register
to serialize the data. In the case of CDUSCC additional capabilities
have been added to meet the specific needs of the various protocols
supported. To minimize confusion, this overview section will not
explicitly describe the subtleties of each of the operating modes.
For clarification of protocol or mode specific operation the user is
directed to section 3 which discusses each supported protocol in
detail.
Transmitter States
Regardless of operating mode (ASYNC or Synchronous) the
CDUSCC transmitter has the ability to be in one of two major states,
the QUIESCENT STATE or the ACTIVE STATE. In synchronous
protocols there is a third major state, the IDLE STATE, which the
transmitter may enter. Figure 46 illustrates the relationship between
these major states. It should be noted that this Figure is greatly
simplified, and that depending upon protocol some of the single
major states of this diagram are actually composed of several
functionally similar, but separate, states. For example, the ‘single’
active state of the diagram reflects five different actual active states
(1-ASYNC, 2-COP, 2-BOP). However, from the user’s point of view
the behavior of the transmitter appears the same, so a single
simplified active state is used in this discussion.
THE USER SHOULD BE AWARE OF THESE
THREE MAJOR STATES, SINCE IT IS NOT
ALWAYS POSSIBLE TO DETERMINE BY
STATUS INFORMATION ALONE EXACTLY
WHAT STATE THE TRANSMITTER IS IN
The QUIESCENT STATE is entered following a power on reset
(POR), transmitter reset command (TxRST) or at the completion of
data transfer (i.e., Tx disabled and TxFIFO empty). Only in the
QUIESCENT STATE can changes be made to the ‘STATIC’ control
registers of the transmitter without the possibility of data loss or
unpredictable results.
The ACTIVE STATE is entered once the transmitter is enabled,
data sent to the TxFIFO, and the serialization process of the TxSR
begun. It should be noted that for synchronous protocols a unique
command is required (via the CCR) to start the serialization process.
Once entered, the ACTIVE STATE is NOT exited until either the Tx
is reset, the TxFIFO and TxSR are empty or CTS (if used) is
de-asserted.
Figure 45. Transmitter Data Path
SPECIAL CHARACTERS:
FLAG, ABORT, DLE,
BREAK, ETC.
MUX
DLE, STX DETECT
TRANSMITTER SHIFT
REGISTER TxSR
Tx LRC/CRC
PARITY
ZERO INSERT
GENERATOR
DATA ENCODER
(1-BIT DELAY
NRZ, NRZI,
FM0, FM1,
MANCHESTER
COP/BOP
TO Tx CONTROLLER
TxD
INTERNAL RxD (NRZ)
BOP
COP/ASYNC
PIN
INTERNAL TxD
TO RECEIVER
MUX
DATA FIFO COMMAND FIFO
S1R S2R
TxFIFO
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DUSCC/CDUSCC Tx Operation
(SYNC Protocols)
Simplified State Diagram
Q = Quiescent
State
– Tx output is ‘MARK’
– Entered on RESET (Tx or MRR)
– Entered on Tx DISABLED
– Entered on CTS de-assertion
(If CTS control enabled)
A = Active State
– Tx output is DATA, FLAG or SYN
– Entered when ready to flow data
– Tx can be ENABLED or DISABLED
– TxFIFO cannot be empty
– CTS flow control (if used) will cause exit to
Q-State if de-asserted
I = IDLE State
– Tx output is FLAG, SYN or MARK
– Entered when TxFIFO becomes empty
– Tx must be ENABLED
– TxFIFO must be empty
– CTS flow control (if used) will cause
exit to Q-State if de-asserted
• IDLE (between frames)
• UNDERRUN (within a frame)
NOTE: This state diagram is very simplified and does not
completely reflect all internal DUSCC states
RESET
START
DATA
FLOW
(TSOM,
TSOMP)
TxFIFO
EMPTY
(TEOM OR
UNDERRUN) DATA TO
TxFIFO
CTS
DE-ASSERTED
(IF USED)
DISABLE Tx
(OR CTS DE-ASSERTED
IF USED)
Figure 46. Transmitter Status
Q
A
I
– TxFIFO can be empty or non-empty
– Tx can be enabled or disabled
•TxFIFO EMPTY
Simply disabling the transmitter WILL NOT cause the CDUSCC to
exit the ACTIVE STATE. In fact, operation of the transmitter in this
fashion (disabled) is a common technique in synchronous protocols
once the frame has been started. Data transfer handshake will
continue even after the transmitter has been disabled once the
ACTIVE STATE has been entered.
Simply disabling the transmitter WILL NOT cause the CDUSCC to
exit the ACTIVE STATE. In fact, operation of the transmitter in this
fashion (disabled) is a common technique in synchronous protocols
once the frame has been started. Data transfer handshake will
continue even after the transmitter has been disabled once the
ACTIVE STATE has been entered.
The IDLE STATE is unique to synchronous protocols. It is entered
when the TxFIFO and TxSR are both empty. If the transmitter is left
enabled while in the IDLE STATE, data flow will resume immediately
(without the need for a CCR command) upon the loading of data into
the Tx data path from the host. Depending upon protocol, data
transfer to the CDUSCC, and CMR set-up parameters, the
CDUSCC can be in the IDLE STATE either during underrun or in
between legitimate frames. Underrun is considered to occur only
while within a frame (i.e., after SOM and before EOM), and is
usually recoverable without data loss only in COP protocols. Line
idle, the time between frames (i.e., after EOM and before SOM) will
never result in data loss since, by definition, there is no data transfer
at this time. Line idle can be with marks or SYN/FLAGs depending
on CMR set-up parameters.
Transmitter Sections
The transmitter of CDUSCC consists of a DATA PATH section and a
CONTROL section. The data path section, illustrated in Figure 45
provides the TxSR with data from any of four possible sources.
These sources are:
– Special character logic (e.g., flag, DLE, break, etc)
– S1R & S2R Registers (e.g., SYN1 & SYN2 patterns)
– TxFIFO (e.g., data from host)
The TxSR shifts out the LSB first, thus right justification of
characters less than eight bits wide must be done by the CPU prior
to sending these characters to the CDUSCC. The output of the
TxSR is routed directly to the data encoder. Additionally the output
of the TxSR is provided to the CRC/LRC/PARITY generation
circuitry. Depending on operating mode selected the appropriate
check code can be multiplexed to the data encoder when required.
In this manner no additional pipeline delay is introduced into the Tx
data path for check code generation.
Transmitter Control
Control of the transmitter can be divided into two categories, static
and dynamic. The static control refers to parameters that once set,
define the transmitter operation, but are not changed ‘on the fly’ as
data is flowing through the transmitter. Dynamic control deals with
conditions that might be required to alter transmitter operation at
times when data is flowing through the transmitter data path.
The static control of the CDUSCC transmitter is achieved by
adjustment to the contents of the registers listed in the following
Table. Setting of bits in these registers will define the protocol, data
rates, clock source, etc for the transmitter. The contents of these
registers should be altered ONLY when the transmitter is disabled
AND in the QUIESCENT STATE, or else unpredictable results can
occur.
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Channel Mode Registers 1 and 2 CMR1, CMR2 Default
SYN1 and SYN2 Registers S1R, S2R Default
T ransmitter Parameter Register TPR Default
T ransmitter Timing Register TTR Default
Pin Configuration Register PCR[5:0] Default
Output and Misc. Register OMR[7:3] Default
Tx/Rx Command Register TRCR Extended
FIFO Threshold Level Register FTLR Extended
Enabling the Transmitter
The transmitter is enabled with the enable transmitter command
(TxENB) via the CCR. If operating in ASYNC modes, the
transmitter will enter the ACTIVE STATE once both the transmitter is
enabled AND data is placed in the TxFIFO. If operating in
SYNCHRONOUS modes, it is also necessary to issue a start
command (TSOM or TSOMP) in addition to enabling the transmitter
and loading the TxFIFO for the transmitter to enter the ACTIVE
STATE. When the disable transmitter command (TxDIS) is issued
and the transmitter is in the ACTIVE STATE, THE TRANSMITTER
CONTINUES TO OPERATE UNTIL THE TxFIFO and TxSR
BECOME EMPTY. It should be kept in mind that enabling or
disabling the transmitter does not directly cause entry or exit of the
ACTIVE or QUIESCENT STATES. The status of the TxFIFO at the
time of (or following) the enable or disable command determines the
state.
TxRDY
TxRDY is the primary indicator for data transfer to the TxFIFO.
When this signal is asserted it signifies that the transmitter is able to
accept additional data into the TxFIFO. TxRDY is the ‘source’ for
other signals used in data transfer handshake. These other signals
are the RTxDRN or TxDRQN lines for DMA transfers and the IRQN
line for interrupts to the CPU. Data should not be written to the
TxFIFO if TxRDY is not asserted. Use of ‘wait on Tx’ mode of CPU
interface or reading the TxFIFO Empty Level Register provide
suitable means by which writing to a full TxFIFO can be averted
(regardless of transmitter state). Writing to the TxFIFO when full
can result in unpredictable transmitter operation and data loss.
Initially the transmitter is in the QUIESCENT STATE and TxRDY
does not become asserted until the transmitter is enabled.
Characters can be loaded into the TxFIFO while the transmitter is in
the QUIESCENT STATE as long as the precautions stated above
are taken to ensure that no attempt is made to load data into a full
TxFIFO. If the FIFO is full when the transmitter is enabled while in
the QUIESCENT STATE, TxRDY will not be asserted until the
condition of TxRDY occurs again.
It is up to the user to select how the TxFIFO will request data from
the CPU via the Output and Misc Register (OMR). Request can be
made as space becomes available in the TxFIFO (FIFO not full –
OMR[4] = 0), or when the TxFIFO empty level is equal to or larger
than the threshold level (FTLR[7:4] while OMR[4] = 1). For clarity in
the following discussion the phrase ‘TxFIFO is available’ will mean
that either the TxFIFO is not full and OMR[4] = 0 or TxFIFO is at or
above threshold and OMR[4] = 1.
TxRDY is asserted when the transmitter is enabled or in the ACTIVE
STATE and the TxFIFO is available. Once asserted TxRDY will not
be reset until the TxFIFO is full.
The CPU may reset TxRDY through a status reset write cycle
(writing a ‘one’ to the TxRDY bit position – GSR[5]). If this is done,
TxRDY will not be asserted until a character is transferred to the
TxSR and the TxFIFO is available. The assertion of TxRDY will
generate interrupt request if both the TxRDY interrupt enable bit and
channel master interrupt enable are set.
NOTE: It is not recommended to reset bits in the GSR by writing
directly to the GSR.
If DMA operation is programmed, either RTxDRQN (half duplex) or
TxDRQN (full–duplex) follows the state of TxRDY regardless of
transmitter being enabled or disabled. These operations differ from
normal TxRDY in that the request signal is negated on the leading
edge of the DMA acknowledge signal when the subsequent transfer
causes the transmit FIFO to become full, while the TxRDY signal is
negated only after the transfer is completed. Underrun status
TRSR[7] set indicates that one or more data characters (not PAD
characters) have been transmitted and the TxFIFO and TxSR are
both empty.
In ‘wait on Tx’ mode, a write to a full FIFO causes the write cycle to
be extended until a FIFO position is available. For 68C562,
DTACKN signal and for 26C562 RDYN signal is asserted to
acknowledge acceptance of the data. In non–wait modes, a write to
the full FIFO is not allowed. In this event, the results are
unpredictable and the transmitter should be reset (TxRST) before
resuming data transmission.
TxRTS Control
If TxRTS CONTROL, TPR[3], is programmed, the channel’s R TS
output is negated six bit times after the last bit (stop bit in ASYNC
MODE) of the last character is transmitted. RTS is normally
asserted and negated by writing to OMR[0]. Therefore, RTS should
be asserted after the transmitter is enabled. Setting of TPR[3]
causes RTS to be negated automatically (if the transmitter is
disabled before the last data character has been shifted out) after all
characters in the transmitter FIFO (if any) are transmitted and five
bit times after the ‘last character’ is shifted out. This feature can be
used to automatically terminate the transmission of a message as
follows:
– Program auto-reset mode: TPR[3] = 1
– Enable transmitter
– Assert RTSN: OMR[0] = 1
– Send message
– Disable transmitter after the last character is loaded into the
TxFIFO
– The last character will be transmitted and OMR[0] will be reset
five bit times after the last bit, causing RTSN to be negated.
The TxD output will remain in the marking state until the
transmitter is enabled again.
The ‘last bit’ in ASYNC is simply the last stop bit of the character. In
BOP and COP, the last character is defined either explicitly by
appending it with TEOM or implicitly through the selection of the
frame underrun control sequence, TPR[7:6] (transmitter parameter
register).
TxCTS Operation
If CTS enable Tx, TPR[2], is set, the CTSN input must be asserted
for the transmitter to operate. Changes in CTSN while a character
is being transmitted do not affect transmission of that character.
However, if the CTSN input becomes negated when TPR[2] is set
and the transmitter is enabled and ready to start sending a new
character, CTS underrun, TRSR[6], is asserted and the TxD output
is placed in the marking (high) state. A CTS underrun does not
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cause the TxFIFO to be flushed. In ASYNC mode, operation
resumes when CTSN is asserted again. In COP and BOP modes,
the transmission of the message is terminated and operation of the
transmitter will not resume until CTSN is asserted and a TSOM or
TSOMP command is invoked. Prior to issuing the command and
re-transmitting the message, the transmitter should be reset, to flush
the TxFIFO.
CTSN ‘asserted/negated’ always refers to the internal CTSN signal
after being sampled by the input sampling circuit (see ICTSR[4]).
After a change-of-state of CTSN is established by the input
sampling circuits (refer to the description of ICTSR[4]), it is sampled
by the Tx controller 1 1/2 bit times before each new character is
serialized out of the Tx shift register. (This is 2 1/2 bits before the
LSB of the new character appears on the TxD pin; there is an
additional 1 bit delay in the transmitter data path due to the data
encoding logic.)
RECEIVER
The receiver data path includes two holding registers, HSRH and
HSRL, an 8-bit character comparison register, CCSR, two
synchronizing flip flops, a receiver shift register, RxSR, the SYN
comparison registers, S1R and S2R, and BISYNC character
comparison logic. The CDUSCC configures this circuitry and
utilizes it according to the mode selected for the channel through the
two mode registers CMR1 and CMR2. For all paths, character data
is assembled according to the character bit count in the RxSR, and
is moved to the RxFIFO with any appended status bits when
assembly is completed. Figure 47 depicts the four data paths
created in the CDUSCC for the various protocols.
Receiver RxFIFO, RxRDY
The receiver converts received serial data on RxD (LSB first) into
parallel data according to the transmission format programmed.
Data is shifted through a synchronizing flip flop and one or more
shift registers, the last of which is the 8-bit receiver shift register
(RxSR). Bits are shifted into the RxSR on the rising edge of each
1X receive clock until the LSB is in RxSR[0]. Hence, the received
character is right justified, with all unused bits in the RxSR cleared
to zero. A receive character length counter generates a character
boundary signal for synchronization of character assembly,
character comparisons, break detection (ASYNC), and RxSR to
RxFIFO transfers (except for BOP residual characters). During
COP and BOP hunt phases, the SYN/FLAG comparison is made
each receive bit time, as are ABORT and IDLE comparisons in BOP
modes.
An internal clock from the BRG, the DPLL or the counter/timer, or an
external 1X or 16X clock may be used as the receiver clock in
ASYNC mode. The BRG or counter/timer should not be used
directly for the receiver clock in synchronous modes, since these
modes require a 1X receive clock that is in phase with the received
data. This clock may come externally from the RTxC or TRxC pins,
or it may be derived internally from the DPLL. Received data is
internally converted to NRZ format for the receiver circuits by using
clock pulses generated by the DPLL.
When a complete character has been assembled in the RxSR, it is
loaded into the receive FIFO with appended status bits. The most
significant data bits of the character are set to zero if the character
length is less than eight bits. In ASYNC and COP modes the user
may select, via RPR[3], whether the data transferred to the FIFO
includes the received parity bit or not. The receiver indicates to the
CPU or DMA controller that it has data in the FIFO by asserting the
channel’s RxRDY status bit (GSR[4] or GSR[0] and, if in DMA
mode, the corresponding receiver DMA request pin.
The RxFIFO consists of sixteen 8-bit holding registers with
appended status bits for character count complete indications (all
protocol modes), character compare indication (ASYNC), EOM
indication (BISYNC/BOP), and parity, framing, CRC errors and other
status bits. Data is loaded into the RxFIFO from the RxSR and
extracted (read) by the CPU or DMA controller via the data bus. A
RxFIFO read creates an empty RxFIFO position for new data from
the RxSR. RxRDY assertion depends on the state of OMR[3]:
1. If OMR[3] is 0 (FIFO not empty), RxRDY is asserted each time a
character is transferred from the receive shift register to the re-
ceive FIFO. If it is not reset by the CPU, RxRDY remains as-
serted until the receive FIFO becomes empty, at which time it is
automatically negated. If it is reset by the CPU, it will remain
negated, regardless of the current state of the receive FIFO, until
a new character is transferred from the RxSR to the RxFIFO.
2. If OMR[3] is 1 (FIFO full), RxRDY is asserted:
a. When a character transfer from the receive shift register
causes RxFIFO to reach threshold levels.
b. When a character with a tagged EOM status bit is loaded into
the FIFO (BISYNC or BOP) regardless of RxFIFO full condition.
c. When the counter/timer is programmed to count received
characters and the character which causes it to reach zero count
is loaded into the FIFO (ICTSR[6]).
d. When the beginning of a break is detected in ASYNC mode
regardless of the RxFIFO full condition.
e. WDT is timed out.
If it is not reset by the CPU, RxRDY remains asserted until the FIFO
becomes empty, at which time it is automatically negated. If it is
reset by the CPU, it will remain negated regardless of the current
state of the receive FIFO, until it is asserted again due to one of the
above conditions. A write operation to GSR register is not
recommended while Rx/Tx are active.
The assertion of RxRDY causes an interrupt to be generated if
IER[4] and the channel’s master interrupt enable (ICR[0]) or ICR[1])
are asserted.
When DMA operation is programmed, the RxRDY status bit is
routed to the DMA control circuitry for use as the channel receiver
DMA request. Assertion of RxRDY results in assertion of
RTxDRQN output.
Several status bits are appended to each character in the RxFIFO.
When the FIFO is read, causing it to be ‘popped’, the status bits
associated with the new character at the top of the RxFIFO are
logically ORed into the RSR. Therefore, the user should read RSR
before reading the RxFIFO in response to RxRDY activation. If
character-by-character status is desired, the RSR should be read
and cleared each time a new character is received. The user may
elect to accumulate status over several characters or over a frame
by clearing RSR at appropriate times. This mode would normally
also be used when operating in DMA mode.
DMA Frame Status Byte: In RxDMA cycle, this status byte can be
loaded into the FIFO following last byte of frame (last byte means
data with EOM status bit set). This byte is updated frame-by-frame
by logical ‘ORing’ of prior status bytes with the present status of the
frame and only used for COP or BOP/BOPL modes while DMA
transfers are in progress. The EOM status (RSR[7]) will not be set
until this byte pops to the top of the FIFO. The DONEN(EOPN) is
asserted while this byte is being read out from RxFIFO.
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 635
DONEN(EOPN) in DFSB Mode:
(i) If ABORT generate DONEN output: ABOR T detect will push
DFSB into FIFO, if DFSB enabled, and then clear DFSB for the
next frame. (No dummy byte for this case.) If DFSB is not
enabled, a dummy byte is pushed into FIFO. Whenever either
the DFSB or dummy byte pops to the top of the RxFIFO, the
DONEN signal will be asserted.
(ii) If ABORT not generate DONEN: No matter whether DFSB is
enabled or not, a dummy byte is always pushed into the FIFO to
indicate the location where the ABORT occurs. DFSB, if
enabled, is not cleared and accumulated with next frame.
(iii)Short frame is similar to ABORT except short frame doesn’t
generate dummy byte. If DFSB and DONE/Short Frame are
enabled, then DFSB is forced into FIFO when short frame occurs
while Rx shift register is enabled. Otherwise no DFSB can be
forced into FIFO.
On the subject of ABORT/DONEN, case (ii) is meant for a default
NMOS compatible mode. If the command has not been set, the
CDUSCC will operate like the existing NMOS. In this case, the
CDUSCC could still use the DFSB without generating DONEN on
ABORT. What the CDUSCC will do when it encounters an ABORT
is simply set the ABORT status bit, reset the receiver and look for
the next frame. The DFSB is not cleared and is accumulating
through the next frame until a closing flag is found. It is important to
point out if this mode is used, the user will see the ABORT bit set in
the DFSB and that means he has at least two frames within the data
buffer he received. The first n–1 frames have been terminated with
an ABORT sequence (n is the total number of frames in the buffer).
In all protocol modes, the CDUSCC protects the contents of the
FIFO and the RxSR from overrun. If a character is received while
the FIFO is full and a character is already in the RxSR waiting to be
transferred into the FIFO, the overrunning character is discarded
and the OVERRUN status bit (RSR[5]) is asserted. If the
overrunning character is an end-of-message character, the
character is lost but the FIFOed EOM status bit will be asserted
when the character in the RxSR is loaded into the FIFO.
Operation of the receiver is controlled by the enable receiver
command. When this command is issued, the CDUSCC goes into
the search for start bit state (ASYNC), search for SYN state (COP
modes), or search for FLAG state (BOP modes). When the disable
receiver command is issued, the receiver ceases operation
immediately, but RxFIFO will retain its contents. The RxFIFO is
cleared on master reset, or by a reset receiver command. However,
disabling the receiver does not affect the RxFIFO, RxRDY, or DMA
request operation.
Receiver DCD Control
If DCD enable Rx, RPR[2], is asserted, the DCD input must be
asserted for the receiver to operate. If RPR[2] is asserted and the
sampling circuit detects that the DCD input has been negated while
a character is being received, the receiver terminates receipt of the
current message (this action, in effect, disables the receiver). If
DCD is subsequently asserted, the receiver will search for the start
bit, SYN pattern, or FLAG, depending on the channel protocol. A
change of state detector is provided on the DCD input of each
channel. The required duration of the DCD level change is
described in the discussion of ICTSR[5]. The user may program a
change of state to cause an interrupt to be generated so that
appropriate action can be taken.
Receiver RTS Control
In ASYNC mode, RPR[4] can be programmed to control the
deactivation of the RTSN output by the receiver. RTSN can be
manually asserted and negated by writing to OMR[0]. However, the
assertion of RPR[4] causes RTS to be negated automatically upon
receipt of a valid start bit if the channel’s receive FIFO is already full
(16 characters). When this occurs, the RTSN negated status bit,
RSR[6], is set. The RTSN will be re-asserted again when RxFIFO
becomes “not full”. This may be used as a flow control feature to
prevent overrun in the receiver by using the RTSN output signal to
control the CTSN input of the remote transmitter. The new character
will be assembled in the RxSR, but its transfer to the FIFO will be
delayed until the CPU reads the FIFO, making the FIFO position
available for the new character.
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 636
Figure 47. Receiver Data Path
BISYNC CHARACTER
COMPARISON LOGIC
P
P
HSRH
S2R
FLAG DETECT
CCSR
S2R
HSRH
S1R
HSRL
ZD (ZERO DELETE)
HSRL
S1R
2 BITS RxSR
CRC/LRC
HSRH HSRL
HSRL
RxSR
RxSR
ZD (ZERO DELETE)
RxSR
S2R S1R
CCSR CRC
FLAG DETECT
DECODER
AND
DEMULTI-
PLEXER
INTERNAL
RxD (NRZ)
1X RCVR CLK
INTERNAL TxD
RxD COP-SINGLE SYN,
DUAL SYN,
BISYNC
BOP WITHOUT CRC
BOP WITH CRC
ASYNC
S1R
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 637
SECTION 3
PROTOCOL DEPENDENT
FEATURES
Philips Semiconductors
ICs for Data Communications
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 638
ASYNC OPERATIONAL MODE
To operate a channel of the CDUSCC in ASYNC Mode, the Channel
Mode Register 1 (CMR1) must specify ASYNC via bits [2:0] = 111.
In ASYNC Mode, the CMR1, CMR2, S1R, TPR, and RPR take on
the bit definitions illustrated in Figures 48 through 56.
Tx ASYNC Mode
When in the active state, serialization will begin when the TxFIFO
data is loaded into the TxSR. The transmitter first sends a start bit,
then programmed number of bits/character (TPR[1:0]), a parity bit (if
specified), and the programmed number of stop bits. Following the
transmission of the stop bits, if a new character is not available in
the TxFIFO, the TxD output goes to marking and the underrun
condition (TRSR[7]) is set. A new character could be unavailable to
the TxSR because of any of three conditions:
– The TxFIFO is empty
– A disable Tx or Reset Tx has been sent to the CCR
– CTS has been de-asserted and CTS enable Tx operation was
selected (TPR[2] is set).
Any of the above conditions will return the transmitter to the
quiescent state.
The T ransmitter re-enters the active state because of either of the
following:
– A new character is loaded into the TxFIFO
– A ‘SEND BREAK’ command (TABRK) is sent to the CCR
While the transmitter is enabled and CTS is asserted (if CTS enable
Tx mode has been selected), the send break command clears the
TxFIFO and forces a continuous space (low) on the TxD output after
the character in TxSR (if any) is serialized. A send break
acknowledge (TRSR[4]) is returned to the CPU to facilitate
re-assertion of the send break command in order to send an integral
number of break characters. The send break condition is cleared
when the reset Tx or disable Tx command is issued.
76543210
00
01
10
11
0
1
00
01
10
11
000
001
010
011
100
101
110
111
— Channel Protocol Mode —
— Parity Mode —
— # Parity —
— Data Encoding —
BOP primary
BOP secondary
BOP loop
BOP loop - no address compare
COP dual SYN
COP dual SYN (BISYNC)
COP single SYN
ASYNC
No parity
Reserved
With parity. Odd or even parity selected by [5].
Force parity. Parity bit is forced to the state selected by [5].
If ‘with parity’ is selected above, a zero in this bit generates even parity; if this bit is a 1, then odd parity is generated.
If ‘force parity’ is selected above, then a 0 will always put a 0 in the parity bit position; a 1 forces a 1 in the parity bit position.
NRZ/Manchester — NRZ mode if DPLL is set to NRZI (default), Manchester if DPLL is set to FM mode. (see CCR)
NRZI — None Return to Zero Inverted.
FM0 — Bi-phase space
FM1 — B-phase Mark
Figure 48. CMR1A (B) Channel Mode Register 1 [ASYNC Mode]
A parity bit is added to the character if ‘with parity’ or ‘force parity’ is selected.
Selects Data Encoding for Rx/Tx.
NOTE: No encoding is supported for ASYNC mode with fractional stop bits selected in TPR[7:4].
Philips Semiconductors User’s Guide
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1994 Mar 21 639
76543210
00
01
10
11
0
000
01
10
11
000
— Frame Check Sequence Select —
— Data Transfer Interface —
— Channel Connection —
None
Reserved – DO NOT USE
Half-duplex, single address DMA
Half-duplex, dual address DMA
Full-duplex, single address DMA
Full-duplex, dual address DMA
Normal
Auto echo
Local loop
Reserved
0
0
1
100
01
10
11
1
1
W ait on Rx only — Read RxFIFO cycle will be selected until data available.
W ait on Tx only — Write TxFIFO cycle will be selected until space available in TxFIFO.
W ait on Rx or Tx — Both of above
Polled or interrupt — Data transfer to the TxFIFO and from RxFIFO are via normal bus cycle.
Figure 49. CMR2A (B) Channel Mode Register 2 [ASYNC Mode]
Reserved – DO NOT USE
Reserved – DO NOT USE
Reserved – DO NOT USE
Reserved – DO NOT USE
Reserved – DO NOT USE
Reserved – DO NOT USE
See DMA operation in Section 2
See W ait Mode in
Section 2
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Channel Mode Register 2 (CMR2A, CMR2B)
Channel Connection
This field selects the mode of operation of the channel. The user
must exercise care when switching into and out of the various
modes. The selected mode will be activated immediately upon
mode selection, even if this occurs in the middle of a received or
transmitted character .
Normal mode: The transmitter and receiver operate independently
in either half- or full-duplex, controlled by the respective enable
commands.
Automatic echo mode: Automatically re-transmits the received
data with a half-bit time delay (ASYNC, 16X clock mode) or a two-bit
time delay (all other modes). The following conditions are true while
in automatic echo mode:
1. Received data is re-clocked and re-transmitted on the TxD out-
put.
2. The receiver clock is used for the transmitter for Async 16X clock
mode. For other modes the transmitter clock must be selected
and supplied through normal methods as described in Section 2.
3. The receiver must be enabled, but the transmitter need not be
enabled.
4. The TxRDY and underrun status bits are inactive.
5. The received parity and/or FCS are checked if required, but are
not regenerated for transmission, i.e., transmitted parity and/or
FCS are as received.
6. In ASYNC mode, character framing is checked, but the stop bits
are re-transmitted as received. A received break is echoed as
received.
7. CPU to receiver communication continues normally, but the CPU
to transmitter link is disabled.
Local loopback mode: In this mode:
1. The transmitter data output and clock are internally connected to
the receiver.
2. The transmit clock is used for the receiver if NRZI or NRZ encod-
ing is used. For FM or Manchester encoding because the re-
ceiver clock is derived from the DPLL, the DPLL source clock
must be maintained.
3. The TxD output is held High.
4. The RxD input is ignored.
5. The receiver and transmitter must be enabled.
6. CPU to transmitter and receiver communications continue nor-
mally.
The above discussion for CMR2 also applies to COP and BOP
modes.
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 640
76543210
Figure 50. S1RA (B) SYN1/Secondary Address Register 1 [ASYNC Mode]
Character compare (5-8 bits)
The value loaded into this register will be compared to the value
clocked into the RxSR. If an exact match occurs, a status bit is set
(RSR[7] in Receiver Status Register (RSR)). The comparison is
always made on entire 8-bit value. If character is received with parity
error (if specified) the comparison will not occur. For characters less
than 8-bits long, the bits should be right justified with the ‘unused’
MSBs set to zero.
The Status is FIFOed and will appear in the RSR when matched
character reaches top of the RxFIFO.
76543210
0
1
00
01
10
11
— Tx Character Length —
— Tx RTS Control —
— Stop Bits Per Character —
5 bits
6 bits
7 bits
8 bits
No
Yes
STOP BIT VALUE
0
1
— CTS Enable Tx —
No
Yes
5 BITS/
1.063
1.125
1.188
1.250
1.313
1.375
1.438
1.500
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
6,7 OR 8
0.563
0.625
0.688
0.750
0.813
0.875
0.938
1.000
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
CHAR BITS/CHAR
0
0
0
0
000
001
010
011
100
101
110
111
0
0
0
0
1000
001
010
011
100
1
1
1
1101
110
111
1
1
1
Figure 51. TPRA (B) Transmitter Parameter Register [ASYNC Mode]
This field selects the number of data bits transmitted per character.
This bit determines if the CTSN input controls the operation of Tx.
This bit controls the de-activation of the RTSN output by the Tx.
This field selects the number of stop bits to be transmitted with each character.
See Tx CTS operation in Section 2
See Tx RTS operation in Section 2
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 641
76543210
0
1
00
01
10
11
— Rx Character Length —
— Strip Parity —
5 bits
6 bits
7 bits
8 bits
No
Yes
reserved (set to zero)
0
1
— DCD Enable Rx —
No
Yes
0
1
— Rx RTS Control —
No
Yes
Figure 52. RPRA (B) Receiver Parameter Register [ASYNC Mode]
This field selects the number of data bits per character to be assembled
by receiver (excluding start, stop and parity bits).
This bit determines if DCD input controls the receiver operation.
This bit controls whether the received parity bit is stripped from the data passed to RxFIFO
(valid for 5, 6, 7 character length).
This bit selects automatic de-assertion of RTSN output upon reception of a start bit when
RxFIFO is full.
See Rx DCD operation in Section 2
See Rx RTS operation in Section 2
Rx ASYNC Mode
When first enabled, the receiver goes into the search for start bit
state, looking for a high-to-low (mark-to-space) transition of the start
bit on the RxD input. If a transition is detected, the state of the RxD
pin is sampled again each 16X clock for 7 1/2 clocks (16X clock
mode) or at the next rising edge of the bit time clock (1X clock
mode). If RxD is sampled High, the start is invalid and the search
for a valid start bit begins again.
If RxD is still Low, a valid start bit is assumed and the receiver
continues to sample the input at one bit time intervals (16 periods of
the 16X Rx clock; one period of the 1X Rx clock) at the theoretical
center of the bit, until the proper number of data bits and the parity
bit (if specified) have been assembled, and the first stop bit has
been detected.
The assembled character is then transferred to the RxFIFO with
appended parity error (if parity is specified) and framing error status
bits. The CDUSCC can be programmed to compare this character
to the contents of S1R. The appended character compare status
bit, RSR[7], is set if the data matches and there is no parity error.
After the stop bit is sampled, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (i.e. framing error) and RxD remains Low for
one-half of the bit period after the stop bit has been received, the
receiver operates as if a new start bit transition (without high-to-low
transition) had been detected.
If a break condition is detected (RxD Low for entire character time
including optional parity and first stop bit), only one character
consisting of all zeros will be loaded into the RxFIFO and break start
detect, RSR[2], will be set. The RxD input must return to a High
condition for at least one half to one bit time (16X clock mode) or for
one bit time (1X clock mode) before the break condition is
terminated and the search for the next start bit begins. At that time,
the break end detect condition, RSR[3], is set.
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 642
76543210
0
1
2
3
4
5
6
7
Parity error*# – The parity bit of the received character was not as expected. A parity error does not
affect the parity bit put into the FIFO as part of the character when strip parity (RPR[3]) is negated.
Framing error*# – At the first stop bit position the RxD input was in the Low (space) state. The
receiver only checks for framing error at the nominal center of the first stop bit regardless of the
number of stop bits programmed in TPR[7:4]. This bit is not set for BREAKS.
BRK start detect* – An all zero character, including parity (if specified) and first stop bit, was received.
The receiver will be capable of detecting breaks which begin in the middle of a previous character.
Only a single all-zero character will be put into the FIFO when a break is detected. Additional entries
to the FIFO are inhibited until the end of break has been detected (see above) and a new character is
received. The RxRDY status bit is asserted immediately upon a Break Start Detect (regardless of
RxFIFO threshold) so that transfer of any data bytes in the RxFIFO (including the Break 00h
character) will not be delayed.
BRK end detect – 1X clock mode: The RxD input has returned to the marking state for at least one
period of the 1X receiver clock after detecting a BREAK. 16X clock mode: The RxD input has
returned to the marking (High) state for at least one-half bit time after detecting a BREAK. A half-bit
time is defined as eight clock cycles of the 16X receiver clock.
Not used
Overrun error* – A new character was received while the receive FIFO was full and a character was
already waiting in the receive shift register to be transferred to the FIFO. The DUSCC protects the 17
characters previously assembled (16 in RxFIFO, 1 in the Rx shift register) and discards the
overrunning character(s). After the CPU reads the FIFO, the character waiting in the RxSR will be
loaded into the available FIFO position. This releases the RxSR and a new character assembly will
start at the next character boundary. In this way, only valid characters will be assembled, i.e., no
partial character assembly will occur regardless of when the RxSR became available during the
incoming data stream.
RTS negated – The R TSN output was negated due to receiving the start bit of a new character while
the RxFIFO was full (see RPR[4]).
Character compare*# – If the counter/timer is programmed to count received characters, this bit is
asserted when the character which causes the count to go to zero is loaded into the receive FIFO. It
is also asserted to indicate that the character currently at the top of RxFIFO matched the contents of
S1R. A character will not compare if it is received with parity error even if the data portion matches.
Figure 53. RSRA (B) Receiver Status Register [ASYNC Mode]
*FIFOed with data in extended mode (CDUSCC)
The logical OR of these bits is presented in GSR[2] or GSR[4]. Certain bits are FIFOed in status
FIFO. As the data is brought to the top of RxFIFO, the status bits are logically ORed. This register
should be cleared if character-by-character status is desired.
#FIFOed with data in default mode (NDUSCC)
Philips Semiconductors User’s Guide
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1994 Mar 21 643
76543210
0
1
2
3
4
5
6
7
Not used (set to 0)
DPLL error – Set while the DPLL is operating in FM mode to indicate that a data transition was not
detected within the detection window for two consecutive bits and that the DPLL was forced into
search mode. This feature is disabled when the DPLL is specified as the clock source for the
transmitter via TTR[6:4].
Send break ACK – Set when the transmitter begins transmission of a break in response to the send
break command. If the command is reinvoked, the bit will be set again at the beginning of the next
character time. The user can control the length of the break by counting character times through
this mechanism.
Not used (set to 0)
CTS underrun – This bit is set only if CTS enable Tx (TPR[2]) is asserted. It indicates that the
transmit shift register was ready to begin serializing a character and found the CTSN input negated.
In ASYNC mode, this bit will be reasserted if cleared by the CPIU while the CTSN input is negated.
T ransmitter underrun – Indicates that the transmit shift register has completed serializing a character
and found no other character to serialize in the TxFIFO. The bit is not set until at least one character
from the transmit FIFO has been serialized. The TxD output is held in the MARK state until another
character is loaded into the TxFIFO. Normal operation then continues.
Figure 54. TRSRA (B) Transmitter and Receiver Status Register [ASYNC Mode]
All these bits are reset by asserting RESETN or by writing ‘1’ in the bit locations. Bits [7:4]
are reset by Reset Tx and bits [3:0] by Reset Rx commands.
Figure 55. IER1A (B) Interrupt Enable Register 1 [ASYNC Mode]
76543210
Parity error
Frame error
BRK start
BRK end
Reserved
Overrun
RTS negated
Character comparison
This register allows user to enable each individual status bit to cause interrupt. Writing ‘1’ in the
bit position will enable this feature. Master interrupt should also be enabled through ICR or IER3.
0
1
2
3
4
5
6
7
76543210
0
1
2
3
4
5
6
7
Delta DCD detect
Delta CTS detect
DPLL error
Send break ACK
CTS underrun
Tx underrun
Reserved
Tx path empty — Enables interrupt when Tx is enabled, data serialized from TxFIFO has been
transmitted and there is no data in TxFIFO and TxSR.
Figure 56. IER2A (B) Interrupt Enable Register 2 [ASYNC Mode]
This register allows user to enable each individual status bit to cause interrupt. Writing ‘1’ in the
bit position will enable this feature. Master interrupt should also be enabled through ICR or IER3.
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 644
Synchronous Operation Overview
Operation of CDUSCC in synchronous modes differs substantially
from ASYNC operation. This is due in part to the requirements set
forth by the synchronous protocols, and in part due to the need for
the sequence.
In the description that follows, the following terminology will be used
(see also Appendix II):
SYN - A unique pattern of bits used to establish BYTE or
FRAME synchronization in COP protocols.
FLAG - A unique pattern of bits (01111110) used to establish
FRAME synchronization in BOP protocols.
PAD - Protocol often requires an ‘opening PAD’ which is a bit
pattern used to synchronize the clock recovery hardware at the
receiving end. The CDUSCC transmitter is capable of producing
an opening PAD by use of the ‘Transmit Start Of Message with
PAD’ (TSOMP) command issued via the CCR.
FRAME - The message information, including header and error
correction information. The frame is bounded by a SYN (or
FLAG) pattern at its start and end. The SYN (or FLAG) may be
optionally preceded by an opening PAD. The ending SYN
(FLAG) may be optionally followed by a closing PAD. The frame
is sometimes referred to as a ‘BLOCK’ in some protocols.
IDLE - The state of the line when a frame is not being
transmitted.
UNDERRUN - The state of the line when a frame is being
transmitted, but the transmitter has run out of actual data for the
moment, and needs ‘LINE-FILL’ characters to maintain bit and
byte synchronization at the receiver end.
FCS - Frame Check Sequence, the error detection pattern (CRC,
LRC) included at the end of the frame to ensure the integrity of
the data of the frame. Sometimes referred to as the BCC or
Block Check Character in some protocols.
BIT ORIENTED PROTOCOL
BOP Operational Mode
To operate a channel of the CDUSCC in BOP Mode, the channel
Mode Register 1 (CMR1) must specify BOP via bits [2:0] = 000
through 011. In BOP Mode the CMR1, CMR2, S1R,S2R, TPR and
RPR take on the bit definitions illustrated in Figures 57 through 62,
respectively,
TxBOP Modes
T ransmitter commands associated with BOP modes are TSOM,
TSOMP, TEOM and transmit ABORT (TABRK).
76543210
00
01
10
11
00
01
10
11
100
101
110
111
— Channel Protocol Mode —
— Address Mode —
— Extended Control —
— Data Encoding —
BOP primary
BOP secondary
BOP loop
BOP loop - no address comparison
8-bit
Extended address
16-bit
16-bit with group
NRZ/Manchester
NRZI
FM0
FM1
000
001
010
011
0
1
Figure 57. CMR1A (B) Channel Mode Register 1 [BOP Mode]
This field contrtols whether a single or multiple octet follows the opening flag(s).
This bit determines the control field.
One octet
Two octet
not used in this mode
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 645
76543210
00
01
10
11
0
000
01
10
11
000
100
101
110
111
— Frame Check Sequence Select —
— Data Transfer Interface —
— Channel Connection —
None
CRC 16 preset 0s
CRC 16 preset 1s
CRC CCITT preset 0s
CRC CCITT preset 1s
Half-duplex, single address DMA
Half-duplex, dual address DMA
Full-duplex, single address DMA
Full-duplex, dual address DMA
Normal
Auto echo
Local loop
Reserved
0
0
1
100
01
10
11
1
1
W ait on Rx only - Read RxFIFO cycle will be selected until data available
W ait on Tx only - write TxFIFO cycle will be selected until space in TxFIFO is available
W ait on Rx or Tx - Both of above will be selected until space in TxFIFO is available
Polled or interrupt - Data transfer to TxFIFO/from RxFIFO via normal read/write
Figure 58. CMR2A (B) Channel Mode Register 2 [BOP Mode]
0
0
0
0
1
1
1
0
1not used in this mode
See description of CMR2
in ASYNC Section
See W ait Mode in
Section 2
See DMA operation in Section 2
Divisor = X16 + X15 + X2 + 1
Divisor = X16 + X12 + X5 + 1
Starting Transmission
A TSOM or TSOMP command must be issued to start BOP
transmission. TSOM (without PAD) causes the TxCRC/LRC
generator to be initialized and a FLAG character to be loaded into
the TxSR and shifted out on the TxD output.
Send SOM acknowledge (TRSR[4]) is asserted when the FLAG
output begins. The user may re-invoke the command to cause
multiple FLAGs to be transmitted. If the command is not re-invoked
and the TxFIFO is empty, FLAG patterns continue to be transmitted
until the TxFIFO is loaded. If data is present in the FIFO, the first
character is loaded into the TxSR and serialization of the data
begins. Note that the TxFIFO may be pre-loaded with data before
the TSOM is issued.
The TSOMP command causes all characters in the TxFIFO (PAD
characters) to be loaded into the TxSR and serialized if the Tx is
enabled. Unlike the transmit SOM without PAD command, data
(non-PAD characters) cannot be pre-loaded into the TxFIFO. If data
is loaded into TxFIFO during transmission of PAD, it will be treated
as PAD character. While the PAD is transmitted, the character
length is automatically set to 8 bits regardless of the value in
TPR[1:0]. When the TxFIFO becomes empty after the PAD, the
TxCRC/LRC generator is initialized, the FLAG is transmitted, and
send SOM acknowledge asserted. Operation then proceeds in the
same manner as the TSOM command; the user has the option to
invoke the TSOM command to cause multiple FLAGs to be
transmitted.
There is no zero insertion (see below) during transmission of the
PAD characters, and they are not preceded by a FLAG or
accumulated in the CRC. Character length of the PAD characters is
automatically set to 8 bits regardless of TPR[1:0].
Address and Control Field Transmission
In this protocol, the first characters loaded into the TxSR from the
TxFIFO are the address and control fields, which have fixed
character lengths of eight bits. The number of address field bytes is
determined by CMR1[4:3]. If extended address field is specified, the
field is terminated if the first address octet is H’00’ or if the LSB of
the octet is a 1. The number of control field bytes is selected by
CMR1[5]. If any information field characters follow the control field
(forming an I field), they are transmitted with the number of bits per
character programmed in TPR[1:0].
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1994 Mar 21 646
76543210
BOP - first address octet
Figure 59. S1RA (B) SYN1/Secondary Address Register 1 [BOP]
76543210
BOP - second address octet
Figure 60. S2RA (B) SYN2/Secondary Address Register 2 [BOP]
76543210
0
1
0
1
00
01
10
11
— Tx Character Length —
— Tx RTS Control —
— Idle —
— Underrun Control —
5 bits
6 bits
7 bits
8 bits
MARKs
FLAGs
FCS - FLAG - Idle Send FCS if specified by FLAG and then IDLE (bit [5]).
Reserved
0
0
— CTS Enable Tx —
— TEOM on Zero Count or Done (EOP) —
0
1
1
1Abort - MARKs Send ABORT (11111111) and place TxD in marking state.
Abort - FLAGs Send ABORT (11111111) and then send FLAGs.
Figure 61. TPRA (B) Transmitter Parameter Register [BOP Mode]
Causes FCS–FLAG to be transmitted if C/T reaches zero count (if
enabled) or EOPN(DONE) is asserted in DMA mode.
In the event of underrun (TxFIFO empty) this field governs the response of transmitter (TxD).
CTSN input controls the operation of Tx (see TxCTS operation in Section 2)
RTS output is controlled by Tx (see TxRTS operation in Section 2)
NOTE: The abort pattern can be 11111111 or 11111110 as defined by TRCR[0]; default is 11111111.
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1994 Mar 21 647
Information Field Transmission and Underrun
After the opening FLAG and first address octet have been
transmitted, an underrun occurs (TRSR[7] = 1) if the TxFIFO is
empty when the transmitter requires a new character. The underrun
control bits (TPR[7:6]) determine whether the transmitter line fills
with either ABORT-MARKs, ABORT-FLAGs (see below), or ends
transmission with the ’normal’ end of message sequence. For
ABORT-MARKs (TPR[7:6] = 10) and for ABORT-FLAGs (TPR[7:6] =
11), and also after a ’Transmit Abort’ command, a new TSOM
command must be issued to resume transmission. For
FCS-FLAG-idle (TPR[7:6] = 00), see below. Regardless of
TPR[7:6], a TSOMP command is ignored, except after a CTS
underrun, unless the transmitter is disabled or reset and then
re-enabled.
EOM on underrun is functionally similar to EOM due to an appended
TEOM command. If the EOM is due to underrun, the normal
character length applies to the last data character. After the last
character is transmitted, the FCS (inverted CRC) and closing FLAG
are sent, frame complete (TRSR[5]) is set and the TxCRC is
initialized. If the TxFIFO is empty after the closing FLAG has been
sent, TxD will assume the programmed idle state of FLAGs or
MARKs (TPR[5]). For TPR[5] = 1 (idle = FLAGs), transmission will
resume, with or without a TSOM command, when data are loaded
into the TxFIFO. For TPR[5] = 0 (idle = MARKs), a new TSOM
command must be issued. If the TxFIFO is not empty at that time,
the TxFIFO data will be loaded into the TxSR and serialized. In that
case, the closing FLAG is the opening FLAG of the next frame.
Ending Transmission
An appended TEOM command also terminates the frame as
described above. It occurs after transmission of the character to
which the TEOM is appended. The TEOM command can be
explicitly asserted through the channel command register. If TPR[4]
= ’1’, the TEOM is automatically appended to a character in DMA
mode, if the EOPN input is asserted when that character is loaded
into the TxFIFO, or if the counter/timer is counting transmitted
characters, when the character which causes the counter to reach
zero count is loaded.
Tx Residual Character Length
The information field of a BOP frame can be any arbitrary number of
bits. Since the CDUSCC operates on a byte or character basis
(TPR[1:0] number of bits/character). A method has been provided
to easily transmit the residual bits remaining in a frame that is not an
integer multiple of the specified character length, with a resolution of
one bit.
When the character with the appended TEOM is loaded from the
TxFIFO, it is transmitted with the character length specified by
OMR[7:5]. In this way, a residual character of 1-8 bits is transmitted
with out requiring the CPU to change the Tx character length for this
last character.
Caution
If the Tx residual character length is not programmed, it will default
to value of 1 bit (OMR[7:5] = 000). So, the Tx will send out only 1 bit
of the last character. Be sure to program the Tx residual character
length correctly.
Control of Number of FLAGs Between Frame
The CDUSCC provides automatic generation of FLAGs between
frames (TPR[5] = 1). In certain situations the user may wish to
control the precise number of FLAGs between frames. In that case,
the user controls the number of FLAGs between frames by invoking
the TSOM command after frame complete is asserted. The
CDUSCC then operates in the same manner as for transmission of
multiple FLAGs at the start of a frame.
When the command is no longer re-invoked, transmission of the
TxFIFO data will begin. If the FIFO is empty, FLAGs continue to be
transmitted.
Zero Insertion
The CDUSCC provides automatic zero insertion in the data stream
to prevent erroneous transmission of the FLAG sequence. All data
characters loaded into the TxSR from the TxFIFO and characters
transmitted from the CRC generator are subject to zero insertion.
For this feature a zero is inserted in the serial data stream each time
five consecutive ones (regardless of character boundaries) have
been transmitted.
Abort Transmission
A TABRK command clears the TxFIFO and inserts an ABORT
character of eight or seven ones (not subject to zero insertion) into
the TxSR for transmission after the current character has been
serialized. A send ABORT ACK (TRSR[4]) facilitates re-assertion of
send abort by the user to guarantee transmission of multiple abort
characters. This feature can be used to send the 15-ones IDLE
sequence.
The transmitter sends either marks or FLAGs after the abort
character(s) has been transmitted, depending on TPR[7:6].
Operation resumes with the transmission of a FLAG when a TSOM
command is invoked. A TSOMP command is ignored, except after
a CTS underrun, unless the transmitter is disabled or reset and then
re-enabled.
TxCRC Accumulation
CRC accumulation can be specified in all BOP modes. The type of
CRC is specified via CMR2[2:0], and is normally selected as
CRC-CCITT preset to ones, although any option is valid. Note that
LRC8 option is not allowed in BOP modes.
The TSOM/TSOMP command sets the CRC accumulator to its initial
state and accumulation begins with the first address octet after the
initial FLAG(s). Accumulation stops when transmission of the first
character of the FCS begins. The CPU can set the accumulator to
its initial state prior to the transmission of any character by using the
appended reset CRC command and can exclude any character from
the accumulation by use of the exclude from CRC command, but
these features would not normally be used in BOP modes. The
CRC generator is also automatically initialized after EOM or an
ABORT is sent.
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1994 Mar 21 648
Table 15. Underrun Control
TPRA[7:6] Protocol TxD Line During Underrun
00 BOP FLAG following either FCS (if selected) or last data character , then idle
COP Last byte of FCS (if selected) or last data character, then idle
10 BOP Abort sequence after last data character , then send MARKs
COP MARKs
11 BOP Abort sequence after last data character , then send FLAGs
COP Last character of SYN sequence, the SYN sequence being SYN1, SYN1/2 or DLE/SYN1 for single
SYN, dual SYN and BISYNC, respectively.
76543210
00
01
10
11
— Rx Character Length —
— All Party Address —
5 bits
6 bits
7 bits
8 bits
— DCD Enable Rx —
0
1
— Overrun Mode —
Hunt — terminate receiving current frame and go into hunt mode.
Continue — continue receiving current frame, Overrun character is lost in this case.
— FCS to FIFO —
Reserved
0Reserved – set to zero
Figure 62. RPRA (B) Receiver Parameter Register [BOP Mode]
If this bit is set Rx terminates operation if DCDN/SYNIN is not asserted.
0
1Don’t recognize all party address
Recognize all party address
If RxFIFO and RxSR are full and a new character is received...
Setting this bit will cause FCS to be loaded into RxFIFO. In this case EOM status bit will be tagged onto
the last byte of FCS. In this mode, two full FLAGs are required between frames.
76543210
0
1
2
3
4
5
6
7
RCL not zero*#
CRC error*#
Flag detect
Idle detect
Short frame detect*
Overrun error*
Abort detect*
EOM detect*#
Figure 63. RSRA (B) Receiver Status Register [BOP Mode]
*FIFOed with data in extended mode (CDUSCC)
#FIFOed with data in default mode (NDUSCC)
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76543210
0
1
2
3
4
5
6
7
RCL not zero*#
CRC error*#
Flag detect
T urnaround detect
Short frame detect*
Overrun error*
Abort/EOP detect*
EOM detect*#
Figure 64. RSRA (B) Receiver Status Register [BOP - Loop Mode]
*FIFOed with data in extended mode (CDUSCC)
#FIFOed with data in default mode (NDUSCC)
Receiver Status Register (RSRA, RSRB)
This register informs the CPU of receiver status. Bits indicated as
‘not used’ in a particular mode will read as zero. The logical OR of
these bits is presented in GSR[2] or GSR[6] (ORed with the bits of
TRSR) for channels A and B, respectively. Unless otherwise
indicated, asserted status bits are reset only by performing a write
operation to the status register with the bits to be reset being ones in
the accompanying data word, or when the RESETN input is
asserted, or when a ‘reset receiver’ command is issued.
Certain status bits are specified as being FIFOed. This means that
they occupy positions in a status FIFO that correspond to the data
FIFO. As the data is brought to the top of the FIFO (the position
read when the RxFIFO is read), the FIFOed status bits are logically
ORed with the previous contents of the corresponding bits in the
status register. This permits the user to obtain status either
character-by-character or on a block basis. For
character-by-character status, the SR bits should be read and then
cleared before reading the character data from RxFIFO. For block
status, the status register is initially cleared and then read after the
message is received. Asserted status bits can be programmed to
generate an interrupt (see Interrupt Enable Register).
Bit[7] EOM Detect:
If the counter/timer is programmed to count received characters, this
bit is asserted when the character which causes the count to go to
zero is loaded into the receive FIFO. It is also asserted to indicate
that the character currently at the top of the FIFO was the last
character of the frame. If transfer FCS to FIFO (RPR[6]) is
asserted, the EOM will be tagged instead onto the last byte of the
FCS. Note that if an overrun occurs, the EOM character may be
lost, but this status bit will still be asserted to indicate that an EOM
was received. This bit will not be set when an abort is received.
Bit[6] ABORT:
BOP: An ABORT sequence consisting of a zero followed by seven
ones was received after receipt of the first address octet but before
receipt of the closing FLAG. The user should read RxFIFO until it is
empty and determine if any valid characters from a previous frame
are in the FIFO. If no character with a tagged EOM detect ([7]) is
found, all characters are from the current frame and should be
discarded along with any previously read by the CPU. An ABORT
detect causes the receiver to automatically go into search for FLAG
state. An abort during a valid frame does not cause the CRC to
reset; this will occur when the next frame begins.
LOOP: Performs the ABORT detect function as described for BOP
without the restriction that the pattern be detected during an active
frame. A zero followed by seven ones is the end-of-poll sequence
which allows the transmitter to go active if the ‘go active on poll’
command has been invoked.
Bit[5] Overrun Error (all modes):
A new character was received while the receive FIFO was full and a
character was already waiting in the receive shift register to be
transferred to the FIFO. The CDUSCC protects the characters
previously assembled and discards the overrunning character(s).
After the CPU read the FIFO, the character waiting in the RxSR will
be loaded into the available FIFO position. This releases the RxSR
and a new character assembly will start at the next character
boundary. In this way, only valid characters will be assembled, i.e.,
no partial character assembly will occur regardless of when the
RxSR became available during the incoming data stream.
Bit[4] Short Frame (BOP/LOOP):
A closing flag was received with missing fields in the frame. See
RxBOP mode on following pages for details.
Bit[3] IDLE (BOP), Turnaround (LOOP):
BOP: An IDLE sequence consisting of a zero followed by fifteen
ones was received. During a valid frame, an abort must precede an
idle. However, outside of a valid frame, an idle is recognized and
abort is not.
LOOP: A turnaround sequence consisting of eight contiguous
zeros was detected outside of an active frame. This should
normally be used to terminate transmitter operation and return the
system to the ‘echoing RxD’ mode.
Bit[2] FLAG Detect (BOP/LOOP):
A FLAG sequence (01111110) was received. Set one bit time after
FLAG is detected in CCSR.
Bit[1] CRC Error:
This bit is set upon receipt of the FCS byte(s), if any, to indicate that
the received FCS was in error. The bit is normally FIFOed with the
last byte of the I field (the character preceding the first FCS byte).
However, if transfer FCS to FIFO (RPR[6]) is asserted, this bit is
FIFOed with the last FCS byte.
Bit[0] RCL Not Zero (BOP/LOOP):
The last character of the I field did not have the character length
specified in RPR[1:0]. The actual received character length of this
byte can be read in TRSR[2:0]. This bit is FIFOed with the EOM
character but TRSR[2:0] is not. An exception occurs if the
command to transfer the FCS to the FIFO is active. In this case, the
bit will be FIFOed with the last byte of the FCS, i.e., with REOM. In
the event that residual characters from two consecutive frames are
received and are both in the FIFO, the length in TRSR[2:0] applies
to the last received residual character.
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1994 Mar 21 650
76543210
000
001
010
011
100
101
110
111
— Rx Residual Character Length —
0 bits
1 bit
2 bits
3 bits
4 bits
5 bits
6 bits
7 bits
DPLL error – Set when DPLL is operating in FM mode and data transition was not detected for two consecutive
bits and DPLL was forced into search mode.
Send SOM/abort ACK – Set at the beginning of transmission of FLAG/ABORT.
Frame complete – Set at the beginning of transmission of end-of-message sequence.
CTS underrun (*loop sending) – CTSN input has been negated.
T ransmitter underrun – TxFIFO and TxSR are empty and TxD is set to the mode specified by TPR[7:6].
* loop mode only – EOP sequence has been detected.
Figure 65. TRSRA (B) Transmitter and Receiver Status Register [BOP Mode]
It gives the length of the last character of I field. Reset by Reset Rx
or Disable Rx.
—All unused bits are cleared to zero when residual character is
loaded in RxFIFO except when residual byte length is 1.
76543210
0
1
2
3
4
5
6
7
RCL not zero
CRC error
Flag detect
Idle/turnaround detect
Short frame
Overrun
ABORT/EOP detect
EOM detect
Figure 66. IER1A (B) Interrupt Enable Register 1 [BOP Mode]
76543210
0
1
2
3
4
5
6
7
Delta DCD detect
Delta CTS/LC detect
DPLL error
Send SOM ACK
CTS underrun/loop sending
Tx underrun
Tx frame complete
Tx path empty
Figure 67. IER2A (B) Interrupt Enable Register 2 [BOP Mode]
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1994 Mar 21 651
TxBOP Loop Mode
The loop modes are used by secondary stations on the loop, while
the primary station operates in the BOP primary mode. Both the
transmitter and receiver must be enabled and should be
programmed to use the same clock source. Loop operation is
initiated by issuing the ’go on-loop’ command. The receiver looks
for the receipt of seven contiguous ones and then asserts the LCN
output to cause external loop control hardware to put the CDUSCC
into the loop, with the TxD output echoing the RxD input with a 2-bit
time delay. The echoing process continues until a go active on poll
(GAP) command is invoked. The CDUSCC then looks for receipt of
an EOP bit pattern (a zero followed by seven ones, 11111110) and
changes the last one of the EOP into a zero making it an opening
FLAG. Loop sending (TRSR[6]) is asserted at that time. The action
of the transmitter after sending the initial FLAG depends on the
status of the transmit FIFO.
If the transmit FIFO is not empty, a normal frame transmission
begins. The operation is then similar to normal BOP operation with
the following differences:
1. An ABORT command, an underrun, or receipt of the turn around
sequence (H’00’) or a FLAG cause the transmitter to cease op-
eration and to revert to echoing the RxD input with a 2-bit time
delay. A new transmission cannot begin until the GAP command
is re-invoked and a new EOP sequence is received.
2. Subsequent to sending the EOM sequence of FCS-FLAG, the
CDUSCC examines the internal GAP flip-flop. If it is not set
(having been reset by the ’reset GAP’ command), the CDUSCC
reverts to echoing the received data. If the internal GAP flip-flop
is still set, transmission of a new frame begins, with the user
having control of sending multiple FLAGs between frames by use
of the ’TSOM’ command. If the FIFO is empty at this time, the
CDUSCC continues to send FLAGs until the data is loaded into
the FIFO or until GAP is reset. If the latter occurs, it reverts to
echoing RxD. When the CDUSCC reverts to echoing RxD in any
of the above cases, the last transmitted zero and seven ones will
form an EOP for the next station down the loop. If the TxFIFO is
empty when the EOP is recognized, the transmitter continues to
send FLAGs until there is data in the FIFO. If a turnaround se-
quence or the reset GAP command is received before the FIFO
is loaded, the transmitter switches to echoing RxD without any
data transmission. Otherwise a frame transmission begins as
above when a character is loaded into the FIFO. The mecha-
nism provides time for the CPU to examine the received frame
(the frame preceding the EOP) to determine if it should respond
or not, while holding its option to initiate a transmission.
Termination of operation in the loop mode should be accomplished
by use of the ’go off loop’ command. When the command is
invoked, the CDUSCC looks for the receipt of seven contiguous
ones. It then negates the LCN output to cause the external loop
control hardware to remove the CDUSCC from the loop without
affecting operation of other units remaining on the loop.
RxBOP MODE
In BOP mode, the receiver may be in any one of four phases: hunt
phase, address field (A) phase, control field (C) phase, or
information field (I) phase. The character length for the A and C
phases is always 8 bits. The I field character length is specified in
RPR[1:0].
Note that if the residual character length is not zero, the unused
most significant bits in the receiver FIFO are not necessarily zero.
The unused bits should be ignored, this will not cause a CRC error.
After an enable receiver command is executed, the receiver enters
hunt phase, in which a comparison for the FLAG string (01111110) is
done every Rx bit time. The FLAG delineates the beginning (and
end) of a received frame and establishes the character boundary.
Each FLAG match in CCSR causes the FLAG detect status bit
(RSR[2]) to be set. FLAGs with an overlapping zero will be
detected. All FLAGs are deleted from the data stream.
Rx Address Field Phase
Once a FLAG has been detected, the receiver will exit hunt phase
and enter address phase. The handling of the address field is
determined by the values programmed in CMR1[2:0], which selects
one of the BOP modes.
The length of the A field may be a single octet, a dual octet, or more
octets, as described below. A primary station or an extended
address secondary station does not perform an address
comparison, and all characters in the A, C, and I fields after the flag
are transferred to the FIFO. Although address field comparisons are
not performed, the length of the address field is still determined by
CMR1[4:3]. For the other secondary address modes, if there is a
match, or the received character(s) match either of the other
enabling conditions (group or all-parties address), all characters in
the A, C, and I fields are transferred to the FIFO. If there is no
match, the receiver returns to the FLAG hunt phase.
The BOP secondary address modes are selected by CMR1[4:3] and
function as in the description that follows.
Rx Single-Octet Address
For receive, the address comparison for a secondary station is
made on the first octet following the opening FLAG. A match occurs
if the first octet after the FLAG matches the contents of S1R, or if all
parties address (RPR[3]) is asserted and the first octet is equal to
H’FF’.
Rx Dual-Octet Address
For receive, the address comparison for a secondary station is
made on the first two octets following the opening FLAG. A match
occurs if the first two octets after the FLAG match the contents of
S1R and S2R respectively, or if all parties address (RPR[3]) is
asserted and the first two octets are equal to H’FF, FF’.
Rx Dual Address with Group Mode
For receive, the address comparison for a secondary station is
made on the first two octets following the opening FLAG. A match
occurs for one of three possible conditions. If the first two octets
after the FLAG match the contents of S1R and S2R, respectively, or
if the first octet is H’FF’ and the second matches the contents of
S2R (group mode), or when all parties address (RPR[3]) is asserted
and the first two octets are equal to H’FF, FF’. The second condition
(group mode) allows a selected group of stations to receive a
message.
Rx Extended Address Mode
Extends address field to the next octet if the LSB of the current
address octet is zero. Address field is terminated if the LSB of the
address is a one. The address field will be terminated after the first
octet if the null address H’00’ is received as the first address octet.
For this mode the receiver does not perform an address comparison
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 652
(all received characters after the opening FLAG are transferred to
the FIFO) but does determine when the address field is terminated.
Rx Control Field Phase
C phase begins after A phase is terminated. The receiver receives
one or two control characters, CMR1[5]. After this phase is
terminated, the character length is switched automatically from 8 bits
to the number of bits specified in RPR[1:0] and the information field
phase is entered.
Rx Information Field Phase
Data received in the I Field will be transferred to the RxFIFO 5 to 8
bits at a time, as specified by the character length (RPR[1:0]).
Normally 8 bit character length is specified. If a shorter length is
used, the received bits are right justified with the unused MSB(s) set
to 0. If the I Field is not an integer multiple of the specified character
length, a residual will remain. This is indicated by the RCL not zero
status bit (RSR[0]) which is FIFOed with the last Rx character of the
frame.
RCL not zero RSR[0] is set if the length of the last character of the I
field does not have the length programmed in RPR[1:0]. The
residual character length in TRSR[2:0] is also valid at that time,
indicating the number of bits valid (right justified) of the last Rx
character, required to complete the frame.
Rx Frame Termination
The frame is terminated when a closing FLAG is detected. The
same FLAG can also serve as the opening FLAG of the next frame
if RPR[6] = 0. For RPR[6] = 1, see description of RPR[6].
Rx CRC Accumulation
The 16 bits received prior to the closing FLAG form the frame check
sequence (if an FCS is specified in CMR2[2:0]). All non-FLAG
characters of the frame are accumulated in the CRC checker and
the result is compared to the expected remainder. Failure to match
will set CRC error flag. EOM detect RSR[7], RCL not zero RSR[0],
and CRC error RSR[1] are normally FIFO’d with the last character of
the I field. The CRC characters themselves are normally not passed
to the RxFIFO. However, if the transfer FCS to FIFO control bit
RPR[6] is asserted, the FCS bytes will be transferred to the FIFO.
In this case the EOM, CRC error, and RCL not zero status bits will
be tagged onto the last byte of the CRC sequence instead of to the
last character of the message. Following the last data byte, the
DFSB will be pushed into FIFO if it is specified (TRCR[6] = 1).
Rx Short Frame Detection
If the closing FLAG is received prior to receipt of the appropriate
number of A field, C field as programmed in CMR1[5:3], and FCS
field octets, a short frame will be detected and RSR[4] will be set.
The I field need not be present in a valid frame.
Rx Abort Detection
An abort (a zero followed by seven ones) comparison is done after
an opening FLAG has been received and up to receipt of the closing
FLAG. A match causes the receiver to enter hunt (FLAG search)
phase. The Abort detect status bit (RSR[6]) is set only if an Abort
was received after receipt of the first address octet and before
receipt of the closing FLAG. The abort is stripped from the received
data stream.
Rx Idle Detection
If a zero followed by 15 contiguous ones is detected, the idle detect
status bit RSR[3] is set. This comparison is done whenever the
receiver is enabled. Therefore, it can occur before or after a
received frame.
Rx Zero Detection
Zero deletion is performed during BOP receive. A zero after 5
contiguous ones is deleted from the data stream regardless of
character boundaries. Deleted zeros are not subject to CRC
accumulation. FLAG, ABORT, and IDLE comparisons are done
prior to zero deletion.
BOP Loop Mode
Operation of the receiver in BOP loop mode is similar to operation in
other BOP modes, except that only certain frame formats are
supported. Several character detection functions that interact with
the operation of the transmitter or transmitter commands are added:
1. When the ‘go on-loop’ command is invoked the receiver looks for
the receipt of a zero followed by seven ones and then asserts
the LCN output.
2. When the ‘go off-loop’ command is invoked, the receiver looks
for the receipt of seven contiguous ones and then negates the
LCN output.
3. The TxD output normally echoes the receive input with a two bit
time delay. When the ’go active on poll’ command is asserted,
the receiver looks for an EOP (a zero followed by seven ones)
and then switches the TxD output line to the normal transmitter
output. Receipt of an EOP or an ABORT sets RSR[6].
4. Receipt of a turnaround sequence (eight contiguous zeros) or
FLAG terminates the transmitter operation, if any, and returns the
TxD output to echoing the RxD input, RSR[3] is set if a turn-
around is received. See transmitter operation for additional de-
tails.
CHARACTER ORIENTED PROT OCOL
COP Operational Mode
To operate a channel of the CDUSCC in COP Mode, the Channel
Mode Register 1 (CMR1) must specify COP via bits [2:0] = 100
through 110. In COP Mode the CMR1, CMR2, S1R,S2R, TPR and
RPR take on the bit definitions illustrated in Figures 68 through 73,
respectively (S1R and S2R should be loaded with the SYN
character).
TxCOP Modes
T ransmitter commands associated with all COP modes are: transmit
SOM (TSOM, transmit start of message), transmit SOM with PAD
(TSOMP), transmit EOM (TEOM, transmit end of message), reset
TxCRC, exclude from CRC, and transmit DLE. The TSOM and
TSOMP commands are identical to BOP modes except that a SYN
character(s) is used as the start of message sequence instead of a
FLAG (01111110).
Starting Transmission
A TSOM or TSOMP command must be issued to start COP
transmission. TSOM (without PAD) causes the TxCRC/LRC
generator to be initialized and one or two SYN characters from
S1R/S2R to be loaded into the TxSR and shifted out on the TxD
output.
A parity bit, if specified, is appended to each SYN character after the
MSB. Send SOM acknowledge (TRSR[4]) is asserted when the
SYN output begins. The user may re-invoke the command to cause
multiple SYNs to be transmitted. If the command is not re-invoked
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1994 Mar 21 653
and the TxFIFO is empty, SYN patterns continue to be transmitted
until the TxFIFO is loaded. If data is present in the FIFO, the first
character is loaded into the TxSR and serialization of the data
begins. Note that the TxFIFO may be pre-loaded with data before
the TSOM is issued.
The TSOMP command causes all characters in the TxFIFO (PAD
characters) to be loaded into the TxSR and serialized if the Tx is
enabled. Unlike the transmit SOM without PAD command, data
(non-PAD characters) cannot be pre-loaded into the TxFIFO. While
the PAD is transmitted, parity is disabled and character length is
automatically set to 8 bits regardless of the value in TPR[1:0]. When
the TxFIFO becomes empty after the PAD, the TxCRC/LRC
generator is initialized, the SYN character(s) are transmitted with
optional parity appended, and send SOM acknowledge (TRSR[4]) is
asserted. Operation then proceeds in the same manner as the
TSOM command; the user has the option to invoke the TSOM
command to cause multiple SYNs to be transmitted.
76543210
00
01
10
11
0
1
000
001
010
011
100
101
110
111
— Channel Protocol Mode —
— Parity Mode —
— BISYNC Coding —
— Data Encoding —
COP dual SYN
COP dual SYN (BISYNC)
COP single SYN
— not used in this mode
ASCII, No parity, 8-bit data, 8-bit CTRL characters. Odd parity bit is generated by users. It’s same as
NMOS DUSCC. Receiver checks the parity bit by look-up table. If an LRC BCC is selected in CMR2[2:0],
then LRC-8 is used (the MSB of the LRC is the logical XOR of all MSBs in the frame).
ASCII, No parity, 8-bit data, 8-bit CTRL characters. The receiver only checks 7 bits for the CTRL character
and ignores the MSB of each character. If an LRC BCC is selected in CMR2[2:0], then LRC-7 is used (the
MSB of the LRC is 0).
ASCII, ODD parity, 7-bit data + 1 odd parity bit, 7-bit CTRL characters + 1 odd parity bit. Parity is
generated/checked by DUSCC. Any CTRL character with parity error will not be treated as a CTRL
character.
ASCII, EVEN parity. Similar to CMR1[4:3] = 10 except parity bit is even.
EBCDIC
ASCII
NRZ/Manchester
NRZI
FM0
FM1
Figure 68. CMR1A (B) Channel Mode Register 1 [COP Mode]
If COP dual SYN (BISYNC) is selected, then CMR1[4:3] will set:
If an LRC BCC is selected in CMR2[2:0], then LRC-7 is used. The MSB of the LRC will be the ODD
PARITY value computed from the 7 other bits that comprise the LRC.
00
01
10
11
not used in this mode
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76543210
00
01
10
11
0
000
01
10
11
000
001
010
011
100
101
110
111
— Frame Check Sequence Select —
— Data Transfer Interface —
— Channel Connection —
None
Not used in this mode
LRC8 preset 0s
LRC8 preset 1s
CRC 16 preset 0s
CRC 16 preset 1s
CRC CCITT preset 0s
CRC CCITT preset 1s
Half-duplex, single address DMA
Half-duplex, dual address DMA
Full-duplex, single address DMA
Full-duplex, dual address DMA
Normal
Auto echo
Local loop
Reserved
0
0
1
100
01
10
11
1
1
W ait on Rx only - Read cycle extended until data available in RxFIFO
W ait on Tx only - Write cycle extended until space available in TxFIFO
W ait on Rx or Tx - Both of above
Polled or interrupt - Normal CPU read/write cycle for TxFIFO and RxFIFO transfer
Figure 69. CMR2A (B) Channel Mode Register 2 [COP Mode]
see DMA operation in Section 2
see Wait Mode in Section 2
see description of CMR2 in ASYNC section
Divisor = X8 + 1
Divisor = X16 + X15 + X2 + 1
Divisor = X16 + X12 + X5 + 1
76543210
Figure 70. S1RA (B) SYN1/Secondary Address Register 1 [COP]
In COP modes, it contains the 5- to 8-bit SYN1 bit pattern, right justified. Parity bit need not be
included in the value placed in the register even if parity is specified in CMR1[4:3]. However, a
character received with parity error, when parity is specified, will not match. If parity is
specified, then any unused bits in this register must be programmed to zeros.
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76543210
In COP dual SYN modes, it contains the 5- to 8-bit SYN2 bit pattern, right justified. Parity bit
need not be included in the value placed in the register even if parity is specified in CMR1[4:3].
However, a character received with parity error, when parity is specified, will not match. If
parity is specified, then any unused bits in this register must be programmed to zeros.
Figure 71. S2RA (B) SYN2/Secondary Address Register 2 [COP]
76543210
0
1
0
1
00
01
10
11
— Tx Character Length —
— Tx RTS Control —
— Idle —
— Underrun Control —
5 bits
6 bits
7 bits
8 bits
MARKs
SYNs
FCS - Idle
Reserved
0
0
— CTS Enable Tx —
— TEOM on Zero Count or Done (EOP) —
0
1
1
1MARKs
SYNs
Figure 72. TPRA (B) Transmitter Parameter Register [COP Mode]
CTSN input controls the operation of Tx (see Tx CTS operation in Section 2)
RTSN output controlled by Tx (see Tx RTS operation in Section 2)
determines if a TEOM is generated automatically at zero count of C/T or
DONE(EOP) signal (see ‘ending transmission’).
Data Transmission and Underrun
After the TSOM/TSOMP command is executed, characters in the
TxFIFO are loaded into the TxSR and shifted out with a parity bit, if
specified, appended after the MSB. If, after the opening SYN(s) and
at least one data byte has been transmitted, the TxFIFO is empty, a
data underrun condition results and the Tx Underrun Status Bit
(TRSR[7]) is asserted. The transmitter’s action on data underrun is
determined by the Tx Underrun Control Bits (TPR[7:6]) and the COP
protocol. If the Tx Underrun Control is set for ‘MARKs’ (TPR[7:6] =
’10’), the transmitter line fills with MARK characters until a character
is loaded into the FIFO. If the Tx Underrun Control is set for ‘SYNs’
(TPR[7:6] = ’11’), the transmitter line fills with SYN, SYN1-SYN2, or
DLE-SYN1 for mono sync, dual sync, and BISYNC transparent
modes, respectively. If the Tx Underrun Control is set for ‘FCS-IDLE
(TPR[7:6] = ’00’), the FCS (BCC) characters are transmitted and
frame complete (TRSR[5]) and Underrun (TRSR[7] are set. TxD
then assumes the programmed idle state (TPR[5]) of MARKs or
SYN1/SYN1-SYN2.
For FCS-IDLE Underrun Control (TPR[7:6] = 00), transmitter
operation resumes immediately (without transmitting a ‘SYN’) when
data is loaded into the TxFIFO or resumes with the transmission of a
SYN sequence when a TSOM command is invoked. A TSOMP
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 656
command is ignored, except after a CTS underrun, unless the
transmitter is disabled or reset and then re-enabled.
For ‘MARK’ or ‘SYN’ Underrun Control (TPR[7:6] = 10 or 11),
transmission resumes immediately (without transmitting a ‘SYN’)
when data are loaded into the TxFIFO. Both a TSOM and a TSOMP
command are not executed unless the transmitter is disabled or
reset and then re-enabled or, after a CTS underrun, CTSN is
asserted again.
Ending Transmission
User may end the transmission by issuing TEOM command (CCR)
after loading last character in the TxFIFO. In DMA mode, assertion
of DONE(EOPN) signal will append TEOM command to the last
character if TPR[4]=1. If counter/timer is counting transmitted
characters, TEOM is tagged with the character that causes counter
to reach zero count. After EOM is transmitted, TxD signal will go
‘IDLE’.
BISYNC
The TDLE command, when appended to a character in the TxFIFO,
causes the DLE character to be loaded into the TxSR and serialized
before the TxFIFO character is loaded into the TxSR and serialized.
This feature is particularly useful for BISYNC operation. The DLE
character will be excluded from the CRC accumulation in BISYNC
transparent mode (see below), but will be included in all other COP
modes.
In BISYNC mode, transmission of a DLE-STX character sequence
(either via a send TDLE command appended to the STX character,
or via DLE and STX loaded into the TxFIFO) puts the transmitter
into the transparent mode of operation and sets TRSR[0]. In this
mode, normally restricted character sequences can be transmitted
as ’normal’ bit sequences. The switch occurs after transmission of
the two characters, so that the DLE and STX are included in the
FCS (BCC) accumulation. If the DLE-STX is to be excluded from
the CRC, the user should issue a ’reset CRC’ command prior to
loading the next character.
Another method of excluding the two characters from the CRC is to
invoke the ‘exclude from CRC’ command prior to loading the
character(s) into the FIFO. While in transparent mode, the
transmitter line fills with DLE-SYN1 and automatically transmits an
extra DLE if it finds a DLE in the TxFIFO (‘DLE stuffing’). The
transmitter reverts to non-transparent mode when the frame
complete status is set in TRSR[5].
Frame Check Sequence
CRC/LRC accumulation can be specified in all COP modes; the type
is specified via CMR2[2:0]. The TSOM/TSOMP commands set the
CRC/LRC accumulator to its initial state and accumulation begins
with the first non-SYN character after the initial SYN(s) are
transmitted. PAD characters are not subject to CRC accumulation.
In non-BISYNC or BISYNC normal modes, all transmitted
characters except linefill characters (SYNs or MARKs) are subject to
accumulation. In BISYNC transparent mode, odd (stuffed) DLEs
and the DLE- SYN1 linefill are excluded from the accumulation.
Characters can be selectively excluded from the accumulation by
invoking the ‘exclude from CRC’ command prior to loading the
character into the FIFO.
Accumulation stops when transmission of the first character of the
FCS (BCC) begins. The CPU can set the accumulator to its initial
state prior to the transmission of any character by using the
appended reset CRC command. The CRC generator is also
automatically initialized after the EOM is sent.
RxCOP Modes
When the receiver is enabled in COP modes, it first goes into the
SYN hunt phase, testing the received data each bit time for receipt
of the appropriate SYN pattern, plus parity if specified, to establish
character boundaries. Receipt of the SYN bit pattern terminates
hunt phase and places the receiver in the data phase, in which all
leading SYNs are stripped and the RxFIFO begins to load starting
with the first non-SYN character. In COP single SYN protocol mode,
S1R contains the SYN character required to establish character
synchronization. In COP dual SYN and BISYNC protocol modes,
S1R and S2R contain the first and second SYN characters,
respectively, required to establish character synchronization. The
SYN character length is the same as the character length
programmed in RPR[1:0], plus the parity bit if parity is specified.
SYN characters received with a parity error, when parity is specified,
are considered invalid and will not cause synchronization to be
achieved.
In COP mode, resetting the receiver clears the receiver data path,
while disabling the receiver does not. If not reset, partial sync
patterns remaining in the receiver will be recognized when it is
enabled.
If external synchronization is programmed (RPR[4] = 1), the internal
SYN detection and special character recognition logic are disabled
and receipt of SYN characters is not required. A pulse on the
SYNIN input pin will establish character synchronization and
terminate hunt phase. The SYNIN pin is ignored after the first input
on the SYNIN pin is received. The receiver must be disabled and
then re-enabled to re-synchronize or to return to normal mode. This
must be programmed in conjunction with CMR1[2:0] = 110. Refer to
the description of RPR[4] for further details (Figure 73).
The SYN detect status bit, RSR[2], is set whenever SYN1,
SYN1-SYN2, or DLE-SYN1 is detected for single SYN, dual
SYN/BISYNC normal, and BISYNC transparent modes, respectively.
SYNC detect bit (RSR[2]) is set when SYN1 and/or SYN2 are
detected by internal logic irrespective of the normal or transparent
BiSYNC operation. After character sync has been attained, the
receiver enters the data phase and assembles characters in the
RxSR, beginning with the first non-SYN character, with the least
significant bit received first. It computes the FCS (BCC) if specified,
checks parity if specified and checks for overrun errors.
The operation of the FCS (BCC) logic depends on the particular
COP mode in use. The FCS (BCC) is initialized upon first entering
the data phase. For non-BISYNC modes, all received characters
after entering data phase are included in the FCS (BCC)
computation, except for leading SYNs and SYNs which are specified
to be stripped by RPR[7]. As each received character is transferred
from the RxSR to the FIFO, the current value of the FCS (BCC)
characters is checked and the CRC ERROR status bit (RSR[1]) is
set if the value of the CRC remainder is not the expected value.
RSR[1] gets set when the character reaches the top of the FIFO.
The EOM status bit, RSR[7], is not set since there is no defined
end-of-message character. Therefore, user has to know when to
check BCC to get exactly BCC status. The receiver computes the
FCS (BCC) for text messages automatically when operating in
BISYNC protocol mode.
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1994 Mar 21 657
— External SYNC — In order to use this feature, the CDUSCC must be programmed to COP single SYN mode,
CMR1[2:0] = 110. A negative signal on the DCDN/SYNIN pin will cause the receiver to establish
synchronization on the next rising edge of the receiver clock. Character assembly will start at this
edge with the RxD input pin considered to have the second bit of data. The sync signal can then be
negated. Receipt of the Active-High external sync input causes the SYN detect status bit (RSR[2])
to be set. When this mode is enabled, the internal SYN (COP mode) detection and special character
recognition (e.g., IDLE, STX, ETX, etc.) circuits are disabled. The user must wait at least eight bit
times after Rx is enabled before applying the SYNIN signal. This time is required to flush the internal
data paths. The receiver remains in this mode and further external sync pulses are ignored until the
receiver is disabled and then re-enabled to re-synchronize or to return to normal mode. Note that
EXT SYNC and DCD ENABLE Rx cannot be asserted simultaneously since they use the same pin.
76543210
00
01
10
11
— Rx Character Length —
5 bits
6 bits
7 bits
8 bits
— DCD Enable Rx —
— SYN Strip —
Figure 73. RPRA (B) Receiver Parameter Register [COP Mode]
determines if DCD input controls receiver operation (see RxDCD control in Section 2)
determines if SYN patterns within a message are passed to RxFIFO (see ‘SYN STRIPPING’)
In BISYNC mode, the assertion of this bit causes the received FCS to be loaded into the
RxFIFO. If the FCS is specified to be transferred to the FIFO, the EOM status bit will be
tagged onto the last byte of the FCS instead of to the last character of the message.
— Auto-Hunt and Pad Check — In BISYNC mode, the assertion of this bit causes the receiver to go into hunt for
character sync mode after detecting certain end-of-message (EOM) characters.
After the EOT and NAK sequences, the receiver also does a check for a closing
PAD of four 1s.
— Strip Parity — In COP mode with parity enabled, this bit controls whether the received parity bit is stripped from
the data placed in the receiver FIFO. It is valid only for programmed character lengths of 5, 6 and
7 bits since the parity bit for 8 bit characters can never go into the FIFO. If the bit is stripped, the
corresponding bit in the received data is set to zero.
— Transfer Received FCS to FIFO —
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1994 Mar 21 658
76543210
0
1
2
3
4
5
6
7
Parity error*# – The parity bit of the received character was not as expected. A parity error does
not affect the parity bit put into the FIFO as part of the character when strip parity (RPR[3]) is
negated. A SYN or other character received with parity error is treated as a data character. Thus,
a SYN with parity error received while in SYN search state will not establish character sync.
Characters received with parity error while in the SYN search state will not set the error bit.
CRC error*# – In BISYNC COP mode, this bit is set upon receipt of the BCC byte(s), if any, to
indicate that the received BCC was in error. The bit is normally FIFOed with the last byte of the
frame (the character preceding the first BCC byte). However, if transfer FCS to FIFO (RPR[6]) is
asserted, this bit is FIFOed with the last BCC byte. The value of this bit should be ignored for
non-text messages or if the received frame was aborted via an ENQ. In non-BISYNC COP modes,
the bit is set with each received character if the current value of the CRC checker is not equal to the
non-error value (see CMR2[2:0]).
SYN detect– A SYN pattern was received. Refer to Detailed Operation for definition of SYN patterns.
Set one bit time after detection of SYN pattern in HSRH, HSRL.
Not used, set to 0
Not used, set to 0
Overrun error* – A new character was received while the receive FIFO was full and a charcter was
already waiting in the receive shift register to be transferred to the FIFO. The DUSCC protects the
five characters previously asssembled (four in RxFIFO, one in Rx shift register) and discards the
overrunning character(s). After the CPU read the FIFO, the character waiting in the RxSR will be
loaded into the available FIFO position. This releases the RxSR and a new character assembly will
start at the next character boundary. In this way, only valid characters will be asssembled, i.e., no
partial character assembly will occur regardless of when the RxSR became available during the
incoming data stream.
PAD error (BISYNC only)* – PAD error detected (see RPR[5]). An ABOR T sequence consisting of a
zero followed by seven ones was received after receipt of the first address octet but before receipt of
the closing FLAG. The user should read RxFIFO until it is empty and determine if any valid
characters from a previous frame are in the FIFO. If no character with a tagged EOM detect ([7]) is
found, all characters are from the current frame and should be discarded along with any previously
read by the CPU. An ABORT detect causes the receiver to automatically go into search for FLAG
state. An abort during a valid frame does not cause the CRC to reset; this will occur when the next
frame begins.
Rx character zero count detect (EOM detect – BISYNC only)*# –The character at the top of the FIFO
was either a text message terminator or a control sequence received outside of a text or header field.
See Detailed Operation of COP Receiver. If transfer FCS to FIFO (RPR[6]) is set, the EOM will
instead be tagged onto the last byte of the FCS. Note that if an overrun occurs during receipt of a
message, the EOM character may be lost, but this status bit will still be asserted to indicate that an
EOM was received. For two-byte EOM comnparisons, only the second byte is tagged (assuming the
CRC is not transferred to the FIFO).
Figure 74. RSRA (B) Receiver Status Register [COP Mode]
*FIFOed with data in extended mode (CDUSCC)
#FIFOed with data in default mode (NDUSCC)
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1994 Mar 21 659
76543210
0
1
2
3
4
5
6
7
Rx Transparent mode – Indicates that a DLE-STX sequence was received and the receiver is
operating in BISYNC transparent mode. Set two bit times after detection of STX in HSRL.
T ransparent mode operation is terminated and the bit is negated automatically when one of the
terminators for transparent text mode is received (DLE-ETX/ETB/ITB/ENQ).
Rx Hunt mode – This bit is asserted after the receiver is reset or disabled. It indicates that the
receiver is in the hunt mode, searching the data stream for a SYN sequence to establish character
synchronization. The bit is negated automatically when character sync is achieved.
Not used
DPLL error – Set while the DPLL is operating in FM mode to indicate that a data transition was not
detected within the detection window for two consecutive bits and that the DPLL was forced into
search mode. This feature is disabled when the DPLL is specified as the clock source for the
transmitter via TTR[6:4].
Send SOM ACK – Set when the transmitter begins transmission of a SYN pattern in response to the
TSOM or TSOMP command. If the command is reinvoked, the bit will be set again at the beginning
of the next transmitted SYN pattern. The user can control the number of SYNs which are sent
through this mechanism.
Frame complete – Asserted at the beginning of transmission of the end of message sequence invoked
by which is either a TEOM command, or when TPR[4]=1, or TPR[7:6]=00. The CPU can invoke the
TSOM command after this bit is set to control the number of SYNs between transmitted frames.
CTS underrun – This bit is set only if CTS enable Tx (TPR[2]) is asserted. It indicates that the
transmit shift register was ready to begin serializing a character and found the CTSN input negated.
T ransmitter underrun – Indicates that the transmit shift register has completed serializing a character
and found no other character to serialize in the TxFIFO. The bit is not set unitl at least one character
from the transmit FIFO (not including PAD characters in synchronous modes) has been serialized.
The transmitter action after transmitter empty depends on function.
Figure 75. TRSRA (B) Transmitter and Receiver Status Register [COP Mode]
76543210
0
1
2
3
4
5
6
7
Parity error
CRC/LRC error
SYN detect
Reserved
Reserved
Overrun
PAD error
EOM detect
Figure 76. IER1A (B) Interrupt Enable Register 1 [COP Mode]
76543210
0
1
2
3
4
5
6
7
Delta DCD detect
Delta CTS
DPLL error
Send SOM ACK
CTS underrun
Tx underrun
Tx frame complete
Tx path empty
Figure 77. IER2A (B) Interrupt Enable Register 2 [COP Mode]
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 660
SYN Pattern Stripping
Leading SYNs (before a message) are always stripped and
excluded from the FCS, but SYN patterns within a message are
treated by the receiver according to the RPR[7] bit. SYN character
patterns are defined for the various COP modes as follows:
COP single SYN mode - SYN1
COP dual SYN mode - SYN1, and SYN2 when immediately
preceded by SYN1.
BISYNC normal mode - SYN1 and SYN2 when immediately
preceded by SYN1, SYN1 is always stripped, even if it is not
followed by SYN2 when stripping is selected.
BISYNC transparent mode - DLE - SYN1, where the DLE is the last
of an odd number of consecutive DLEs.
RPR[7]
0 Strip only leading SYNs and do not accumulate in FCS.
1 Strip all SYNs. Additionally , strip odd DLEs when operating in
BISYNC transparent mode. Do not accumulate stripped
characters in FCS.
NOTE: In BISYNC transparent mode, odd DLEs are never included
in FCS. RPR[7] chooses whether they go to the RxFIFO or not.
Processing of the SYN patterns is determined by the RPR[7] bit, the
COP mode, and the position of the pattern in the frame. This is
summarized in Table 16.
The value of the RPR[7] field does not affect the setting of the SYN
DETECT status bit, RSR[2], and the generation of a SYNOUT pulse
when a SYN pattern is received.
BISYNC FEATURES
The CDUSCC provides support for both BISYNC normal and
transparent operations. The following summarizes the features
provided. Both EBCDIC and ASCII text messages can be handled
by the CDUSCC as selected by CMR1[5]. The receiver has the
capability of recognizing special characters for the BISYNC protocol
mode (see Table 17). All sequences in Table 17, except SOH and
STX, when detected explicitly cause a status to be affected.
The first character received when entering data phase for a header
or text message should be an SOH, an STX, or a DLE-STX
two-character sequence. Receipt of any of these initializes the CRC
generator and starts the CRC accumulation. The SOH places the
receiver in header mode, receipt of the STX places it in text mode,
and receipt of the DLE-STX sequence (at any time) automatically
places the receiver in transparent mode and sets the XPNT mode
status bit, TRSR[0]. There is no explicit status associated with SOH
and STX. If any other characters are received when entering the
data phase, the message is treated as a control message and will
not be accumulated in CRC.
After the data phase is established, the receiver searches the data
stream for an end of message control character(s):
Header field: ENQ, ETB, or ITB
Normal text field: ENQ, ETX, ETB, or ITB
T ransparent text field: DLE-ENQ, DLE-ETX, DLE-ETB, or DLE-ITB
Control message field: EOT, NAK, ACK0, ACK1, WACK, RVI or TTD
Detection of any one of these sequences causes the EOM status
bit, RSR[7], to be set. Also if RPR[5] is set and the receiver does
not detect a closing PAD (four 1’s) after the ’EOT’ or ’NAK’, the PAD
error status bit, RSR[6], is set. When the abort sequence ENQ or
DLE-ENQ is detected, the character is tagged with an EOM status
and transferred to the FIFO, but the appended CRC error status bit
should be ignored. For the other EOM control sequences, the
receiver waits for the next two bytes (the CRC bytes) to be received,
checks the value of the CRC generator, and tags the transferred
character with a CRC error, RSR[1], if the CRC remainder is not
correct. See Figure 78 for an example of FCS (BCC) accumulation
in various BISYNC messages.
The CRC bytes are normally not transferred to the FIFO, unless the
transfer FCS to FIFO control bit, RPR[6], is asserted. In this case
the EOM and CRC error status bits will be tagged onto the last byte
of the last FCS byte instead of to the last character of the message.
After detecting one of the end-of-message (EOM) character
sequences and setting RSR[7], the receiver automatically goes into
auto hunt mode for the SYNC characters and PAD check if RPR[5]
is set.
Table 16. SYN Pattern Processing
Mode RPR[7] Leading SYNs Within a Message
BISYNC 0 no FCS no FCS
no FIFO Pattern into FIFO
1no FCS no FCS
no FIFO no FIFO
COP 0 no FCS Accumulate in FCS
no FIFO Pattern into FIFO
1no FCS no FCS
no FIFO no FIFO
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Table 17. BISYNC Features
Sequence ASCII EBCDIC Description
BISYNC — Single Character Sequence
SOH 01H 01H Start of header
STX 02H 02H Start of text
ETX 83H 03H End of text
EOT 04H 37H End of transmission
ENQ 85H 2DH Enquiry
DLE 10H 10H Data link escape
NAK 15H 3DH Negative ack
ETB 97H 26H End of transmission block
ITB 1FH 1FH End of intermediate transmission block
BISYNC — Two Character Sequence
ACK0 H‘10,B0’ 10,70H Acknowledge 0
ACK1 H‘10,31’ 10,61H Acknowledge 1
WACK H‘10,3B’ 10,6BH W ait before transmit positive ack
RVI H‘10,BC’ 10,7CH Reverse interrupt
TTD H‘02,85’ 02,2DH Temporary text delay
BISYNC — (Transparent Text Mode) — Two Character Sequences
DLE-ENQ H‘10,85’ 10,2DH Enquiry
DLE-ITB H‘10,1F’ 10,1FH End of intermediate transmission block
DLE-ETB H‘10,97’ 10,26H End of transmission block
DLE-ETX H‘10,83’ 10,03H End of text
DLE-STX H‘10,02’ 10,02H Start of transparent mode
Figure 78. BISYNC BCC Accumulation Examples
1–
2–
3–
4–
5–
SYN SYN SOH ––––STX––––ETX BCC BCC
SYN SYN STX –––––––– BCC BCCSYN SYN ETB PAD
SYN SYN SOH
SYN SYN SOH ––––DLE STX DLE DLE SYN DLE SYN DLE ETX BCC BCC PAD––––ENQ ETB ITB ETX
SYN SYN DLE–STX DLE SYN DLE ITB DLE STXBCC BCC PAD–––––– SYN SYN DLE ITB –– ETX BCC BCC
NOTE:
1. The BCC accumulator is stopped after the end of message character sequence. All shaded areas are accumulated.
2. ENQ (DLE-ENQ) in a text message should be treated as an abort.
3. Opening SYNs will be stripped by the receiver.
BLOCK 1
BLOCK 1
BLOCK 2
BLOCK 2
––––STX––––ITB BCC BCC SYN SYN DLE STX –––– DLE ETX BCC BCC PAD
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Table 18. Summary of COP Features
COP Dual SYN Mode
SYN detect SYN1–SYN2
Linefill SYN1–SYN2
SYN stripping SYN1–SYN2 used to establish character sync, i.e., leading SYNs. Subsequent to this (after receiving
first non-SYN character), SYN1 and SYN1–SYN2 if stripping is specified by RPR[7].
Excluded from FCS1SYN1 and SYN1–SYN2 before beginning of message, i.e., leading SYNs and, if SYN stripping is
specified by RPR[7] anywhere else in the message for the Rx; linefill SYN1–SYN2 for Tx regardless of
RPR[7]. (If SYN stripping is not specified, then SYNs within a message will be included in FCS by Rx.)
BISYNC Normal Mode
SYN detect SYN1–SYN2
Linefill SYN1–SYN2
SYN stripping SYN1–SYN2 used to establish character synchronization, i.e., leading SYNs. Subsequent to this (after
receiving first non-SYN character), SYN1 and SYN1–SYN2 if stripping is specified by RPR[7].
Excluded from FCS All SYNs either before or within a message, regardless of RPR[7], plus additional characters as
required by the protocol, e.g., the first character of header or text is SOH, STX or DLE+STX.
BISYNC Transparent Mode
SYN detect DLE–SYN11
Linefill DLE–SYN1
SYN stripping DLE–SYN1 and odd DLEs if stripping is specified by RPR[7]
Excluded from FCS DLE–SYN1 and odd DLEs, regardless of RPR[7]
COP Single SYN Mode
SYN detect SYN1
Linefill SYN1
SYN stripping SYN1 used to establish character synchronization, i.e., leading SYNs. Subsequent to this (after
receiving first non-SYN character), SYN1 is stripping if specified by RPR[7].
Excluded from FCS2SYN1 before beginning of message, i.e., leading SYNs and, if SYN stripping is specified by RPR[7]
anywhere else in the message for the Rx; linefill SYN1 for Tx regardless of RPR[7]. (If SYN stripping is
not specified, then SYNs within a message will be included in FCS by Rx.)
NOTES:
1. In non-BISYNC COP modes (single or dual SYN case), if SYN stripping is off, i.e., RPR[7] = 0, then SYNs within a message will be included
in FCS by receiver. Therefore, the remote transmitter should be careful not to let the TxFIFO underrun since the linefill SYN characters are
not accumulated in FCS by the T ransmitter regardless of RPR[7]. Letting the TxFIFO underrun will result in a CRC error in the receiver.
2. DLE indicates last DLE of an odd number of consecutive DLEs.
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APPENDIX 1
Philips Semiconductors
ICs for Data Communications
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FUNDAMENTAL CDUSCC FUNCTIONS
The design of the CDUSCC has been directed at providing a device
which relieves the system processor from the numerous and varied
tasks associated with synchronous protocols. These tasks include
clock recovery (digital phase-locked loop) from data stream;
generation, detection and deletion of various control characters;
error detection; modem control; baud rate generation; character
counting and miscellaneous time interval generation. The CDUSCC
also provides asynchronous communication.
ASYNCHRONOUS vs SYNCHRONOUS
TRANSMISSION
Asynchronous data is typically produced by low-speed terminals
with bit rates ≤ 9600bps. In asynchronous systems (Figure 79a),
the transmission line is in a mark (binary 1) condition in its idle state.
As each character is transmitted, it is preceded by a start bit, or
transition from mark to space (binary 0), which indicates to the
receiving terminal that a character is being transmitted. The
receiving device detects the start bit and the data bits that make up
the character. At the end of the character transmission, the line is
returned to a mark condition by one or more stop bit(s), and is ready
for the beginning of the next character. An asynchronous character
varies in length depending on the information code employed: five
bits for Baudot code, seven for ASCII (plus an optional parity bit)
and eight for EBCDIC. This process is repeated
character-by-character until the entire message has been sent. The
start and stop bits permit the receiving terminal to synchronize itself
to the transmitter on a character-by-character basis.
Synchronous transmission (Figure 79b) makes use of an internal
clocking source within the modem to synchronize the transmitter
and receiver. Once a synchronization character (SYN or FLAG) has
been sensed by the receiving terminal, data transmission proceeds
character-by-character without intervening start and stop bits. The
incoming stream of data bits is interpreted on the basis of the
receive clock supplied by the modem. This
clock is usually derived from the received data through a phase
locked loop. The receiving device accepts data from the modem
until it detects a special ending character or a character terminal
count at which time it knows that the message is over.
The message block is usually composed of one or two
synchronization characters, a number of data and control characters
(typically 100 to 10,000), a terminating character, and one or two
error control characters. Between messages, the communication
line may idle in SYN or FLAG characters or be held to mark.
Note that synchronous modems can be used to transmit
asynchronous data and conversely, asynchronous modems can be
used for synchronous data if the receiving terminal can derive the
clock from the data.
Asynchronous transmission is advantageous when transmission is
irregular (such as that initiated by a keyboard operator’s typing
speed). It is also inexpensive due to the simple interface logic and
circuitry required. Synchronous transmission, on the other hand,
makes far better use of the transmission facility by eliminating the
start and stop bits on each character. Furthermore, synchronous
data is suitable for multi-level modulation which combines two or
four bits in one signal element (baud). This can facilitate data rate of
4.8Kb/s or 9.6Kb/s over a bandwidth of 2.4KHz. Synchronous
modems offer higher transmission speeds, but are more expensive
because they require precisely synchronized clock and data.
Synchronous communication offers more efficient use of a channel
capacity. For example, in async mode, efficiency could be as low as
5/9 and not higher than 8/9.5. Here the imposition of start, stop and
parity reduces channel efficiency. In synchronous protocols, the
inef ficiency is caused by the SYN characters, address, FCS and
closing sequence. The data in between may be as long as one
wishes.
CHARACTERISTICS OF DATA LINK CONTROLS
Data Link Control (DLC) can be classified into Character Oriented
Protocols (COP) and Bit Oriented Protocols (BOP). In COP a
defined set of communication control characters effects the orderly
operation of the data link. These control characters are part of an
information code set, such as ASCII or EBCDIC. The code set also
a. ASYNCHRONOUS
b. SYNCHRONOUS (BOP, COP and BISYNC)
IDLE STATE
START BIT
MARK
SPACE
DATA BITS
OPTIONAL PARITY BIT
STOP BITS
FRAME FRAME
SYNC CHARACTER
ONE COMPLETE CHARACTER SUBSEQUENT FRAMES HAVE
NO RELATION TO PREVIOUS
5 TO 8
MARK
SPACE
DATA BITS
Choice of the proper timing mode depends on the application. Asynchronous transmission (a) is used mostly with man-machine interfaces while synchronous transmission
(b) offers the high speed necessary for machine-machine communication.
Figure 79. Serial Data Stream Formats
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consists of graphic characters (alphanumeric, $, ., etc.). COP
messages are transmitted in blocks which are composed of a
header or control field, a body or text field and trailer or error
checking field. Specific end/begin characters are used as field or
block delimiters for IBMs Binary Synchronous Communications
(BISYNC) protocol. Examples are SOH (Start of Header), STX
(Start of Text), ETX (End of text), ITB (Intermediate Transmission
Block), and EOT (End of T ransmission). In the Digital Data
Communications Message Protocol (DDCMP) developed by Digital
Equipment Corporation, character count is used to determine the
length of the text field while a SOH character delimits the header
field.
BOPs make use of only two or three specific control characters for
operation of the data link. These characters are used to delimit the
beginning (FLAG) and end (FLAG, ABORT) of a message frame,
Upon receipt of the opening FLAG, positional significance is used to
delineate the bit sequence that follows into prescribed fields. These
fields are address, control, information, and frame check sequence.
The address, control and frame check fields are of fixed length; the
information field length is variable and may be zero. Examples of
BOPs are IBM’s Synchronous Data Link Control (SDLC), ANSI’s
Advanced Data Communication Control Procedures (ADCCP),
ISO’s High-Level Data Link Control (HDLC), Burrough’s Data Link
Control (BDLC), and various other protocols developed by computer
mainframe manufacturers. All of the above-mentioned protocols are
similar and can be treated as subsets of ADCCP.
Automatic Request for Repeat (ARQ)
The two types of ARQs are stop-and-wait and continuous ARQ.
Each provides defined methods for acknowledging correct (error
free) reception of transmitted blocks of information.
When a connection is established in the stop-and-wait ARQ, the
transmitter sends one block and then stops. Eventually, the receiver
acquires that block, subjects the block to an error check, and then
sends an ACK control character to the transmitter to indicate that
the block is correct or a NAK control character to indicate an error.
If an ACK is returned, the transmitter sends the next block in
sequence. If a NAK is returned, that block is re-transmitted. Thus,
the stop-and-wait mode involves periods of idleness, including
propagation delays between each block, so that the line is not
communicating nearly at its rated capacity. A line efficiency of 25%
to 50% is not uncommon, depending on the error rate on the line.
IBM’s BISYNC protocol is the most popular implementation of
stop-and-wait type of ARQ.
In continuous ARQ, the transmitter keeps sending one block after
another without stopping. The receiver and transmitter retain
individual counts of the blocks outstanding and provide buffer
storage to retain those blocks. Only when an erroneous block is
detected does the receiver tell the transmitter to re-send that block
and all subsequent in-transit, but unacknowledged blocks. Some
DLCs permit up to 127 blocks to be unacknowledged at any one
time. IBM’s SDLC, Burrough’s Data Link Control (BDLC), and
Digital Equipment Corporation’s DDCMP employ continuous ARQ.
Under ideal conditions, the link can exceed 90% efficiency with this
type of ARQ.
COP Messages
As stated earlier, COP messages are transmitted in units called
blocks. The components of a transmission block are shown in
Figure 78. The Header field contains auxiliary information that
identifies the address of the message destination or source, the job
number (if any), the type of message (data or control), the control
action, and a positive or negative acknowledgment to insure
error-free reception of a previous message(s).
Control actions are used to reset or initialize a secondary station, to
acknowledge good or bad reception of blocks, to inquire why a
response or acknowledgment has not occurred within a specific time
period, or to abort a transfer sequence. Examples of typical control
function inquiries or responses are given below:
This is Station A transmitting
I have a message for Station B
Are you ready to receive?
I received your last message.
I’m finished; now it’ s your turn to transmit.
Do you have anything to send me?
I can’t listen now, so don’t send me anything.
I don’t hear you, so I’m hanging up.
The control information is conveyed via special characters or
character sequences.
The Text field contains the data, if any, being transmitted. This
variable length field is absent in control messages. The Text may be
characters of the information code set or may be transparent to that
code set. In the latter case, pure data (binary, packed decimal,
floating point), specialized codes, or machine language computer
programs must be distinguished from characters in the code set
being used. This is accomplished through the use of a transparent
mode whose implementation depends on the specific DLC.
To assure correct reception of information over communication
facilities, a sequence of check bits, often called Block Check
Character(s) or BCC, are generated and transmitted as the Error
Check field. Each block of data transmitted is error-checked at the
receiving station in one of several ways, depending on the code and
functions employed. These checking methods include:
1. Vertical Redundancy Check (VRC a parity check on each char-
acter) in conjunction with a Longitudinal Redundancy Check
(LRC a horizontal parity, i.e., exclusive OR, on the characters)
that is sent as the Error Check field. Note that certain control
characters and transparent mode information is not subject to
LRC.
2. Cyclic Redundancy Check (CRC) which involves a polynomial
division of the bit stream by a CRC polynomial. The dividend
polynomial is initially preset to 0 and the 1s and 0s of the data
stream become the coefficients of the dividend polynomial. The
division uses subtraction modulo 2 (no carries) and the remain-
der is transmitted as the Error Check field. The receiving station
compares the transmitted remainder with its own computed re-
mainder and an equal condition indicates that no error has oc-
curred. The polynomial value depends on the protocol and code
set being used.
BOP Messages
Bit Oriented Protocols (BOPs) are more straightforward and
universal than the COPs just discussed. BOP messages are
transmitted in frames and all messages adhere to one standard from
format shown in Figure 79.
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Common characteristics of BOPs are:
•Independence of codes, line configurations, and peripherals.
•Positional significance is used instead of control characters or
character counts
•There is one standard frame format for messages
•Continuous ARQ operation allows up to 7 outstanding frames
(127 when a seven-bit frame count is maintained)
•Half or full-duplex operation is possible
•Information transparency is achieved through zero insertion and
deletion
•Error checking is on a complete frame
As shown in Figure 79, a frame starts with the 8-bit FLAG sequence,
01111110, followed in position by an ADDRESS sequence, a
CONTROL sequence, an INFORMATION sequence (if present), a
FRAME CHECK SEQUENCE, and ending with another FLAG
sequence. Each station attached to the data link continuously
searches for the FLAG sequence and an ADDRESS sequence. In
multi-point operation, for example, a secondary station must detect a
FLAG immediately followed by its own ADDRESS to enable the
receiver.
When the primary station transmits, the station ADDRESS
sequence it designates which secondary station is to receive the
balance of the transmitted frame. When a secondary station
transmits, the ADDRESS tells the primary station which secondary
station originated the frame. A secondary station must recognize its
valid address before it can accept a frame and take any action on
the contents of that frame. Also, the primary station will accept a
frame only when it contains the address of a secondary station that
has been given permission to transmit. To ensure the integrity of
the data being transmitted, the ADDRESS sequence appears within
each frame. This enhances flexibility in that the primary station can
interleave receptions from several secondary stations without
intermixing individual station information transfer. Using straight
binary coding, an 8-bit ADDRESS sequence can differentiate
between 256 terminals or stations.
Some BOPs (ADCCP and HDLC) permit the use of an extended
ADDRESS field to address more than 256 terminals. To do this, the
least-significant bit of an ADDRESS byte is set to zero if another
ADDRESS byte is to follow; a one is used to indicate that the current
address byte is the last one. Since only 7 bits are used for the
actual station address, each ADDRESS byte can differentiate
between (up to) 128 terminals. There is no limit to the number of
ADDRESS bytes in an extended ADDRESS field.
An “all parties” or “global address” of eight 1s can be interpreted as
a legitimate secondary station address (in addition to the specified
secondary station address) which will activate the receiver. This
pattern must follow the opening FLAG.
The CONTROL field follows the ADDRESS sequence. It is the
heart of the BOP message for it determines the type of message,
the send-and-receive frame sequence counts (for continuous ARQ),
a poll command from the primary station or final response from the
secondary station. The primary station uses CONTROL to tell
(command) the addressed secondary station what operation to
perform. The secondary station uses CONTROL to react (respond)
to the primary station.
The CONTROL field takes on any one of three formats depending
on whether the field is to indicate:
•Information transfer
•Supervisory commands/responses
•Non-sequenced commands/responses
Actual implementation of these three message types is beyond the
scope of this handbook. Refer to the appropriate BOP DLC
specification listed in Chapter 7.
A one byte CONTROL field uses three bits for transmit and three
bits for receive sequence counts. This means up to seven frames
can be unacknowledged at any one time. To increase the number of
outstanding frames, a second byte is used to provide four additional
bits for transmit and four for receive sequence counts. This
extended CONTROL field enables up to 127 frames to be
outstanding. Note that buffer storage is required to contain all of the
outstanding frames, for they may have to be re-transmitted if they
are received in error.
The INFORMATION field may vary in length, including different
lengths in sequential frames making up a complete transmission.
The data may be configured in any code structure, including straight
binary, binary coded decimal, packed decimal, EBCDIC, ASCII, and
Baudot. The INFORMATION field may be used to convey any kind
of code. However, the content of the field must be self-defining by
actual or implied means. For example, peripheral device control
characters, such as CARRIAGE RETURN, will actually be part of
the INFORMATION field, while the code being used, whether it be
ASCII or EBCDIC, may be implied in the address of a specific
terminal designed for a specific code. Furthermore, whether a frame
contains an INFORMATION field at all depends on the particular
CONTROL format transmitted.
Because there is no restriction on the bit patterns that may appear
between the end of the start FLAG and the beginning of the end
FLAG, the transmitted data stream may contain six or more
contiguous ones and this pattern could be interpreted as a FLAG,
and inadvertently terminate an incomplete frame. To circumvent
this, once the start FLAG has been completed the transmitting
station starts counting the number of contiguous 1s; when five 1s
occur, the transmitter automatically inserts a 0 following the fifth 1.
The receiver, too, counts the number of contiguous 1s. When the
number is five, it inspects the sixth bit; if the sixth bit is 0, the
receiving station drops the 0, resets its counter and continues
receiving. But if the sixth bit is a 1, the receiving station continues to
receive and act on the pending FLAG.
The FRAME CHECK SEQUENCE (FCS) is included in all BOP
frames to detect errors which may occur during transmission. This
field is 16 bits long and immediately precedes the end-of-frame
FLAG. The contents of the FCS field, based on a cyclic redundancy
check, is an inverted remainder derived from a division of the
transmitted data by a generator polynomial. The dividend is initially
preset to 1s, and the data stream that follows becomes the dividend.
The generator polynomial for CRC-CCITT is:
G(x) = X16 + X12 + X5 + 1
All data transmitted between the start FLAG and the end FLAG is
included in the checking accumulation, except those 0 bits inserted
to prevent unwanted FLAGS. Because the received CRC is subject
to CRC accumulation, the result of a transmission correctly received
is the hexadecimal constant F0B8.
A comparison of common DLCs is given in Table 19.
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Table 19. Protocol Characteristics
FEATURE DDCMP BISYNC SDLC ADCCP HDLC
Full Duplex Yes No Yes Yes Yes
Half Duplex Yes Yes Yes Yes Yes
Serial Yes Yes Yes Yes Yes
Parallel Yes No No No No
Data T ransparency Count Character Stuffing Bit Stuffing Bit Stuffing Bit Stuffing
Asynchronous Operation Yes No No No No
Synchronous Operation Yes Yes Yes Yes Yes
Point-to-Point Yes Yes Yes Yes Yes
Multi-point Yes Yes Yes Yes Yes
Error Detection (CRC) CRC-16 CRC-16 CRC-CCITT CRC-CCITT CRC-CCITT
Re-T ransmit Error Recovery Yes Yes Yes Yes Yes
Bootstrapping Capability Yes No No No No
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APPENDIX 2
Philips Semiconductors
Data Communications
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TEST MODES
CDUSCC has three test modes which can be exercised as
described below:
BRG Test
All the internal baud rates of the BRG can be tested through TRxC
output pin. A simple set up will allow a user to quickly check if the
BRG is working correctly. Rx, Tx and DPLL blocks need not be
enabled in this setup. The RTxC pin is ignored in these tests.
To test the receiver baud rates on TRxCA pin:
After resetting the chip, load the following two registers:
PCRA = ‘05’ ; TRxCA pin is an output for
receiver BRG @ 16X
RTRA = ‘2F’ ; Receive clock select is from
BRG @ 32X the shift rate
; In this case the bit rate is
38.4k x 32.
Then give enough time for the output to come out.
To test the transmitter baud rates on TRxCA pin:
After resetting the chip, load the following two registers:
PCRA = ‘04’ ; TRxCA pin is an output for
receiver BRG @ 16X
TTRA = ‘2F’ ; Receive clock select is from
BRG @ 32X the shift rate.
; In this case the bit rate is
38.4k x 32.
Then give enough time for the output to come out.
By varying the value in the RTRA/TTRA register from hex ‘2F’ to ‘20’
all the baud rates can be tested. These tests can be done with a
single loop count. When switching one baud rate to another on the
fly, make sure that you don’t strobe for the output wave forms during
these periods. Three new baud rates can be selected by enabling
TRCR[1] and appropriate TTR bits.
Tx PLA Test
Tx PLA test can be done by following steps given below:
– Force RTxCA pin low
– Force DCDNA pin low
– PCRA = 00 ; TRxC/RTxC as 1X external
clocks
– TTRA = 80 ; TRxC external clock
– RTRA = 80 ; TRxC external clock
– CCRA = C6 ; enable Tx PLA test (see
timing)
– Force RTxCA pin high at falling edge of 31st TRxC clocks
– Test TxDA pin high on falling edge of 10,001th TRxC clocks
– Force DCDNA pin high to shift signature bits per two clocks
– signature = 0FBEE Hex (18 bits 10,001th to 10,036th clock,
LSB first)
– CCRA = 03 ; Tx disable command
– CCRA = 00 ; Reset Tx command
Rx PLA Test
Tx PLA test can be done by following steps given below:
– Force RTxCA pin low
– Force DCDNA pin low
– PCRA = 00 ; TRxC/RTxC as 1X external
clocks
– TTRA = 80 ; TRxC external clock
– RTRA = 80 ; TRxC external clock
– CCRA = C7 ; enable Rx PLA test (see
timing)
– Force RTxCA pin high at falling edge of 31st TRxC clocks
– Test SYNOUTAN output on falling edge of 10,001th TRxC
clocks
– Force DCDNA pin high to shift signature bits per two clocks
– signature = 7045 Hex (16 bits 10,001th to 10,032nd clock, LSB
first)
– CCRA = 43 ; Rx disable command
– CCRA = 40 ; Reset Rx command
TIMING
WRN
TRxC
RTxC
DCDN
31st 10,001th
Rising edge of WRN must be followed by falling edge of TRxC when Tx/Rx PLA test is being enabled through CCR command
Channels A and B, Tx and Rx PLA can be tested together by writing to both channels and enabling RTxC and DCDN accordingly.
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CROSS-REFERENCE
Philips Semiconductors
Data Communications
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1994 Mar 21 671
A7 Bit Control, 529
ASYNC operational mode, 581
Block Diagram
SC26C562, 533
SC68C562, 534
Capabilities, CDUSCC vs NDUSCC, 528
CID Definitions, 529
Command Registers
channel command, 570
channel command table, 571
counter/timer, 573
DMA commands, 574
DPLL commands, 573
receiver commands, 572
test modes, 573
transmitter CCR commands, 570
Tx/Rx command register, 570
Crystal oscillator, 559
DMA Control, 548
CDUSCC DMA modes, 548
DMA commands, 574
DMA frame status byte, (DFSB), 549
DMA interface, 548
DONEN/EOPN operation, 549
full–duplex dual address, 548
full–duplex single address, 548
half–duplex dual address, 548
half–duplex single address, 548
receiver DMA request operation
SC26C562
dual address mode, 551
single address mode, 550
SC68C562
dual address mode, 552
single address mode, 553
transmitter DMA request operation
SC26C562
dual address mode, 551
single address mode, 550
SC68C562
dual address mode, 552
single address mode, 553
FIFO
fill/empty level registers, 556
receiver, 555
receiver FIFO, 555
block diagram, 555
transmit, 554
TxFIFO threshold criteria, 554
TxFIFO threshold level register, 558
Hardware/Software, compatibility, 528
Host Interface, 529
I/O Control, general purpose I/O, 568
Interrupts
acknowledge modes
SC26C562, 541
SC68C562, 542
control and priority, 540
control register, 544
control relationships
default mode, 543
extended mode, 548
default interrupt mode, 542
enable register, 545
enable registers
1, 2 and 3, 546
register 2, 546
register 3, 546
encoding of interrupt status, 547
extended interrupt mode, 542
handling, 540
interrupt driven systems, 540
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interrupt enable
register 1, 586
register 2, 586
interrupt vector register, 547
modified vector register, 547
vectored mode, SC68C562, 545
Pin Configurations
SC26C562, 521
SC68C562, 522
Pin Descriptions, 524–527
Registers
bit assignment table, 531–533
CDUSCC register address map, 530
channel command, 570
channel mode
register 1, 581, 587, 596
register 2, 582, 588, 597
control register, 544
Counter/Timer
control, 565
control and value, 564
high, 566–568
preset, 566–568
enable register, 545
FIFO fill/empty level, 556
general status, 537
input and Counter/Timer status, 538
interrupt enable
register 1, 586, 593, 602
register 2, 586, 593, 602
interrupt enable registers, register 1, 546
interrupt vector register, 547
modified vector, 547
output and miscellaneous, 569
Pin Configuration, 568
receive FIFO filled level, 557
receiver and transmitter status, 538
receiver parameter register, 584, 591, 600
receiver status register, 585, 591, 592, 601
receiver timing, 562
rules governing, 528
status register organization
default mode, 536
extended mode, 537
Status registers, 536
SYN1/secondary address register, 1, 583, 589, 597
SYN2/secondary address register, 2, 589, 598
transmit FIFO empty level, 557
transmitter and receiver status, 586, 593, 602
transmitter parameter register, 583, 589, 598
transmitter timing, 561
transmitter/receiver miscellaneous status, 539
Tx/Rx command register, 570
TxFIFO threshold level, 558
Rx
baud rates, 562
pattern recognition, 539
receive FIFO filled level register, 557
receiver ASYNC mode, 584
receiver clock sources, 560
receiver commands, 572
receiver data path, 579
receiver DCD control, 578
receiver DMA request operation, SC68C562
dual address mode, 552
single address mode, 553
receiver FIFO, block diagram, 555
receiver operation, 577
receiver RTS control, 578
receiver RxFIFO, RxRDY, 577
receiver timing register, 562
RTxC function select, 567
RxFIFO threshold level register, 558
RxRDY activate mode, 569
TRxC and RTxC function select, 567
Status, DMA frame status byte, (DFSB), 549
Synchronous operation
abort transmission, 590
address and control field transmission, 588
BiSYNC, 599
BiSYNC BCC accumulation, 604
BiSYNC features, 603
BiSYNC features table, 604
BOP operational mode, 587
control of number of FLAGs, 590
COP operational mode, 595
data transmission and underrun for COP mode, 598
ending transmission, 590
information field transmission and underrun, 590
overview, 587
RxBOP mode, 594
RxCOP modes, 599
starting transmission, 588
summary of COP features table, 605
SYN pattern processing table, 603
Philips Semiconductors User’s Guide
CMOS DUSSC User’s Guide
1994 Mar 21 673
SYN pattern stripping, 603
Tx residual character length, 590
TxBOP loop mode, 594
TxBOP modes, 587
TxCOP modes, 595
TxCRC accumulation, 590
underrun control table, 591
zero insertion, 590
Timing circuits, 559
bit rate generator, 559
Counter/Timer
clock selection, 564
clock sources, 563
control and value registers, 564
control register, 565
counter/timer commands, 573
operation, 564
preset register, 566–568
register, 566–568
digital phase–locked loop operation, 560
DPLL commands, 573
DPLL NRZI mode operation, 560
DPLL operation, FM mode, 563
DPLL waveforms, 563
receiver clock sources, 560
receiver timing register, 562
transmitter clock sources, 559
transmitter timing register, 561
Txbaud rates, 561
enabling the transmitter, 576
FIFO threshold level register, 558
overview of transmitter operation, 574
timing register, 561
transmit FIFO empty level register, 557
Transmit FIFOs, 554
transmitter CCR commands, 570
transmitter clock sources, 559
transmitter control, 575
transmitter data path, 574
transmitter DMA request operation, SC68C562
dual address mode, 552
single address mode, 553
transmitter states, 574
TRxC function select, 567
Tx ASYNC mode, 581
Tx FIFO threshold criteria, 554
Tx Path empty status bit, 539
TxBOP modes, 587
TxCTS operation, 576
TxRDY, 576
TxRDY activate mode, 569
TxRTS control, 576
